diff options
Diffstat (limited to 'drivers/net/dl2k.h')
-rw-r--r-- | drivers/net/dl2k.h | 163 |
1 files changed, 5 insertions, 158 deletions
diff --git a/drivers/net/dl2k.h b/drivers/net/dl2k.h index 5b801775f42d..d66c605b4075 100644 --- a/drivers/net/dl2k.h +++ b/drivers/net/dl2k.h | |||
@@ -298,23 +298,6 @@ enum _pcs_reg { | |||
298 | }; | 298 | }; |
299 | 299 | ||
300 | /* Basic Mode Control Register */ | 300 | /* Basic Mode Control Register */ |
301 | typedef union t_MII_BMCR { | ||
302 | u16 image; | ||
303 | struct { | ||
304 | u16 _bit_5_0:6; // bit 5:0 | ||
305 | u16 speed1000:1; // bit 6 | ||
306 | u16 col_test_enable:1; // bit 7 | ||
307 | u16 duplex_mode:1; // bit 8 | ||
308 | u16 restart_an:1; // bit 9 | ||
309 | u16 isolate:1; // bit 10 | ||
310 | u16 power_down:1; // bit 11 | ||
311 | u16 an_enable:1; // bit 12 | ||
312 | u16 speed100:1; // bit 13 | ||
313 | u16 loopback:1; // bit 14 | ||
314 | u16 reset:1; // bit 15 | ||
315 | } bits; | ||
316 | } BMCR_t, *PBMCR_t; | ||
317 | |||
318 | enum _mii_bmcr { | 301 | enum _mii_bmcr { |
319 | MII_BMCR_RESET = 0x8000, | 302 | MII_BMCR_RESET = 0x8000, |
320 | MII_BMCR_LOOP_BACK = 0x4000, | 303 | MII_BMCR_LOOP_BACK = 0x4000, |
@@ -333,28 +316,6 @@ enum _mii_bmcr { | |||
333 | }; | 316 | }; |
334 | 317 | ||
335 | /* Basic Mode Status Register */ | 318 | /* Basic Mode Status Register */ |
336 | typedef union t_MII_BMSR { | ||
337 | u16 image; | ||
338 | struct { | ||
339 | u16 ext_capability:1; // bit 0 | ||
340 | u16 japper_detect:1; // bit 1 | ||
341 | u16 link_status:1; // bit 2 | ||
342 | u16 an_ability:1; // bit 3 | ||
343 | u16 remote_fault:1; // bit 4 | ||
344 | u16 an_complete:1; // bit 5 | ||
345 | u16 preamble_supp:1; // bit 6 | ||
346 | u16 _bit_7:1; // bit 7 | ||
347 | u16 ext_status:1; // bit 8 | ||
348 | u16 media_100BT2_HD:1; // bit 9 | ||
349 | u16 media_100BT2_FD:1; // bit 10 | ||
350 | u16 media_10BT_HD:1; // bit 11 | ||
351 | u16 media_10BT_FD:1; // bit 12 | ||
352 | u16 media_100BX_HD:1; // bit 13 | ||
353 | u16 media_100BX_FD:1; // bit 14 | ||
354 | u16 media_100BT4:1; // bit 15 | ||
355 | } bits; | ||
356 | } BMSR_t, *PBMSR_t; | ||
357 | |||
358 | enum _mii_bmsr { | 319 | enum _mii_bmsr { |
359 | MII_BMSR_100BT4 = 0x8000, | 320 | MII_BMSR_100BT4 = 0x8000, |
360 | MII_BMSR_100BX_FD = 0x4000, | 321 | MII_BMSR_100BX_FD = 0x4000, |
@@ -374,24 +335,6 @@ enum _mii_bmsr { | |||
374 | }; | 335 | }; |
375 | 336 | ||
376 | /* ANAR */ | 337 | /* ANAR */ |
377 | typedef union t_MII_ANAR { | ||
378 | u16 image; | ||
379 | struct { | ||
380 | u16 selector:5; // bit 4:0 | ||
381 | u16 media_10BT_HD:1; // bit 5 | ||
382 | u16 media_10BT_FD:1; // bit 6 | ||
383 | u16 media_100BX_HD:1; // bit 7 | ||
384 | u16 media_100BX_FD:1; // bit 8 | ||
385 | u16 media_100BT4:1; // bit 9 | ||
386 | u16 pause:1; // bit 10 | ||
387 | u16 asymmetric:1; // bit 11 | ||
388 | u16 _bit12:1; // bit 12 | ||
389 | u16 remote_fault:1; // bit 13 | ||
390 | u16 _bit14:1; // bit 14 | ||
391 | u16 next_page:1; // bit 15 | ||
392 | } bits; | ||
393 | } ANAR_t, *PANAR_t; | ||
394 | |||
395 | enum _mii_anar { | 338 | enum _mii_anar { |
396 | MII_ANAR_NEXT_PAGE = 0x8000, | 339 | MII_ANAR_NEXT_PAGE = 0x8000, |
397 | MII_ANAR_REMOTE_FAULT = 0x4000, | 340 | MII_ANAR_REMOTE_FAULT = 0x4000, |
@@ -407,24 +350,6 @@ enum _mii_anar { | |||
407 | }; | 350 | }; |
408 | 351 | ||
409 | /* ANLPAR */ | 352 | /* ANLPAR */ |
410 | typedef union t_MII_ANLPAR { | ||
411 | u16 image; | ||
412 | struct { | ||
413 | u16 selector:5; // bit 4:0 | ||
414 | u16 media_10BT_HD:1; // bit 5 | ||
415 | u16 media_10BT_FD:1; // bit 6 | ||
416 | u16 media_100BX_HD:1; // bit 7 | ||
417 | u16 media_100BX_FD:1; // bit 8 | ||
418 | u16 media_100BT4:1; // bit 9 | ||
419 | u16 pause:1; // bit 10 | ||
420 | u16 asymmetric:1; // bit 11 | ||
421 | u16 _bit12:1; // bit 12 | ||
422 | u16 remote_fault:1; // bit 13 | ||
423 | u16 _bit14:1; // bit 14 | ||
424 | u16 next_page:1; // bit 15 | ||
425 | } bits; | ||
426 | } ANLPAR_t, *PANLPAR_t; | ||
427 | |||
428 | enum _mii_anlpar { | 353 | enum _mii_anlpar { |
429 | MII_ANLPAR_NEXT_PAGE = MII_ANAR_NEXT_PAGE, | 354 | MII_ANLPAR_NEXT_PAGE = MII_ANAR_NEXT_PAGE, |
430 | MII_ANLPAR_REMOTE_FAULT = MII_ANAR_REMOTE_FAULT, | 355 | MII_ANLPAR_REMOTE_FAULT = MII_ANAR_REMOTE_FAULT, |
@@ -439,18 +364,6 @@ enum _mii_anlpar { | |||
439 | }; | 364 | }; |
440 | 365 | ||
441 | /* Auto-Negotiation Expansion Register */ | 366 | /* Auto-Negotiation Expansion Register */ |
442 | typedef union t_MII_ANER { | ||
443 | u16 image; | ||
444 | struct { | ||
445 | u16 lp_negotiable:1; // bit 0 | ||
446 | u16 page_received:1; // bit 1 | ||
447 | u16 nextpagable:1; // bit 2 | ||
448 | u16 lp_nextpagable:1; // bit 3 | ||
449 | u16 pdetect_fault:1; // bit 4 | ||
450 | u16 _bit15_5:11; // bit 15:5 | ||
451 | } bits; | ||
452 | } ANER_t, *PANER_t; | ||
453 | |||
454 | enum _mii_aner { | 367 | enum _mii_aner { |
455 | MII_ANER_PAR_DETECT_FAULT = 0x0010, | 368 | MII_ANER_PAR_DETECT_FAULT = 0x0010, |
456 | MII_ANER_LP_NEXTPAGABLE = 0x0008, | 369 | MII_ANER_LP_NEXTPAGABLE = 0x0008, |
@@ -460,19 +373,6 @@ enum _mii_aner { | |||
460 | }; | 373 | }; |
461 | 374 | ||
462 | /* MASTER-SLAVE Control Register */ | 375 | /* MASTER-SLAVE Control Register */ |
463 | typedef union t_MII_MSCR { | ||
464 | u16 image; | ||
465 | struct { | ||
466 | u16 _bit_7_0:8; // bit 7:0 | ||
467 | u16 media_1000BT_HD:1; // bit 8 | ||
468 | u16 media_1000BT_FD:1; // bit 9 | ||
469 | u16 port_type:1; // bit 10 | ||
470 | u16 cfg_value:1; // bit 11 | ||
471 | u16 cfg_enable:1; // bit 12 | ||
472 | u16 test_mode:3; // bit 15:13 | ||
473 | } bits; | ||
474 | } MSCR_t, *PMSCR_t; | ||
475 | |||
476 | enum _mii_mscr { | 376 | enum _mii_mscr { |
477 | MII_MSCR_TEST_MODE = 0xe000, | 377 | MII_MSCR_TEST_MODE = 0xe000, |
478 | MII_MSCR_CFG_ENABLE = 0x1000, | 378 | MII_MSCR_CFG_ENABLE = 0x1000, |
@@ -483,20 +383,6 @@ enum _mii_mscr { | |||
483 | }; | 383 | }; |
484 | 384 | ||
485 | /* MASTER-SLAVE Status Register */ | 385 | /* MASTER-SLAVE Status Register */ |
486 | typedef union t_MII_MSSR { | ||
487 | u16 image; | ||
488 | struct { | ||
489 | u16 idle_err_count:8; // bit 7:0 | ||
490 | u16 _bit_9_8:2; // bit 9:8 | ||
491 | u16 lp_1000BT_HD:1; // bit 10 | ||
492 | u16 lp_1000BT_FD:1; // bit 11 | ||
493 | u16 remote_rcv_status:1; // bit 12 | ||
494 | u16 local_rcv_status:1; // bit 13 | ||
495 | u16 cfg_resolution:1; // bit 14 | ||
496 | u16 cfg_fault:1; // bit 15 | ||
497 | } bits; | ||
498 | } MSSR_t, *PMSSR_t; | ||
499 | |||
500 | enum _mii_mssr { | 386 | enum _mii_mssr { |
501 | MII_MSSR_CFG_FAULT = 0x8000, | 387 | MII_MSSR_CFG_FAULT = 0x8000, |
502 | MII_MSSR_CFG_RES = 0x4000, | 388 | MII_MSSR_CFG_RES = 0x4000, |
@@ -508,17 +394,6 @@ enum _mii_mssr { | |||
508 | }; | 394 | }; |
509 | 395 | ||
510 | /* IEEE Extened Status Register */ | 396 | /* IEEE Extened Status Register */ |
511 | typedef union t_MII_ESR { | ||
512 | u16 image; | ||
513 | struct { | ||
514 | u16 _bit_11_0:12; // bit 11:0 | ||
515 | u16 media_1000BT_HD:2; // bit 12 | ||
516 | u16 media_1000BT_FD:1; // bit 13 | ||
517 | u16 media_1000BX_HD:1; // bit 14 | ||
518 | u16 media_1000BX_FD:1; // bit 15 | ||
519 | } bits; | ||
520 | } ESR_t, *PESR_t; | ||
521 | |||
522 | enum _mii_esr { | 397 | enum _mii_esr { |
523 | MII_ESR_1000BX_FD = 0x8000, | 398 | MII_ESR_1000BX_FD = 0x8000, |
524 | MII_ESR_1000BX_HD = 0x4000, | 399 | MII_ESR_1000BX_HD = 0x4000, |
@@ -526,6 +401,7 @@ enum _mii_esr { | |||
526 | MII_ESR_1000BT_HD = 0x1000, | 401 | MII_ESR_1000BT_HD = 0x1000, |
527 | }; | 402 | }; |
528 | /* PHY Specific Control Register */ | 403 | /* PHY Specific Control Register */ |
404 | #if 0 | ||
529 | typedef union t_MII_PHY_SCR { | 405 | typedef union t_MII_PHY_SCR { |
530 | u16 image; | 406 | u16 image; |
531 | struct { | 407 | struct { |
@@ -543,6 +419,7 @@ typedef union t_MII_PHY_SCR { | |||
543 | u16 xmit_fifo_depth:2; // bit 15:14 | 419 | u16 xmit_fifo_depth:2; // bit 15:14 |
544 | } bits; | 420 | } bits; |
545 | } PHY_SCR_t, *PPHY_SCR_t; | 421 | } PHY_SCR_t, *PPHY_SCR_t; |
422 | #endif | ||
546 | 423 | ||
547 | typedef enum t_MII_ADMIN_STATUS { | 424 | typedef enum t_MII_ADMIN_STATUS { |
548 | adm_reset, | 425 | adm_reset, |
@@ -556,21 +433,6 @@ typedef enum t_MII_ADMIN_STATUS { | |||
556 | /* PCS control and status registers bitmap as the same as MII */ | 433 | /* PCS control and status registers bitmap as the same as MII */ |
557 | /* PCS Extended Status register bitmap as the same as MII */ | 434 | /* PCS Extended Status register bitmap as the same as MII */ |
558 | /* PCS ANAR */ | 435 | /* PCS ANAR */ |
559 | typedef union t_PCS_ANAR { | ||
560 | u16 image; | ||
561 | struct { | ||
562 | u16 _bit_4_0:5; // bit 4:0 | ||
563 | u16 full_duplex:1; // bit 5 | ||
564 | u16 half_duplex:1; // bit 6 | ||
565 | u16 asymmetric:1; // bit 7 | ||
566 | u16 pause:1; // bit 8 | ||
567 | u16 _bit_11_9:3; // bit 11:9 | ||
568 | u16 remote_fault:2; // bit 13:12 | ||
569 | u16 _bit_14:1; // bit 14 | ||
570 | u16 next_page:1; // bit 15 | ||
571 | } bits; | ||
572 | } ANAR_PCS_t, *PANAR_PCS_t; | ||
573 | |||
574 | enum _pcs_anar { | 436 | enum _pcs_anar { |
575 | PCS_ANAR_NEXT_PAGE = 0x8000, | 437 | PCS_ANAR_NEXT_PAGE = 0x8000, |
576 | PCS_ANAR_REMOTE_FAULT = 0x3000, | 438 | PCS_ANAR_REMOTE_FAULT = 0x3000, |
@@ -580,21 +442,6 @@ enum _pcs_anar { | |||
580 | PCS_ANAR_FULL_DUPLEX = 0x0020, | 442 | PCS_ANAR_FULL_DUPLEX = 0x0020, |
581 | }; | 443 | }; |
582 | /* PCS ANLPAR */ | 444 | /* PCS ANLPAR */ |
583 | typedef union t_PCS_ANLPAR { | ||
584 | u16 image; | ||
585 | struct { | ||
586 | u16 _bit_4_0:5; // bit 4:0 | ||
587 | u16 full_duplex:1; // bit 5 | ||
588 | u16 half_duplex:1; // bit 6 | ||
589 | u16 asymmetric:1; // bit 7 | ||
590 | u16 pause:1; // bit 8 | ||
591 | u16 _bit_11_9:3; // bit 11:9 | ||
592 | u16 remote_fault:2; // bit 13:12 | ||
593 | u16 _bit_14:1; // bit 14 | ||
594 | u16 next_page:1; // bit 15 | ||
595 | } bits; | ||
596 | } ANLPAR_PCS_t, *PANLPAR_PCS_t; | ||
597 | |||
598 | enum _pcs_anlpar { | 445 | enum _pcs_anlpar { |
599 | PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE, | 446 | PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE, |
600 | PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT, | 447 | PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT, |
@@ -633,9 +480,9 @@ struct mii_data { | |||
633 | 480 | ||
634 | /* The Rx and Tx buffer descriptors. */ | 481 | /* The Rx and Tx buffer descriptors. */ |
635 | struct netdev_desc { | 482 | struct netdev_desc { |
636 | u64 next_desc; | 483 | __le64 next_desc; |
637 | u64 status; | 484 | __le64 status; |
638 | u64 fraginfo; | 485 | __le64 fraginfo; |
639 | }; | 486 | }; |
640 | 487 | ||
641 | #define PRIV_ALIGN 15 /* Required alignment mask */ | 488 | #define PRIV_ALIGN 15 /* Required alignment mask */ |