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path: root/drivers/net/dl2k.c
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Diffstat (limited to 'drivers/net/dl2k.c')
-rw-r--r--drivers/net/dl2k.c215
1 files changed, 107 insertions, 108 deletions
diff --git a/drivers/net/dl2k.c b/drivers/net/dl2k.c
index 47cce9cad30f..e233d04a2132 100644
--- a/drivers/net/dl2k.c
+++ b/drivers/net/dl2k.c
@@ -1316,9 +1316,10 @@ rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1316 ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x", 1316 ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
1317 i, 1317 i,
1318 (u32) (np->tx_ring_dma + i * sizeof (*desc)), 1318 (u32) (np->tx_ring_dma + i * sizeof (*desc)),
1319 (u32) desc->next_desc, 1319 (u32)le64_to_cpu(desc->next_desc),
1320 (u32) desc->status, (u32) (desc->fraginfo >> 32), 1320 (u32)le64_to_cpu(desc->status),
1321 (u32) desc->fraginfo); 1321 (u32)(le64_to_cpu(desc->fraginfo) >> 32),
1322 (u32)le64_to_cpu(desc->fraginfo));
1322 printk ("\n"); 1323 printk ("\n");
1323 } 1324 }
1324 printk ("\n"); 1325 printk ("\n");
@@ -1435,7 +1436,7 @@ mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1435static int 1436static int
1436mii_wait_link (struct net_device *dev, int wait) 1437mii_wait_link (struct net_device *dev, int wait)
1437{ 1438{
1438 BMSR_t bmsr; 1439 __u16 bmsr;
1439 int phy_addr; 1440 int phy_addr;
1440 struct netdev_private *np; 1441 struct netdev_private *np;
1441 1442
@@ -1443,8 +1444,8 @@ mii_wait_link (struct net_device *dev, int wait)
1443 phy_addr = np->phy_addr; 1444 phy_addr = np->phy_addr;
1444 1445
1445 do { 1446 do {
1446 bmsr.image = mii_read (dev, phy_addr, MII_BMSR); 1447 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1447 if (bmsr.bits.link_status) 1448 if (bmsr & MII_BMSR_LINK_STATUS)
1448 return 0; 1449 return 0;
1449 mdelay (1); 1450 mdelay (1);
1450 } while (--wait > 0); 1451 } while (--wait > 0);
@@ -1453,70 +1454,72 @@ mii_wait_link (struct net_device *dev, int wait)
1453static int 1454static int
1454mii_get_media (struct net_device *dev) 1455mii_get_media (struct net_device *dev)
1455{ 1456{
1456 ANAR_t negotiate; 1457 __u16 negotiate;
1457 BMSR_t bmsr; 1458 __u16 bmsr;
1458 BMCR_t bmcr; 1459 __u16 mscr;
1459 MSCR_t mscr; 1460 __u16 mssr;
1460 MSSR_t mssr;
1461 int phy_addr; 1461 int phy_addr;
1462 struct netdev_private *np; 1462 struct netdev_private *np;
1463 1463
1464 np = netdev_priv(dev); 1464 np = netdev_priv(dev);
1465 phy_addr = np->phy_addr; 1465 phy_addr = np->phy_addr;
1466 1466
1467 bmsr.image = mii_read (dev, phy_addr, MII_BMSR); 1467 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1468 if (np->an_enable) { 1468 if (np->an_enable) {
1469 if (!bmsr.bits.an_complete) { 1469 if (!(bmsr & MII_BMSR_AN_COMPLETE)) {
1470 /* Auto-Negotiation not completed */ 1470 /* Auto-Negotiation not completed */
1471 return -1; 1471 return -1;
1472 } 1472 }
1473 negotiate.image = mii_read (dev, phy_addr, MII_ANAR) & 1473 negotiate = mii_read (dev, phy_addr, MII_ANAR) &
1474 mii_read (dev, phy_addr, MII_ANLPAR); 1474 mii_read (dev, phy_addr, MII_ANLPAR);
1475 mscr.image = mii_read (dev, phy_addr, MII_MSCR); 1475 mscr = mii_read (dev, phy_addr, MII_MSCR);
1476 mssr.image = mii_read (dev, phy_addr, MII_MSSR); 1476 mssr = mii_read (dev, phy_addr, MII_MSSR);
1477 if (mscr.bits.media_1000BT_FD & mssr.bits.lp_1000BT_FD) { 1477 if (mscr & MII_MSCR_1000BT_FD && mssr & MII_MSSR_LP_1000BT_FD) {
1478 np->speed = 1000; 1478 np->speed = 1000;
1479 np->full_duplex = 1; 1479 np->full_duplex = 1;
1480 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n"); 1480 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1481 } else if (mscr.bits.media_1000BT_HD & mssr.bits.lp_1000BT_HD) { 1481 } else if (mscr & MII_MSCR_1000BT_HD && mssr & MII_MSSR_LP_1000BT_HD) {
1482 np->speed = 1000; 1482 np->speed = 1000;
1483 np->full_duplex = 0; 1483 np->full_duplex = 0;
1484 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n"); 1484 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1485 } else if (negotiate.bits.media_100BX_FD) { 1485 } else if (negotiate & MII_ANAR_100BX_FD) {
1486 np->speed = 100; 1486 np->speed = 100;
1487 np->full_duplex = 1; 1487 np->full_duplex = 1;
1488 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n"); 1488 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1489 } else if (negotiate.bits.media_100BX_HD) { 1489 } else if (negotiate & MII_ANAR_100BX_HD) {
1490 np->speed = 100; 1490 np->speed = 100;
1491 np->full_duplex = 0; 1491 np->full_duplex = 0;
1492 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n"); 1492 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1493 } else if (negotiate.bits.media_10BT_FD) { 1493 } else if (negotiate & MII_ANAR_10BT_FD) {
1494 np->speed = 10; 1494 np->speed = 10;
1495 np->full_duplex = 1; 1495 np->full_duplex = 1;
1496 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n"); 1496 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1497 } else if (negotiate.bits.media_10BT_HD) { 1497 } else if (negotiate & MII_ANAR_10BT_HD) {
1498 np->speed = 10; 1498 np->speed = 10;
1499 np->full_duplex = 0; 1499 np->full_duplex = 0;
1500 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n"); 1500 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1501 } 1501 }
1502 if (negotiate.bits.pause) { 1502 if (negotiate & MII_ANAR_PAUSE) {
1503 np->tx_flow &= 1; 1503 np->tx_flow &= 1;
1504 np->rx_flow &= 1; 1504 np->rx_flow &= 1;
1505 } else if (negotiate.bits.asymmetric) { 1505 } else if (negotiate & MII_ANAR_ASYMMETRIC) {
1506 np->tx_flow = 0; 1506 np->tx_flow = 0;
1507 np->rx_flow &= 1; 1507 np->rx_flow &= 1;
1508 } 1508 }
1509 /* else tx_flow, rx_flow = user select */ 1509 /* else tx_flow, rx_flow = user select */
1510 } else { 1510 } else {
1511 bmcr.image = mii_read (dev, phy_addr, MII_BMCR); 1511 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1512 if (bmcr.bits.speed100 == 1 && bmcr.bits.speed1000 == 0) { 1512 switch (bmcr & (MII_BMCR_SPEED_100 | MII_BMCR_SPEED_1000)) {
1513 case MII_BMCR_SPEED_1000:
1514 printk (KERN_INFO "Operating at 1000 Mbps, ");
1515 break;
1516 case MII_BMCR_SPEED_100:
1513 printk (KERN_INFO "Operating at 100 Mbps, "); 1517 printk (KERN_INFO "Operating at 100 Mbps, ");
1514 } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 0) { 1518 break;
1519 case 0:
1515 printk (KERN_INFO "Operating at 10 Mbps, "); 1520 printk (KERN_INFO "Operating at 10 Mbps, ");
1516 } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 1) {
1517 printk (KERN_INFO "Operating at 1000 Mbps, ");
1518 } 1521 }
1519 if (bmcr.bits.duplex_mode) { 1522 if (bmcr & MII_BMCR_DUPLEX_MODE) {
1520 printk ("Full duplex\n"); 1523 printk ("Full duplex\n");
1521 } else { 1524 } else {
1522 printk ("Half duplex\n"); 1525 printk ("Half duplex\n");
@@ -1537,10 +1540,10 @@ mii_get_media (struct net_device *dev)
1537static int 1540static int
1538mii_set_media (struct net_device *dev) 1541mii_set_media (struct net_device *dev)
1539{ 1542{
1540 PHY_SCR_t pscr; 1543 __u16 pscr;
1541 BMCR_t bmcr; 1544 __u16 bmcr;
1542 BMSR_t bmsr; 1545 __u16 bmsr;
1543 ANAR_t anar; 1546 __u16 anar;
1544 int phy_addr; 1547 int phy_addr;
1545 struct netdev_private *np; 1548 struct netdev_private *np;
1546 np = netdev_priv(dev); 1549 np = netdev_priv(dev);
@@ -1549,76 +1552,77 @@ mii_set_media (struct net_device *dev)
1549 /* Does user set speed? */ 1552 /* Does user set speed? */
1550 if (np->an_enable) { 1553 if (np->an_enable) {
1551 /* Advertise capabilities */ 1554 /* Advertise capabilities */
1552 bmsr.image = mii_read (dev, phy_addr, MII_BMSR); 1555 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1553 anar.image = mii_read (dev, phy_addr, MII_ANAR); 1556 anar = mii_read (dev, phy_addr, MII_ANAR) &
1554 anar.bits.media_100BX_FD = bmsr.bits.media_100BX_FD; 1557 ~MII_ANAR_100BX_FD &
1555 anar.bits.media_100BX_HD = bmsr.bits.media_100BX_HD; 1558 ~MII_ANAR_100BX_HD &
1556 anar.bits.media_100BT4 = bmsr.bits.media_100BT4; 1559 ~MII_ANAR_100BT4 &
1557 anar.bits.media_10BT_FD = bmsr.bits.media_10BT_FD; 1560 ~MII_ANAR_10BT_FD &
1558 anar.bits.media_10BT_HD = bmsr.bits.media_10BT_HD; 1561 ~MII_ANAR_10BT_HD;
1559 anar.bits.pause = 1; 1562 if (bmsr & MII_BMSR_100BX_FD)
1560 anar.bits.asymmetric = 1; 1563 anar |= MII_ANAR_100BX_FD;
1561 mii_write (dev, phy_addr, MII_ANAR, anar.image); 1564 if (bmsr & MII_BMSR_100BX_HD)
1565 anar |= MII_ANAR_100BX_HD;
1566 if (bmsr & MII_BMSR_100BT4)
1567 anar |= MII_ANAR_100BT4;
1568 if (bmsr & MII_BMSR_10BT_FD)
1569 anar |= MII_ANAR_10BT_FD;
1570 if (bmsr & MII_BMSR_10BT_HD)
1571 anar |= MII_ANAR_10BT_HD;
1572 anar |= MII_ANAR_PAUSE | MII_ANAR_ASYMMETRIC;
1573 mii_write (dev, phy_addr, MII_ANAR, anar);
1562 1574
1563 /* Enable Auto crossover */ 1575 /* Enable Auto crossover */
1564 pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR); 1576 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1565 pscr.bits.mdi_crossover_mode = 3; /* 11'b */ 1577 pscr |= 3 << 5; /* 11'b */
1566 mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image); 1578 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1567 1579
1568 /* Soft reset PHY */ 1580 /* Soft reset PHY */
1569 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET); 1581 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1570 bmcr.image = 0; 1582 bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN | MII_BMCR_RESET;
1571 bmcr.bits.an_enable = 1; 1583 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1572 bmcr.bits.restart_an = 1;
1573 bmcr.bits.reset = 1;
1574 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1575 mdelay(1); 1584 mdelay(1);
1576 } else { 1585 } else {
1577 /* Force speed setting */ 1586 /* Force speed setting */
1578 /* 1) Disable Auto crossover */ 1587 /* 1) Disable Auto crossover */
1579 pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR); 1588 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1580 pscr.bits.mdi_crossover_mode = 0; 1589 pscr &= ~(3 << 5);
1581 mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image); 1590 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1582 1591
1583 /* 2) PHY Reset */ 1592 /* 2) PHY Reset */
1584 bmcr.image = mii_read (dev, phy_addr, MII_BMCR); 1593 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1585 bmcr.bits.reset = 1; 1594 bmcr |= MII_BMCR_RESET;
1586 mii_write (dev, phy_addr, MII_BMCR, bmcr.image); 1595 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1587 1596
1588 /* 3) Power Down */ 1597 /* 3) Power Down */
1589 bmcr.image = 0x1940; /* must be 0x1940 */ 1598 bmcr = 0x1940; /* must be 0x1940 */
1590 mii_write (dev, phy_addr, MII_BMCR, bmcr.image); 1599 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1591 mdelay (100); /* wait a certain time */ 1600 mdelay (100); /* wait a certain time */
1592 1601
1593 /* 4) Advertise nothing */ 1602 /* 4) Advertise nothing */
1594 mii_write (dev, phy_addr, MII_ANAR, 0); 1603 mii_write (dev, phy_addr, MII_ANAR, 0);
1595 1604
1596 /* 5) Set media and Power Up */ 1605 /* 5) Set media and Power Up */
1597 bmcr.image = 0; 1606 bmcr = MII_BMCR_POWER_DOWN;
1598 bmcr.bits.power_down = 1;
1599 if (np->speed == 100) { 1607 if (np->speed == 100) {
1600 bmcr.bits.speed100 = 1; 1608 bmcr |= MII_BMCR_SPEED_100;
1601 bmcr.bits.speed1000 = 0;
1602 printk (KERN_INFO "Manual 100 Mbps, "); 1609 printk (KERN_INFO "Manual 100 Mbps, ");
1603 } else if (np->speed == 10) { 1610 } else if (np->speed == 10) {
1604 bmcr.bits.speed100 = 0;
1605 bmcr.bits.speed1000 = 0;
1606 printk (KERN_INFO "Manual 10 Mbps, "); 1611 printk (KERN_INFO "Manual 10 Mbps, ");
1607 } 1612 }
1608 if (np->full_duplex) { 1613 if (np->full_duplex) {
1609 bmcr.bits.duplex_mode = 1; 1614 bmcr |= MII_BMCR_DUPLEX_MODE;
1610 printk ("Full duplex\n"); 1615 printk ("Full duplex\n");
1611 } else { 1616 } else {
1612 bmcr.bits.duplex_mode = 0;
1613 printk ("Half duplex\n"); 1617 printk ("Half duplex\n");
1614 } 1618 }
1615#if 0 1619#if 0
1616 /* Set 1000BaseT Master/Slave setting */ 1620 /* Set 1000BaseT Master/Slave setting */
1617 mscr.image = mii_read (dev, phy_addr, MII_MSCR); 1621 mscr = mii_read (dev, phy_addr, MII_MSCR);
1618 mscr.bits.cfg_enable = 1; 1622 mscr |= MII_MSCR_CFG_ENABLE;
1619 mscr.bits.cfg_value = 0; 1623 mscr &= ~MII_MSCR_CFG_VALUE = 0;
1620#endif 1624#endif
1621 mii_write (dev, phy_addr, MII_BMCR, bmcr.image); 1625 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1622 mdelay(10); 1626 mdelay(10);
1623 } 1627 }
1624 return 0; 1628 return 0;
@@ -1627,43 +1631,42 @@ mii_set_media (struct net_device *dev)
1627static int 1631static int
1628mii_get_media_pcs (struct net_device *dev) 1632mii_get_media_pcs (struct net_device *dev)
1629{ 1633{
1630 ANAR_PCS_t negotiate; 1634 __u16 negotiate;
1631 BMSR_t bmsr; 1635 __u16 bmsr;
1632 BMCR_t bmcr;
1633 int phy_addr; 1636 int phy_addr;
1634 struct netdev_private *np; 1637 struct netdev_private *np;
1635 1638
1636 np = netdev_priv(dev); 1639 np = netdev_priv(dev);
1637 phy_addr = np->phy_addr; 1640 phy_addr = np->phy_addr;
1638 1641
1639 bmsr.image = mii_read (dev, phy_addr, PCS_BMSR); 1642 bmsr = mii_read (dev, phy_addr, PCS_BMSR);
1640 if (np->an_enable) { 1643 if (np->an_enable) {
1641 if (!bmsr.bits.an_complete) { 1644 if (!(bmsr & MII_BMSR_AN_COMPLETE)) {
1642 /* Auto-Negotiation not completed */ 1645 /* Auto-Negotiation not completed */
1643 return -1; 1646 return -1;
1644 } 1647 }
1645 negotiate.image = mii_read (dev, phy_addr, PCS_ANAR) & 1648 negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
1646 mii_read (dev, phy_addr, PCS_ANLPAR); 1649 mii_read (dev, phy_addr, PCS_ANLPAR);
1647 np->speed = 1000; 1650 np->speed = 1000;
1648 if (negotiate.bits.full_duplex) { 1651 if (negotiate & PCS_ANAR_FULL_DUPLEX) {
1649 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n"); 1652 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1650 np->full_duplex = 1; 1653 np->full_duplex = 1;
1651 } else { 1654 } else {
1652 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n"); 1655 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1653 np->full_duplex = 0; 1656 np->full_duplex = 0;
1654 } 1657 }
1655 if (negotiate.bits.pause) { 1658 if (negotiate & PCS_ANAR_PAUSE) {
1656 np->tx_flow &= 1; 1659 np->tx_flow &= 1;
1657 np->rx_flow &= 1; 1660 np->rx_flow &= 1;
1658 } else if (negotiate.bits.asymmetric) { 1661 } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
1659 np->tx_flow = 0; 1662 np->tx_flow = 0;
1660 np->rx_flow &= 1; 1663 np->rx_flow &= 1;
1661 } 1664 }
1662 /* else tx_flow, rx_flow = user select */ 1665 /* else tx_flow, rx_flow = user select */
1663 } else { 1666 } else {
1664 bmcr.image = mii_read (dev, phy_addr, PCS_BMCR); 1667 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
1665 printk (KERN_INFO "Operating at 1000 Mbps, "); 1668 printk (KERN_INFO "Operating at 1000 Mbps, ");
1666 if (bmcr.bits.duplex_mode) { 1669 if (bmcr & MII_BMCR_DUPLEX_MODE) {
1667 printk ("Full duplex\n"); 1670 printk ("Full duplex\n");
1668 } else { 1671 } else {
1669 printk ("Half duplex\n"); 1672 printk ("Half duplex\n");
@@ -1684,9 +1687,9 @@ mii_get_media_pcs (struct net_device *dev)
1684static int 1687static int
1685mii_set_media_pcs (struct net_device *dev) 1688mii_set_media_pcs (struct net_device *dev)
1686{ 1689{
1687 BMCR_t bmcr; 1690 __u16 bmcr;
1688 ESR_t esr; 1691 __u16 esr;
1689 ANAR_PCS_t anar; 1692 __u16 anar;
1690 int phy_addr; 1693 int phy_addr;
1691 struct netdev_private *np; 1694 struct netdev_private *np;
1692 np = netdev_priv(dev); 1695 np = netdev_priv(dev);
@@ -1695,41 +1698,37 @@ mii_set_media_pcs (struct net_device *dev)
1695 /* Auto-Negotiation? */ 1698 /* Auto-Negotiation? */
1696 if (np->an_enable) { 1699 if (np->an_enable) {
1697 /* Advertise capabilities */ 1700 /* Advertise capabilities */
1698 esr.image = mii_read (dev, phy_addr, PCS_ESR); 1701 esr = mii_read (dev, phy_addr, PCS_ESR);
1699 anar.image = mii_read (dev, phy_addr, MII_ANAR); 1702 anar = mii_read (dev, phy_addr, MII_ANAR) &
1700 anar.bits.half_duplex = 1703 ~PCS_ANAR_HALF_DUPLEX &
1701 esr.bits.media_1000BT_HD | esr.bits.media_1000BX_HD; 1704 ~PCS_ANAR_FULL_DUPLEX;
1702 anar.bits.full_duplex = 1705 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
1703 esr.bits.media_1000BT_FD | esr.bits.media_1000BX_FD; 1706 anar |= PCS_ANAR_HALF_DUPLEX;
1704 anar.bits.pause = 1; 1707 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
1705 anar.bits.asymmetric = 1; 1708 anar |= PCS_ANAR_FULL_DUPLEX;
1706 mii_write (dev, phy_addr, MII_ANAR, anar.image); 1709 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
1710 mii_write (dev, phy_addr, MII_ANAR, anar);
1707 1711
1708 /* Soft reset PHY */ 1712 /* Soft reset PHY */
1709 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET); 1713 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1710 bmcr.image = 0; 1714 bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN |
1711 bmcr.bits.an_enable = 1; 1715 MII_BMCR_RESET;
1712 bmcr.bits.restart_an = 1; 1716 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1713 bmcr.bits.reset = 1;
1714 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1715 mdelay(1); 1717 mdelay(1);
1716 } else { 1718 } else {
1717 /* Force speed setting */ 1719 /* Force speed setting */
1718 /* PHY Reset */ 1720 /* PHY Reset */
1719 bmcr.image = 0; 1721 bmcr = MII_BMCR_RESET;
1720 bmcr.bits.reset = 1; 1722 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1721 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1722 mdelay(10); 1723 mdelay(10);
1723 bmcr.image = 0;
1724 bmcr.bits.an_enable = 0;
1725 if (np->full_duplex) { 1724 if (np->full_duplex) {
1726 bmcr.bits.duplex_mode = 1; 1725 bmcr = MII_BMCR_DUPLEX_MODE;
1727 printk (KERN_INFO "Manual full duplex\n"); 1726 printk (KERN_INFO "Manual full duplex\n");
1728 } else { 1727 } else {
1729 bmcr.bits.duplex_mode = 0; 1728 bmcr = 0;
1730 printk (KERN_INFO "Manual half duplex\n"); 1729 printk (KERN_INFO "Manual half duplex\n");
1731 } 1730 }
1732 mii_write (dev, phy_addr, MII_BMCR, bmcr.image); 1731 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1733 mdelay(10); 1732 mdelay(10);
1734 1733
1735 /* Advertise nothing */ 1734 /* Advertise nothing */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-03 00:20:38 -0500