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path: root/drivers/net/davinci_emac.c
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Diffstat (limited to 'drivers/net/davinci_emac.c')
-rw-r--r--drivers/net/davinci_emac.c41
1 files changed, 24 insertions, 17 deletions
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index c735b62baa03..1605bc225b0c 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -464,6 +464,7 @@ struct emac_priv {
464 void __iomem *ctrl_base; 464 void __iomem *ctrl_base;
465 void __iomem *emac_ctrl_ram; 465 void __iomem *emac_ctrl_ram;
466 u32 ctrl_ram_size; 466 u32 ctrl_ram_size;
467 u32 hw_ram_addr;
467 struct emac_txch *txch[EMAC_DEF_MAX_TX_CH]; 468 struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
468 struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH]; 469 struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
469 u32 link; /* 1=link on, 0=link off */ 470 u32 link; /* 1=link on, 0=link off */
@@ -497,11 +498,9 @@ static struct clk *emac_clk;
497static unsigned long emac_bus_frequency; 498static unsigned long emac_bus_frequency;
498static unsigned long mdio_max_freq; 499static unsigned long mdio_max_freq;
499 500
500/* EMAC internal utility function */ 501#define emac_virt_to_phys(addr, priv) \
501static inline u32 emac_virt_to_phys(void __iomem *addr) 502 (((u32 __force)(addr) - (u32 __force)(priv->emac_ctrl_ram)) \
502{ 503 + priv->hw_ram_addr)
503 return (u32 __force) io_v2p(addr);
504}
505 504
506/* Cache macros - Packet buffers would be from skb pool which is cached */ 505/* Cache macros - Packet buffers would be from skb pool which is cached */
507#define EMAC_VIRT_NOCACHE(addr) (addr) 506#define EMAC_VIRT_NOCACHE(addr) (addr)
@@ -1309,7 +1308,7 @@ static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1309 curr_bd = txch->active_queue_head; 1308 curr_bd = txch->active_queue_head;
1310 if (NULL == curr_bd) { 1309 if (NULL == curr_bd) {
1311 emac_write(EMAC_TXCP(ch), 1310 emac_write(EMAC_TXCP(ch),
1312 emac_virt_to_phys(txch->last_hw_bdprocessed)); 1311 emac_virt_to_phys(txch->last_hw_bdprocessed, priv));
1313 txch->no_active_pkts++; 1312 txch->no_active_pkts++;
1314 spin_unlock_irqrestore(&priv->tx_lock, flags); 1313 spin_unlock_irqrestore(&priv->tx_lock, flags);
1315 return 0; 1314 return 0;
@@ -1319,7 +1318,7 @@ static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1319 while ((curr_bd) && 1318 while ((curr_bd) &&
1320 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && 1319 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1321 (pkts_processed < budget)) { 1320 (pkts_processed < budget)) {
1322 emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd)); 1321 emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd, priv));
1323 txch->active_queue_head = curr_bd->next; 1322 txch->active_queue_head = curr_bd->next;
1324 if (frame_status & EMAC_CPPI_EOQ_BIT) { 1323 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1325 if (curr_bd->next) { /* misqueued packet */ 1324 if (curr_bd->next) { /* misqueued packet */
@@ -1406,7 +1405,7 @@ static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch)
1406 txch->active_queue_tail = curr_bd; 1405 txch->active_queue_tail = curr_bd;
1407 if (1 != txch->queue_active) { 1406 if (1 != txch->queue_active) {
1408 emac_write(EMAC_TXHDP(ch), 1407 emac_write(EMAC_TXHDP(ch),
1409 emac_virt_to_phys(curr_bd)); 1408 emac_virt_to_phys(curr_bd, priv));
1410 txch->queue_active = 1; 1409 txch->queue_active = 1;
1411 } 1410 }
1412 ++txch->queue_reinit; 1411 ++txch->queue_reinit;
@@ -1418,10 +1417,11 @@ static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch)
1418 tail_bd->next = curr_bd; 1417 tail_bd->next = curr_bd;
1419 txch->active_queue_tail = curr_bd; 1418 txch->active_queue_tail = curr_bd;
1420 tail_bd = EMAC_VIRT_NOCACHE(tail_bd); 1419 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1421 tail_bd->h_next = (int)emac_virt_to_phys(curr_bd); 1420 tail_bd->h_next = (int)emac_virt_to_phys(curr_bd, priv);
1422 frame_status = tail_bd->mode; 1421 frame_status = tail_bd->mode;
1423 if (frame_status & EMAC_CPPI_EOQ_BIT) { 1422 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1424 emac_write(EMAC_TXHDP(ch), emac_virt_to_phys(curr_bd)); 1423 emac_write(EMAC_TXHDP(ch),
1424 emac_virt_to_phys(curr_bd, priv));
1425 frame_status &= ~(EMAC_CPPI_EOQ_BIT); 1425 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1426 tail_bd->mode = frame_status; 1426 tail_bd->mode = frame_status;
1427 ++txch->end_of_queue_add; 1427 ++txch->end_of_queue_add;
@@ -1611,7 +1611,8 @@ static int emac_init_rxch(struct emac_priv *priv, u32 ch, char *param)
1611 } 1611 }
1612 1612
1613 /* populate the hardware descriptor */ 1613 /* populate the hardware descriptor */
1614 curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head); 1614 curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head,
1615 priv);
1615 /* FIXME buff_ptr = dma_map_single(... data_ptr ...) */ 1616 /* FIXME buff_ptr = dma_map_single(... data_ptr ...) */
1616 curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr); 1617 curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr);
1617 curr_bd->off_b_len = rxch->buf_size; 1618 curr_bd->off_b_len = rxch->buf_size;
@@ -1886,7 +1887,7 @@ static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
1886 rxch->active_queue_tail = curr_bd; 1887 rxch->active_queue_tail = curr_bd;
1887 if (0 != rxch->queue_active) { 1888 if (0 != rxch->queue_active) {
1888 emac_write(EMAC_RXHDP(ch), 1889 emac_write(EMAC_RXHDP(ch),
1889 emac_virt_to_phys(rxch->active_queue_head)); 1890 emac_virt_to_phys(rxch->active_queue_head, priv));
1890 rxch->queue_active = 1; 1891 rxch->queue_active = 1;
1891 } 1892 }
1892 } else { 1893 } else {
@@ -1897,11 +1898,11 @@ static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
1897 rxch->active_queue_tail = curr_bd; 1898 rxch->active_queue_tail = curr_bd;
1898 tail_bd->next = curr_bd; 1899 tail_bd->next = curr_bd;
1899 tail_bd = EMAC_VIRT_NOCACHE(tail_bd); 1900 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1900 tail_bd->h_next = emac_virt_to_phys(curr_bd); 1901 tail_bd->h_next = emac_virt_to_phys(curr_bd, priv);
1901 frame_status = tail_bd->mode; 1902 frame_status = tail_bd->mode;
1902 if (frame_status & EMAC_CPPI_EOQ_BIT) { 1903 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1903 emac_write(EMAC_RXHDP(ch), 1904 emac_write(EMAC_RXHDP(ch),
1904 emac_virt_to_phys(curr_bd)); 1905 emac_virt_to_phys(curr_bd, priv));
1905 frame_status &= ~(EMAC_CPPI_EOQ_BIT); 1906 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1906 tail_bd->mode = frame_status; 1907 tail_bd->mode = frame_status;
1907 ++rxch->end_of_queue_add; 1908 ++rxch->end_of_queue_add;
@@ -1994,7 +1995,7 @@ static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1994 curr_pkt->num_bufs = 1; 1995 curr_pkt->num_bufs = 1;
1995 curr_pkt->pkt_length = 1996 curr_pkt->pkt_length =
1996 (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK); 1997 (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK);
1997 emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd)); 1998 emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd, priv));
1998 ++rxch->processed_bd; 1999 ++rxch->processed_bd;
1999 last_bd = curr_bd; 2000 last_bd = curr_bd;
2000 curr_bd = last_bd->next; 2001 curr_bd = last_bd->next;
@@ -2005,7 +2006,7 @@ static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
2005 if (curr_bd) { 2006 if (curr_bd) {
2006 ++rxch->mis_queued_packets; 2007 ++rxch->mis_queued_packets;
2007 emac_write(EMAC_RXHDP(ch), 2008 emac_write(EMAC_RXHDP(ch),
2008 emac_virt_to_phys(curr_bd)); 2009 emac_virt_to_phys(curr_bd, priv));
2009 } else { 2010 } else {
2010 ++rxch->end_of_queue; 2011 ++rxch->end_of_queue;
2011 rxch->queue_active = 0; 2012 rxch->queue_active = 0;
@@ -2106,7 +2107,7 @@ static int emac_hw_enable(struct emac_priv *priv)
2106 emac_write(EMAC_RXINTMASKSET, BIT(ch)); 2107 emac_write(EMAC_RXINTMASKSET, BIT(ch));
2107 rxch->queue_active = 1; 2108 rxch->queue_active = 1;
2108 emac_write(EMAC_RXHDP(ch), 2109 emac_write(EMAC_RXHDP(ch),
2109 emac_virt_to_phys(rxch->active_queue_head)); 2110 emac_virt_to_phys(rxch->active_queue_head, priv));
2110 } 2111 }
2111 2112
2112 /* Enable MII */ 2113 /* Enable MII */
@@ -2702,6 +2703,12 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
2702 priv->ctrl_ram_size = pdata->ctrl_ram_size; 2703 priv->ctrl_ram_size = pdata->ctrl_ram_size;
2703 priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset; 2704 priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset;
2704 2705
2706 if (pdata->hw_ram_addr)
2707 priv->hw_ram_addr = pdata->hw_ram_addr;
2708 else
2709 priv->hw_ram_addr = (u32 __force)res->start +
2710 pdata->ctrl_ram_offset;
2711
2705 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 2712 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2706 if (!res) { 2713 if (!res) {
2707 dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n"); 2714 dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n");