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-rw-r--r--drivers/net/cxgb4/Makefile7
-rw-r--r--drivers/net/cxgb4/cxgb4.h739
-rw-r--r--drivers/net/cxgb4/cxgb4_main.c3401
-rw-r--r--drivers/net/cxgb4/cxgb4_uld.h239
-rw-r--r--drivers/net/cxgb4/l2t.c624
-rw-r--r--drivers/net/cxgb4/l2t.h110
-rw-r--r--drivers/net/cxgb4/sge.c2436
-rw-r--r--drivers/net/cxgb4/t4_hw.c3147
-rw-r--r--drivers/net/cxgb4/t4_hw.h100
-rw-r--r--drivers/net/cxgb4/t4_msg.h665
-rw-r--r--drivers/net/cxgb4/t4_regs.h878
-rw-r--r--drivers/net/cxgb4/t4fw_api.h1580
12 files changed, 13926 insertions, 0 deletions
diff --git a/drivers/net/cxgb4/Makefile b/drivers/net/cxgb4/Makefile
new file mode 100644
index 000000000000..498667487f52
--- /dev/null
+++ b/drivers/net/cxgb4/Makefile
@@ -0,0 +1,7 @@
1#
2# Chelsio T4 driver
3#
4
5obj-$(CONFIG_CHELSIO_T4) += cxgb4.o
6
7cxgb4-objs := cxgb4_main.o l2t.o t4_hw.o sge.o
diff --git a/drivers/net/cxgb4/cxgb4.h b/drivers/net/cxgb4/cxgb4.h
new file mode 100644
index 000000000000..8856a75fcc94
--- /dev/null
+++ b/drivers/net/cxgb4/cxgb4.h
@@ -0,0 +1,739 @@
1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
38#include <linux/bitops.h>
39#include <linux/cache.h>
40#include <linux/interrupt.h>
41#include <linux/list.h>
42#include <linux/netdevice.h>
43#include <linux/pci.h>
44#include <linux/spinlock.h>
45#include <linux/timer.h>
46#include <asm/io.h>
47#include "cxgb4_uld.h"
48#include "t4_hw.h"
49
50#define FW_VERSION_MAJOR 1
51#define FW_VERSION_MINOR 1
52#define FW_VERSION_MICRO 0
53
54enum {
55 MAX_NPORTS = 4, /* max # of ports */
56 SERNUM_LEN = 24, /* Serial # length */
57 EC_LEN = 16, /* E/C length */
58 ID_LEN = 16, /* ID length */
59};
60
61enum {
62 MEM_EDC0,
63 MEM_EDC1,
64 MEM_MC
65};
66
67enum dev_master {
68 MASTER_CANT,
69 MASTER_MAY,
70 MASTER_MUST
71};
72
73enum dev_state {
74 DEV_STATE_UNINIT,
75 DEV_STATE_INIT,
76 DEV_STATE_ERR
77};
78
79enum {
80 PAUSE_RX = 1 << 0,
81 PAUSE_TX = 1 << 1,
82 PAUSE_AUTONEG = 1 << 2
83};
84
85struct port_stats {
86 u64 tx_octets; /* total # of octets in good frames */
87 u64 tx_frames; /* all good frames */
88 u64 tx_bcast_frames; /* all broadcast frames */
89 u64 tx_mcast_frames; /* all multicast frames */
90 u64 tx_ucast_frames; /* all unicast frames */
91 u64 tx_error_frames; /* all error frames */
92
93 u64 tx_frames_64; /* # of Tx frames in a particular range */
94 u64 tx_frames_65_127;
95 u64 tx_frames_128_255;
96 u64 tx_frames_256_511;
97 u64 tx_frames_512_1023;
98 u64 tx_frames_1024_1518;
99 u64 tx_frames_1519_max;
100
101 u64 tx_drop; /* # of dropped Tx frames */
102 u64 tx_pause; /* # of transmitted pause frames */
103 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
104 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
105 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
106 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
107 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
108 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
109 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
110 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
111
112 u64 rx_octets; /* total # of octets in good frames */
113 u64 rx_frames; /* all good frames */
114 u64 rx_bcast_frames; /* all broadcast frames */
115 u64 rx_mcast_frames; /* all multicast frames */
116 u64 rx_ucast_frames; /* all unicast frames */
117 u64 rx_too_long; /* # of frames exceeding MTU */
118 u64 rx_jabber; /* # of jabber frames */
119 u64 rx_fcs_err; /* # of received frames with bad FCS */
120 u64 rx_len_err; /* # of received frames with length error */
121 u64 rx_symbol_err; /* symbol errors */
122 u64 rx_runt; /* # of short frames */
123
124 u64 rx_frames_64; /* # of Rx frames in a particular range */
125 u64 rx_frames_65_127;
126 u64 rx_frames_128_255;
127 u64 rx_frames_256_511;
128 u64 rx_frames_512_1023;
129 u64 rx_frames_1024_1518;
130 u64 rx_frames_1519_max;
131
132 u64 rx_pause; /* # of received pause frames */
133 u64 rx_ppp0; /* # of received PPP prio 0 frames */
134 u64 rx_ppp1; /* # of received PPP prio 1 frames */
135 u64 rx_ppp2; /* # of received PPP prio 2 frames */
136 u64 rx_ppp3; /* # of received PPP prio 3 frames */
137 u64 rx_ppp4; /* # of received PPP prio 4 frames */
138 u64 rx_ppp5; /* # of received PPP prio 5 frames */
139 u64 rx_ppp6; /* # of received PPP prio 6 frames */
140 u64 rx_ppp7; /* # of received PPP prio 7 frames */
141
142 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
143 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
144 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
145 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
146 u64 rx_trunc0; /* buffer-group 0 truncated packets */
147 u64 rx_trunc1; /* buffer-group 1 truncated packets */
148 u64 rx_trunc2; /* buffer-group 2 truncated packets */
149 u64 rx_trunc3; /* buffer-group 3 truncated packets */
150};
151
152struct lb_port_stats {
153 u64 octets;
154 u64 frames;
155 u64 bcast_frames;
156 u64 mcast_frames;
157 u64 ucast_frames;
158 u64 error_frames;
159
160 u64 frames_64;
161 u64 frames_65_127;
162 u64 frames_128_255;
163 u64 frames_256_511;
164 u64 frames_512_1023;
165 u64 frames_1024_1518;
166 u64 frames_1519_max;
167
168 u64 drop;
169
170 u64 ovflow0;
171 u64 ovflow1;
172 u64 ovflow2;
173 u64 ovflow3;
174 u64 trunc0;
175 u64 trunc1;
176 u64 trunc2;
177 u64 trunc3;
178};
179
180struct tp_tcp_stats {
181 u32 tcpOutRsts;
182 u64 tcpInSegs;
183 u64 tcpOutSegs;
184 u64 tcpRetransSegs;
185};
186
187struct tp_err_stats {
188 u32 macInErrs[4];
189 u32 hdrInErrs[4];
190 u32 tcpInErrs[4];
191 u32 tnlCongDrops[4];
192 u32 ofldChanDrops[4];
193 u32 tnlTxDrops[4];
194 u32 ofldVlanDrops[4];
195 u32 tcp6InErrs[4];
196 u32 ofldNoNeigh;
197 u32 ofldCongDefer;
198};
199
200struct tp_params {
201 unsigned int ntxchan; /* # of Tx channels */
202 unsigned int tre; /* log2 of core clocks per TP tick */
203};
204
205struct vpd_params {
206 unsigned int cclk;
207 u8 ec[EC_LEN + 1];
208 u8 sn[SERNUM_LEN + 1];
209 u8 id[ID_LEN + 1];
210};
211
212struct pci_params {
213 unsigned char speed;
214 unsigned char width;
215};
216
217struct adapter_params {
218 struct tp_params tp;
219 struct vpd_params vpd;
220 struct pci_params pci;
221
222 unsigned int fw_vers;
223 unsigned int tp_vers;
224 u8 api_vers[7];
225
226 unsigned short mtus[NMTUS];
227 unsigned short a_wnd[NCCTRL_WIN];
228 unsigned short b_wnd[NCCTRL_WIN];
229
230 unsigned char nports; /* # of ethernet ports */
231 unsigned char portvec;
232 unsigned char rev; /* chip revision */
233 unsigned char offload;
234
235 unsigned int ofldq_wr_cred;
236};
237
238struct trace_params {
239 u32 data[TRACE_LEN / 4];
240 u32 mask[TRACE_LEN / 4];
241 unsigned short snap_len;
242 unsigned short min_len;
243 unsigned char skip_ofst;
244 unsigned char skip_len;
245 unsigned char invert;
246 unsigned char port;
247};
248
249struct link_config {
250 unsigned short supported; /* link capabilities */
251 unsigned short advertising; /* advertised capabilities */
252 unsigned short requested_speed; /* speed user has requested */
253 unsigned short speed; /* actual link speed */
254 unsigned char requested_fc; /* flow control user has requested */
255 unsigned char fc; /* actual link flow control */
256 unsigned char autoneg; /* autonegotiating? */
257 unsigned char link_ok; /* link up? */
258};
259
260#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
261
262enum {
263 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
264 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
265 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
266 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
267};
268
269enum {
270 MAX_EGRQ = 128, /* max # of egress queues, including FLs */
271 MAX_INGQ = 64 /* max # of interrupt-capable ingress queues */
272};
273
274struct adapter;
275struct vlan_group;
276struct sge_rspq;
277
278struct port_info {
279 struct adapter *adapter;
280 struct vlan_group *vlan_grp;
281 u16 viid;
282 s16 xact_addr_filt; /* index of exact MAC address filter */
283 u16 rss_size; /* size of VI's RSS table slice */
284 s8 mdio_addr;
285 u8 port_type;
286 u8 mod_type;
287 u8 port_id;
288 u8 tx_chan;
289 u8 lport; /* associated offload logical port */
290 u8 rx_offload; /* CSO, etc */
291 u8 nqsets; /* # of qsets */
292 u8 first_qset; /* index of first qset */
293 struct link_config link_cfg;
294};
295
296/* port_info.rx_offload flags */
297enum {
298 RX_CSO = 1 << 0,
299};
300
301struct dentry;
302struct work_struct;
303
304enum { /* adapter flags */
305 FULL_INIT_DONE = (1 << 0),
306 USING_MSI = (1 << 1),
307 USING_MSIX = (1 << 2),
308 QUEUES_BOUND = (1 << 3),
309 FW_OK = (1 << 4),
310};
311
312struct rx_sw_desc;
313
314struct sge_fl { /* SGE free-buffer queue state */
315 unsigned int avail; /* # of available Rx buffers */
316 unsigned int pend_cred; /* new buffers since last FL DB ring */
317 unsigned int cidx; /* consumer index */
318 unsigned int pidx; /* producer index */
319 unsigned long alloc_failed; /* # of times buffer allocation failed */
320 unsigned long large_alloc_failed;
321 unsigned long starving;
322 /* RO fields */
323 unsigned int cntxt_id; /* SGE context id for the free list */
324 unsigned int size; /* capacity of free list */
325 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
326 __be64 *desc; /* address of HW Rx descriptor ring */
327 dma_addr_t addr; /* bus address of HW ring start */
328};
329
330/* A packet gather list */
331struct pkt_gl {
332 skb_frag_t frags[MAX_SKB_FRAGS];
333 void *va; /* virtual address of first byte */
334 unsigned int nfrags; /* # of fragments */
335 unsigned int tot_len; /* total length of fragments */
336};
337
338typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
339 const struct pkt_gl *gl);
340
341struct sge_rspq { /* state for an SGE response queue */
342 struct napi_struct napi;
343 const __be64 *cur_desc; /* current descriptor in queue */
344 unsigned int cidx; /* consumer index */
345 u8 gen; /* current generation bit */
346 u8 intr_params; /* interrupt holdoff parameters */
347 u8 next_intr_params; /* holdoff params for next interrupt */
348 u8 pktcnt_idx; /* interrupt packet threshold */
349 u8 uld; /* ULD handling this queue */
350 u8 idx; /* queue index within its group */
351 int offset; /* offset into current Rx buffer */
352 u16 cntxt_id; /* SGE context id for the response q */
353 u16 abs_id; /* absolute SGE id for the response q */
354 __be64 *desc; /* address of HW response ring */
355 dma_addr_t phys_addr; /* physical address of the ring */
356 unsigned int iqe_len; /* entry size */
357 unsigned int size; /* capacity of response queue */
358 struct adapter *adap;
359 struct net_device *netdev; /* associated net device */
360 rspq_handler_t handler;
361};
362
363struct sge_eth_stats { /* Ethernet queue statistics */
364 unsigned long pkts; /* # of ethernet packets */
365 unsigned long lro_pkts; /* # of LRO super packets */
366 unsigned long lro_merged; /* # of wire packets merged by LRO */
367 unsigned long rx_cso; /* # of Rx checksum offloads */
368 unsigned long vlan_ex; /* # of Rx VLAN extractions */
369 unsigned long rx_drops; /* # of packets dropped due to no mem */
370};
371
372struct sge_eth_rxq { /* SW Ethernet Rx queue */
373 struct sge_rspq rspq;
374 struct sge_fl fl;
375 struct sge_eth_stats stats;
376} ____cacheline_aligned_in_smp;
377
378struct sge_ofld_stats { /* offload queue statistics */
379 unsigned long pkts; /* # of packets */
380 unsigned long imm; /* # of immediate-data packets */
381 unsigned long an; /* # of asynchronous notifications */
382 unsigned long nomem; /* # of responses deferred due to no mem */
383};
384
385struct sge_ofld_rxq { /* SW offload Rx queue */
386 struct sge_rspq rspq;
387 struct sge_fl fl;
388 struct sge_ofld_stats stats;
389} ____cacheline_aligned_in_smp;
390
391struct tx_desc {
392 __be64 flit[8];
393};
394
395struct tx_sw_desc;
396
397struct sge_txq {
398 unsigned int in_use; /* # of in-use Tx descriptors */
399 unsigned int size; /* # of descriptors */
400 unsigned int cidx; /* SW consumer index */
401 unsigned int pidx; /* producer index */
402 unsigned long stops; /* # of times q has been stopped */
403 unsigned long restarts; /* # of queue restarts */
404 unsigned int cntxt_id; /* SGE context id for the Tx q */
405 struct tx_desc *desc; /* address of HW Tx descriptor ring */
406 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
407 struct sge_qstat *stat; /* queue status entry */
408 dma_addr_t phys_addr; /* physical address of the ring */
409};
410
411struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
412 struct sge_txq q;
413 struct netdev_queue *txq; /* associated netdev TX queue */
414 unsigned long tso; /* # of TSO requests */
415 unsigned long tx_cso; /* # of Tx checksum offloads */
416 unsigned long vlan_ins; /* # of Tx VLAN insertions */
417 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
418} ____cacheline_aligned_in_smp;
419
420struct sge_ofld_txq { /* state for an SGE offload Tx queue */
421 struct sge_txq q;
422 struct adapter *adap;
423 struct sk_buff_head sendq; /* list of backpressured packets */
424 struct tasklet_struct qresume_tsk; /* restarts the queue */
425 u8 full; /* the Tx ring is full */
426 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
427} ____cacheline_aligned_in_smp;
428
429struct sge_ctrl_txq { /* state for an SGE control Tx queue */
430 struct sge_txq q;
431 struct adapter *adap;
432 struct sk_buff_head sendq; /* list of backpressured packets */
433 struct tasklet_struct qresume_tsk; /* restarts the queue */
434 u8 full; /* the Tx ring is full */
435} ____cacheline_aligned_in_smp;
436
437struct sge {
438 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
439 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
440 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
441
442 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
443 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
444 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
445 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
446
447 struct sge_rspq intrq ____cacheline_aligned_in_smp;
448 spinlock_t intrq_lock;
449
450 u16 max_ethqsets; /* # of available Ethernet queue sets */
451 u16 ethqsets; /* # of active Ethernet queue sets */
452 u16 ethtxq_rover; /* Tx queue to clean up next */
453 u16 ofldqsets; /* # of active offload queue sets */
454 u16 rdmaqs; /* # of available RDMA Rx queues */
455 u16 ofld_rxq[MAX_OFLD_QSETS];
456 u16 rdma_rxq[NCHAN];
457 u16 timer_val[SGE_NTIMERS];
458 u8 counter_val[SGE_NCOUNTERS];
459 unsigned int starve_thres;
460 u8 idma_state[2];
461 void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */
462 struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */
463 DECLARE_BITMAP(starving_fl, MAX_EGRQ);
464 DECLARE_BITMAP(txq_maperr, MAX_EGRQ);
465 struct timer_list rx_timer; /* refills starving FLs */
466 struct timer_list tx_timer; /* checks Tx queues */
467};
468
469#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
470#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
471#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
472
473struct l2t_data;
474
475struct adapter {
476 void __iomem *regs;
477 struct pci_dev *pdev;
478 struct device *pdev_dev;
479 unsigned long registered_device_map;
480 unsigned long open_device_map;
481 unsigned long flags;
482
483 const char *name;
484 int msg_enable;
485
486 struct adapter_params params;
487 struct cxgb4_virt_res vres;
488 unsigned int swintr;
489
490 unsigned int wol;
491
492 struct {
493 unsigned short vec;
494 char desc[14];
495 } msix_info[MAX_INGQ + 1];
496
497 struct sge sge;
498
499 struct net_device *port[MAX_NPORTS];
500 u8 chan_map[NCHAN]; /* channel -> port map */
501
502 struct l2t_data *l2t;
503 void *uld_handle[CXGB4_ULD_MAX];
504 struct list_head list_node;
505
506 struct tid_info tids;
507 void **tid_release_head;
508 spinlock_t tid_release_lock;
509 struct work_struct tid_release_task;
510 bool tid_release_task_busy;
511
512 struct dentry *debugfs_root;
513
514 spinlock_t stats_lock;
515};
516
517static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
518{
519 return readl(adap->regs + reg_addr);
520}
521
522static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
523{
524 writel(val, adap->regs + reg_addr);
525}
526
527#ifndef readq
528static inline u64 readq(const volatile void __iomem *addr)
529{
530 return readl(addr) + ((u64)readl(addr + 4) << 32);
531}
532
533static inline void writeq(u64 val, volatile void __iomem *addr)
534{
535 writel(val, addr);
536 writel(val >> 32, addr + 4);
537}
538#endif
539
540static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
541{
542 return readq(adap->regs + reg_addr);
543}
544
545static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
546{
547 writeq(val, adap->regs + reg_addr);
548}
549
550/**
551 * netdev2pinfo - return the port_info structure associated with a net_device
552 * @dev: the netdev
553 *
554 * Return the struct port_info associated with a net_device
555 */
556static inline struct port_info *netdev2pinfo(const struct net_device *dev)
557{
558 return netdev_priv(dev);
559}
560
561/**
562 * adap2pinfo - return the port_info of a port
563 * @adap: the adapter
564 * @idx: the port index
565 *
566 * Return the port_info structure for the port of the given index.
567 */
568static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
569{
570 return netdev_priv(adap->port[idx]);
571}
572
573/**
574 * netdev2adap - return the adapter structure associated with a net_device
575 * @dev: the netdev
576 *
577 * Return the struct adapter associated with a net_device
578 */
579static inline struct adapter *netdev2adap(const struct net_device *dev)
580{
581 return netdev2pinfo(dev)->adapter;
582}
583
584void t4_os_portmod_changed(const struct adapter *adap, int port_id);
585void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
586
587void *t4_alloc_mem(size_t size);
588void t4_free_mem(void *addr);
589
590void t4_free_sge_resources(struct adapter *adap);
591irq_handler_t t4_intr_handler(struct adapter *adap);
592netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
593int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
594 const struct pkt_gl *gl);
595int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
596int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
597int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
598 struct net_device *dev, int intr_idx,
599 struct sge_fl *fl, rspq_handler_t hnd);
600int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
601 struct net_device *dev, struct netdev_queue *netdevq,
602 unsigned int iqid);
603int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
604 struct net_device *dev, unsigned int iqid,
605 unsigned int cmplqid);
606int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
607 struct net_device *dev, unsigned int iqid);
608irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
609void t4_sge_init(struct adapter *adap);
610void t4_sge_start(struct adapter *adap);
611void t4_sge_stop(struct adapter *adap);
612
613#define for_each_port(adapter, iter) \
614 for (iter = 0; iter < (adapter)->params.nports; ++iter)
615
616static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
617{
618 return adap->params.vpd.cclk / 1000;
619}
620
621static inline unsigned int us_to_core_ticks(const struct adapter *adap,
622 unsigned int us)
623{
624 return (us * adap->params.vpd.cclk) / 1000;
625}
626
627void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
628 u32 val);
629
630int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
631 void *rpl, bool sleep_ok);
632
633static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
634 int size, void *rpl)
635{
636 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
637}
638
639static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
640 int size, void *rpl)
641{
642 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
643}
644
645void t4_intr_enable(struct adapter *adapter);
646void t4_intr_disable(struct adapter *adapter);
647void t4_intr_clear(struct adapter *adapter);
648int t4_slow_intr_handler(struct adapter *adapter);
649
650int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
651 struct link_config *lc);
652int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
653int t4_seeprom_wp(struct adapter *adapter, bool enable);
654int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
655int t4_check_fw_version(struct adapter *adapter);
656int t4_prep_adapter(struct adapter *adapter);
657int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
658void t4_fatal_err(struct adapter *adapter);
659void t4_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on);
660int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
661 int filter_index, int enable);
662void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
663 int filter_index, int *enabled);
664int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
665 int start, int n, const u16 *rspq, unsigned int nrspq);
666int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
667 unsigned int flags);
668int t4_read_rss(struct adapter *adapter, u16 *entries);
669int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity);
670int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
671 u64 *parity);
672
673void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
674void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
675
676void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
677void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st);
678void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
679 struct tp_tcp_stats *v6);
680void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
681 const unsigned short *alpha, const unsigned short *beta);
682
683void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
684 const u8 *addr);
685int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
686 u64 mask0, u64 mask1, unsigned int crc, bool enable);
687
688int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
689 enum dev_master master, enum dev_state *state);
690int t4_fw_bye(struct adapter *adap, unsigned int mbox);
691int t4_early_init(struct adapter *adap, unsigned int mbox);
692int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
693int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
694 unsigned int vf, unsigned int nparams, const u32 *params,
695 u32 *val);
696int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
697 unsigned int vf, unsigned int nparams, const u32 *params,
698 const u32 *val);
699int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
700 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
701 unsigned int rxqi, unsigned int rxq, unsigned int tc,
702 unsigned int vi, unsigned int cmask, unsigned int pmask,
703 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
704int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
705 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
706 unsigned int *rss_size);
707int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
708 unsigned int vf, unsigned int viid);
709int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
710 int mtu, int promisc, int all_multi, int bcast, bool sleep_ok);
711int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
712 unsigned int viid, bool free, unsigned int naddr,
713 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
714int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
715 int idx, const u8 *addr, bool persist, bool add_smt);
716int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
717 bool ucast, u64 vec, bool sleep_ok);
718int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
719 bool rx_en, bool tx_en);
720int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
721 unsigned int nblinks);
722int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
723 unsigned int mmd, unsigned int reg, u16 *valp);
724int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
725 unsigned int mmd, unsigned int reg, u16 val);
726int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
727 unsigned int pf, unsigned int vf, unsigned int iqid,
728 unsigned int fl0id, unsigned int fl1id);
729int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
730 unsigned int vf, unsigned int iqtype, unsigned int iqid,
731 unsigned int fl0id, unsigned int fl1id);
732int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
733 unsigned int vf, unsigned int eqid);
734int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
735 unsigned int vf, unsigned int eqid);
736int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
737 unsigned int vf, unsigned int eqid);
738int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
739#endif /* __CXGB4_H__ */
diff --git a/drivers/net/cxgb4/cxgb4_main.c b/drivers/net/cxgb4/cxgb4_main.c
new file mode 100644
index 000000000000..1bad50041427
--- /dev/null
+++ b/drivers/net/cxgb4/cxgb4_main.c
@@ -0,0 +1,3401 @@
1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37#include <linux/bitmap.h>
38#include <linux/crc32.h>
39#include <linux/ctype.h>
40#include <linux/debugfs.h>
41#include <linux/err.h>
42#include <linux/etherdevice.h>
43#include <linux/firmware.h>
44#include <linux/if_vlan.h>
45#include <linux/init.h>
46#include <linux/log2.h>
47#include <linux/mdio.h>
48#include <linux/module.h>
49#include <linux/moduleparam.h>
50#include <linux/mutex.h>
51#include <linux/netdevice.h>
52#include <linux/pci.h>
53#include <linux/aer.h>
54#include <linux/rtnetlink.h>
55#include <linux/sched.h>
56#include <linux/seq_file.h>
57#include <linux/sockios.h>
58#include <linux/vmalloc.h>
59#include <linux/workqueue.h>
60#include <net/neighbour.h>
61#include <net/netevent.h>
62#include <asm/uaccess.h>
63
64#include "cxgb4.h"
65#include "t4_regs.h"
66#include "t4_msg.h"
67#include "t4fw_api.h"
68#include "l2t.h"
69
70#define DRV_VERSION "1.0.0-ko"
71#define DRV_DESC "Chelsio T4 Network Driver"
72
73/*
74 * Max interrupt hold-off timer value in us. Queues fall back to this value
75 * under extreme memory pressure so it's largish to give the system time to
76 * recover.
77 */
78#define MAX_SGE_TIMERVAL 200U
79
80enum {
81 MEMWIN0_APERTURE = 65536,
82 MEMWIN0_BASE = 0x30000,
83 MEMWIN1_APERTURE = 32768,
84 MEMWIN1_BASE = 0x28000,
85 MEMWIN2_APERTURE = 2048,
86 MEMWIN2_BASE = 0x1b800,
87};
88
89enum {
90 MAX_TXQ_ENTRIES = 16384,
91 MAX_CTRL_TXQ_ENTRIES = 1024,
92 MAX_RSPQ_ENTRIES = 16384,
93 MAX_RX_BUFFERS = 16384,
94 MIN_TXQ_ENTRIES = 32,
95 MIN_CTRL_TXQ_ENTRIES = 32,
96 MIN_RSPQ_ENTRIES = 128,
97 MIN_FL_ENTRIES = 16
98};
99
100#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
101 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
102 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
103
104#define CH_DEVICE(devid) { PCI_VDEVICE(CHELSIO, devid), 0 }
105
106static DEFINE_PCI_DEVICE_TABLE(cxgb4_pci_tbl) = {
107 CH_DEVICE(0xa000), /* PE10K */
108 { 0, }
109};
110
111#define FW_FNAME "cxgb4/t4fw.bin"
112
113MODULE_DESCRIPTION(DRV_DESC);
114MODULE_AUTHOR("Chelsio Communications");
115MODULE_LICENSE("Dual BSD/GPL");
116MODULE_VERSION(DRV_VERSION);
117MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
118MODULE_FIRMWARE(FW_FNAME);
119
120static int dflt_msg_enable = DFLT_MSG_ENABLE;
121
122module_param(dflt_msg_enable, int, 0644);
123MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
124
125/*
126 * The driver uses the best interrupt scheme available on a platform in the
127 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
128 * of these schemes the driver may consider as follows:
129 *
130 * msi = 2: choose from among all three options
131 * msi = 1: only consider MSI and INTx interrupts
132 * msi = 0: force INTx interrupts
133 */
134static int msi = 2;
135
136module_param(msi, int, 0644);
137MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
138
139/*
140 * Queue interrupt hold-off timer values. Queues default to the first of these
141 * upon creation.
142 */
143static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
144
145module_param_array(intr_holdoff, uint, NULL, 0644);
146MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
147 "0..4 in microseconds");
148
149static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
150
151module_param_array(intr_cnt, uint, NULL, 0644);
152MODULE_PARM_DESC(intr_cnt,
153 "thresholds 1..3 for queue interrupt packet counters");
154
155static int vf_acls;
156
157#ifdef CONFIG_PCI_IOV
158module_param(vf_acls, bool, 0644);
159MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement");
160
161static unsigned int num_vf[4];
162
163module_param_array(num_vf, uint, NULL, 0644);
164MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
165#endif
166
167static struct dentry *cxgb4_debugfs_root;
168
169static LIST_HEAD(adapter_list);
170static DEFINE_MUTEX(uld_mutex);
171static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
172static const char *uld_str[] = { "RDMA", "iSCSI" };
173
174static void link_report(struct net_device *dev)
175{
176 if (!netif_carrier_ok(dev))
177 netdev_info(dev, "link down\n");
178 else {
179 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
180
181 const char *s = "10Mbps";
182 const struct port_info *p = netdev_priv(dev);
183
184 switch (p->link_cfg.speed) {
185 case SPEED_10000:
186 s = "10Gbps";
187 break;
188 case SPEED_1000:
189 s = "1000Mbps";
190 break;
191 case SPEED_100:
192 s = "100Mbps";
193 break;
194 }
195
196 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
197 fc[p->link_cfg.fc]);
198 }
199}
200
201void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
202{
203 struct net_device *dev = adapter->port[port_id];
204
205 /* Skip changes from disabled ports. */
206 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
207 if (link_stat)
208 netif_carrier_on(dev);
209 else
210 netif_carrier_off(dev);
211
212 link_report(dev);
213 }
214}
215
216void t4_os_portmod_changed(const struct adapter *adap, int port_id)
217{
218 static const char *mod_str[] = {
219 NULL, "LR", "SR", "ER", "passive DA", "active DA"
220 };
221
222 const struct net_device *dev = adap->port[port_id];
223 const struct port_info *pi = netdev_priv(dev);
224
225 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
226 netdev_info(dev, "port module unplugged\n");
227 else
228 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
229}
230
231/*
232 * Configure the exact and hash address filters to handle a port's multicast
233 * and secondary unicast MAC addresses.
234 */
235static int set_addr_filters(const struct net_device *dev, bool sleep)
236{
237 u64 mhash = 0;
238 u64 uhash = 0;
239 bool free = true;
240 u16 filt_idx[7];
241 const u8 *addr[7];
242 int ret, naddr = 0;
243 const struct netdev_hw_addr *ha;
244 int uc_cnt = netdev_uc_count(dev);
245 int mc_cnt = netdev_mc_count(dev);
246 const struct port_info *pi = netdev_priv(dev);
247
248 /* first do the secondary unicast addresses */
249 netdev_for_each_uc_addr(ha, dev) {
250 addr[naddr++] = ha->addr;
251 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
252 ret = t4_alloc_mac_filt(pi->adapter, 0, pi->viid, free,
253 naddr, addr, filt_idx, &uhash, sleep);
254 if (ret < 0)
255 return ret;
256
257 free = false;
258 naddr = 0;
259 }
260 }
261
262 /* next set up the multicast addresses */
263 netdev_for_each_mc_addr(ha, dev) {
264 addr[naddr++] = ha->addr;
265 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
266 ret = t4_alloc_mac_filt(pi->adapter, 0, pi->viid, free,
267 naddr, addr, filt_idx, &mhash, sleep);
268 if (ret < 0)
269 return ret;
270
271 free = false;
272 naddr = 0;
273 }
274 }
275
276 return t4_set_addr_hash(pi->adapter, 0, pi->viid, uhash != 0,
277 uhash | mhash, sleep);
278}
279
280/*
281 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
282 * If @mtu is -1 it is left unchanged.
283 */
284static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
285{
286 int ret;
287 struct port_info *pi = netdev_priv(dev);
288
289 ret = set_addr_filters(dev, sleep_ok);
290 if (ret == 0)
291 ret = t4_set_rxmode(pi->adapter, 0, pi->viid, mtu,
292 (dev->flags & IFF_PROMISC) ? 1 : 0,
293 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1,
294 sleep_ok);
295 return ret;
296}
297
298/**
299 * link_start - enable a port
300 * @dev: the port to enable
301 *
302 * Performs the MAC and PHY actions needed to enable a port.
303 */
304static int link_start(struct net_device *dev)
305{
306 int ret;
307 struct port_info *pi = netdev_priv(dev);
308
309 /*
310 * We do not set address filters and promiscuity here, the stack does
311 * that step explicitly.
312 */
313 ret = t4_set_rxmode(pi->adapter, 0, pi->viid, dev->mtu, -1, -1, -1,
314 true);
315 if (ret == 0) {
316 ret = t4_change_mac(pi->adapter, 0, pi->viid,
317 pi->xact_addr_filt, dev->dev_addr, true,
318 false);
319 if (ret >= 0) {
320 pi->xact_addr_filt = ret;
321 ret = 0;
322 }
323 }
324 if (ret == 0)
325 ret = t4_link_start(pi->adapter, 0, pi->tx_chan, &pi->link_cfg);
326 if (ret == 0)
327 ret = t4_enable_vi(pi->adapter, 0, pi->viid, true, true);
328 return ret;
329}
330
331/*
332 * Response queue handler for the FW event queue.
333 */
334static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
335 const struct pkt_gl *gl)
336{
337 u8 opcode = ((const struct rss_header *)rsp)->opcode;
338
339 rsp++; /* skip RSS header */
340 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
341 const struct cpl_sge_egr_update *p = (void *)rsp;
342 unsigned int qid = EGR_QID(ntohl(p->opcode_qid));
343 struct sge_txq *txq = q->adap->sge.egr_map[qid];
344
345 txq->restarts++;
346 if ((u8 *)txq < (u8 *)q->adap->sge.ethrxq) {
347 struct sge_eth_txq *eq;
348
349 eq = container_of(txq, struct sge_eth_txq, q);
350 netif_tx_wake_queue(eq->txq);
351 } else {
352 struct sge_ofld_txq *oq;
353
354 oq = container_of(txq, struct sge_ofld_txq, q);
355 tasklet_schedule(&oq->qresume_tsk);
356 }
357 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
358 const struct cpl_fw6_msg *p = (void *)rsp;
359
360 if (p->type == 0)
361 t4_handle_fw_rpl(q->adap, p->data);
362 } else if (opcode == CPL_L2T_WRITE_RPL) {
363 const struct cpl_l2t_write_rpl *p = (void *)rsp;
364
365 do_l2t_write_rpl(q->adap, p);
366 } else
367 dev_err(q->adap->pdev_dev,
368 "unexpected CPL %#x on FW event queue\n", opcode);
369 return 0;
370}
371
372/**
373 * uldrx_handler - response queue handler for ULD queues
374 * @q: the response queue that received the packet
375 * @rsp: the response queue descriptor holding the offload message
376 * @gl: the gather list of packet fragments
377 *
378 * Deliver an ingress offload packet to a ULD. All processing is done by
379 * the ULD, we just maintain statistics.
380 */
381static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
382 const struct pkt_gl *gl)
383{
384 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
385
386 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
387 rxq->stats.nomem++;
388 return -1;
389 }
390 if (gl == NULL)
391 rxq->stats.imm++;
392 else if (gl == CXGB4_MSG_AN)
393 rxq->stats.an++;
394 else
395 rxq->stats.pkts++;
396 return 0;
397}
398
399static void disable_msi(struct adapter *adapter)
400{
401 if (adapter->flags & USING_MSIX) {
402 pci_disable_msix(adapter->pdev);
403 adapter->flags &= ~USING_MSIX;
404 } else if (adapter->flags & USING_MSI) {
405 pci_disable_msi(adapter->pdev);
406 adapter->flags &= ~USING_MSI;
407 }
408}
409
410/*
411 * Interrupt handler for non-data events used with MSI-X.
412 */
413static irqreturn_t t4_nondata_intr(int irq, void *cookie)
414{
415 struct adapter *adap = cookie;
416
417 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE));
418 if (v & PFSW) {
419 adap->swintr = 1;
420 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v);
421 }
422 t4_slow_intr_handler(adap);
423 return IRQ_HANDLED;
424}
425
426/*
427 * Name the MSI-X interrupts.
428 */
429static void name_msix_vecs(struct adapter *adap)
430{
431 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc) - 1;
432
433 /* non-data interrupts */
434 snprintf(adap->msix_info[0].desc, n, "%s", adap->name);
435 adap->msix_info[0].desc[n] = 0;
436
437 /* FW events */
438 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq", adap->name);
439 adap->msix_info[1].desc[n] = 0;
440
441 /* Ethernet queues */
442 for_each_port(adap, j) {
443 struct net_device *d = adap->port[j];
444 const struct port_info *pi = netdev_priv(d);
445
446 for (i = 0; i < pi->nqsets; i++, msi_idx++) {
447 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
448 d->name, i);
449 adap->msix_info[msi_idx].desc[n] = 0;
450 }
451 }
452
453 /* offload queues */
454 for_each_ofldrxq(&adap->sge, i) {
455 snprintf(adap->msix_info[msi_idx].desc, n, "%s-ofld%d",
456 adap->name, i);
457 adap->msix_info[msi_idx++].desc[n] = 0;
458 }
459 for_each_rdmarxq(&adap->sge, i) {
460 snprintf(adap->msix_info[msi_idx].desc, n, "%s-rdma%d",
461 adap->name, i);
462 adap->msix_info[msi_idx++].desc[n] = 0;
463 }
464}
465
466static int request_msix_queue_irqs(struct adapter *adap)
467{
468 struct sge *s = &adap->sge;
469 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, msi = 2;
470
471 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
472 adap->msix_info[1].desc, &s->fw_evtq);
473 if (err)
474 return err;
475
476 for_each_ethrxq(s, ethqidx) {
477 err = request_irq(adap->msix_info[msi].vec, t4_sge_intr_msix, 0,
478 adap->msix_info[msi].desc,
479 &s->ethrxq[ethqidx].rspq);
480 if (err)
481 goto unwind;
482 msi++;
483 }
484 for_each_ofldrxq(s, ofldqidx) {
485 err = request_irq(adap->msix_info[msi].vec, t4_sge_intr_msix, 0,
486 adap->msix_info[msi].desc,
487 &s->ofldrxq[ofldqidx].rspq);
488 if (err)
489 goto unwind;
490 msi++;
491 }
492 for_each_rdmarxq(s, rdmaqidx) {
493 err = request_irq(adap->msix_info[msi].vec, t4_sge_intr_msix, 0,
494 adap->msix_info[msi].desc,
495 &s->rdmarxq[rdmaqidx].rspq);
496 if (err)
497 goto unwind;
498 msi++;
499 }
500 return 0;
501
502unwind:
503 while (--rdmaqidx >= 0)
504 free_irq(adap->msix_info[--msi].vec,
505 &s->rdmarxq[rdmaqidx].rspq);
506 while (--ofldqidx >= 0)
507 free_irq(adap->msix_info[--msi].vec,
508 &s->ofldrxq[ofldqidx].rspq);
509 while (--ethqidx >= 0)
510 free_irq(adap->msix_info[--msi].vec, &s->ethrxq[ethqidx].rspq);
511 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
512 return err;
513}
514
515static void free_msix_queue_irqs(struct adapter *adap)
516{
517 int i, msi = 2;
518 struct sge *s = &adap->sge;
519
520 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
521 for_each_ethrxq(s, i)
522 free_irq(adap->msix_info[msi++].vec, &s->ethrxq[i].rspq);
523 for_each_ofldrxq(s, i)
524 free_irq(adap->msix_info[msi++].vec, &s->ofldrxq[i].rspq);
525 for_each_rdmarxq(s, i)
526 free_irq(adap->msix_info[msi++].vec, &s->rdmarxq[i].rspq);
527}
528
529/**
530 * setup_rss - configure RSS
531 * @adap: the adapter
532 *
533 * Sets up RSS to distribute packets to multiple receive queues. We
534 * configure the RSS CPU lookup table to distribute to the number of HW
535 * receive queues, and the response queue lookup table to narrow that
536 * down to the response queues actually configured for each port.
537 * We always configure the RSS mapping for all ports since the mapping
538 * table has plenty of entries.
539 */
540static int setup_rss(struct adapter *adap)
541{
542 int i, j, err;
543 u16 rss[MAX_ETH_QSETS];
544
545 for_each_port(adap, i) {
546 const struct port_info *pi = adap2pinfo(adap, i);
547 const struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
548
549 for (j = 0; j < pi->nqsets; j++)
550 rss[j] = q[j].rspq.abs_id;
551
552 err = t4_config_rss_range(adap, 0, pi->viid, 0, pi->rss_size,
553 rss, pi->nqsets);
554 if (err)
555 return err;
556 }
557 return 0;
558}
559
560/*
561 * Wait until all NAPI handlers are descheduled.
562 */
563static void quiesce_rx(struct adapter *adap)
564{
565 int i;
566
567 for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
568 struct sge_rspq *q = adap->sge.ingr_map[i];
569
570 if (q && q->handler)
571 napi_disable(&q->napi);
572 }
573}
574
575/*
576 * Enable NAPI scheduling and interrupt generation for all Rx queues.
577 */
578static void enable_rx(struct adapter *adap)
579{
580 int i;
581
582 for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
583 struct sge_rspq *q = adap->sge.ingr_map[i];
584
585 if (!q)
586 continue;
587 if (q->handler)
588 napi_enable(&q->napi);
589 /* 0-increment GTS to start the timer and enable interrupts */
590 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
591 SEINTARM(q->intr_params) |
592 INGRESSQID(q->cntxt_id));
593 }
594}
595
596/**
597 * setup_sge_queues - configure SGE Tx/Rx/response queues
598 * @adap: the adapter
599 *
600 * Determines how many sets of SGE queues to use and initializes them.
601 * We support multiple queue sets per port if we have MSI-X, otherwise
602 * just one queue set per port.
603 */
604static int setup_sge_queues(struct adapter *adap)
605{
606 int err, msi_idx, i, j;
607 struct sge *s = &adap->sge;
608
609 bitmap_zero(s->starving_fl, MAX_EGRQ);
610 bitmap_zero(s->txq_maperr, MAX_EGRQ);
611
612 if (adap->flags & USING_MSIX)
613 msi_idx = 1; /* vector 0 is for non-queue interrupts */
614 else {
615 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
616 NULL, NULL);
617 if (err)
618 return err;
619 msi_idx = -((int)s->intrq.abs_id + 1);
620 }
621
622 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
623 msi_idx, NULL, fwevtq_handler);
624 if (err) {
625freeout: t4_free_sge_resources(adap);
626 return err;
627 }
628
629 for_each_port(adap, i) {
630 struct net_device *dev = adap->port[i];
631 struct port_info *pi = netdev_priv(dev);
632 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
633 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
634
635 for (j = 0; j < pi->nqsets; j++, q++) {
636 if (msi_idx > 0)
637 msi_idx++;
638 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
639 msi_idx, &q->fl,
640 t4_ethrx_handler);
641 if (err)
642 goto freeout;
643 q->rspq.idx = j;
644 memset(&q->stats, 0, sizeof(q->stats));
645 }
646 for (j = 0; j < pi->nqsets; j++, t++) {
647 err = t4_sge_alloc_eth_txq(adap, t, dev,
648 netdev_get_tx_queue(dev, j),
649 s->fw_evtq.cntxt_id);
650 if (err)
651 goto freeout;
652 }
653 }
654
655 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
656 for_each_ofldrxq(s, i) {
657 struct sge_ofld_rxq *q = &s->ofldrxq[i];
658 struct net_device *dev = adap->port[i / j];
659
660 if (msi_idx > 0)
661 msi_idx++;
662 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, msi_idx,
663 &q->fl, uldrx_handler);
664 if (err)
665 goto freeout;
666 memset(&q->stats, 0, sizeof(q->stats));
667 s->ofld_rxq[i] = q->rspq.abs_id;
668 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], dev,
669 s->fw_evtq.cntxt_id);
670 if (err)
671 goto freeout;
672 }
673
674 for_each_rdmarxq(s, i) {
675 struct sge_ofld_rxq *q = &s->rdmarxq[i];
676
677 if (msi_idx > 0)
678 msi_idx++;
679 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
680 msi_idx, &q->fl, uldrx_handler);
681 if (err)
682 goto freeout;
683 memset(&q->stats, 0, sizeof(q->stats));
684 s->rdma_rxq[i] = q->rspq.abs_id;
685 }
686
687 for_each_port(adap, i) {
688 /*
689 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
690 * have RDMA queues, and that's the right value.
691 */
692 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
693 s->fw_evtq.cntxt_id,
694 s->rdmarxq[i].rspq.cntxt_id);
695 if (err)
696 goto freeout;
697 }
698
699 t4_write_reg(adap, MPS_TRC_RSS_CONTROL,
700 RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
701 QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
702 return 0;
703}
704
705/*
706 * Returns 0 if new FW was successfully loaded, a positive errno if a load was
707 * started but failed, and a negative errno if flash load couldn't start.
708 */
709static int upgrade_fw(struct adapter *adap)
710{
711 int ret;
712 u32 vers;
713 const struct fw_hdr *hdr;
714 const struct firmware *fw;
715 struct device *dev = adap->pdev_dev;
716
717 ret = request_firmware(&fw, FW_FNAME, dev);
718 if (ret < 0) {
719 dev_err(dev, "unable to load firmware image " FW_FNAME
720 ", error %d\n", ret);
721 return ret;
722 }
723
724 hdr = (const struct fw_hdr *)fw->data;
725 vers = ntohl(hdr->fw_ver);
726 if (FW_HDR_FW_VER_MAJOR_GET(vers) != FW_VERSION_MAJOR) {
727 ret = -EINVAL; /* wrong major version, won't do */
728 goto out;
729 }
730
731 /*
732 * If the flash FW is unusable or we found something newer, load it.
733 */
734 if (FW_HDR_FW_VER_MAJOR_GET(adap->params.fw_vers) != FW_VERSION_MAJOR ||
735 vers > adap->params.fw_vers) {
736 ret = -t4_load_fw(adap, fw->data, fw->size);
737 if (!ret)
738 dev_info(dev, "firmware upgraded to version %pI4 from "
739 FW_FNAME "\n", &hdr->fw_ver);
740 }
741out: release_firmware(fw);
742 return ret;
743}
744
745/*
746 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
747 * The allocated memory is cleared.
748 */
749void *t4_alloc_mem(size_t size)
750{
751 void *p = kmalloc(size, GFP_KERNEL);
752
753 if (!p)
754 p = vmalloc(size);
755 if (p)
756 memset(p, 0, size);
757 return p;
758}
759
760/*
761 * Free memory allocated through alloc_mem().
762 */
763void t4_free_mem(void *addr)
764{
765 if (is_vmalloc_addr(addr))
766 vfree(addr);
767 else
768 kfree(addr);
769}
770
771static inline int is_offload(const struct adapter *adap)
772{
773 return adap->params.offload;
774}
775
776/*
777 * Implementation of ethtool operations.
778 */
779
780static u32 get_msglevel(struct net_device *dev)
781{
782 return netdev2adap(dev)->msg_enable;
783}
784
785static void set_msglevel(struct net_device *dev, u32 val)
786{
787 netdev2adap(dev)->msg_enable = val;
788}
789
790static char stats_strings[][ETH_GSTRING_LEN] = {
791 "TxOctetsOK ",
792 "TxFramesOK ",
793 "TxBroadcastFrames ",
794 "TxMulticastFrames ",
795 "TxUnicastFrames ",
796 "TxErrorFrames ",
797
798 "TxFrames64 ",
799 "TxFrames65To127 ",
800 "TxFrames128To255 ",
801 "TxFrames256To511 ",
802 "TxFrames512To1023 ",
803 "TxFrames1024To1518 ",
804 "TxFrames1519ToMax ",
805
806 "TxFramesDropped ",
807 "TxPauseFrames ",
808 "TxPPP0Frames ",
809 "TxPPP1Frames ",
810 "TxPPP2Frames ",
811 "TxPPP3Frames ",
812 "TxPPP4Frames ",
813 "TxPPP5Frames ",
814 "TxPPP6Frames ",
815 "TxPPP7Frames ",
816
817 "RxOctetsOK ",
818 "RxFramesOK ",
819 "RxBroadcastFrames ",
820 "RxMulticastFrames ",
821 "RxUnicastFrames ",
822
823 "RxFramesTooLong ",
824 "RxJabberErrors ",
825 "RxFCSErrors ",
826 "RxLengthErrors ",
827 "RxSymbolErrors ",
828 "RxRuntFrames ",
829
830 "RxFrames64 ",
831 "RxFrames65To127 ",
832 "RxFrames128To255 ",
833 "RxFrames256To511 ",
834 "RxFrames512To1023 ",
835 "RxFrames1024To1518 ",
836 "RxFrames1519ToMax ",
837
838 "RxPauseFrames ",
839 "RxPPP0Frames ",
840 "RxPPP1Frames ",
841 "RxPPP2Frames ",
842 "RxPPP3Frames ",
843 "RxPPP4Frames ",
844 "RxPPP5Frames ",
845 "RxPPP6Frames ",
846 "RxPPP7Frames ",
847
848 "RxBG0FramesDropped ",
849 "RxBG1FramesDropped ",
850 "RxBG2FramesDropped ",
851 "RxBG3FramesDropped ",
852 "RxBG0FramesTrunc ",
853 "RxBG1FramesTrunc ",
854 "RxBG2FramesTrunc ",
855 "RxBG3FramesTrunc ",
856
857 "TSO ",
858 "TxCsumOffload ",
859 "RxCsumGood ",
860 "VLANextractions ",
861 "VLANinsertions ",
862};
863
864static int get_sset_count(struct net_device *dev, int sset)
865{
866 switch (sset) {
867 case ETH_SS_STATS:
868 return ARRAY_SIZE(stats_strings);
869 default:
870 return -EOPNOTSUPP;
871 }
872}
873
874#define T4_REGMAP_SIZE (160 * 1024)
875
876static int get_regs_len(struct net_device *dev)
877{
878 return T4_REGMAP_SIZE;
879}
880
881static int get_eeprom_len(struct net_device *dev)
882{
883 return EEPROMSIZE;
884}
885
886static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
887{
888 struct adapter *adapter = netdev2adap(dev);
889
890 strcpy(info->driver, KBUILD_MODNAME);
891 strcpy(info->version, DRV_VERSION);
892 strcpy(info->bus_info, pci_name(adapter->pdev));
893
894 if (!adapter->params.fw_vers)
895 strcpy(info->fw_version, "N/A");
896 else
897 snprintf(info->fw_version, sizeof(info->fw_version),
898 "%u.%u.%u.%u, TP %u.%u.%u.%u",
899 FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers),
900 FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers),
901 FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers),
902 FW_HDR_FW_VER_BUILD_GET(adapter->params.fw_vers),
903 FW_HDR_FW_VER_MAJOR_GET(adapter->params.tp_vers),
904 FW_HDR_FW_VER_MINOR_GET(adapter->params.tp_vers),
905 FW_HDR_FW_VER_MICRO_GET(adapter->params.tp_vers),
906 FW_HDR_FW_VER_BUILD_GET(adapter->params.tp_vers));
907}
908
909static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
910{
911 if (stringset == ETH_SS_STATS)
912 memcpy(data, stats_strings, sizeof(stats_strings));
913}
914
915/*
916 * port stats maintained per queue of the port. They should be in the same
917 * order as in stats_strings above.
918 */
919struct queue_port_stats {
920 u64 tso;
921 u64 tx_csum;
922 u64 rx_csum;
923 u64 vlan_ex;
924 u64 vlan_ins;
925};
926
927static void collect_sge_port_stats(const struct adapter *adap,
928 const struct port_info *p, struct queue_port_stats *s)
929{
930 int i;
931 const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
932 const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
933
934 memset(s, 0, sizeof(*s));
935 for (i = 0; i < p->nqsets; i++, rx++, tx++) {
936 s->tso += tx->tso;
937 s->tx_csum += tx->tx_cso;
938 s->rx_csum += rx->stats.rx_cso;
939 s->vlan_ex += rx->stats.vlan_ex;
940 s->vlan_ins += tx->vlan_ins;
941 }
942}
943
944static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
945 u64 *data)
946{
947 struct port_info *pi = netdev_priv(dev);
948 struct adapter *adapter = pi->adapter;
949
950 t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data);
951
952 data += sizeof(struct port_stats) / sizeof(u64);
953 collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
954}
955
956/*
957 * Return a version number to identify the type of adapter. The scheme is:
958 * - bits 0..9: chip version
959 * - bits 10..15: chip revision
960 */
961static inline unsigned int mk_adap_vers(const struct adapter *ap)
962{
963 return 4 | (ap->params.rev << 10);
964}
965
966static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start,
967 unsigned int end)
968{
969 u32 *p = buf + start;
970
971 for ( ; start <= end; start += sizeof(u32))
972 *p++ = t4_read_reg(ap, start);
973}
974
975static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
976 void *buf)
977{
978 static const unsigned int reg_ranges[] = {
979 0x1008, 0x1108,
980 0x1180, 0x11b4,
981 0x11fc, 0x123c,
982 0x1300, 0x173c,
983 0x1800, 0x18fc,
984 0x3000, 0x30d8,
985 0x30e0, 0x5924,
986 0x5960, 0x59d4,
987 0x5a00, 0x5af8,
988 0x6000, 0x6098,
989 0x6100, 0x6150,
990 0x6200, 0x6208,
991 0x6240, 0x6248,
992 0x6280, 0x6338,
993 0x6370, 0x638c,
994 0x6400, 0x643c,
995 0x6500, 0x6524,
996 0x6a00, 0x6a38,
997 0x6a60, 0x6a78,
998 0x6b00, 0x6b84,
999 0x6bf0, 0x6c84,
1000 0x6cf0, 0x6d84,
1001 0x6df0, 0x6e84,
1002 0x6ef0, 0x6f84,
1003 0x6ff0, 0x7084,
1004 0x70f0, 0x7184,
1005 0x71f0, 0x7284,
1006 0x72f0, 0x7384,
1007 0x73f0, 0x7450,
1008 0x7500, 0x7530,
1009 0x7600, 0x761c,
1010 0x7680, 0x76cc,
1011 0x7700, 0x7798,
1012 0x77c0, 0x77fc,
1013 0x7900, 0x79fc,
1014 0x7b00, 0x7c38,
1015 0x7d00, 0x7efc,
1016 0x8dc0, 0x8e1c,
1017 0x8e30, 0x8e78,
1018 0x8ea0, 0x8f6c,
1019 0x8fc0, 0x9074,
1020 0x90fc, 0x90fc,
1021 0x9400, 0x9458,
1022 0x9600, 0x96bc,
1023 0x9800, 0x9808,
1024 0x9820, 0x983c,
1025 0x9850, 0x9864,
1026 0x9c00, 0x9c6c,
1027 0x9c80, 0x9cec,
1028 0x9d00, 0x9d6c,
1029 0x9d80, 0x9dec,
1030 0x9e00, 0x9e6c,
1031 0x9e80, 0x9eec,
1032 0x9f00, 0x9f6c,
1033 0x9f80, 0x9fec,
1034 0xd004, 0xd03c,
1035 0xdfc0, 0xdfe0,
1036 0xe000, 0xea7c,
1037 0xf000, 0x11190,
1038 0x19040, 0x19124,
1039 0x19150, 0x191b0,
1040 0x191d0, 0x191e8,
1041 0x19238, 0x1924c,
1042 0x193f8, 0x19474,
1043 0x19490, 0x194f8,
1044 0x19800, 0x19f30,
1045 0x1a000, 0x1a06c,
1046 0x1a0b0, 0x1a120,
1047 0x1a128, 0x1a138,
1048 0x1a190, 0x1a1c4,
1049 0x1a1fc, 0x1a1fc,
1050 0x1e040, 0x1e04c,
1051 0x1e240, 0x1e28c,
1052 0x1e2c0, 0x1e2c0,
1053 0x1e2e0, 0x1e2e0,
1054 0x1e300, 0x1e384,
1055 0x1e3c0, 0x1e3c8,
1056 0x1e440, 0x1e44c,
1057 0x1e640, 0x1e68c,
1058 0x1e6c0, 0x1e6c0,
1059 0x1e6e0, 0x1e6e0,
1060 0x1e700, 0x1e784,
1061 0x1e7c0, 0x1e7c8,
1062 0x1e840, 0x1e84c,
1063 0x1ea40, 0x1ea8c,
1064 0x1eac0, 0x1eac0,
1065 0x1eae0, 0x1eae0,
1066 0x1eb00, 0x1eb84,
1067 0x1ebc0, 0x1ebc8,
1068 0x1ec40, 0x1ec4c,
1069 0x1ee40, 0x1ee8c,
1070 0x1eec0, 0x1eec0,
1071 0x1eee0, 0x1eee0,
1072 0x1ef00, 0x1ef84,
1073 0x1efc0, 0x1efc8,
1074 0x1f040, 0x1f04c,
1075 0x1f240, 0x1f28c,
1076 0x1f2c0, 0x1f2c0,
1077 0x1f2e0, 0x1f2e0,
1078 0x1f300, 0x1f384,
1079 0x1f3c0, 0x1f3c8,
1080 0x1f440, 0x1f44c,
1081 0x1f640, 0x1f68c,
1082 0x1f6c0, 0x1f6c0,
1083 0x1f6e0, 0x1f6e0,
1084 0x1f700, 0x1f784,
1085 0x1f7c0, 0x1f7c8,
1086 0x1f840, 0x1f84c,
1087 0x1fa40, 0x1fa8c,
1088 0x1fac0, 0x1fac0,
1089 0x1fae0, 0x1fae0,
1090 0x1fb00, 0x1fb84,
1091 0x1fbc0, 0x1fbc8,
1092 0x1fc40, 0x1fc4c,
1093 0x1fe40, 0x1fe8c,
1094 0x1fec0, 0x1fec0,
1095 0x1fee0, 0x1fee0,
1096 0x1ff00, 0x1ff84,
1097 0x1ffc0, 0x1ffc8,
1098 0x20000, 0x2002c,
1099 0x20100, 0x2013c,
1100 0x20190, 0x201c8,
1101 0x20200, 0x20318,
1102 0x20400, 0x20528,
1103 0x20540, 0x20614,
1104 0x21000, 0x21040,
1105 0x2104c, 0x21060,
1106 0x210c0, 0x210ec,
1107 0x21200, 0x21268,
1108 0x21270, 0x21284,
1109 0x212fc, 0x21388,
1110 0x21400, 0x21404,
1111 0x21500, 0x21518,
1112 0x2152c, 0x2153c,
1113 0x21550, 0x21554,
1114 0x21600, 0x21600,
1115 0x21608, 0x21628,
1116 0x21630, 0x2163c,
1117 0x21700, 0x2171c,
1118 0x21780, 0x2178c,
1119 0x21800, 0x21c38,
1120 0x21c80, 0x21d7c,
1121 0x21e00, 0x21e04,
1122 0x22000, 0x2202c,
1123 0x22100, 0x2213c,
1124 0x22190, 0x221c8,
1125 0x22200, 0x22318,
1126 0x22400, 0x22528,
1127 0x22540, 0x22614,
1128 0x23000, 0x23040,
1129 0x2304c, 0x23060,
1130 0x230c0, 0x230ec,
1131 0x23200, 0x23268,
1132 0x23270, 0x23284,
1133 0x232fc, 0x23388,
1134 0x23400, 0x23404,
1135 0x23500, 0x23518,
1136 0x2352c, 0x2353c,
1137 0x23550, 0x23554,
1138 0x23600, 0x23600,
1139 0x23608, 0x23628,
1140 0x23630, 0x2363c,
1141 0x23700, 0x2371c,
1142 0x23780, 0x2378c,
1143 0x23800, 0x23c38,
1144 0x23c80, 0x23d7c,
1145 0x23e00, 0x23e04,
1146 0x24000, 0x2402c,
1147 0x24100, 0x2413c,
1148 0x24190, 0x241c8,
1149 0x24200, 0x24318,
1150 0x24400, 0x24528,
1151 0x24540, 0x24614,
1152 0x25000, 0x25040,
1153 0x2504c, 0x25060,
1154 0x250c0, 0x250ec,
1155 0x25200, 0x25268,
1156 0x25270, 0x25284,
1157 0x252fc, 0x25388,
1158 0x25400, 0x25404,
1159 0x25500, 0x25518,
1160 0x2552c, 0x2553c,
1161 0x25550, 0x25554,
1162 0x25600, 0x25600,
1163 0x25608, 0x25628,
1164 0x25630, 0x2563c,
1165 0x25700, 0x2571c,
1166 0x25780, 0x2578c,
1167 0x25800, 0x25c38,
1168 0x25c80, 0x25d7c,
1169 0x25e00, 0x25e04,
1170 0x26000, 0x2602c,
1171 0x26100, 0x2613c,
1172 0x26190, 0x261c8,
1173 0x26200, 0x26318,
1174 0x26400, 0x26528,
1175 0x26540, 0x26614,
1176 0x27000, 0x27040,
1177 0x2704c, 0x27060,
1178 0x270c0, 0x270ec,
1179 0x27200, 0x27268,
1180 0x27270, 0x27284,
1181 0x272fc, 0x27388,
1182 0x27400, 0x27404,
1183 0x27500, 0x27518,
1184 0x2752c, 0x2753c,
1185 0x27550, 0x27554,
1186 0x27600, 0x27600,
1187 0x27608, 0x27628,
1188 0x27630, 0x2763c,
1189 0x27700, 0x2771c,
1190 0x27780, 0x2778c,
1191 0x27800, 0x27c38,
1192 0x27c80, 0x27d7c,
1193 0x27e00, 0x27e04
1194 };
1195
1196 int i;
1197 struct adapter *ap = netdev2adap(dev);
1198
1199 regs->version = mk_adap_vers(ap);
1200
1201 memset(buf, 0, T4_REGMAP_SIZE);
1202 for (i = 0; i < ARRAY_SIZE(reg_ranges); i += 2)
1203 reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]);
1204}
1205
1206static int restart_autoneg(struct net_device *dev)
1207{
1208 struct port_info *p = netdev_priv(dev);
1209
1210 if (!netif_running(dev))
1211 return -EAGAIN;
1212 if (p->link_cfg.autoneg != AUTONEG_ENABLE)
1213 return -EINVAL;
1214 t4_restart_aneg(p->adapter, 0, p->tx_chan);
1215 return 0;
1216}
1217
1218static int identify_port(struct net_device *dev, u32 data)
1219{
1220 if (data == 0)
1221 data = 2; /* default to 2 seconds */
1222
1223 return t4_identify_port(netdev2adap(dev), 0, netdev2pinfo(dev)->viid,
1224 data * 5);
1225}
1226
1227static unsigned int from_fw_linkcaps(unsigned int type, unsigned int caps)
1228{
1229 unsigned int v = 0;
1230
1231 if (type == FW_PORT_TYPE_BT_SGMII || type == FW_PORT_TYPE_BT_XAUI) {
1232 v |= SUPPORTED_TP;
1233 if (caps & FW_PORT_CAP_SPEED_100M)
1234 v |= SUPPORTED_100baseT_Full;
1235 if (caps & FW_PORT_CAP_SPEED_1G)
1236 v |= SUPPORTED_1000baseT_Full;
1237 if (caps & FW_PORT_CAP_SPEED_10G)
1238 v |= SUPPORTED_10000baseT_Full;
1239 } else if (type == FW_PORT_TYPE_KX4 || type == FW_PORT_TYPE_KX) {
1240 v |= SUPPORTED_Backplane;
1241 if (caps & FW_PORT_CAP_SPEED_1G)
1242 v |= SUPPORTED_1000baseKX_Full;
1243 if (caps & FW_PORT_CAP_SPEED_10G)
1244 v |= SUPPORTED_10000baseKX4_Full;
1245 } else if (type == FW_PORT_TYPE_KR)
1246 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
1247 else if (type == FW_PORT_TYPE_FIBER)
1248 v |= SUPPORTED_FIBRE;
1249
1250 if (caps & FW_PORT_CAP_ANEG)
1251 v |= SUPPORTED_Autoneg;
1252 return v;
1253}
1254
1255static unsigned int to_fw_linkcaps(unsigned int caps)
1256{
1257 unsigned int v = 0;
1258
1259 if (caps & ADVERTISED_100baseT_Full)
1260 v |= FW_PORT_CAP_SPEED_100M;
1261 if (caps & ADVERTISED_1000baseT_Full)
1262 v |= FW_PORT_CAP_SPEED_1G;
1263 if (caps & ADVERTISED_10000baseT_Full)
1264 v |= FW_PORT_CAP_SPEED_10G;
1265 return v;
1266}
1267
1268static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1269{
1270 const struct port_info *p = netdev_priv(dev);
1271
1272 if (p->port_type == FW_PORT_TYPE_BT_SGMII ||
1273 p->port_type == FW_PORT_TYPE_BT_XAUI)
1274 cmd->port = PORT_TP;
1275 else if (p->port_type == FW_PORT_TYPE_FIBER)
1276 cmd->port = PORT_FIBRE;
1277 else if (p->port_type == FW_PORT_TYPE_TWINAX)
1278 cmd->port = PORT_DA;
1279 else
1280 cmd->port = PORT_OTHER;
1281
1282 if (p->mdio_addr >= 0) {
1283 cmd->phy_address = p->mdio_addr;
1284 cmd->transceiver = XCVR_EXTERNAL;
1285 cmd->mdio_support = p->port_type == FW_PORT_TYPE_BT_SGMII ?
1286 MDIO_SUPPORTS_C22 : MDIO_SUPPORTS_C45;
1287 } else {
1288 cmd->phy_address = 0; /* not really, but no better option */
1289 cmd->transceiver = XCVR_INTERNAL;
1290 cmd->mdio_support = 0;
1291 }
1292
1293 cmd->supported = from_fw_linkcaps(p->port_type, p->link_cfg.supported);
1294 cmd->advertising = from_fw_linkcaps(p->port_type,
1295 p->link_cfg.advertising);
1296 cmd->speed = netif_carrier_ok(dev) ? p->link_cfg.speed : 0;
1297 cmd->duplex = DUPLEX_FULL;
1298 cmd->autoneg = p->link_cfg.autoneg;
1299 cmd->maxtxpkt = 0;
1300 cmd->maxrxpkt = 0;
1301 return 0;
1302}
1303
1304static unsigned int speed_to_caps(int speed)
1305{
1306 if (speed == SPEED_100)
1307 return FW_PORT_CAP_SPEED_100M;
1308 if (speed == SPEED_1000)
1309 return FW_PORT_CAP_SPEED_1G;
1310 if (speed == SPEED_10000)
1311 return FW_PORT_CAP_SPEED_10G;
1312 return 0;
1313}
1314
1315static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1316{
1317 unsigned int cap;
1318 struct port_info *p = netdev_priv(dev);
1319 struct link_config *lc = &p->link_cfg;
1320
1321 if (cmd->duplex != DUPLEX_FULL) /* only full-duplex supported */
1322 return -EINVAL;
1323
1324 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
1325 /*
1326 * PHY offers a single speed. See if that's what's
1327 * being requested.
1328 */
1329 if (cmd->autoneg == AUTONEG_DISABLE &&
1330 (lc->supported & speed_to_caps(cmd->speed)))
1331 return 0;
1332 return -EINVAL;
1333 }
1334
1335 if (cmd->autoneg == AUTONEG_DISABLE) {
1336 cap = speed_to_caps(cmd->speed);
1337
1338 if (!(lc->supported & cap) || cmd->speed == SPEED_1000 ||
1339 cmd->speed == SPEED_10000)
1340 return -EINVAL;
1341 lc->requested_speed = cap;
1342 lc->advertising = 0;
1343 } else {
1344 cap = to_fw_linkcaps(cmd->advertising);
1345 if (!(lc->supported & cap))
1346 return -EINVAL;
1347 lc->requested_speed = 0;
1348 lc->advertising = cap | FW_PORT_CAP_ANEG;
1349 }
1350 lc->autoneg = cmd->autoneg;
1351
1352 if (netif_running(dev))
1353 return t4_link_start(p->adapter, 0, p->tx_chan, lc);
1354 return 0;
1355}
1356
1357static void get_pauseparam(struct net_device *dev,
1358 struct ethtool_pauseparam *epause)
1359{
1360 struct port_info *p = netdev_priv(dev);
1361
1362 epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
1363 epause->rx_pause = (p->link_cfg.fc & PAUSE_RX) != 0;
1364 epause->tx_pause = (p->link_cfg.fc & PAUSE_TX) != 0;
1365}
1366
1367static int set_pauseparam(struct net_device *dev,
1368 struct ethtool_pauseparam *epause)
1369{
1370 struct port_info *p = netdev_priv(dev);
1371 struct link_config *lc = &p->link_cfg;
1372
1373 if (epause->autoneg == AUTONEG_DISABLE)
1374 lc->requested_fc = 0;
1375 else if (lc->supported & FW_PORT_CAP_ANEG)
1376 lc->requested_fc = PAUSE_AUTONEG;
1377 else
1378 return -EINVAL;
1379
1380 if (epause->rx_pause)
1381 lc->requested_fc |= PAUSE_RX;
1382 if (epause->tx_pause)
1383 lc->requested_fc |= PAUSE_TX;
1384 if (netif_running(dev))
1385 return t4_link_start(p->adapter, 0, p->tx_chan, lc);
1386 return 0;
1387}
1388
1389static u32 get_rx_csum(struct net_device *dev)
1390{
1391 struct port_info *p = netdev_priv(dev);
1392
1393 return p->rx_offload & RX_CSO;
1394}
1395
1396static int set_rx_csum(struct net_device *dev, u32 data)
1397{
1398 struct port_info *p = netdev_priv(dev);
1399
1400 if (data)
1401 p->rx_offload |= RX_CSO;
1402 else
1403 p->rx_offload &= ~RX_CSO;
1404 return 0;
1405}
1406
1407static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1408{
1409 const struct port_info *pi = netdev_priv(dev);
1410 const struct sge *s = &pi->adapter->sge;
1411
1412 e->rx_max_pending = MAX_RX_BUFFERS;
1413 e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
1414 e->rx_jumbo_max_pending = 0;
1415 e->tx_max_pending = MAX_TXQ_ENTRIES;
1416
1417 e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
1418 e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
1419 e->rx_jumbo_pending = 0;
1420 e->tx_pending = s->ethtxq[pi->first_qset].q.size;
1421}
1422
1423static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1424{
1425 int i;
1426 const struct port_info *pi = netdev_priv(dev);
1427 struct adapter *adapter = pi->adapter;
1428 struct sge *s = &adapter->sge;
1429
1430 if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
1431 e->tx_pending > MAX_TXQ_ENTRIES ||
1432 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
1433 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
1434 e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
1435 return -EINVAL;
1436
1437 if (adapter->flags & FULL_INIT_DONE)
1438 return -EBUSY;
1439
1440 for (i = 0; i < pi->nqsets; ++i) {
1441 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
1442 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
1443 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
1444 }
1445 return 0;
1446}
1447
1448static int closest_timer(const struct sge *s, int time)
1449{
1450 int i, delta, match = 0, min_delta = INT_MAX;
1451
1452 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1453 delta = time - s->timer_val[i];
1454 if (delta < 0)
1455 delta = -delta;
1456 if (delta < min_delta) {
1457 min_delta = delta;
1458 match = i;
1459 }
1460 }
1461 return match;
1462}
1463
1464static int closest_thres(const struct sge *s, int thres)
1465{
1466 int i, delta, match = 0, min_delta = INT_MAX;
1467
1468 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1469 delta = thres - s->counter_val[i];
1470 if (delta < 0)
1471 delta = -delta;
1472 if (delta < min_delta) {
1473 min_delta = delta;
1474 match = i;
1475 }
1476 }
1477 return match;
1478}
1479
1480/*
1481 * Return a queue's interrupt hold-off time in us. 0 means no timer.
1482 */
1483static unsigned int qtimer_val(const struct adapter *adap,
1484 const struct sge_rspq *q)
1485{
1486 unsigned int idx = q->intr_params >> 1;
1487
1488 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1489}
1490
1491/**
1492 * set_rxq_intr_params - set a queue's interrupt holdoff parameters
1493 * @adap: the adapter
1494 * @q: the Rx queue
1495 * @us: the hold-off time in us, or 0 to disable timer
1496 * @cnt: the hold-off packet count, or 0 to disable counter
1497 *
1498 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1499 * one of the two needs to be enabled for the queue to generate interrupts.
1500 */
1501static int set_rxq_intr_params(struct adapter *adap, struct sge_rspq *q,
1502 unsigned int us, unsigned int cnt)
1503{
1504 if ((us | cnt) == 0)
1505 cnt = 1;
1506
1507 if (cnt) {
1508 int err;
1509 u32 v, new_idx;
1510
1511 new_idx = closest_thres(&adap->sge, cnt);
1512 if (q->desc && q->pktcnt_idx != new_idx) {
1513 /* the queue has already been created, update it */
1514 v = FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
1515 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1516 FW_PARAMS_PARAM_YZ(q->cntxt_id);
1517 err = t4_set_params(adap, 0, 0, 0, 1, &v, &new_idx);
1518 if (err)
1519 return err;
1520 }
1521 q->pktcnt_idx = new_idx;
1522 }
1523
1524 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1525 q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
1526 return 0;
1527}
1528
1529static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1530{
1531 const struct port_info *pi = netdev_priv(dev);
1532 struct adapter *adap = pi->adapter;
1533
1534 return set_rxq_intr_params(adap, &adap->sge.ethrxq[pi->first_qset].rspq,
1535 c->rx_coalesce_usecs, c->rx_max_coalesced_frames);
1536}
1537
1538static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1539{
1540 const struct port_info *pi = netdev_priv(dev);
1541 const struct adapter *adap = pi->adapter;
1542 const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
1543
1544 c->rx_coalesce_usecs = qtimer_val(adap, rq);
1545 c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN) ?
1546 adap->sge.counter_val[rq->pktcnt_idx] : 0;
1547 return 0;
1548}
1549
1550/*
1551 * Translate a physical EEPROM address to virtual. The first 1K is accessed
1552 * through virtual addresses starting at 31K, the rest is accessed through
1553 * virtual addresses starting at 0. This mapping is correct only for PF0.
1554 */
1555static int eeprom_ptov(unsigned int phys_addr)
1556{
1557 if (phys_addr < 1024)
1558 return phys_addr + (31 << 10);
1559 if (phys_addr < EEPROMSIZE)
1560 return phys_addr - 1024;
1561 return -EINVAL;
1562}
1563
1564/*
1565 * The next two routines implement eeprom read/write from physical addresses.
1566 * The physical->virtual translation is correct only for PF0.
1567 */
1568static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
1569{
1570 int vaddr = eeprom_ptov(phys_addr);
1571
1572 if (vaddr >= 0)
1573 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
1574 return vaddr < 0 ? vaddr : 0;
1575}
1576
1577static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
1578{
1579 int vaddr = eeprom_ptov(phys_addr);
1580
1581 if (vaddr >= 0)
1582 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
1583 return vaddr < 0 ? vaddr : 0;
1584}
1585
1586#define EEPROM_MAGIC 0x38E2F10C
1587
1588static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
1589 u8 *data)
1590{
1591 int i, err = 0;
1592 struct adapter *adapter = netdev2adap(dev);
1593
1594 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
1595 if (!buf)
1596 return -ENOMEM;
1597
1598 e->magic = EEPROM_MAGIC;
1599 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
1600 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
1601
1602 if (!err)
1603 memcpy(data, buf + e->offset, e->len);
1604 kfree(buf);
1605 return err;
1606}
1607
1608static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
1609 u8 *data)
1610{
1611 u8 *buf;
1612 int err = 0;
1613 u32 aligned_offset, aligned_len, *p;
1614 struct adapter *adapter = netdev2adap(dev);
1615
1616 if (eeprom->magic != EEPROM_MAGIC)
1617 return -EINVAL;
1618
1619 aligned_offset = eeprom->offset & ~3;
1620 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
1621
1622 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
1623 /*
1624 * RMW possibly needed for first or last words.
1625 */
1626 buf = kmalloc(aligned_len, GFP_KERNEL);
1627 if (!buf)
1628 return -ENOMEM;
1629 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1630 if (!err && aligned_len > 4)
1631 err = eeprom_rd_phys(adapter,
1632 aligned_offset + aligned_len - 4,
1633 (u32 *)&buf[aligned_len - 4]);
1634 if (err)
1635 goto out;
1636 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
1637 } else
1638 buf = data;
1639
1640 err = t4_seeprom_wp(adapter, false);
1641 if (err)
1642 goto out;
1643
1644 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1645 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1646 aligned_offset += 4;
1647 }
1648
1649 if (!err)
1650 err = t4_seeprom_wp(adapter, true);
1651out:
1652 if (buf != data)
1653 kfree(buf);
1654 return err;
1655}
1656
1657static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
1658{
1659 int ret;
1660 const struct firmware *fw;
1661 struct adapter *adap = netdev2adap(netdev);
1662
1663 ef->data[sizeof(ef->data) - 1] = '\0';
1664 ret = request_firmware(&fw, ef->data, adap->pdev_dev);
1665 if (ret < 0)
1666 return ret;
1667
1668 ret = t4_load_fw(adap, fw->data, fw->size);
1669 release_firmware(fw);
1670 if (!ret)
1671 dev_info(adap->pdev_dev, "loaded firmware %s\n", ef->data);
1672 return ret;
1673}
1674
1675#define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
1676#define BCAST_CRC 0xa0ccc1a6
1677
1678static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1679{
1680 wol->supported = WAKE_BCAST | WAKE_MAGIC;
1681 wol->wolopts = netdev2adap(dev)->wol;
1682 memset(&wol->sopass, 0, sizeof(wol->sopass));
1683}
1684
1685static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1686{
1687 int err = 0;
1688 struct port_info *pi = netdev_priv(dev);
1689
1690 if (wol->wolopts & ~WOL_SUPPORTED)
1691 return -EINVAL;
1692 t4_wol_magic_enable(pi->adapter, pi->tx_chan,
1693 (wol->wolopts & WAKE_MAGIC) ? dev->dev_addr : NULL);
1694 if (wol->wolopts & WAKE_BCAST) {
1695 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0xfe, ~0ULL,
1696 ~0ULL, 0, false);
1697 if (!err)
1698 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 1,
1699 ~6ULL, ~0ULL, BCAST_CRC, true);
1700 } else
1701 t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0, 0, 0, 0, false);
1702 return err;
1703}
1704
1705static int set_tso(struct net_device *dev, u32 value)
1706{
1707 if (value)
1708 dev->features |= NETIF_F_TSO | NETIF_F_TSO6;
1709 else
1710 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
1711 return 0;
1712}
1713
1714static int set_flags(struct net_device *dev, u32 flags)
1715{
1716 if (flags & ~ETH_FLAG_RXHASH)
1717 return -EOPNOTSUPP;
1718
1719 if (flags & ETH_FLAG_RXHASH)
1720 dev->features |= NETIF_F_RXHASH;
1721 else
1722 dev->features &= ~NETIF_F_RXHASH;
1723 return 0;
1724}
1725
1726static struct ethtool_ops cxgb_ethtool_ops = {
1727 .get_settings = get_settings,
1728 .set_settings = set_settings,
1729 .get_drvinfo = get_drvinfo,
1730 .get_msglevel = get_msglevel,
1731 .set_msglevel = set_msglevel,
1732 .get_ringparam = get_sge_param,
1733 .set_ringparam = set_sge_param,
1734 .get_coalesce = get_coalesce,
1735 .set_coalesce = set_coalesce,
1736 .get_eeprom_len = get_eeprom_len,
1737 .get_eeprom = get_eeprom,
1738 .set_eeprom = set_eeprom,
1739 .get_pauseparam = get_pauseparam,
1740 .set_pauseparam = set_pauseparam,
1741 .get_rx_csum = get_rx_csum,
1742 .set_rx_csum = set_rx_csum,
1743 .set_tx_csum = ethtool_op_set_tx_ipv6_csum,
1744 .set_sg = ethtool_op_set_sg,
1745 .get_link = ethtool_op_get_link,
1746 .get_strings = get_strings,
1747 .phys_id = identify_port,
1748 .nway_reset = restart_autoneg,
1749 .get_sset_count = get_sset_count,
1750 .get_ethtool_stats = get_stats,
1751 .get_regs_len = get_regs_len,
1752 .get_regs = get_regs,
1753 .get_wol = get_wol,
1754 .set_wol = set_wol,
1755 .set_tso = set_tso,
1756 .set_flags = set_flags,
1757 .flash_device = set_flash,
1758};
1759
1760/*
1761 * debugfs support
1762 */
1763
1764static int mem_open(struct inode *inode, struct file *file)
1765{
1766 file->private_data = inode->i_private;
1767 return 0;
1768}
1769
1770static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
1771 loff_t *ppos)
1772{
1773 loff_t pos = *ppos;
1774 loff_t avail = file->f_path.dentry->d_inode->i_size;
1775 unsigned int mem = (uintptr_t)file->private_data & 3;
1776 struct adapter *adap = file->private_data - mem;
1777
1778 if (pos < 0)
1779 return -EINVAL;
1780 if (pos >= avail)
1781 return 0;
1782 if (count > avail - pos)
1783 count = avail - pos;
1784
1785 while (count) {
1786 size_t len;
1787 int ret, ofst;
1788 __be32 data[16];
1789
1790 if (mem == MEM_MC)
1791 ret = t4_mc_read(adap, pos, data, NULL);
1792 else
1793 ret = t4_edc_read(adap, mem, pos, data, NULL);
1794 if (ret)
1795 return ret;
1796
1797 ofst = pos % sizeof(data);
1798 len = min(count, sizeof(data) - ofst);
1799 if (copy_to_user(buf, (u8 *)data + ofst, len))
1800 return -EFAULT;
1801
1802 buf += len;
1803 pos += len;
1804 count -= len;
1805 }
1806 count = pos - *ppos;
1807 *ppos = pos;
1808 return count;
1809}
1810
1811static const struct file_operations mem_debugfs_fops = {
1812 .owner = THIS_MODULE,
1813 .open = mem_open,
1814 .read = mem_read,
1815};
1816
1817static void __devinit add_debugfs_mem(struct adapter *adap, const char *name,
1818 unsigned int idx, unsigned int size_mb)
1819{
1820 struct dentry *de;
1821
1822 de = debugfs_create_file(name, S_IRUSR, adap->debugfs_root,
1823 (void *)adap + idx, &mem_debugfs_fops);
1824 if (de && de->d_inode)
1825 de->d_inode->i_size = size_mb << 20;
1826}
1827
1828static int __devinit setup_debugfs(struct adapter *adap)
1829{
1830 int i;
1831
1832 if (IS_ERR_OR_NULL(adap->debugfs_root))
1833 return -1;
1834
1835 i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE);
1836 if (i & EDRAM0_ENABLE)
1837 add_debugfs_mem(adap, "edc0", MEM_EDC0, 5);
1838 if (i & EDRAM1_ENABLE)
1839 add_debugfs_mem(adap, "edc1", MEM_EDC1, 5);
1840 if (i & EXT_MEM_ENABLE)
1841 add_debugfs_mem(adap, "mc", MEM_MC,
1842 EXT_MEM_SIZE_GET(t4_read_reg(adap, MA_EXT_MEMORY_BAR)));
1843 if (adap->l2t)
1844 debugfs_create_file("l2t", S_IRUSR, adap->debugfs_root, adap,
1845 &t4_l2t_fops);
1846 return 0;
1847}
1848
1849/*
1850 * upper-layer driver support
1851 */
1852
1853/*
1854 * Allocate an active-open TID and set it to the supplied value.
1855 */
1856int cxgb4_alloc_atid(struct tid_info *t, void *data)
1857{
1858 int atid = -1;
1859
1860 spin_lock_bh(&t->atid_lock);
1861 if (t->afree) {
1862 union aopen_entry *p = t->afree;
1863
1864 atid = p - t->atid_tab;
1865 t->afree = p->next;
1866 p->data = data;
1867 t->atids_in_use++;
1868 }
1869 spin_unlock_bh(&t->atid_lock);
1870 return atid;
1871}
1872EXPORT_SYMBOL(cxgb4_alloc_atid);
1873
1874/*
1875 * Release an active-open TID.
1876 */
1877void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1878{
1879 union aopen_entry *p = &t->atid_tab[atid];
1880
1881 spin_lock_bh(&t->atid_lock);
1882 p->next = t->afree;
1883 t->afree = p;
1884 t->atids_in_use--;
1885 spin_unlock_bh(&t->atid_lock);
1886}
1887EXPORT_SYMBOL(cxgb4_free_atid);
1888
1889/*
1890 * Allocate a server TID and set it to the supplied value.
1891 */
1892int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1893{
1894 int stid;
1895
1896 spin_lock_bh(&t->stid_lock);
1897 if (family == PF_INET) {
1898 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1899 if (stid < t->nstids)
1900 __set_bit(stid, t->stid_bmap);
1901 else
1902 stid = -1;
1903 } else {
1904 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
1905 if (stid < 0)
1906 stid = -1;
1907 }
1908 if (stid >= 0) {
1909 t->stid_tab[stid].data = data;
1910 stid += t->stid_base;
1911 t->stids_in_use++;
1912 }
1913 spin_unlock_bh(&t->stid_lock);
1914 return stid;
1915}
1916EXPORT_SYMBOL(cxgb4_alloc_stid);
1917
1918/*
1919 * Release a server TID.
1920 */
1921void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1922{
1923 stid -= t->stid_base;
1924 spin_lock_bh(&t->stid_lock);
1925 if (family == PF_INET)
1926 __clear_bit(stid, t->stid_bmap);
1927 else
1928 bitmap_release_region(t->stid_bmap, stid, 2);
1929 t->stid_tab[stid].data = NULL;
1930 t->stids_in_use--;
1931 spin_unlock_bh(&t->stid_lock);
1932}
1933EXPORT_SYMBOL(cxgb4_free_stid);
1934
1935/*
1936 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1937 */
1938static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1939 unsigned int tid)
1940{
1941 struct cpl_tid_release *req;
1942
1943 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1944 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
1945 INIT_TP_WR(req, tid);
1946 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1947}
1948
1949/*
1950 * Queue a TID release request and if necessary schedule a work queue to
1951 * process it.
1952 */
1953void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1954 unsigned int tid)
1955{
1956 void **p = &t->tid_tab[tid];
1957 struct adapter *adap = container_of(t, struct adapter, tids);
1958
1959 spin_lock_bh(&adap->tid_release_lock);
1960 *p = adap->tid_release_head;
1961 /* Low 2 bits encode the Tx channel number */
1962 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1963 if (!adap->tid_release_task_busy) {
1964 adap->tid_release_task_busy = true;
1965 schedule_work(&adap->tid_release_task);
1966 }
1967 spin_unlock_bh(&adap->tid_release_lock);
1968}
1969EXPORT_SYMBOL(cxgb4_queue_tid_release);
1970
1971/*
1972 * Process the list of pending TID release requests.
1973 */
1974static void process_tid_release_list(struct work_struct *work)
1975{
1976 struct sk_buff *skb;
1977 struct adapter *adap;
1978
1979 adap = container_of(work, struct adapter, tid_release_task);
1980
1981 spin_lock_bh(&adap->tid_release_lock);
1982 while (adap->tid_release_head) {
1983 void **p = adap->tid_release_head;
1984 unsigned int chan = (uintptr_t)p & 3;
1985 p = (void *)p - chan;
1986
1987 adap->tid_release_head = *p;
1988 *p = NULL;
1989 spin_unlock_bh(&adap->tid_release_lock);
1990
1991 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1992 GFP_KERNEL)))
1993 schedule_timeout_uninterruptible(1);
1994
1995 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1996 t4_ofld_send(adap, skb);
1997 spin_lock_bh(&adap->tid_release_lock);
1998 }
1999 adap->tid_release_task_busy = false;
2000 spin_unlock_bh(&adap->tid_release_lock);
2001}
2002
2003/*
2004 * Release a TID and inform HW. If we are unable to allocate the release
2005 * message we defer to a work queue.
2006 */
2007void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
2008{
2009 void *old;
2010 struct sk_buff *skb;
2011 struct adapter *adap = container_of(t, struct adapter, tids);
2012
2013 old = t->tid_tab[tid];
2014 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
2015 if (likely(skb)) {
2016 t->tid_tab[tid] = NULL;
2017 mk_tid_release(skb, chan, tid);
2018 t4_ofld_send(adap, skb);
2019 } else
2020 cxgb4_queue_tid_release(t, chan, tid);
2021 if (old)
2022 atomic_dec(&t->tids_in_use);
2023}
2024EXPORT_SYMBOL(cxgb4_remove_tid);
2025
2026/*
2027 * Allocate and initialize the TID tables. Returns 0 on success.
2028 */
2029static int tid_init(struct tid_info *t)
2030{
2031 size_t size;
2032 unsigned int natids = t->natids;
2033
2034 size = t->ntids * sizeof(*t->tid_tab) + natids * sizeof(*t->atid_tab) +
2035 t->nstids * sizeof(*t->stid_tab) +
2036 BITS_TO_LONGS(t->nstids) * sizeof(long);
2037 t->tid_tab = t4_alloc_mem(size);
2038 if (!t->tid_tab)
2039 return -ENOMEM;
2040
2041 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
2042 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
2043 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids];
2044 spin_lock_init(&t->stid_lock);
2045 spin_lock_init(&t->atid_lock);
2046
2047 t->stids_in_use = 0;
2048 t->afree = NULL;
2049 t->atids_in_use = 0;
2050 atomic_set(&t->tids_in_use, 0);
2051
2052 /* Setup the free list for atid_tab and clear the stid bitmap. */
2053 if (natids) {
2054 while (--natids)
2055 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
2056 t->afree = t->atid_tab;
2057 }
2058 bitmap_zero(t->stid_bmap, t->nstids);
2059 return 0;
2060}
2061
2062/**
2063 * cxgb4_create_server - create an IP server
2064 * @dev: the device
2065 * @stid: the server TID
2066 * @sip: local IP address to bind server to
2067 * @sport: the server's TCP port
2068 * @queue: queue to direct messages from this server to
2069 *
2070 * Create an IP server for the given port and address.
2071 * Returns <0 on error and one of the %NET_XMIT_* values on success.
2072 */
2073int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
2074 __be32 sip, __be16 sport, unsigned int queue)
2075{
2076 unsigned int chan;
2077 struct sk_buff *skb;
2078 struct adapter *adap;
2079 struct cpl_pass_open_req *req;
2080
2081 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
2082 if (!skb)
2083 return -ENOMEM;
2084
2085 adap = netdev2adap(dev);
2086 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
2087 INIT_TP_WR(req, 0);
2088 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
2089 req->local_port = sport;
2090 req->peer_port = htons(0);
2091 req->local_ip = sip;
2092 req->peer_ip = htonl(0);
2093 chan = netdev2pinfo(adap->sge.ingr_map[queue]->netdev)->tx_chan;
2094 req->opt0 = cpu_to_be64(TX_CHAN(chan));
2095 req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
2096 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
2097 return t4_mgmt_tx(adap, skb);
2098}
2099EXPORT_SYMBOL(cxgb4_create_server);
2100
2101/**
2102 * cxgb4_create_server6 - create an IPv6 server
2103 * @dev: the device
2104 * @stid: the server TID
2105 * @sip: local IPv6 address to bind server to
2106 * @sport: the server's TCP port
2107 * @queue: queue to direct messages from this server to
2108 *
2109 * Create an IPv6 server for the given port and address.
2110 * Returns <0 on error and one of the %NET_XMIT_* values on success.
2111 */
2112int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
2113 const struct in6_addr *sip, __be16 sport,
2114 unsigned int queue)
2115{
2116 unsigned int chan;
2117 struct sk_buff *skb;
2118 struct adapter *adap;
2119 struct cpl_pass_open_req6 *req;
2120
2121 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
2122 if (!skb)
2123 return -ENOMEM;
2124
2125 adap = netdev2adap(dev);
2126 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
2127 INIT_TP_WR(req, 0);
2128 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
2129 req->local_port = sport;
2130 req->peer_port = htons(0);
2131 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
2132 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
2133 req->peer_ip_hi = cpu_to_be64(0);
2134 req->peer_ip_lo = cpu_to_be64(0);
2135 chan = netdev2pinfo(adap->sge.ingr_map[queue]->netdev)->tx_chan;
2136 req->opt0 = cpu_to_be64(TX_CHAN(chan));
2137 req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
2138 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
2139 return t4_mgmt_tx(adap, skb);
2140}
2141EXPORT_SYMBOL(cxgb4_create_server6);
2142
2143/**
2144 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
2145 * @mtus: the HW MTU table
2146 * @mtu: the target MTU
2147 * @idx: index of selected entry in the MTU table
2148 *
2149 * Returns the index and the value in the HW MTU table that is closest to
2150 * but does not exceed @mtu, unless @mtu is smaller than any value in the
2151 * table, in which case that smallest available value is selected.
2152 */
2153unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
2154 unsigned int *idx)
2155{
2156 unsigned int i = 0;
2157
2158 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
2159 ++i;
2160 if (idx)
2161 *idx = i;
2162 return mtus[i];
2163}
2164EXPORT_SYMBOL(cxgb4_best_mtu);
2165
2166/**
2167 * cxgb4_port_chan - get the HW channel of a port
2168 * @dev: the net device for the port
2169 *
2170 * Return the HW Tx channel of the given port.
2171 */
2172unsigned int cxgb4_port_chan(const struct net_device *dev)
2173{
2174 return netdev2pinfo(dev)->tx_chan;
2175}
2176EXPORT_SYMBOL(cxgb4_port_chan);
2177
2178/**
2179 * cxgb4_port_viid - get the VI id of a port
2180 * @dev: the net device for the port
2181 *
2182 * Return the VI id of the given port.
2183 */
2184unsigned int cxgb4_port_viid(const struct net_device *dev)
2185{
2186 return netdev2pinfo(dev)->viid;
2187}
2188EXPORT_SYMBOL(cxgb4_port_viid);
2189
2190/**
2191 * cxgb4_port_idx - get the index of a port
2192 * @dev: the net device for the port
2193 *
2194 * Return the index of the given port.
2195 */
2196unsigned int cxgb4_port_idx(const struct net_device *dev)
2197{
2198 return netdev2pinfo(dev)->port_id;
2199}
2200EXPORT_SYMBOL(cxgb4_port_idx);
2201
2202/**
2203 * cxgb4_netdev_by_hwid - return the net device of a HW port
2204 * @pdev: identifies the adapter
2205 * @id: the HW port id
2206 *
2207 * Return the net device associated with the interface with the given HW
2208 * id.
2209 */
2210struct net_device *cxgb4_netdev_by_hwid(struct pci_dev *pdev, unsigned int id)
2211{
2212 const struct adapter *adap = pci_get_drvdata(pdev);
2213
2214 if (!adap || id >= NCHAN)
2215 return NULL;
2216 id = adap->chan_map[id];
2217 return id < MAX_NPORTS ? adap->port[id] : NULL;
2218}
2219EXPORT_SYMBOL(cxgb4_netdev_by_hwid);
2220
2221void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
2222 struct tp_tcp_stats *v6)
2223{
2224 struct adapter *adap = pci_get_drvdata(pdev);
2225
2226 spin_lock(&adap->stats_lock);
2227 t4_tp_get_tcp_stats(adap, v4, v6);
2228 spin_unlock(&adap->stats_lock);
2229}
2230EXPORT_SYMBOL(cxgb4_get_tcp_stats);
2231
2232void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
2233 const unsigned int *pgsz_order)
2234{
2235 struct adapter *adap = netdev2adap(dev);
2236
2237 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK, tag_mask);
2238 t4_write_reg(adap, ULP_RX_ISCSI_PSZ, HPZ0(pgsz_order[0]) |
2239 HPZ1(pgsz_order[1]) | HPZ2(pgsz_order[2]) |
2240 HPZ3(pgsz_order[3]));
2241}
2242EXPORT_SYMBOL(cxgb4_iscsi_init);
2243
2244static struct pci_driver cxgb4_driver;
2245
2246static void check_neigh_update(struct neighbour *neigh)
2247{
2248 const struct device *parent;
2249 const struct net_device *netdev = neigh->dev;
2250
2251 if (netdev->priv_flags & IFF_802_1Q_VLAN)
2252 netdev = vlan_dev_real_dev(netdev);
2253 parent = netdev->dev.parent;
2254 if (parent && parent->driver == &cxgb4_driver.driver)
2255 t4_l2t_update(dev_get_drvdata(parent), neigh);
2256}
2257
2258static int netevent_cb(struct notifier_block *nb, unsigned long event,
2259 void *data)
2260{
2261 switch (event) {
2262 case NETEVENT_NEIGH_UPDATE:
2263 check_neigh_update(data);
2264 break;
2265 case NETEVENT_PMTU_UPDATE:
2266 case NETEVENT_REDIRECT:
2267 default:
2268 break;
2269 }
2270 return 0;
2271}
2272
2273static bool netevent_registered;
2274static struct notifier_block cxgb4_netevent_nb = {
2275 .notifier_call = netevent_cb
2276};
2277
2278static void uld_attach(struct adapter *adap, unsigned int uld)
2279{
2280 void *handle;
2281 struct cxgb4_lld_info lli;
2282
2283 lli.pdev = adap->pdev;
2284 lli.l2t = adap->l2t;
2285 lli.tids = &adap->tids;
2286 lli.ports = adap->port;
2287 lli.vr = &adap->vres;
2288 lli.mtus = adap->params.mtus;
2289 if (uld == CXGB4_ULD_RDMA) {
2290 lli.rxq_ids = adap->sge.rdma_rxq;
2291 lli.nrxq = adap->sge.rdmaqs;
2292 } else if (uld == CXGB4_ULD_ISCSI) {
2293 lli.rxq_ids = adap->sge.ofld_rxq;
2294 lli.nrxq = adap->sge.ofldqsets;
2295 }
2296 lli.ntxq = adap->sge.ofldqsets;
2297 lli.nchan = adap->params.nports;
2298 lli.nports = adap->params.nports;
2299 lli.wr_cred = adap->params.ofldq_wr_cred;
2300 lli.adapter_type = adap->params.rev;
2301 lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2));
2302 lli.udb_density = 1 << QUEUESPERPAGEPF0_GET(
2303 t4_read_reg(adap, SGE_EGRESS_QUEUES_PER_PAGE_PF));
2304 lli.ucq_density = 1 << QUEUESPERPAGEPF0_GET(
2305 t4_read_reg(adap, SGE_INGRESS_QUEUES_PER_PAGE_PF));
2306 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);
2307 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
2308 lli.fw_vers = adap->params.fw_vers;
2309
2310 handle = ulds[uld].add(&lli);
2311 if (IS_ERR(handle)) {
2312 dev_warn(adap->pdev_dev,
2313 "could not attach to the %s driver, error %ld\n",
2314 uld_str[uld], PTR_ERR(handle));
2315 return;
2316 }
2317
2318 adap->uld_handle[uld] = handle;
2319
2320 if (!netevent_registered) {
2321 register_netevent_notifier(&cxgb4_netevent_nb);
2322 netevent_registered = true;
2323 }
2324}
2325
2326static void attach_ulds(struct adapter *adap)
2327{
2328 unsigned int i;
2329
2330 mutex_lock(&uld_mutex);
2331 list_add_tail(&adap->list_node, &adapter_list);
2332 for (i = 0; i < CXGB4_ULD_MAX; i++)
2333 if (ulds[i].add)
2334 uld_attach(adap, i);
2335 mutex_unlock(&uld_mutex);
2336}
2337
2338static void detach_ulds(struct adapter *adap)
2339{
2340 unsigned int i;
2341
2342 mutex_lock(&uld_mutex);
2343 list_del(&adap->list_node);
2344 for (i = 0; i < CXGB4_ULD_MAX; i++)
2345 if (adap->uld_handle[i]) {
2346 ulds[i].state_change(adap->uld_handle[i],
2347 CXGB4_STATE_DETACH);
2348 adap->uld_handle[i] = NULL;
2349 }
2350 if (netevent_registered && list_empty(&adapter_list)) {
2351 unregister_netevent_notifier(&cxgb4_netevent_nb);
2352 netevent_registered = false;
2353 }
2354 mutex_unlock(&uld_mutex);
2355}
2356
2357static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2358{
2359 unsigned int i;
2360
2361 mutex_lock(&uld_mutex);
2362 for (i = 0; i < CXGB4_ULD_MAX; i++)
2363 if (adap->uld_handle[i])
2364 ulds[i].state_change(adap->uld_handle[i], new_state);
2365 mutex_unlock(&uld_mutex);
2366}
2367
2368/**
2369 * cxgb4_register_uld - register an upper-layer driver
2370 * @type: the ULD type
2371 * @p: the ULD methods
2372 *
2373 * Registers an upper-layer driver with this driver and notifies the ULD
2374 * about any presently available devices that support its type. Returns
2375 * %-EBUSY if a ULD of the same type is already registered.
2376 */
2377int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
2378{
2379 int ret = 0;
2380 struct adapter *adap;
2381
2382 if (type >= CXGB4_ULD_MAX)
2383 return -EINVAL;
2384 mutex_lock(&uld_mutex);
2385 if (ulds[type].add) {
2386 ret = -EBUSY;
2387 goto out;
2388 }
2389 ulds[type] = *p;
2390 list_for_each_entry(adap, &adapter_list, list_node)
2391 uld_attach(adap, type);
2392out: mutex_unlock(&uld_mutex);
2393 return ret;
2394}
2395EXPORT_SYMBOL(cxgb4_register_uld);
2396
2397/**
2398 * cxgb4_unregister_uld - unregister an upper-layer driver
2399 * @type: the ULD type
2400 *
2401 * Unregisters an existing upper-layer driver.
2402 */
2403int cxgb4_unregister_uld(enum cxgb4_uld type)
2404{
2405 struct adapter *adap;
2406
2407 if (type >= CXGB4_ULD_MAX)
2408 return -EINVAL;
2409 mutex_lock(&uld_mutex);
2410 list_for_each_entry(adap, &adapter_list, list_node)
2411 adap->uld_handle[type] = NULL;
2412 ulds[type].add = NULL;
2413 mutex_unlock(&uld_mutex);
2414 return 0;
2415}
2416EXPORT_SYMBOL(cxgb4_unregister_uld);
2417
2418/**
2419 * cxgb_up - enable the adapter
2420 * @adap: adapter being enabled
2421 *
2422 * Called when the first port is enabled, this function performs the
2423 * actions necessary to make an adapter operational, such as completing
2424 * the initialization of HW modules, and enabling interrupts.
2425 *
2426 * Must be called with the rtnl lock held.
2427 */
2428static int cxgb_up(struct adapter *adap)
2429{
2430 int err = 0;
2431
2432 if (!(adap->flags & FULL_INIT_DONE)) {
2433 err = setup_sge_queues(adap);
2434 if (err)
2435 goto out;
2436 err = setup_rss(adap);
2437 if (err) {
2438 t4_free_sge_resources(adap);
2439 goto out;
2440 }
2441 if (adap->flags & USING_MSIX)
2442 name_msix_vecs(adap);
2443 adap->flags |= FULL_INIT_DONE;
2444 }
2445
2446 if (adap->flags & USING_MSIX) {
2447 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2448 adap->msix_info[0].desc, adap);
2449 if (err)
2450 goto irq_err;
2451
2452 err = request_msix_queue_irqs(adap);
2453 if (err) {
2454 free_irq(adap->msix_info[0].vec, adap);
2455 goto irq_err;
2456 }
2457 } else {
2458 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2459 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
2460 adap->name, adap);
2461 if (err)
2462 goto irq_err;
2463 }
2464 enable_rx(adap);
2465 t4_sge_start(adap);
2466 t4_intr_enable(adap);
2467 notify_ulds(adap, CXGB4_STATE_UP);
2468 out:
2469 return err;
2470 irq_err:
2471 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2472 goto out;
2473}
2474
2475static void cxgb_down(struct adapter *adapter)
2476{
2477 t4_intr_disable(adapter);
2478 cancel_work_sync(&adapter->tid_release_task);
2479 adapter->tid_release_task_busy = false;
2480
2481 if (adapter->flags & USING_MSIX) {
2482 free_msix_queue_irqs(adapter);
2483 free_irq(adapter->msix_info[0].vec, adapter);
2484 } else
2485 free_irq(adapter->pdev->irq, adapter);
2486 quiesce_rx(adapter);
2487}
2488
2489/*
2490 * net_device operations
2491 */
2492static int cxgb_open(struct net_device *dev)
2493{
2494 int err;
2495 struct port_info *pi = netdev_priv(dev);
2496 struct adapter *adapter = pi->adapter;
2497
2498 if (!adapter->open_device_map && (err = cxgb_up(adapter)) < 0)
2499 return err;
2500
2501 dev->real_num_tx_queues = pi->nqsets;
2502 set_bit(pi->tx_chan, &adapter->open_device_map);
2503 link_start(dev);
2504 netif_tx_start_all_queues(dev);
2505 return 0;
2506}
2507
2508static int cxgb_close(struct net_device *dev)
2509{
2510 int ret;
2511 struct port_info *pi = netdev_priv(dev);
2512 struct adapter *adapter = pi->adapter;
2513
2514 netif_tx_stop_all_queues(dev);
2515 netif_carrier_off(dev);
2516 ret = t4_enable_vi(adapter, 0, pi->viid, false, false);
2517
2518 clear_bit(pi->tx_chan, &adapter->open_device_map);
2519
2520 if (!adapter->open_device_map)
2521 cxgb_down(adapter);
2522 return 0;
2523}
2524
2525static struct net_device_stats *cxgb_get_stats(struct net_device *dev)
2526{
2527 struct port_stats stats;
2528 struct port_info *p = netdev_priv(dev);
2529 struct adapter *adapter = p->adapter;
2530 struct net_device_stats *ns = &dev->stats;
2531
2532 spin_lock(&adapter->stats_lock);
2533 t4_get_port_stats(adapter, p->tx_chan, &stats);
2534 spin_unlock(&adapter->stats_lock);
2535
2536 ns->tx_bytes = stats.tx_octets;
2537 ns->tx_packets = stats.tx_frames;
2538 ns->rx_bytes = stats.rx_octets;
2539 ns->rx_packets = stats.rx_frames;
2540 ns->multicast = stats.rx_mcast_frames;
2541
2542 /* detailed rx_errors */
2543 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2544 stats.rx_runt;
2545 ns->rx_over_errors = 0;
2546 ns->rx_crc_errors = stats.rx_fcs_err;
2547 ns->rx_frame_errors = stats.rx_symbol_err;
2548 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
2549 stats.rx_ovflow2 + stats.rx_ovflow3 +
2550 stats.rx_trunc0 + stats.rx_trunc1 +
2551 stats.rx_trunc2 + stats.rx_trunc3;
2552 ns->rx_missed_errors = 0;
2553
2554 /* detailed tx_errors */
2555 ns->tx_aborted_errors = 0;
2556 ns->tx_carrier_errors = 0;
2557 ns->tx_fifo_errors = 0;
2558 ns->tx_heartbeat_errors = 0;
2559 ns->tx_window_errors = 0;
2560
2561 ns->tx_errors = stats.tx_error_frames;
2562 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2563 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2564 return ns;
2565}
2566
2567static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2568{
2569 int ret = 0, prtad, devad;
2570 struct port_info *pi = netdev_priv(dev);
2571 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2572
2573 switch (cmd) {
2574 case SIOCGMIIPHY:
2575 if (pi->mdio_addr < 0)
2576 return -EOPNOTSUPP;
2577 data->phy_id = pi->mdio_addr;
2578 break;
2579 case SIOCGMIIREG:
2580 case SIOCSMIIREG:
2581 if (mdio_phy_id_is_c45(data->phy_id)) {
2582 prtad = mdio_phy_id_prtad(data->phy_id);
2583 devad = mdio_phy_id_devad(data->phy_id);
2584 } else if (data->phy_id < 32) {
2585 prtad = data->phy_id;
2586 devad = 0;
2587 data->reg_num &= 0x1f;
2588 } else
2589 return -EINVAL;
2590
2591 if (cmd == SIOCGMIIREG)
2592 ret = t4_mdio_rd(pi->adapter, 0, prtad, devad,
2593 data->reg_num, &data->val_out);
2594 else
2595 ret = t4_mdio_wr(pi->adapter, 0, prtad, devad,
2596 data->reg_num, data->val_in);
2597 break;
2598 default:
2599 return -EOPNOTSUPP;
2600 }
2601 return ret;
2602}
2603
2604static void cxgb_set_rxmode(struct net_device *dev)
2605{
2606 /* unfortunately we can't return errors to the stack */
2607 set_rxmode(dev, -1, false);
2608}
2609
2610static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2611{
2612 int ret;
2613 struct port_info *pi = netdev_priv(dev);
2614
2615 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
2616 return -EINVAL;
2617 ret = t4_set_rxmode(pi->adapter, 0, pi->viid, new_mtu, -1, -1, -1,
2618 true);
2619 if (!ret)
2620 dev->mtu = new_mtu;
2621 return ret;
2622}
2623
2624static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2625{
2626 int ret;
2627 struct sockaddr *addr = p;
2628 struct port_info *pi = netdev_priv(dev);
2629
2630 if (!is_valid_ether_addr(addr->sa_data))
2631 return -EINVAL;
2632
2633 ret = t4_change_mac(pi->adapter, 0, pi->viid, pi->xact_addr_filt,
2634 addr->sa_data, true, true);
2635 if (ret < 0)
2636 return ret;
2637
2638 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2639 pi->xact_addr_filt = ret;
2640 return 0;
2641}
2642
2643static void vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2644{
2645 struct port_info *pi = netdev_priv(dev);
2646
2647 pi->vlan_grp = grp;
2648 t4_set_vlan_accel(pi->adapter, 1 << pi->tx_chan, grp != NULL);
2649}
2650
2651#ifdef CONFIG_NET_POLL_CONTROLLER
2652static void cxgb_netpoll(struct net_device *dev)
2653{
2654 struct port_info *pi = netdev_priv(dev);
2655 struct adapter *adap = pi->adapter;
2656
2657 if (adap->flags & USING_MSIX) {
2658 int i;
2659 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
2660
2661 for (i = pi->nqsets; i; i--, rx++)
2662 t4_sge_intr_msix(0, &rx->rspq);
2663 } else
2664 t4_intr_handler(adap)(0, adap);
2665}
2666#endif
2667
2668static const struct net_device_ops cxgb4_netdev_ops = {
2669 .ndo_open = cxgb_open,
2670 .ndo_stop = cxgb_close,
2671 .ndo_start_xmit = t4_eth_xmit,
2672 .ndo_get_stats = cxgb_get_stats,
2673 .ndo_set_rx_mode = cxgb_set_rxmode,
2674 .ndo_set_mac_address = cxgb_set_mac_addr,
2675 .ndo_validate_addr = eth_validate_addr,
2676 .ndo_do_ioctl = cxgb_ioctl,
2677 .ndo_change_mtu = cxgb_change_mtu,
2678 .ndo_vlan_rx_register = vlan_rx_register,
2679#ifdef CONFIG_NET_POLL_CONTROLLER
2680 .ndo_poll_controller = cxgb_netpoll,
2681#endif
2682};
2683
2684void t4_fatal_err(struct adapter *adap)
2685{
2686 t4_set_reg_field(adap, SGE_CONTROL, GLOBALENABLE, 0);
2687 t4_intr_disable(adap);
2688 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
2689}
2690
2691static void setup_memwin(struct adapter *adap)
2692{
2693 u32 bar0;
2694
2695 bar0 = pci_resource_start(adap->pdev, 0); /* truncation intentional */
2696 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
2697 (bar0 + MEMWIN0_BASE) | BIR(0) |
2698 WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
2699 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
2700 (bar0 + MEMWIN1_BASE) | BIR(0) |
2701 WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
2702 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
2703 (bar0 + MEMWIN2_BASE) | BIR(0) |
2704 WINDOW(ilog2(MEMWIN2_APERTURE) - 10));
2705}
2706
2707/*
2708 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
2709 */
2710#define MAX_ATIDS 8192U
2711
2712/*
2713 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
2714 */
2715static int adap_init0(struct adapter *adap)
2716{
2717 int ret;
2718 u32 v, port_vec;
2719 enum dev_state state;
2720 u32 params[7], val[7];
2721 struct fw_caps_config_cmd c;
2722
2723 ret = t4_check_fw_version(adap);
2724 if (ret == -EINVAL || ret > 0) {
2725 if (upgrade_fw(adap) >= 0) /* recache FW version */
2726 ret = t4_check_fw_version(adap);
2727 }
2728 if (ret < 0)
2729 return ret;
2730
2731 /* contact FW, request master */
2732 ret = t4_fw_hello(adap, 0, 0, MASTER_MUST, &state);
2733 if (ret < 0) {
2734 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
2735 ret);
2736 return ret;
2737 }
2738
2739 /* reset device */
2740 ret = t4_fw_reset(adap, 0, PIORSTMODE | PIORST);
2741 if (ret < 0)
2742 goto bye;
2743
2744 /* get device capabilities */
2745 memset(&c, 0, sizeof(c));
2746 c.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2747 FW_CMD_REQUEST | FW_CMD_READ);
2748 c.retval_len16 = htonl(FW_LEN16(c));
2749 ret = t4_wr_mbox(adap, 0, &c, sizeof(c), &c);
2750 if (ret < 0)
2751 goto bye;
2752
2753 /* select capabilities we'll be using */
2754 if (c.niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
2755 if (!vf_acls)
2756 c.niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
2757 else
2758 c.niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
2759 } else if (vf_acls) {
2760 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
2761 goto bye;
2762 }
2763 c.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2764 FW_CMD_REQUEST | FW_CMD_WRITE);
2765 ret = t4_wr_mbox(adap, 0, &c, sizeof(c), NULL);
2766 if (ret < 0)
2767 goto bye;
2768
2769 ret = t4_config_glbl_rss(adap, 0,
2770 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
2771 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
2772 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP);
2773 if (ret < 0)
2774 goto bye;
2775
2776 ret = t4_cfg_pfvf(adap, 0, 0, 0, 64, 64, 64, 0, 0, 4, 0xf, 0xf, 16,
2777 FW_CMD_CAP_PF, FW_CMD_CAP_PF);
2778 if (ret < 0)
2779 goto bye;
2780
2781 for (v = 0; v < SGE_NTIMERS - 1; v++)
2782 adap->sge.timer_val[v] = min(intr_holdoff[v], MAX_SGE_TIMERVAL);
2783 adap->sge.timer_val[SGE_NTIMERS - 1] = MAX_SGE_TIMERVAL;
2784 adap->sge.counter_val[0] = 1;
2785 for (v = 1; v < SGE_NCOUNTERS; v++)
2786 adap->sge.counter_val[v] = min(intr_cnt[v - 1],
2787 THRESHOLD_3_MASK);
2788 t4_sge_init(adap);
2789
2790 /* get basic stuff going */
2791 ret = t4_early_init(adap, 0);
2792 if (ret < 0)
2793 goto bye;
2794
2795#define FW_PARAM_DEV(param) \
2796 (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
2797 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
2798
2799#define FW_PARAM_PFVF(param) \
2800 (FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
2801 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
2802
2803 params[0] = FW_PARAM_DEV(PORTVEC);
2804 params[1] = FW_PARAM_PFVF(L2T_START);
2805 params[2] = FW_PARAM_PFVF(L2T_END);
2806 params[3] = FW_PARAM_PFVF(FILTER_START);
2807 params[4] = FW_PARAM_PFVF(FILTER_END);
2808 ret = t4_query_params(adap, 0, 0, 0, 5, params, val);
2809 if (ret < 0)
2810 goto bye;
2811 port_vec = val[0];
2812 adap->tids.ftid_base = val[3];
2813 adap->tids.nftids = val[4] - val[3] + 1;
2814
2815 if (c.ofldcaps) {
2816 /* query offload-related parameters */
2817 params[0] = FW_PARAM_DEV(NTID);
2818 params[1] = FW_PARAM_PFVF(SERVER_START);
2819 params[2] = FW_PARAM_PFVF(SERVER_END);
2820 params[3] = FW_PARAM_PFVF(TDDP_START);
2821 params[4] = FW_PARAM_PFVF(TDDP_END);
2822 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
2823 ret = t4_query_params(adap, 0, 0, 0, 6, params, val);
2824 if (ret < 0)
2825 goto bye;
2826 adap->tids.ntids = val[0];
2827 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
2828 adap->tids.stid_base = val[1];
2829 adap->tids.nstids = val[2] - val[1] + 1;
2830 adap->vres.ddp.start = val[3];
2831 adap->vres.ddp.size = val[4] - val[3] + 1;
2832 adap->params.ofldq_wr_cred = val[5];
2833 adap->params.offload = 1;
2834 }
2835 if (c.rdmacaps) {
2836 params[0] = FW_PARAM_PFVF(STAG_START);
2837 params[1] = FW_PARAM_PFVF(STAG_END);
2838 params[2] = FW_PARAM_PFVF(RQ_START);
2839 params[3] = FW_PARAM_PFVF(RQ_END);
2840 params[4] = FW_PARAM_PFVF(PBL_START);
2841 params[5] = FW_PARAM_PFVF(PBL_END);
2842 ret = t4_query_params(adap, 0, 0, 0, 6, params, val);
2843 if (ret < 0)
2844 goto bye;
2845 adap->vres.stag.start = val[0];
2846 adap->vres.stag.size = val[1] - val[0] + 1;
2847 adap->vres.rq.start = val[2];
2848 adap->vres.rq.size = val[3] - val[2] + 1;
2849 adap->vres.pbl.start = val[4];
2850 adap->vres.pbl.size = val[5] - val[4] + 1;
2851 }
2852 if (c.iscsicaps) {
2853 params[0] = FW_PARAM_PFVF(ISCSI_START);
2854 params[1] = FW_PARAM_PFVF(ISCSI_END);
2855 ret = t4_query_params(adap, 0, 0, 0, 2, params, val);
2856 if (ret < 0)
2857 goto bye;
2858 adap->vres.iscsi.start = val[0];
2859 adap->vres.iscsi.size = val[1] - val[0] + 1;
2860 }
2861#undef FW_PARAM_PFVF
2862#undef FW_PARAM_DEV
2863
2864 adap->params.nports = hweight32(port_vec);
2865 adap->params.portvec = port_vec;
2866 adap->flags |= FW_OK;
2867
2868 /* These are finalized by FW initialization, load their values now */
2869 v = t4_read_reg(adap, TP_TIMER_RESOLUTION);
2870 adap->params.tp.tre = TIMERRESOLUTION_GET(v);
2871 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
2872 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
2873 adap->params.b_wnd);
2874
2875 /* tweak some settings */
2876 t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849);
2877 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
2878 t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
2879 v = t4_read_reg(adap, TP_PIO_DATA);
2880 t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
2881 setup_memwin(adap);
2882 return 0;
2883
2884 /*
2885 * If a command timed out or failed with EIO FW does not operate within
2886 * its spec or something catastrophic happened to HW/FW, stop issuing
2887 * commands.
2888 */
2889bye: if (ret != -ETIMEDOUT && ret != -EIO)
2890 t4_fw_bye(adap, 0);
2891 return ret;
2892}
2893
2894static inline bool is_10g_port(const struct link_config *lc)
2895{
2896 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0;
2897}
2898
2899static inline void init_rspq(struct sge_rspq *q, u8 timer_idx, u8 pkt_cnt_idx,
2900 unsigned int size, unsigned int iqe_size)
2901{
2902 q->intr_params = QINTR_TIMER_IDX(timer_idx) |
2903 (pkt_cnt_idx < SGE_NCOUNTERS ? QINTR_CNT_EN : 0);
2904 q->pktcnt_idx = pkt_cnt_idx < SGE_NCOUNTERS ? pkt_cnt_idx : 0;
2905 q->iqe_len = iqe_size;
2906 q->size = size;
2907}
2908
2909/*
2910 * Perform default configuration of DMA queues depending on the number and type
2911 * of ports we found and the number of available CPUs. Most settings can be
2912 * modified by the admin prior to actual use.
2913 */
2914static void __devinit cfg_queues(struct adapter *adap)
2915{
2916 struct sge *s = &adap->sge;
2917 int i, q10g = 0, n10g = 0, qidx = 0;
2918
2919 for_each_port(adap, i)
2920 n10g += is_10g_port(&adap2pinfo(adap, i)->link_cfg);
2921
2922 /*
2923 * We default to 1 queue per non-10G port and up to # of cores queues
2924 * per 10G port.
2925 */
2926 if (n10g)
2927 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
2928 if (q10g > num_online_cpus())
2929 q10g = num_online_cpus();
2930
2931 for_each_port(adap, i) {
2932 struct port_info *pi = adap2pinfo(adap, i);
2933
2934 pi->first_qset = qidx;
2935 pi->nqsets = is_10g_port(&pi->link_cfg) ? q10g : 1;
2936 qidx += pi->nqsets;
2937 }
2938
2939 s->ethqsets = qidx;
2940 s->max_ethqsets = qidx; /* MSI-X may lower it later */
2941
2942 if (is_offload(adap)) {
2943 /*
2944 * For offload we use 1 queue/channel if all ports are up to 1G,
2945 * otherwise we divide all available queues amongst the channels
2946 * capped by the number of available cores.
2947 */
2948 if (n10g) {
2949 i = min_t(int, ARRAY_SIZE(s->ofldrxq),
2950 num_online_cpus());
2951 s->ofldqsets = roundup(i, adap->params.nports);
2952 } else
2953 s->ofldqsets = adap->params.nports;
2954 /* For RDMA one Rx queue per channel suffices */
2955 s->rdmaqs = adap->params.nports;
2956 }
2957
2958 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
2959 struct sge_eth_rxq *r = &s->ethrxq[i];
2960
2961 init_rspq(&r->rspq, 0, 0, 1024, 64);
2962 r->fl.size = 72;
2963 }
2964
2965 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
2966 s->ethtxq[i].q.size = 1024;
2967
2968 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
2969 s->ctrlq[i].q.size = 512;
2970
2971 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
2972 s->ofldtxq[i].q.size = 1024;
2973
2974 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
2975 struct sge_ofld_rxq *r = &s->ofldrxq[i];
2976
2977 init_rspq(&r->rspq, 0, 0, 1024, 64);
2978 r->rspq.uld = CXGB4_ULD_ISCSI;
2979 r->fl.size = 72;
2980 }
2981
2982 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
2983 struct sge_ofld_rxq *r = &s->rdmarxq[i];
2984
2985 init_rspq(&r->rspq, 0, 0, 511, 64);
2986 r->rspq.uld = CXGB4_ULD_RDMA;
2987 r->fl.size = 72;
2988 }
2989
2990 init_rspq(&s->fw_evtq, 6, 0, 512, 64);
2991 init_rspq(&s->intrq, 6, 0, 2 * MAX_INGQ, 64);
2992}
2993
2994/*
2995 * Reduce the number of Ethernet queues across all ports to at most n.
2996 * n provides at least one queue per port.
2997 */
2998static void __devinit reduce_ethqs(struct adapter *adap, int n)
2999{
3000 int i;
3001 struct port_info *pi;
3002
3003 while (n < adap->sge.ethqsets)
3004 for_each_port(adap, i) {
3005 pi = adap2pinfo(adap, i);
3006 if (pi->nqsets > 1) {
3007 pi->nqsets--;
3008 adap->sge.ethqsets--;
3009 if (adap->sge.ethqsets <= n)
3010 break;
3011 }
3012 }
3013
3014 n = 0;
3015 for_each_port(adap, i) {
3016 pi = adap2pinfo(adap, i);
3017 pi->first_qset = n;
3018 n += pi->nqsets;
3019 }
3020}
3021
3022/* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
3023#define EXTRA_VECS 2
3024
3025static int __devinit enable_msix(struct adapter *adap)
3026{
3027 int ofld_need = 0;
3028 int i, err, want, need;
3029 struct sge *s = &adap->sge;
3030 unsigned int nchan = adap->params.nports;
3031 struct msix_entry entries[MAX_INGQ + 1];
3032
3033 for (i = 0; i < ARRAY_SIZE(entries); ++i)
3034 entries[i].entry = i;
3035
3036 want = s->max_ethqsets + EXTRA_VECS;
3037 if (is_offload(adap)) {
3038 want += s->rdmaqs + s->ofldqsets;
3039 /* need nchan for each possible ULD */
3040 ofld_need = 2 * nchan;
3041 }
3042 need = adap->params.nports + EXTRA_VECS + ofld_need;
3043
3044 while ((err = pci_enable_msix(adap->pdev, entries, want)) >= need)
3045 want = err;
3046
3047 if (!err) {
3048 /*
3049 * Distribute available vectors to the various queue groups.
3050 * Every group gets its minimum requirement and NIC gets top
3051 * priority for leftovers.
3052 */
3053 i = want - EXTRA_VECS - ofld_need;
3054 if (i < s->max_ethqsets) {
3055 s->max_ethqsets = i;
3056 if (i < s->ethqsets)
3057 reduce_ethqs(adap, i);
3058 }
3059 if (is_offload(adap)) {
3060 i = want - EXTRA_VECS - s->max_ethqsets;
3061 i -= ofld_need - nchan;
3062 s->ofldqsets = (i / nchan) * nchan; /* round down */
3063 }
3064 for (i = 0; i < want; ++i)
3065 adap->msix_info[i].vec = entries[i].vector;
3066 } else if (err > 0)
3067 dev_info(adap->pdev_dev,
3068 "only %d MSI-X vectors left, not using MSI-X\n", err);
3069 return err;
3070}
3071
3072#undef EXTRA_VECS
3073
3074static void __devinit print_port_info(struct adapter *adap)
3075{
3076 static const char *base[] = {
3077 "R", "KX4", "T", "KX", "T", "KR", "CX4"
3078 };
3079
3080 int i;
3081 char buf[80];
3082
3083 for_each_port(adap, i) {
3084 struct net_device *dev = adap->port[i];
3085 const struct port_info *pi = netdev_priv(dev);
3086 char *bufp = buf;
3087
3088 if (!test_bit(i, &adap->registered_device_map))
3089 continue;
3090
3091 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
3092 bufp += sprintf(bufp, "100/");
3093 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
3094 bufp += sprintf(bufp, "1000/");
3095 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
3096 bufp += sprintf(bufp, "10G/");
3097 if (bufp != buf)
3098 --bufp;
3099 sprintf(bufp, "BASE-%s", base[pi->port_type]);
3100
3101 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s\n",
3102 adap->params.vpd.id, adap->params.rev,
3103 buf, is_offload(adap) ? "R" : "",
3104 adap->params.pci.width,
3105 (adap->flags & USING_MSIX) ? " MSI-X" :
3106 (adap->flags & USING_MSI) ? " MSI" : "");
3107 if (adap->name == dev->name)
3108 netdev_info(dev, "S/N: %s, E/C: %s\n",
3109 adap->params.vpd.sn, adap->params.vpd.ec);
3110 }
3111}
3112
3113#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | NETIF_F_TSO6 |\
3114 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
3115
3116static int __devinit init_one(struct pci_dev *pdev,
3117 const struct pci_device_id *ent)
3118{
3119 int func, i, err;
3120 struct port_info *pi;
3121 unsigned int highdma = 0;
3122 struct adapter *adapter = NULL;
3123
3124 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
3125
3126 err = pci_request_regions(pdev, KBUILD_MODNAME);
3127 if (err) {
3128 /* Just info, some other driver may have claimed the device. */
3129 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
3130 return err;
3131 }
3132
3133 /* We control everything through PF 0 */
3134 func = PCI_FUNC(pdev->devfn);
3135 if (func > 0)
3136 goto sriov;
3137
3138 err = pci_enable_device(pdev);
3139 if (err) {
3140 dev_err(&pdev->dev, "cannot enable PCI device\n");
3141 goto out_release_regions;
3142 }
3143
3144 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3145 highdma = NETIF_F_HIGHDMA;
3146 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3147 if (err) {
3148 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
3149 "coherent allocations\n");
3150 goto out_disable_device;
3151 }
3152 } else {
3153 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3154 if (err) {
3155 dev_err(&pdev->dev, "no usable DMA configuration\n");
3156 goto out_disable_device;
3157 }
3158 }
3159
3160 pci_enable_pcie_error_reporting(pdev);
3161 pci_set_master(pdev);
3162 pci_save_state(pdev);
3163
3164 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
3165 if (!adapter) {
3166 err = -ENOMEM;
3167 goto out_disable_device;
3168 }
3169
3170 adapter->regs = pci_ioremap_bar(pdev, 0);
3171 if (!adapter->regs) {
3172 dev_err(&pdev->dev, "cannot map device registers\n");
3173 err = -ENOMEM;
3174 goto out_free_adapter;
3175 }
3176
3177 adapter->pdev = pdev;
3178 adapter->pdev_dev = &pdev->dev;
3179 adapter->name = pci_name(pdev);
3180 adapter->msg_enable = dflt_msg_enable;
3181 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
3182
3183 spin_lock_init(&adapter->stats_lock);
3184 spin_lock_init(&adapter->tid_release_lock);
3185
3186 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
3187
3188 err = t4_prep_adapter(adapter);
3189 if (err)
3190 goto out_unmap_bar;
3191 err = adap_init0(adapter);
3192 if (err)
3193 goto out_unmap_bar;
3194
3195 for_each_port(adapter, i) {
3196 struct net_device *netdev;
3197
3198 netdev = alloc_etherdev_mq(sizeof(struct port_info),
3199 MAX_ETH_QSETS);
3200 if (!netdev) {
3201 err = -ENOMEM;
3202 goto out_free_dev;
3203 }
3204
3205 SET_NETDEV_DEV(netdev, &pdev->dev);
3206
3207 adapter->port[i] = netdev;
3208 pi = netdev_priv(netdev);
3209 pi->adapter = adapter;
3210 pi->xact_addr_filt = -1;
3211 pi->rx_offload = RX_CSO;
3212 pi->port_id = i;
3213 netif_carrier_off(netdev);
3214 netif_tx_stop_all_queues(netdev);
3215 netdev->irq = pdev->irq;
3216
3217 netdev->features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
3218 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3219 netdev->features |= NETIF_F_GRO | NETIF_F_RXHASH | highdma;
3220 netdev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3221 netdev->vlan_features = netdev->features & VLAN_FEAT;
3222
3223 netdev->netdev_ops = &cxgb4_netdev_ops;
3224 SET_ETHTOOL_OPS(netdev, &cxgb_ethtool_ops);
3225 }
3226
3227 pci_set_drvdata(pdev, adapter);
3228
3229 if (adapter->flags & FW_OK) {
3230 err = t4_port_init(adapter, 0, 0, 0);
3231 if (err)
3232 goto out_free_dev;
3233 }
3234
3235 /*
3236 * Configure queues and allocate tables now, they can be needed as
3237 * soon as the first register_netdev completes.
3238 */
3239 cfg_queues(adapter);
3240
3241 adapter->l2t = t4_init_l2t();
3242 if (!adapter->l2t) {
3243 /* We tolerate a lack of L2T, giving up some functionality */
3244 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
3245 adapter->params.offload = 0;
3246 }
3247
3248 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
3249 dev_warn(&pdev->dev, "could not allocate TID table, "
3250 "continuing\n");
3251 adapter->params.offload = 0;
3252 }
3253
3254 /*
3255 * The card is now ready to go. If any errors occur during device
3256 * registration we do not fail the whole card but rather proceed only
3257 * with the ports we manage to register successfully. However we must
3258 * register at least one net device.
3259 */
3260 for_each_port(adapter, i) {
3261 err = register_netdev(adapter->port[i]);
3262 if (err)
3263 dev_warn(&pdev->dev,
3264 "cannot register net device %s, skipping\n",
3265 adapter->port[i]->name);
3266 else {
3267 /*
3268 * Change the name we use for messages to the name of
3269 * the first successfully registered interface.
3270 */
3271 if (!adapter->registered_device_map)
3272 adapter->name = adapter->port[i]->name;
3273
3274 __set_bit(i, &adapter->registered_device_map);
3275 adapter->chan_map[adap2pinfo(adapter, i)->tx_chan] = i;
3276 }
3277 }
3278 if (!adapter->registered_device_map) {
3279 dev_err(&pdev->dev, "could not register any net devices\n");
3280 goto out_free_dev;
3281 }
3282
3283 if (cxgb4_debugfs_root) {
3284 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
3285 cxgb4_debugfs_root);
3286 setup_debugfs(adapter);
3287 }
3288
3289 /* See what interrupts we'll be using */
3290 if (msi > 1 && enable_msix(adapter) == 0)
3291 adapter->flags |= USING_MSIX;
3292 else if (msi > 0 && pci_enable_msi(pdev) == 0)
3293 adapter->flags |= USING_MSI;
3294
3295 if (is_offload(adapter))
3296 attach_ulds(adapter);
3297
3298 print_port_info(adapter);
3299
3300sriov:
3301#ifdef CONFIG_PCI_IOV
3302 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
3303 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
3304 dev_info(&pdev->dev,
3305 "instantiated %u virtual functions\n",
3306 num_vf[func]);
3307#endif
3308 return 0;
3309
3310 out_free_dev:
3311 t4_free_mem(adapter->tids.tid_tab);
3312 t4_free_mem(adapter->l2t);
3313 for_each_port(adapter, i)
3314 if (adapter->port[i])
3315 free_netdev(adapter->port[i]);
3316 if (adapter->flags & FW_OK)
3317 t4_fw_bye(adapter, 0);
3318 out_unmap_bar:
3319 iounmap(adapter->regs);
3320 out_free_adapter:
3321 kfree(adapter);
3322 out_disable_device:
3323 pci_disable_pcie_error_reporting(pdev);
3324 pci_disable_device(pdev);
3325 out_release_regions:
3326 pci_release_regions(pdev);
3327 pci_set_drvdata(pdev, NULL);
3328 return err;
3329}
3330
3331static void __devexit remove_one(struct pci_dev *pdev)
3332{
3333 struct adapter *adapter = pci_get_drvdata(pdev);
3334
3335 pci_disable_sriov(pdev);
3336
3337 if (adapter) {
3338 int i;
3339
3340 if (is_offload(adapter))
3341 detach_ulds(adapter);
3342
3343 for_each_port(adapter, i)
3344 if (test_bit(i, &adapter->registered_device_map))
3345 unregister_netdev(adapter->port[i]);
3346
3347 if (adapter->debugfs_root)
3348 debugfs_remove_recursive(adapter->debugfs_root);
3349
3350 t4_sge_stop(adapter);
3351 t4_free_sge_resources(adapter);
3352 t4_free_mem(adapter->l2t);
3353 t4_free_mem(adapter->tids.tid_tab);
3354 disable_msi(adapter);
3355
3356 for_each_port(adapter, i)
3357 if (adapter->port[i])
3358 free_netdev(adapter->port[i]);
3359
3360 if (adapter->flags & FW_OK)
3361 t4_fw_bye(adapter, 0);
3362 iounmap(adapter->regs);
3363 kfree(adapter);
3364 pci_disable_pcie_error_reporting(pdev);
3365 pci_disable_device(pdev);
3366 pci_release_regions(pdev);
3367 pci_set_drvdata(pdev, NULL);
3368 } else if (PCI_FUNC(pdev->devfn) > 0)
3369 pci_release_regions(pdev);
3370}
3371
3372static struct pci_driver cxgb4_driver = {
3373 .name = KBUILD_MODNAME,
3374 .id_table = cxgb4_pci_tbl,
3375 .probe = init_one,
3376 .remove = __devexit_p(remove_one),
3377};
3378
3379static int __init cxgb4_init_module(void)
3380{
3381 int ret;
3382
3383 /* Debugfs support is optional, just warn if this fails */
3384 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
3385 if (!cxgb4_debugfs_root)
3386 pr_warning("could not create debugfs entry, continuing\n");
3387
3388 ret = pci_register_driver(&cxgb4_driver);
3389 if (ret < 0)
3390 debugfs_remove(cxgb4_debugfs_root);
3391 return ret;
3392}
3393
3394static void __exit cxgb4_cleanup_module(void)
3395{
3396 pci_unregister_driver(&cxgb4_driver);
3397 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
3398}
3399
3400module_init(cxgb4_init_module);
3401module_exit(cxgb4_cleanup_module);
diff --git a/drivers/net/cxgb4/cxgb4_uld.h b/drivers/net/cxgb4/cxgb4_uld.h
new file mode 100644
index 000000000000..5b98546ac92d
--- /dev/null
+++ b/drivers/net/cxgb4/cxgb4_uld.h
@@ -0,0 +1,239 @@
1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_OFLD_H
36#define __CXGB4_OFLD_H
37
38#include <linux/cache.h>
39#include <linux/spinlock.h>
40#include <linux/skbuff.h>
41#include <asm/atomic.h>
42
43/* CPL message priority levels */
44enum {
45 CPL_PRIORITY_DATA = 0, /* data messages */
46 CPL_PRIORITY_SETUP = 1, /* connection setup messages */
47 CPL_PRIORITY_TEARDOWN = 0, /* connection teardown messages */
48 CPL_PRIORITY_LISTEN = 1, /* listen start/stop messages */
49 CPL_PRIORITY_ACK = 1, /* RX ACK messages */
50 CPL_PRIORITY_CONTROL = 1 /* control messages */
51};
52
53#define INIT_TP_WR(w, tid) do { \
54 (w)->wr.wr_hi = htonl(FW_WR_OP(FW_TP_WR) | \
55 FW_WR_IMMDLEN(sizeof(*w) - sizeof(w->wr))); \
56 (w)->wr.wr_mid = htonl(FW_WR_LEN16(DIV_ROUND_UP(sizeof(*w), 16)) | \
57 FW_WR_FLOWID(tid)); \
58 (w)->wr.wr_lo = cpu_to_be64(0); \
59} while (0)
60
61#define INIT_TP_WR_CPL(w, cpl, tid) do { \
62 INIT_TP_WR(w, tid); \
63 OPCODE_TID(w) = htonl(MK_OPCODE_TID(cpl, tid)); \
64} while (0)
65
66#define INIT_ULPTX_WR(w, wrlen, atomic, tid) do { \
67 (w)->wr.wr_hi = htonl(FW_WR_OP(FW_ULPTX_WR) | FW_WR_ATOMIC(atomic)); \
68 (w)->wr.wr_mid = htonl(FW_WR_LEN16(DIV_ROUND_UP(wrlen, 16)) | \
69 FW_WR_FLOWID(tid)); \
70 (w)->wr.wr_lo = cpu_to_be64(0); \
71} while (0)
72
73/* Special asynchronous notification message */
74#define CXGB4_MSG_AN ((void *)1)
75
76struct serv_entry {
77 void *data;
78};
79
80union aopen_entry {
81 void *data;
82 union aopen_entry *next;
83};
84
85/*
86 * Holds the size, base address, free list start, etc of the TID, server TID,
87 * and active-open TID tables. The tables themselves are allocated dynamically.
88 */
89struct tid_info {
90 void **tid_tab;
91 unsigned int ntids;
92
93 struct serv_entry *stid_tab;
94 unsigned long *stid_bmap;
95 unsigned int nstids;
96 unsigned int stid_base;
97
98 union aopen_entry *atid_tab;
99 unsigned int natids;
100
101 unsigned int nftids;
102 unsigned int ftid_base;
103
104 spinlock_t atid_lock ____cacheline_aligned_in_smp;
105 union aopen_entry *afree;
106 unsigned int atids_in_use;
107
108 spinlock_t stid_lock;
109 unsigned int stids_in_use;
110
111 atomic_t tids_in_use;
112};
113
114static inline void *lookup_tid(const struct tid_info *t, unsigned int tid)
115{
116 return tid < t->ntids ? t->tid_tab[tid] : NULL;
117}
118
119static inline void *lookup_atid(const struct tid_info *t, unsigned int atid)
120{
121 return atid < t->natids ? t->atid_tab[atid].data : NULL;
122}
123
124static inline void *lookup_stid(const struct tid_info *t, unsigned int stid)
125{
126 stid -= t->stid_base;
127 return stid < t->nstids ? t->stid_tab[stid].data : NULL;
128}
129
130static inline void cxgb4_insert_tid(struct tid_info *t, void *data,
131 unsigned int tid)
132{
133 t->tid_tab[tid] = data;
134 atomic_inc(&t->tids_in_use);
135}
136
137int cxgb4_alloc_atid(struct tid_info *t, void *data);
138int cxgb4_alloc_stid(struct tid_info *t, int family, void *data);
139void cxgb4_free_atid(struct tid_info *t, unsigned int atid);
140void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family);
141void cxgb4_remove_tid(struct tid_info *t, unsigned int qid, unsigned int tid);
142void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
143 unsigned int tid);
144
145struct in6_addr;
146
147int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
148 __be32 sip, __be16 sport, unsigned int queue);
149int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
150 const struct in6_addr *sip, __be16 sport,
151 unsigned int queue);
152
153static inline void set_wr_txq(struct sk_buff *skb, int prio, int queue)
154{
155 skb_set_queue_mapping(skb, (queue << 1) | prio);
156}
157
158enum cxgb4_uld {
159 CXGB4_ULD_RDMA,
160 CXGB4_ULD_ISCSI,
161 CXGB4_ULD_MAX
162};
163
164enum cxgb4_state {
165 CXGB4_STATE_UP,
166 CXGB4_STATE_START_RECOVERY,
167 CXGB4_STATE_DOWN,
168 CXGB4_STATE_DETACH
169};
170
171struct pci_dev;
172struct l2t_data;
173struct net_device;
174struct pkt_gl;
175struct tp_tcp_stats;
176
177struct cxgb4_range {
178 unsigned int start;
179 unsigned int size;
180};
181
182struct cxgb4_virt_res { /* virtualized HW resources */
183 struct cxgb4_range ddp;
184 struct cxgb4_range iscsi;
185 struct cxgb4_range stag;
186 struct cxgb4_range rq;
187 struct cxgb4_range pbl;
188};
189
190/*
191 * Block of information the LLD provides to ULDs attaching to a device.
192 */
193struct cxgb4_lld_info {
194 struct pci_dev *pdev; /* associated PCI device */
195 struct l2t_data *l2t; /* L2 table */
196 struct tid_info *tids; /* TID table */
197 struct net_device **ports; /* device ports */
198 const struct cxgb4_virt_res *vr; /* assorted HW resources */
199 const unsigned short *mtus; /* MTU table */
200 const unsigned short *rxq_ids; /* the ULD's Rx queue ids */
201 unsigned short nrxq; /* # of Rx queues */
202 unsigned short ntxq; /* # of Tx queues */
203 unsigned char nchan:4; /* # of channels */
204 unsigned char nports:4; /* # of ports */
205 unsigned char wr_cred; /* WR 16-byte credits */
206 unsigned char adapter_type; /* type of adapter */
207 unsigned char fw_api_ver; /* FW API version */
208 unsigned int fw_vers; /* FW version */
209 unsigned int iscsi_iolen; /* iSCSI max I/O length */
210 unsigned short udb_density; /* # of user DB/page */
211 unsigned short ucq_density; /* # of user CQs/page */
212 void __iomem *gts_reg; /* address of GTS register */
213 void __iomem *db_reg; /* address of kernel doorbell */
214};
215
216struct cxgb4_uld_info {
217 const char *name;
218 void *(*add)(const struct cxgb4_lld_info *p);
219 int (*rx_handler)(void *handle, const __be64 *rsp,
220 const struct pkt_gl *gl);
221 int (*state_change)(void *handle, enum cxgb4_state new_state);
222};
223
224int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p);
225int cxgb4_unregister_uld(enum cxgb4_uld type);
226int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb);
227unsigned int cxgb4_port_chan(const struct net_device *dev);
228unsigned int cxgb4_port_viid(const struct net_device *dev);
229unsigned int cxgb4_port_idx(const struct net_device *dev);
230struct net_device *cxgb4_netdev_by_hwid(struct pci_dev *pdev, unsigned int id);
231unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
232 unsigned int *idx);
233void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
234 struct tp_tcp_stats *v6);
235void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
236 const unsigned int *pgsz_order);
237struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl,
238 unsigned int skb_len, unsigned int pull_len);
239#endif /* !__CXGB4_OFLD_H */
diff --git a/drivers/net/cxgb4/l2t.c b/drivers/net/cxgb4/l2t.c
new file mode 100644
index 000000000000..9f96724a133a
--- /dev/null
+++ b/drivers/net/cxgb4/l2t.c
@@ -0,0 +1,624 @@
1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/skbuff.h>
36#include <linux/netdevice.h>
37#include <linux/if.h>
38#include <linux/if_vlan.h>
39#include <linux/jhash.h>
40#include <net/neighbour.h>
41#include "cxgb4.h"
42#include "l2t.h"
43#include "t4_msg.h"
44#include "t4fw_api.h"
45
46#define VLAN_NONE 0xfff
47
48/* identifies sync vs async L2T_WRITE_REQs */
49#define F_SYNC_WR (1 << 12)
50
51enum {
52 L2T_STATE_VALID, /* entry is up to date */
53 L2T_STATE_STALE, /* entry may be used but needs revalidation */
54 L2T_STATE_RESOLVING, /* entry needs address resolution */
55 L2T_STATE_SYNC_WRITE, /* synchronous write of entry underway */
56
57 /* when state is one of the below the entry is not hashed */
58 L2T_STATE_SWITCHING, /* entry is being used by a switching filter */
59 L2T_STATE_UNUSED /* entry not in use */
60};
61
62struct l2t_data {
63 rwlock_t lock;
64 atomic_t nfree; /* number of free entries */
65 struct l2t_entry *rover; /* starting point for next allocation */
66 struct l2t_entry l2tab[L2T_SIZE];
67};
68
69static inline unsigned int vlan_prio(const struct l2t_entry *e)
70{
71 return e->vlan >> 13;
72}
73
74static inline void l2t_hold(struct l2t_data *d, struct l2t_entry *e)
75{
76 if (atomic_add_return(1, &e->refcnt) == 1) /* 0 -> 1 transition */
77 atomic_dec(&d->nfree);
78}
79
80/*
81 * To avoid having to check address families we do not allow v4 and v6
82 * neighbors to be on the same hash chain. We keep v4 entries in the first
83 * half of available hash buckets and v6 in the second.
84 */
85enum {
86 L2T_SZ_HALF = L2T_SIZE / 2,
87 L2T_HASH_MASK = L2T_SZ_HALF - 1
88};
89
90static inline unsigned int arp_hash(const u32 *key, int ifindex)
91{
92 return jhash_2words(*key, ifindex, 0) & L2T_HASH_MASK;
93}
94
95static inline unsigned int ipv6_hash(const u32 *key, int ifindex)
96{
97 u32 xor = key[0] ^ key[1] ^ key[2] ^ key[3];
98
99 return L2T_SZ_HALF + (jhash_2words(xor, ifindex, 0) & L2T_HASH_MASK);
100}
101
102static unsigned int addr_hash(const u32 *addr, int addr_len, int ifindex)
103{
104 return addr_len == 4 ? arp_hash(addr, ifindex) :
105 ipv6_hash(addr, ifindex);
106}
107
108/*
109 * Checks if an L2T entry is for the given IP/IPv6 address. It does not check
110 * whether the L2T entry and the address are of the same address family.
111 * Callers ensure an address is only checked against L2T entries of the same
112 * family, something made trivial by the separation of IP and IPv6 hash chains
113 * mentioned above. Returns 0 if there's a match,
114 */
115static int addreq(const struct l2t_entry *e, const u32 *addr)
116{
117 if (e->v6)
118 return (e->addr[0] ^ addr[0]) | (e->addr[1] ^ addr[1]) |
119 (e->addr[2] ^ addr[2]) | (e->addr[3] ^ addr[3]);
120 return e->addr[0] ^ addr[0];
121}
122
123static void neigh_replace(struct l2t_entry *e, struct neighbour *n)
124{
125 neigh_hold(n);
126 if (e->neigh)
127 neigh_release(e->neigh);
128 e->neigh = n;
129}
130
131/*
132 * Write an L2T entry. Must be called with the entry locked.
133 * The write may be synchronous or asynchronous.
134 */
135static int write_l2e(struct adapter *adap, struct l2t_entry *e, int sync)
136{
137 struct sk_buff *skb;
138 struct cpl_l2t_write_req *req;
139
140 skb = alloc_skb(sizeof(*req), GFP_ATOMIC);
141 if (!skb)
142 return -ENOMEM;
143
144 req = (struct cpl_l2t_write_req *)__skb_put(skb, sizeof(*req));
145 INIT_TP_WR(req, 0);
146
147 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ,
148 e->idx | (sync ? F_SYNC_WR : 0) |
149 TID_QID(adap->sge.fw_evtq.abs_id)));
150 req->params = htons(L2T_W_PORT(e->lport) | L2T_W_NOREPLY(!sync));
151 req->l2t_idx = htons(e->idx);
152 req->vlan = htons(e->vlan);
153 if (e->neigh)
154 memcpy(e->dmac, e->neigh->ha, sizeof(e->dmac));
155 memcpy(req->dst_mac, e->dmac, sizeof(req->dst_mac));
156
157 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
158 t4_ofld_send(adap, skb);
159
160 if (sync && e->state != L2T_STATE_SWITCHING)
161 e->state = L2T_STATE_SYNC_WRITE;
162 return 0;
163}
164
165/*
166 * Send packets waiting in an L2T entry's ARP queue. Must be called with the
167 * entry locked.
168 */
169static void send_pending(struct adapter *adap, struct l2t_entry *e)
170{
171 while (e->arpq_head) {
172 struct sk_buff *skb = e->arpq_head;
173
174 e->arpq_head = skb->next;
175 skb->next = NULL;
176 t4_ofld_send(adap, skb);
177 }
178 e->arpq_tail = NULL;
179}
180
181/*
182 * Process a CPL_L2T_WRITE_RPL. Wake up the ARP queue if it completes a
183 * synchronous L2T_WRITE. Note that the TID in the reply is really the L2T
184 * index it refers to.
185 */
186void do_l2t_write_rpl(struct adapter *adap, const struct cpl_l2t_write_rpl *rpl)
187{
188 unsigned int tid = GET_TID(rpl);
189 unsigned int idx = tid & (L2T_SIZE - 1);
190
191 if (unlikely(rpl->status != CPL_ERR_NONE)) {
192 dev_err(adap->pdev_dev,
193 "Unexpected L2T_WRITE_RPL status %u for entry %u\n",
194 rpl->status, idx);
195 return;
196 }
197
198 if (tid & F_SYNC_WR) {
199 struct l2t_entry *e = &adap->l2t->l2tab[idx];
200
201 spin_lock(&e->lock);
202 if (e->state != L2T_STATE_SWITCHING) {
203 send_pending(adap, e);
204 e->state = (e->neigh->nud_state & NUD_STALE) ?
205 L2T_STATE_STALE : L2T_STATE_VALID;
206 }
207 spin_unlock(&e->lock);
208 }
209}
210
211/*
212 * Add a packet to an L2T entry's queue of packets awaiting resolution.
213 * Must be called with the entry's lock held.
214 */
215static inline void arpq_enqueue(struct l2t_entry *e, struct sk_buff *skb)
216{
217 skb->next = NULL;
218 if (e->arpq_head)
219 e->arpq_tail->next = skb;
220 else
221 e->arpq_head = skb;
222 e->arpq_tail = skb;
223}
224
225int cxgb4_l2t_send(struct net_device *dev, struct sk_buff *skb,
226 struct l2t_entry *e)
227{
228 struct adapter *adap = netdev2adap(dev);
229
230again:
231 switch (e->state) {
232 case L2T_STATE_STALE: /* entry is stale, kick off revalidation */
233 neigh_event_send(e->neigh, NULL);
234 spin_lock_bh(&e->lock);
235 if (e->state == L2T_STATE_STALE)
236 e->state = L2T_STATE_VALID;
237 spin_unlock_bh(&e->lock);
238 case L2T_STATE_VALID: /* fast-path, send the packet on */
239 return t4_ofld_send(adap, skb);
240 case L2T_STATE_RESOLVING:
241 case L2T_STATE_SYNC_WRITE:
242 spin_lock_bh(&e->lock);
243 if (e->state != L2T_STATE_SYNC_WRITE &&
244 e->state != L2T_STATE_RESOLVING) {
245 spin_unlock_bh(&e->lock);
246 goto again;
247 }
248 arpq_enqueue(e, skb);
249 spin_unlock_bh(&e->lock);
250
251 if (e->state == L2T_STATE_RESOLVING &&
252 !neigh_event_send(e->neigh, NULL)) {
253 spin_lock_bh(&e->lock);
254 if (e->state == L2T_STATE_RESOLVING && e->arpq_head)
255 write_l2e(adap, e, 1);
256 spin_unlock_bh(&e->lock);
257 }
258 }
259 return 0;
260}
261EXPORT_SYMBOL(cxgb4_l2t_send);
262
263/*
264 * Allocate a free L2T entry. Must be called with l2t_data.lock held.
265 */
266static struct l2t_entry *alloc_l2e(struct l2t_data *d)
267{
268 struct l2t_entry *end, *e, **p;
269
270 if (!atomic_read(&d->nfree))
271 return NULL;
272
273 /* there's definitely a free entry */
274 for (e = d->rover, end = &d->l2tab[L2T_SIZE]; e != end; ++e)
275 if (atomic_read(&e->refcnt) == 0)
276 goto found;
277
278 for (e = d->l2tab; atomic_read(&e->refcnt); ++e)
279 ;
280found:
281 d->rover = e + 1;
282 atomic_dec(&d->nfree);
283
284 /*
285 * The entry we found may be an inactive entry that is
286 * presently in the hash table. We need to remove it.
287 */
288 if (e->state < L2T_STATE_SWITCHING)
289 for (p = &d->l2tab[e->hash].first; *p; p = &(*p)->next)
290 if (*p == e) {
291 *p = e->next;
292 e->next = NULL;
293 break;
294 }
295
296 e->state = L2T_STATE_UNUSED;
297 return e;
298}
299
300/*
301 * Called when an L2T entry has no more users.
302 */
303static void t4_l2e_free(struct l2t_entry *e)
304{
305 struct l2t_data *d;
306
307 spin_lock_bh(&e->lock);
308 if (atomic_read(&e->refcnt) == 0) { /* hasn't been recycled */
309 if (e->neigh) {
310 neigh_release(e->neigh);
311 e->neigh = NULL;
312 }
313 }
314 spin_unlock_bh(&e->lock);
315
316 d = container_of(e, struct l2t_data, l2tab[e->idx]);
317 atomic_inc(&d->nfree);
318}
319
320void cxgb4_l2t_release(struct l2t_entry *e)
321{
322 if (atomic_dec_and_test(&e->refcnt))
323 t4_l2e_free(e);
324}
325EXPORT_SYMBOL(cxgb4_l2t_release);
326
327/*
328 * Update an L2T entry that was previously used for the same next hop as neigh.
329 * Must be called with softirqs disabled.
330 */
331static void reuse_entry(struct l2t_entry *e, struct neighbour *neigh)
332{
333 unsigned int nud_state;
334
335 spin_lock(&e->lock); /* avoid race with t4_l2t_free */
336 if (neigh != e->neigh)
337 neigh_replace(e, neigh);
338 nud_state = neigh->nud_state;
339 if (memcmp(e->dmac, neigh->ha, sizeof(e->dmac)) ||
340 !(nud_state & NUD_VALID))
341 e->state = L2T_STATE_RESOLVING;
342 else if (nud_state & NUD_CONNECTED)
343 e->state = L2T_STATE_VALID;
344 else
345 e->state = L2T_STATE_STALE;
346 spin_unlock(&e->lock);
347}
348
349struct l2t_entry *cxgb4_l2t_get(struct l2t_data *d, struct neighbour *neigh,
350 const struct net_device *physdev,
351 unsigned int priority)
352{
353 u8 lport;
354 u16 vlan;
355 struct l2t_entry *e;
356 int addr_len = neigh->tbl->key_len;
357 u32 *addr = (u32 *)neigh->primary_key;
358 int ifidx = neigh->dev->ifindex;
359 int hash = addr_hash(addr, addr_len, ifidx);
360
361 if (neigh->dev->flags & IFF_LOOPBACK)
362 lport = netdev2pinfo(physdev)->tx_chan + 4;
363 else
364 lport = netdev2pinfo(physdev)->lport;
365
366 if (neigh->dev->priv_flags & IFF_802_1Q_VLAN)
367 vlan = vlan_dev_vlan_id(neigh->dev);
368 else
369 vlan = VLAN_NONE;
370
371 write_lock_bh(&d->lock);
372 for (e = d->l2tab[hash].first; e; e = e->next)
373 if (!addreq(e, addr) && e->ifindex == ifidx &&
374 e->vlan == vlan && e->lport == lport) {
375 l2t_hold(d, e);
376 if (atomic_read(&e->refcnt) == 1)
377 reuse_entry(e, neigh);
378 goto done;
379 }
380
381 /* Need to allocate a new entry */
382 e = alloc_l2e(d);
383 if (e) {
384 spin_lock(&e->lock); /* avoid race with t4_l2t_free */
385 e->state = L2T_STATE_RESOLVING;
386 memcpy(e->addr, addr, addr_len);
387 e->ifindex = ifidx;
388 e->hash = hash;
389 e->lport = lport;
390 e->v6 = addr_len == 16;
391 atomic_set(&e->refcnt, 1);
392 neigh_replace(e, neigh);
393 e->vlan = vlan;
394 e->next = d->l2tab[hash].first;
395 d->l2tab[hash].first = e;
396 spin_unlock(&e->lock);
397 }
398done:
399 write_unlock_bh(&d->lock);
400 return e;
401}
402EXPORT_SYMBOL(cxgb4_l2t_get);
403
404/*
405 * Called when address resolution fails for an L2T entry to handle packets
406 * on the arpq head. If a packet specifies a failure handler it is invoked,
407 * otherwise the packet is sent to the device.
408 */
409static void handle_failed_resolution(struct adapter *adap, struct sk_buff *arpq)
410{
411 while (arpq) {
412 struct sk_buff *skb = arpq;
413 const struct l2t_skb_cb *cb = L2T_SKB_CB(skb);
414
415 arpq = skb->next;
416 skb->next = NULL;
417 if (cb->arp_err_handler)
418 cb->arp_err_handler(cb->handle, skb);
419 else
420 t4_ofld_send(adap, skb);
421 }
422}
423
424/*
425 * Called when the host's neighbor layer makes a change to some entry that is
426 * loaded into the HW L2 table.
427 */
428void t4_l2t_update(struct adapter *adap, struct neighbour *neigh)
429{
430 struct l2t_entry *e;
431 struct sk_buff *arpq = NULL;
432 struct l2t_data *d = adap->l2t;
433 int addr_len = neigh->tbl->key_len;
434 u32 *addr = (u32 *) neigh->primary_key;
435 int ifidx = neigh->dev->ifindex;
436 int hash = addr_hash(addr, addr_len, ifidx);
437
438 read_lock_bh(&d->lock);
439 for (e = d->l2tab[hash].first; e; e = e->next)
440 if (!addreq(e, addr) && e->ifindex == ifidx) {
441 spin_lock(&e->lock);
442 if (atomic_read(&e->refcnt))
443 goto found;
444 spin_unlock(&e->lock);
445 break;
446 }
447 read_unlock_bh(&d->lock);
448 return;
449
450 found:
451 read_unlock(&d->lock);
452
453 if (neigh != e->neigh)
454 neigh_replace(e, neigh);
455
456 if (e->state == L2T_STATE_RESOLVING) {
457 if (neigh->nud_state & NUD_FAILED) {
458 arpq = e->arpq_head;
459 e->arpq_head = e->arpq_tail = NULL;
460 } else if ((neigh->nud_state & (NUD_CONNECTED | NUD_STALE)) &&
461 e->arpq_head) {
462 write_l2e(adap, e, 1);
463 }
464 } else {
465 e->state = neigh->nud_state & NUD_CONNECTED ?
466 L2T_STATE_VALID : L2T_STATE_STALE;
467 if (memcmp(e->dmac, neigh->ha, sizeof(e->dmac)))
468 write_l2e(adap, e, 0);
469 }
470
471 spin_unlock_bh(&e->lock);
472
473 if (arpq)
474 handle_failed_resolution(adap, arpq);
475}
476
477/*
478 * Allocate an L2T entry for use by a switching rule. Such entries need to be
479 * explicitly freed and while busy they are not on any hash chain, so normal
480 * address resolution updates do not see them.
481 */
482struct l2t_entry *t4_l2t_alloc_switching(struct l2t_data *d)
483{
484 struct l2t_entry *e;
485
486 write_lock_bh(&d->lock);
487 e = alloc_l2e(d);
488 if (e) {
489 spin_lock(&e->lock); /* avoid race with t4_l2t_free */
490 e->state = L2T_STATE_SWITCHING;
491 atomic_set(&e->refcnt, 1);
492 spin_unlock(&e->lock);
493 }
494 write_unlock_bh(&d->lock);
495 return e;
496}
497
498/*
499 * Sets/updates the contents of a switching L2T entry that has been allocated
500 * with an earlier call to @t4_l2t_alloc_switching.
501 */
502int t4_l2t_set_switching(struct adapter *adap, struct l2t_entry *e, u16 vlan,
503 u8 port, u8 *eth_addr)
504{
505 e->vlan = vlan;
506 e->lport = port;
507 memcpy(e->dmac, eth_addr, ETH_ALEN);
508 return write_l2e(adap, e, 0);
509}
510
511struct l2t_data *t4_init_l2t(void)
512{
513 int i;
514 struct l2t_data *d;
515
516 d = t4_alloc_mem(sizeof(*d));
517 if (!d)
518 return NULL;
519
520 d->rover = d->l2tab;
521 atomic_set(&d->nfree, L2T_SIZE);
522 rwlock_init(&d->lock);
523
524 for (i = 0; i < L2T_SIZE; ++i) {
525 d->l2tab[i].idx = i;
526 d->l2tab[i].state = L2T_STATE_UNUSED;
527 spin_lock_init(&d->l2tab[i].lock);
528 atomic_set(&d->l2tab[i].refcnt, 0);
529 }
530 return d;
531}
532
533#include <linux/module.h>
534#include <linux/debugfs.h>
535#include <linux/seq_file.h>
536
537static inline void *l2t_get_idx(struct seq_file *seq, loff_t pos)
538{
539 struct l2t_entry *l2tab = seq->private;
540
541 return pos >= L2T_SIZE ? NULL : &l2tab[pos];
542}
543
544static void *l2t_seq_start(struct seq_file *seq, loff_t *pos)
545{
546 return *pos ? l2t_get_idx(seq, *pos - 1) : SEQ_START_TOKEN;
547}
548
549static void *l2t_seq_next(struct seq_file *seq, void *v, loff_t *pos)
550{
551 v = l2t_get_idx(seq, *pos);
552 if (v)
553 ++*pos;
554 return v;
555}
556
557static void l2t_seq_stop(struct seq_file *seq, void *v)
558{
559}
560
561static char l2e_state(const struct l2t_entry *e)
562{
563 switch (e->state) {
564 case L2T_STATE_VALID: return 'V';
565 case L2T_STATE_STALE: return 'S';
566 case L2T_STATE_SYNC_WRITE: return 'W';
567 case L2T_STATE_RESOLVING: return e->arpq_head ? 'A' : 'R';
568 case L2T_STATE_SWITCHING: return 'X';
569 default:
570 return 'U';
571 }
572}
573
574static int l2t_seq_show(struct seq_file *seq, void *v)
575{
576 if (v == SEQ_START_TOKEN)
577 seq_puts(seq, " Idx IP address "
578 "Ethernet address VLAN/P LP State Users Port\n");
579 else {
580 char ip[60];
581 struct l2t_entry *e = v;
582
583 spin_lock_bh(&e->lock);
584 if (e->state == L2T_STATE_SWITCHING)
585 ip[0] = '\0';
586 else
587 sprintf(ip, e->v6 ? "%pI6c" : "%pI4", e->addr);
588 seq_printf(seq, "%4u %-25s %17pM %4d %u %2u %c %5u %s\n",
589 e->idx, ip, e->dmac,
590 e->vlan & VLAN_VID_MASK, vlan_prio(e), e->lport,
591 l2e_state(e), atomic_read(&e->refcnt),
592 e->neigh ? e->neigh->dev->name : "");
593 spin_unlock_bh(&e->lock);
594 }
595 return 0;
596}
597
598static const struct seq_operations l2t_seq_ops = {
599 .start = l2t_seq_start,
600 .next = l2t_seq_next,
601 .stop = l2t_seq_stop,
602 .show = l2t_seq_show
603};
604
605static int l2t_seq_open(struct inode *inode, struct file *file)
606{
607 int rc = seq_open(file, &l2t_seq_ops);
608
609 if (!rc) {
610 struct adapter *adap = inode->i_private;
611 struct seq_file *seq = file->private_data;
612
613 seq->private = adap->l2t->l2tab;
614 }
615 return rc;
616}
617
618const struct file_operations t4_l2t_fops = {
619 .owner = THIS_MODULE,
620 .open = l2t_seq_open,
621 .read = seq_read,
622 .llseek = seq_lseek,
623 .release = seq_release,
624};
diff --git a/drivers/net/cxgb4/l2t.h b/drivers/net/cxgb4/l2t.h
new file mode 100644
index 000000000000..643f27ed3cf4
--- /dev/null
+++ b/drivers/net/cxgb4/l2t.h
@@ -0,0 +1,110 @@
1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_L2T_H
36#define __CXGB4_L2T_H
37
38#include <linux/spinlock.h>
39#include <linux/if_ether.h>
40#include <asm/atomic.h>
41
42struct adapter;
43struct l2t_data;
44struct neighbour;
45struct net_device;
46struct file_operations;
47struct cpl_l2t_write_rpl;
48
49/*
50 * Each L2T entry plays multiple roles. First of all, it keeps state for the
51 * corresponding entry of the HW L2 table and maintains a queue of offload
52 * packets awaiting address resolution. Second, it is a node of a hash table
53 * chain, where the nodes of the chain are linked together through their next
54 * pointer. Finally, each node is a bucket of a hash table, pointing to the
55 * first element in its chain through its first pointer.
56 */
57struct l2t_entry {
58 u16 state; /* entry state */
59 u16 idx; /* entry index */
60 u32 addr[4]; /* next hop IP or IPv6 address */
61 int ifindex; /* neighbor's net_device's ifindex */
62 struct neighbour *neigh; /* associated neighbour */
63 struct l2t_entry *first; /* start of hash chain */
64 struct l2t_entry *next; /* next l2t_entry on chain */
65 struct sk_buff *arpq_head; /* queue of packets awaiting resolution */
66 struct sk_buff *arpq_tail;
67 spinlock_t lock;
68 atomic_t refcnt; /* entry reference count */
69 u16 hash; /* hash bucket the entry is on */
70 u16 vlan; /* VLAN TCI (id: bits 0-11, prio: 13-15 */
71 u8 v6; /* whether entry is for IPv6 */
72 u8 lport; /* associated offload logical interface */
73 u8 dmac[ETH_ALEN]; /* neighbour's MAC address */
74};
75
76typedef void (*arp_err_handler_t)(void *handle, struct sk_buff *skb);
77
78/*
79 * Callback stored in an skb to handle address resolution failure.
80 */
81struct l2t_skb_cb {
82 void *handle;
83 arp_err_handler_t arp_err_handler;
84};
85
86#define L2T_SKB_CB(skb) ((struct l2t_skb_cb *)(skb)->cb)
87
88static inline void t4_set_arp_err_handler(struct sk_buff *skb, void *handle,
89 arp_err_handler_t handler)
90{
91 L2T_SKB_CB(skb)->handle = handle;
92 L2T_SKB_CB(skb)->arp_err_handler = handler;
93}
94
95void cxgb4_l2t_release(struct l2t_entry *e);
96int cxgb4_l2t_send(struct net_device *dev, struct sk_buff *skb,
97 struct l2t_entry *e);
98struct l2t_entry *cxgb4_l2t_get(struct l2t_data *d, struct neighbour *neigh,
99 const struct net_device *physdev,
100 unsigned int priority);
101
102void t4_l2t_update(struct adapter *adap, struct neighbour *neigh);
103struct l2t_entry *t4_l2t_alloc_switching(struct l2t_data *d);
104int t4_l2t_set_switching(struct adapter *adap, struct l2t_entry *e, u16 vlan,
105 u8 port, u8 *eth_addr);
106struct l2t_data *t4_init_l2t(void);
107void do_l2t_write_rpl(struct adapter *p, const struct cpl_l2t_write_rpl *rpl);
108
109extern const struct file_operations t4_l2t_fops;
110#endif /* __CXGB4_L2T_H */
diff --git a/drivers/net/cxgb4/sge.c b/drivers/net/cxgb4/sge.c
new file mode 100644
index 000000000000..d1f8f225e45a
--- /dev/null
+++ b/drivers/net/cxgb4/sge.c
@@ -0,0 +1,2436 @@
1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/skbuff.h>
36#include <linux/netdevice.h>
37#include <linux/etherdevice.h>
38#include <linux/if_vlan.h>
39#include <linux/ip.h>
40#include <linux/dma-mapping.h>
41#include <linux/jiffies.h>
42#include <net/ipv6.h>
43#include <net/tcp.h>
44#include "cxgb4.h"
45#include "t4_regs.h"
46#include "t4_msg.h"
47#include "t4fw_api.h"
48
49/*
50 * Rx buffer size. We use largish buffers if possible but settle for single
51 * pages under memory shortage.
52 */
53#if PAGE_SHIFT >= 16
54# define FL_PG_ORDER 0
55#else
56# define FL_PG_ORDER (16 - PAGE_SHIFT)
57#endif
58
59/* RX_PULL_LEN should be <= RX_COPY_THRES */
60#define RX_COPY_THRES 256
61#define RX_PULL_LEN 128
62
63/*
64 * Main body length for sk_buffs used for Rx Ethernet packets with fragments.
65 * Should be >= RX_PULL_LEN but possibly bigger to give pskb_may_pull some room.
66 */
67#define RX_PKT_SKB_LEN 512
68
69/* Ethernet header padding prepended to RX_PKTs */
70#define RX_PKT_PAD 2
71
72/*
73 * Max number of Tx descriptors we clean up at a time. Should be modest as
74 * freeing skbs isn't cheap and it happens while holding locks. We just need
75 * to free packets faster than they arrive, we eventually catch up and keep
76 * the amortized cost reasonable. Must be >= 2 * TXQ_STOP_THRES.
77 */
78#define MAX_TX_RECLAIM 16
79
80/*
81 * Max number of Rx buffers we replenish at a time. Again keep this modest,
82 * allocating buffers isn't cheap either.
83 */
84#define MAX_RX_REFILL 16U
85
86/*
87 * Period of the Rx queue check timer. This timer is infrequent as it has
88 * something to do only when the system experiences severe memory shortage.
89 */
90#define RX_QCHECK_PERIOD (HZ / 2)
91
92/*
93 * Period of the Tx queue check timer.
94 */
95#define TX_QCHECK_PERIOD (HZ / 2)
96
97/*
98 * Max number of Tx descriptors to be reclaimed by the Tx timer.
99 */
100#define MAX_TIMER_TX_RECLAIM 100
101
102/*
103 * Timer index used when backing off due to memory shortage.
104 */
105#define NOMEM_TMR_IDX (SGE_NTIMERS - 1)
106
107/*
108 * An FL with <= FL_STARVE_THRES buffers is starving and a periodic timer will
109 * attempt to refill it.
110 */
111#define FL_STARVE_THRES 4
112
113/*
114 * Suspend an Ethernet Tx queue with fewer available descriptors than this.
115 * This is the same as calc_tx_descs() for a TSO packet with
116 * nr_frags == MAX_SKB_FRAGS.
117 */
118#define ETHTXQ_STOP_THRES \
119 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8))
120
121/*
122 * Suspension threshold for non-Ethernet Tx queues. We require enough room
123 * for a full sized WR.
124 */
125#define TXQ_STOP_THRES (SGE_MAX_WR_LEN / sizeof(struct tx_desc))
126
127/*
128 * Max Tx descriptor space we allow for an Ethernet packet to be inlined
129 * into a WR.
130 */
131#define MAX_IMM_TX_PKT_LEN 128
132
133/*
134 * Max size of a WR sent through a control Tx queue.
135 */
136#define MAX_CTRL_WR_LEN SGE_MAX_WR_LEN
137
138enum {
139 /* packet alignment in FL buffers */
140 FL_ALIGN = L1_CACHE_BYTES < 32 ? 32 : L1_CACHE_BYTES,
141 /* egress status entry size */
142 STAT_LEN = L1_CACHE_BYTES > 64 ? 128 : 64
143};
144
145struct tx_sw_desc { /* SW state per Tx descriptor */
146 struct sk_buff *skb;
147 struct ulptx_sgl *sgl;
148};
149
150struct rx_sw_desc { /* SW state per Rx descriptor */
151 struct page *page;
152 dma_addr_t dma_addr;
153};
154
155/*
156 * The low bits of rx_sw_desc.dma_addr have special meaning.
157 */
158enum {
159 RX_LARGE_BUF = 1 << 0, /* buffer is larger than PAGE_SIZE */
160 RX_UNMAPPED_BUF = 1 << 1, /* buffer is not mapped */
161};
162
163static inline dma_addr_t get_buf_addr(const struct rx_sw_desc *d)
164{
165 return d->dma_addr & ~(dma_addr_t)(RX_LARGE_BUF | RX_UNMAPPED_BUF);
166}
167
168static inline bool is_buf_mapped(const struct rx_sw_desc *d)
169{
170 return !(d->dma_addr & RX_UNMAPPED_BUF);
171}
172
173/**
174 * txq_avail - return the number of available slots in a Tx queue
175 * @q: the Tx queue
176 *
177 * Returns the number of descriptors in a Tx queue available to write new
178 * packets.
179 */
180static inline unsigned int txq_avail(const struct sge_txq *q)
181{
182 return q->size - 1 - q->in_use;
183}
184
185/**
186 * fl_cap - return the capacity of a free-buffer list
187 * @fl: the FL
188 *
189 * Returns the capacity of a free-buffer list. The capacity is less than
190 * the size because one descriptor needs to be left unpopulated, otherwise
191 * HW will think the FL is empty.
192 */
193static inline unsigned int fl_cap(const struct sge_fl *fl)
194{
195 return fl->size - 8; /* 1 descriptor = 8 buffers */
196}
197
198static inline bool fl_starving(const struct sge_fl *fl)
199{
200 return fl->avail - fl->pend_cred <= FL_STARVE_THRES;
201}
202
203static int map_skb(struct device *dev, const struct sk_buff *skb,
204 dma_addr_t *addr)
205{
206 const skb_frag_t *fp, *end;
207 const struct skb_shared_info *si;
208
209 *addr = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
210 if (dma_mapping_error(dev, *addr))
211 goto out_err;
212
213 si = skb_shinfo(skb);
214 end = &si->frags[si->nr_frags];
215
216 for (fp = si->frags; fp < end; fp++) {
217 *++addr = dma_map_page(dev, fp->page, fp->page_offset, fp->size,
218 DMA_TO_DEVICE);
219 if (dma_mapping_error(dev, *addr))
220 goto unwind;
221 }
222 return 0;
223
224unwind:
225 while (fp-- > si->frags)
226 dma_unmap_page(dev, *--addr, fp->size, DMA_TO_DEVICE);
227
228 dma_unmap_single(dev, addr[-1], skb_headlen(skb), DMA_TO_DEVICE);
229out_err:
230 return -ENOMEM;
231}
232
233#ifdef CONFIG_NEED_DMA_MAP_STATE
234static void unmap_skb(struct device *dev, const struct sk_buff *skb,
235 const dma_addr_t *addr)
236{
237 const skb_frag_t *fp, *end;
238 const struct skb_shared_info *si;
239
240 dma_unmap_single(dev, *addr++, skb_headlen(skb), DMA_TO_DEVICE);
241
242 si = skb_shinfo(skb);
243 end = &si->frags[si->nr_frags];
244 for (fp = si->frags; fp < end; fp++)
245 dma_unmap_page(dev, *addr++, fp->size, DMA_TO_DEVICE);
246}
247
248/**
249 * deferred_unmap_destructor - unmap a packet when it is freed
250 * @skb: the packet
251 *
252 * This is the packet destructor used for Tx packets that need to remain
253 * mapped until they are freed rather than until their Tx descriptors are
254 * freed.
255 */
256static void deferred_unmap_destructor(struct sk_buff *skb)
257{
258 unmap_skb(skb->dev->dev.parent, skb, (dma_addr_t *)skb->head);
259}
260#endif
261
262static void unmap_sgl(struct device *dev, const struct sk_buff *skb,
263 const struct ulptx_sgl *sgl, const struct sge_txq *q)
264{
265 const struct ulptx_sge_pair *p;
266 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
267
268 if (likely(skb_headlen(skb)))
269 dma_unmap_single(dev, be64_to_cpu(sgl->addr0), ntohl(sgl->len0),
270 DMA_TO_DEVICE);
271 else {
272 dma_unmap_page(dev, be64_to_cpu(sgl->addr0), ntohl(sgl->len0),
273 DMA_TO_DEVICE);
274 nfrags--;
275 }
276
277 /*
278 * the complexity below is because of the possibility of a wrap-around
279 * in the middle of an SGL
280 */
281 for (p = sgl->sge; nfrags >= 2; nfrags -= 2) {
282 if (likely((u8 *)(p + 1) <= (u8 *)q->stat)) {
283unmap: dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
284 ntohl(p->len[0]), DMA_TO_DEVICE);
285 dma_unmap_page(dev, be64_to_cpu(p->addr[1]),
286 ntohl(p->len[1]), DMA_TO_DEVICE);
287 p++;
288 } else if ((u8 *)p == (u8 *)q->stat) {
289 p = (const struct ulptx_sge_pair *)q->desc;
290 goto unmap;
291 } else if ((u8 *)p + 8 == (u8 *)q->stat) {
292 const __be64 *addr = (const __be64 *)q->desc;
293
294 dma_unmap_page(dev, be64_to_cpu(addr[0]),
295 ntohl(p->len[0]), DMA_TO_DEVICE);
296 dma_unmap_page(dev, be64_to_cpu(addr[1]),
297 ntohl(p->len[1]), DMA_TO_DEVICE);
298 p = (const struct ulptx_sge_pair *)&addr[2];
299 } else {
300 const __be64 *addr = (const __be64 *)q->desc;
301
302 dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
303 ntohl(p->len[0]), DMA_TO_DEVICE);
304 dma_unmap_page(dev, be64_to_cpu(addr[0]),
305 ntohl(p->len[1]), DMA_TO_DEVICE);
306 p = (const struct ulptx_sge_pair *)&addr[1];
307 }
308 }
309 if (nfrags) {
310 __be64 addr;
311
312 if ((u8 *)p == (u8 *)q->stat)
313 p = (const struct ulptx_sge_pair *)q->desc;
314 addr = (u8 *)p + 16 <= (u8 *)q->stat ? p->addr[0] :
315 *(const __be64 *)q->desc;
316 dma_unmap_page(dev, be64_to_cpu(addr), ntohl(p->len[0]),
317 DMA_TO_DEVICE);
318 }
319}
320
321/**
322 * free_tx_desc - reclaims Tx descriptors and their buffers
323 * @adapter: the adapter
324 * @q: the Tx queue to reclaim descriptors from
325 * @n: the number of descriptors to reclaim
326 * @unmap: whether the buffers should be unmapped for DMA
327 *
328 * Reclaims Tx descriptors from an SGE Tx queue and frees the associated
329 * Tx buffers. Called with the Tx queue lock held.
330 */
331static void free_tx_desc(struct adapter *adap, struct sge_txq *q,
332 unsigned int n, bool unmap)
333{
334 struct tx_sw_desc *d;
335 unsigned int cidx = q->cidx;
336 struct device *dev = adap->pdev_dev;
337
338 d = &q->sdesc[cidx];
339 while (n--) {
340 if (d->skb) { /* an SGL is present */
341 if (unmap)
342 unmap_sgl(dev, d->skb, d->sgl, q);
343 kfree_skb(d->skb);
344 d->skb = NULL;
345 }
346 ++d;
347 if (++cidx == q->size) {
348 cidx = 0;
349 d = q->sdesc;
350 }
351 }
352 q->cidx = cidx;
353}
354
355/*
356 * Return the number of reclaimable descriptors in a Tx queue.
357 */
358static inline int reclaimable(const struct sge_txq *q)
359{
360 int hw_cidx = ntohs(q->stat->cidx);
361 hw_cidx -= q->cidx;
362 return hw_cidx < 0 ? hw_cidx + q->size : hw_cidx;
363}
364
365/**
366 * reclaim_completed_tx - reclaims completed Tx descriptors
367 * @adap: the adapter
368 * @q: the Tx queue to reclaim completed descriptors from
369 * @unmap: whether the buffers should be unmapped for DMA
370 *
371 * Reclaims Tx descriptors that the SGE has indicated it has processed,
372 * and frees the associated buffers if possible. Called with the Tx
373 * queue locked.
374 */
375static inline void reclaim_completed_tx(struct adapter *adap, struct sge_txq *q,
376 bool unmap)
377{
378 int avail = reclaimable(q);
379
380 if (avail) {
381 /*
382 * Limit the amount of clean up work we do at a time to keep
383 * the Tx lock hold time O(1).
384 */
385 if (avail > MAX_TX_RECLAIM)
386 avail = MAX_TX_RECLAIM;
387
388 free_tx_desc(adap, q, avail, unmap);
389 q->in_use -= avail;
390 }
391}
392
393static inline int get_buf_size(const struct rx_sw_desc *d)
394{
395#if FL_PG_ORDER > 0
396 return (d->dma_addr & RX_LARGE_BUF) ? (PAGE_SIZE << FL_PG_ORDER) :
397 PAGE_SIZE;
398#else
399 return PAGE_SIZE;
400#endif
401}
402
403/**
404 * free_rx_bufs - free the Rx buffers on an SGE free list
405 * @adap: the adapter
406 * @q: the SGE free list to free buffers from
407 * @n: how many buffers to free
408 *
409 * Release the next @n buffers on an SGE free-buffer Rx queue. The
410 * buffers must be made inaccessible to HW before calling this function.
411 */
412static void free_rx_bufs(struct adapter *adap, struct sge_fl *q, int n)
413{
414 while (n--) {
415 struct rx_sw_desc *d = &q->sdesc[q->cidx];
416
417 if (is_buf_mapped(d))
418 dma_unmap_page(adap->pdev_dev, get_buf_addr(d),
419 get_buf_size(d), PCI_DMA_FROMDEVICE);
420 put_page(d->page);
421 d->page = NULL;
422 if (++q->cidx == q->size)
423 q->cidx = 0;
424 q->avail--;
425 }
426}
427
428/**
429 * unmap_rx_buf - unmap the current Rx buffer on an SGE free list
430 * @adap: the adapter
431 * @q: the SGE free list
432 *
433 * Unmap the current buffer on an SGE free-buffer Rx queue. The
434 * buffer must be made inaccessible to HW before calling this function.
435 *
436 * This is similar to @free_rx_bufs above but does not free the buffer.
437 * Do note that the FL still loses any further access to the buffer.
438 */
439static void unmap_rx_buf(struct adapter *adap, struct sge_fl *q)
440{
441 struct rx_sw_desc *d = &q->sdesc[q->cidx];
442
443 if (is_buf_mapped(d))
444 dma_unmap_page(adap->pdev_dev, get_buf_addr(d),
445 get_buf_size(d), PCI_DMA_FROMDEVICE);
446 d->page = NULL;
447 if (++q->cidx == q->size)
448 q->cidx = 0;
449 q->avail--;
450}
451
452static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
453{
454 if (q->pend_cred >= 8) {
455 wmb();
456 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL), DBPRIO |
457 QID(q->cntxt_id) | PIDX(q->pend_cred / 8));
458 q->pend_cred &= 7;
459 }
460}
461
462static inline void set_rx_sw_desc(struct rx_sw_desc *sd, struct page *pg,
463 dma_addr_t mapping)
464{
465 sd->page = pg;
466 sd->dma_addr = mapping; /* includes size low bits */
467}
468
469/**
470 * refill_fl - refill an SGE Rx buffer ring
471 * @adap: the adapter
472 * @q: the ring to refill
473 * @n: the number of new buffers to allocate
474 * @gfp: the gfp flags for the allocations
475 *
476 * (Re)populate an SGE free-buffer queue with up to @n new packet buffers,
477 * allocated with the supplied gfp flags. The caller must assure that
478 * @n does not exceed the queue's capacity. If afterwards the queue is
479 * found critically low mark it as starving in the bitmap of starving FLs.
480 *
481 * Returns the number of buffers allocated.
482 */
483static unsigned int refill_fl(struct adapter *adap, struct sge_fl *q, int n,
484 gfp_t gfp)
485{
486 struct page *pg;
487 dma_addr_t mapping;
488 unsigned int cred = q->avail;
489 __be64 *d = &q->desc[q->pidx];
490 struct rx_sw_desc *sd = &q->sdesc[q->pidx];
491
492 gfp |= __GFP_NOWARN; /* failures are expected */
493
494#if FL_PG_ORDER > 0
495 /*
496 * Prefer large buffers
497 */
498 while (n) {
499 pg = alloc_pages(gfp | __GFP_COMP, FL_PG_ORDER);
500 if (unlikely(!pg)) {
501 q->large_alloc_failed++;
502 break; /* fall back to single pages */
503 }
504
505 mapping = dma_map_page(adap->pdev_dev, pg, 0,
506 PAGE_SIZE << FL_PG_ORDER,
507 PCI_DMA_FROMDEVICE);
508 if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) {
509 __free_pages(pg, FL_PG_ORDER);
510 goto out; /* do not try small pages for this error */
511 }
512 mapping |= RX_LARGE_BUF;
513 *d++ = cpu_to_be64(mapping);
514
515 set_rx_sw_desc(sd, pg, mapping);
516 sd++;
517
518 q->avail++;
519 if (++q->pidx == q->size) {
520 q->pidx = 0;
521 sd = q->sdesc;
522 d = q->desc;
523 }
524 n--;
525 }
526#endif
527
528 while (n--) {
529 pg = __netdev_alloc_page(adap->port[0], gfp);
530 if (unlikely(!pg)) {
531 q->alloc_failed++;
532 break;
533 }
534
535 mapping = dma_map_page(adap->pdev_dev, pg, 0, PAGE_SIZE,
536 PCI_DMA_FROMDEVICE);
537 if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) {
538 netdev_free_page(adap->port[0], pg);
539 goto out;
540 }
541 *d++ = cpu_to_be64(mapping);
542
543 set_rx_sw_desc(sd, pg, mapping);
544 sd++;
545
546 q->avail++;
547 if (++q->pidx == q->size) {
548 q->pidx = 0;
549 sd = q->sdesc;
550 d = q->desc;
551 }
552 }
553
554out: cred = q->avail - cred;
555 q->pend_cred += cred;
556 ring_fl_db(adap, q);
557
558 if (unlikely(fl_starving(q))) {
559 smp_wmb();
560 set_bit(q->cntxt_id, adap->sge.starving_fl);
561 }
562
563 return cred;
564}
565
566static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl)
567{
568 refill_fl(adap, fl, min(MAX_RX_REFILL, fl_cap(fl) - fl->avail),
569 GFP_ATOMIC);
570}
571
572/**
573 * alloc_ring - allocate resources for an SGE descriptor ring
574 * @dev: the PCI device's core device
575 * @nelem: the number of descriptors
576 * @elem_size: the size of each descriptor
577 * @sw_size: the size of the SW state associated with each ring element
578 * @phys: the physical address of the allocated ring
579 * @metadata: address of the array holding the SW state for the ring
580 * @stat_size: extra space in HW ring for status information
581 *
582 * Allocates resources for an SGE descriptor ring, such as Tx queues,
583 * free buffer lists, or response queues. Each SGE ring requires
584 * space for its HW descriptors plus, optionally, space for the SW state
585 * associated with each HW entry (the metadata). The function returns
586 * three values: the virtual address for the HW ring (the return value
587 * of the function), the bus address of the HW ring, and the address
588 * of the SW ring.
589 */
590static void *alloc_ring(struct device *dev, size_t nelem, size_t elem_size,
591 size_t sw_size, dma_addr_t *phys, void *metadata,
592 size_t stat_size)
593{
594 size_t len = nelem * elem_size + stat_size;
595 void *s = NULL;
596 void *p = dma_alloc_coherent(dev, len, phys, GFP_KERNEL);
597
598 if (!p)
599 return NULL;
600 if (sw_size) {
601 s = kcalloc(nelem, sw_size, GFP_KERNEL);
602
603 if (!s) {
604 dma_free_coherent(dev, len, p, *phys);
605 return NULL;
606 }
607 }
608 if (metadata)
609 *(void **)metadata = s;
610 memset(p, 0, len);
611 return p;
612}
613
614/**
615 * sgl_len - calculates the size of an SGL of the given capacity
616 * @n: the number of SGL entries
617 *
618 * Calculates the number of flits needed for a scatter/gather list that
619 * can hold the given number of entries.
620 */
621static inline unsigned int sgl_len(unsigned int n)
622{
623 n--;
624 return (3 * n) / 2 + (n & 1) + 2;
625}
626
627/**
628 * flits_to_desc - returns the num of Tx descriptors for the given flits
629 * @n: the number of flits
630 *
631 * Returns the number of Tx descriptors needed for the supplied number
632 * of flits.
633 */
634static inline unsigned int flits_to_desc(unsigned int n)
635{
636 BUG_ON(n > SGE_MAX_WR_LEN / 8);
637 return DIV_ROUND_UP(n, 8);
638}
639
640/**
641 * is_eth_imm - can an Ethernet packet be sent as immediate data?
642 * @skb: the packet
643 *
644 * Returns whether an Ethernet packet is small enough to fit as
645 * immediate data.
646 */
647static inline int is_eth_imm(const struct sk_buff *skb)
648{
649 return skb->len <= MAX_IMM_TX_PKT_LEN - sizeof(struct cpl_tx_pkt);
650}
651
652/**
653 * calc_tx_flits - calculate the number of flits for a packet Tx WR
654 * @skb: the packet
655 *
656 * Returns the number of flits needed for a Tx WR for the given Ethernet
657 * packet, including the needed WR and CPL headers.
658 */
659static inline unsigned int calc_tx_flits(const struct sk_buff *skb)
660{
661 unsigned int flits;
662
663 if (is_eth_imm(skb))
664 return DIV_ROUND_UP(skb->len + sizeof(struct cpl_tx_pkt), 8);
665
666 flits = sgl_len(skb_shinfo(skb)->nr_frags + 1) + 4;
667 if (skb_shinfo(skb)->gso_size)
668 flits += 2;
669 return flits;
670}
671
672/**
673 * calc_tx_descs - calculate the number of Tx descriptors for a packet
674 * @skb: the packet
675 *
676 * Returns the number of Tx descriptors needed for the given Ethernet
677 * packet, including the needed WR and CPL headers.
678 */
679static inline unsigned int calc_tx_descs(const struct sk_buff *skb)
680{
681 return flits_to_desc(calc_tx_flits(skb));
682}
683
684/**
685 * write_sgl - populate a scatter/gather list for a packet
686 * @skb: the packet
687 * @q: the Tx queue we are writing into
688 * @sgl: starting location for writing the SGL
689 * @end: points right after the end of the SGL
690 * @start: start offset into skb main-body data to include in the SGL
691 * @addr: the list of bus addresses for the SGL elements
692 *
693 * Generates a gather list for the buffers that make up a packet.
694 * The caller must provide adequate space for the SGL that will be written.
695 * The SGL includes all of the packet's page fragments and the data in its
696 * main body except for the first @start bytes. @sgl must be 16-byte
697 * aligned and within a Tx descriptor with available space. @end points
698 * right after the end of the SGL but does not account for any potential
699 * wrap around, i.e., @end > @sgl.
700 */
701static void write_sgl(const struct sk_buff *skb, struct sge_txq *q,
702 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
703 const dma_addr_t *addr)
704{
705 unsigned int i, len;
706 struct ulptx_sge_pair *to;
707 const struct skb_shared_info *si = skb_shinfo(skb);
708 unsigned int nfrags = si->nr_frags;
709 struct ulptx_sge_pair buf[MAX_SKB_FRAGS / 2 + 1];
710
711 len = skb_headlen(skb) - start;
712 if (likely(len)) {
713 sgl->len0 = htonl(len);
714 sgl->addr0 = cpu_to_be64(addr[0] + start);
715 nfrags++;
716 } else {
717 sgl->len0 = htonl(si->frags[0].size);
718 sgl->addr0 = cpu_to_be64(addr[1]);
719 }
720
721 sgl->cmd_nsge = htonl(ULPTX_CMD(ULP_TX_SC_DSGL) | ULPTX_NSGE(nfrags));
722 if (likely(--nfrags == 0))
723 return;
724 /*
725 * Most of the complexity below deals with the possibility we hit the
726 * end of the queue in the middle of writing the SGL. For this case
727 * only we create the SGL in a temporary buffer and then copy it.
728 */
729 to = (u8 *)end > (u8 *)q->stat ? buf : sgl->sge;
730
731 for (i = (nfrags != si->nr_frags); nfrags >= 2; nfrags -= 2, to++) {
732 to->len[0] = cpu_to_be32(si->frags[i].size);
733 to->len[1] = cpu_to_be32(si->frags[++i].size);
734 to->addr[0] = cpu_to_be64(addr[i]);
735 to->addr[1] = cpu_to_be64(addr[++i]);
736 }
737 if (nfrags) {
738 to->len[0] = cpu_to_be32(si->frags[i].size);
739 to->len[1] = cpu_to_be32(0);
740 to->addr[0] = cpu_to_be64(addr[i + 1]);
741 }
742 if (unlikely((u8 *)end > (u8 *)q->stat)) {
743 unsigned int part0 = (u8 *)q->stat - (u8 *)sgl->sge, part1;
744
745 if (likely(part0))
746 memcpy(sgl->sge, buf, part0);
747 part1 = (u8 *)end - (u8 *)q->stat;
748 memcpy(q->desc, (u8 *)buf + part0, part1);
749 end = (void *)q->desc + part1;
750 }
751 if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */
752 *(u64 *)end = 0;
753}
754
755/**
756 * ring_tx_db - check and potentially ring a Tx queue's doorbell
757 * @adap: the adapter
758 * @q: the Tx queue
759 * @n: number of new descriptors to give to HW
760 *
761 * Ring the doorbel for a Tx queue.
762 */
763static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
764{
765 wmb(); /* write descriptors before telling HW */
766 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
767 QID(q->cntxt_id) | PIDX(n));
768}
769
770/**
771 * inline_tx_skb - inline a packet's data into Tx descriptors
772 * @skb: the packet
773 * @q: the Tx queue where the packet will be inlined
774 * @pos: starting position in the Tx queue where to inline the packet
775 *
776 * Inline a packet's contents directly into Tx descriptors, starting at
777 * the given position within the Tx DMA ring.
778 * Most of the complexity of this operation is dealing with wrap arounds
779 * in the middle of the packet we want to inline.
780 */
781static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
782 void *pos)
783{
784 u64 *p;
785 int left = (void *)q->stat - pos;
786
787 if (likely(skb->len <= left)) {
788 if (likely(!skb->data_len))
789 skb_copy_from_linear_data(skb, pos, skb->len);
790 else
791 skb_copy_bits(skb, 0, pos, skb->len);
792 pos += skb->len;
793 } else {
794 skb_copy_bits(skb, 0, pos, left);
795 skb_copy_bits(skb, left, q->desc, skb->len - left);
796 pos = (void *)q->desc + (skb->len - left);
797 }
798
799 /* 0-pad to multiple of 16 */
800 p = PTR_ALIGN(pos, 8);
801 if ((uintptr_t)p & 8)
802 *p = 0;
803}
804
805/*
806 * Figure out what HW csum a packet wants and return the appropriate control
807 * bits.
808 */
809static u64 hwcsum(const struct sk_buff *skb)
810{
811 int csum_type;
812 const struct iphdr *iph = ip_hdr(skb);
813
814 if (iph->version == 4) {
815 if (iph->protocol == IPPROTO_TCP)
816 csum_type = TX_CSUM_TCPIP;
817 else if (iph->protocol == IPPROTO_UDP)
818 csum_type = TX_CSUM_UDPIP;
819 else {
820nocsum: /*
821 * unknown protocol, disable HW csum
822 * and hope a bad packet is detected
823 */
824 return TXPKT_L4CSUM_DIS;
825 }
826 } else {
827 /*
828 * this doesn't work with extension headers
829 */
830 const struct ipv6hdr *ip6h = (const struct ipv6hdr *)iph;
831
832 if (ip6h->nexthdr == IPPROTO_TCP)
833 csum_type = TX_CSUM_TCPIP6;
834 else if (ip6h->nexthdr == IPPROTO_UDP)
835 csum_type = TX_CSUM_UDPIP6;
836 else
837 goto nocsum;
838 }
839
840 if (likely(csum_type >= TX_CSUM_TCPIP))
841 return TXPKT_CSUM_TYPE(csum_type) |
842 TXPKT_IPHDR_LEN(skb_network_header_len(skb)) |
843 TXPKT_ETHHDR_LEN(skb_network_offset(skb) - ETH_HLEN);
844 else {
845 int start = skb_transport_offset(skb);
846
847 return TXPKT_CSUM_TYPE(csum_type) | TXPKT_CSUM_START(start) |
848 TXPKT_CSUM_LOC(start + skb->csum_offset);
849 }
850}
851
852static void eth_txq_stop(struct sge_eth_txq *q)
853{
854 netif_tx_stop_queue(q->txq);
855 q->q.stops++;
856}
857
858static inline void txq_advance(struct sge_txq *q, unsigned int n)
859{
860 q->in_use += n;
861 q->pidx += n;
862 if (q->pidx >= q->size)
863 q->pidx -= q->size;
864}
865
866/**
867 * t4_eth_xmit - add a packet to an Ethernet Tx queue
868 * @skb: the packet
869 * @dev: the egress net device
870 *
871 * Add a packet to an SGE Ethernet Tx queue. Runs with softirqs disabled.
872 */
873netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev)
874{
875 u32 wr_mid;
876 u64 cntrl, *end;
877 int qidx, credits;
878 unsigned int flits, ndesc;
879 struct adapter *adap;
880 struct sge_eth_txq *q;
881 const struct port_info *pi;
882 struct fw_eth_tx_pkt_wr *wr;
883 struct cpl_tx_pkt_core *cpl;
884 const struct skb_shared_info *ssi;
885 dma_addr_t addr[MAX_SKB_FRAGS + 1];
886
887 /*
888 * The chip min packet length is 10 octets but play safe and reject
889 * anything shorter than an Ethernet header.
890 */
891 if (unlikely(skb->len < ETH_HLEN)) {
892out_free: dev_kfree_skb(skb);
893 return NETDEV_TX_OK;
894 }
895
896 pi = netdev_priv(dev);
897 adap = pi->adapter;
898 qidx = skb_get_queue_mapping(skb);
899 q = &adap->sge.ethtxq[qidx + pi->first_qset];
900
901 reclaim_completed_tx(adap, &q->q, true);
902
903 flits = calc_tx_flits(skb);
904 ndesc = flits_to_desc(flits);
905 credits = txq_avail(&q->q) - ndesc;
906
907 if (unlikely(credits < 0)) {
908 eth_txq_stop(q);
909 dev_err(adap->pdev_dev,
910 "%s: Tx ring %u full while queue awake!\n",
911 dev->name, qidx);
912 return NETDEV_TX_BUSY;
913 }
914
915 if (!is_eth_imm(skb) &&
916 unlikely(map_skb(adap->pdev_dev, skb, addr) < 0)) {
917 q->mapping_err++;
918 goto out_free;
919 }
920
921 wr_mid = FW_WR_LEN16(DIV_ROUND_UP(flits, 2));
922 if (unlikely(credits < ETHTXQ_STOP_THRES)) {
923 eth_txq_stop(q);
924 wr_mid |= FW_WR_EQUEQ | FW_WR_EQUIQ;
925 }
926
927 wr = (void *)&q->q.desc[q->q.pidx];
928 wr->equiq_to_len16 = htonl(wr_mid);
929 wr->r3 = cpu_to_be64(0);
930 end = (u64 *)wr + flits;
931
932 ssi = skb_shinfo(skb);
933 if (ssi->gso_size) {
934 struct cpl_tx_pkt_lso *lso = (void *)wr;
935 bool v6 = (ssi->gso_type & SKB_GSO_TCPV6) != 0;
936 int l3hdr_len = skb_network_header_len(skb);
937 int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN;
938
939 wr->op_immdlen = htonl(FW_WR_OP(FW_ETH_TX_PKT_WR) |
940 FW_WR_IMMDLEN(sizeof(*lso)));
941 lso->lso_ctrl = htonl(LSO_OPCODE(CPL_TX_PKT_LSO) |
942 LSO_FIRST_SLICE | LSO_LAST_SLICE |
943 LSO_IPV6(v6) |
944 LSO_ETHHDR_LEN(eth_xtra_len / 4) |
945 LSO_IPHDR_LEN(l3hdr_len / 4) |
946 LSO_TCPHDR_LEN(tcp_hdr(skb)->doff));
947 lso->ipid_ofst = htons(0);
948 lso->mss = htons(ssi->gso_size);
949 lso->seqno_offset = htonl(0);
950 lso->len = htonl(skb->len);
951 cpl = (void *)(lso + 1);
952 cntrl = TXPKT_CSUM_TYPE(v6 ? TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |
953 TXPKT_IPHDR_LEN(l3hdr_len) |
954 TXPKT_ETHHDR_LEN(eth_xtra_len);
955 q->tso++;
956 q->tx_cso += ssi->gso_segs;
957 } else {
958 int len;
959
960 len = is_eth_imm(skb) ? skb->len + sizeof(*cpl) : sizeof(*cpl);
961 wr->op_immdlen = htonl(FW_WR_OP(FW_ETH_TX_PKT_WR) |
962 FW_WR_IMMDLEN(len));
963 cpl = (void *)(wr + 1);
964 if (skb->ip_summed == CHECKSUM_PARTIAL) {
965 cntrl = hwcsum(skb) | TXPKT_IPCSUM_DIS;
966 q->tx_cso++;
967 } else
968 cntrl = TXPKT_L4CSUM_DIS | TXPKT_IPCSUM_DIS;
969 }
970
971 if (vlan_tx_tag_present(skb)) {
972 q->vlan_ins++;
973 cntrl |= TXPKT_VLAN_VLD | TXPKT_VLAN(vlan_tx_tag_get(skb));
974 }
975
976 cpl->ctrl0 = htonl(TXPKT_OPCODE(CPL_TX_PKT_XT) |
977 TXPKT_INTF(pi->tx_chan) | TXPKT_PF(0));
978 cpl->pack = htons(0);
979 cpl->len = htons(skb->len);
980 cpl->ctrl1 = cpu_to_be64(cntrl);
981
982 if (is_eth_imm(skb)) {
983 inline_tx_skb(skb, &q->q, cpl + 1);
984 dev_kfree_skb(skb);
985 } else {
986 int last_desc;
987
988 write_sgl(skb, &q->q, (struct ulptx_sgl *)(cpl + 1), end, 0,
989 addr);
990 skb_orphan(skb);
991
992 last_desc = q->q.pidx + ndesc - 1;
993 if (last_desc >= q->q.size)
994 last_desc -= q->q.size;
995 q->q.sdesc[last_desc].skb = skb;
996 q->q.sdesc[last_desc].sgl = (struct ulptx_sgl *)(cpl + 1);
997 }
998
999 txq_advance(&q->q, ndesc);
1000
1001 ring_tx_db(adap, &q->q, ndesc);
1002 return NETDEV_TX_OK;
1003}
1004
1005/**
1006 * reclaim_completed_tx_imm - reclaim completed control-queue Tx descs
1007 * @q: the SGE control Tx queue
1008 *
1009 * This is a variant of reclaim_completed_tx() that is used for Tx queues
1010 * that send only immediate data (presently just the control queues) and
1011 * thus do not have any sk_buffs to release.
1012 */
1013static inline void reclaim_completed_tx_imm(struct sge_txq *q)
1014{
1015 int hw_cidx = ntohs(q->stat->cidx);
1016 int reclaim = hw_cidx - q->cidx;
1017
1018 if (reclaim < 0)
1019 reclaim += q->size;
1020
1021 q->in_use -= reclaim;
1022 q->cidx = hw_cidx;
1023}
1024
1025/**
1026 * is_imm - check whether a packet can be sent as immediate data
1027 * @skb: the packet
1028 *
1029 * Returns true if a packet can be sent as a WR with immediate data.
1030 */
1031static inline int is_imm(const struct sk_buff *skb)
1032{
1033 return skb->len <= MAX_CTRL_WR_LEN;
1034}
1035
1036/**
1037 * ctrlq_check_stop - check if a control queue is full and should stop
1038 * @q: the queue
1039 * @wr: most recent WR written to the queue
1040 *
1041 * Check if a control queue has become full and should be stopped.
1042 * We clean up control queue descriptors very lazily, only when we are out.
1043 * If the queue is still full after reclaiming any completed descriptors
1044 * we suspend it and have the last WR wake it up.
1045 */
1046static void ctrlq_check_stop(struct sge_ctrl_txq *q, struct fw_wr_hdr *wr)
1047{
1048 reclaim_completed_tx_imm(&q->q);
1049 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) {
1050 wr->lo |= htonl(FW_WR_EQUEQ | FW_WR_EQUIQ);
1051 q->q.stops++;
1052 q->full = 1;
1053 }
1054}
1055
1056/**
1057 * ctrl_xmit - send a packet through an SGE control Tx queue
1058 * @q: the control queue
1059 * @skb: the packet
1060 *
1061 * Send a packet through an SGE control Tx queue. Packets sent through
1062 * a control queue must fit entirely as immediate data.
1063 */
1064static int ctrl_xmit(struct sge_ctrl_txq *q, struct sk_buff *skb)
1065{
1066 unsigned int ndesc;
1067 struct fw_wr_hdr *wr;
1068
1069 if (unlikely(!is_imm(skb))) {
1070 WARN_ON(1);
1071 dev_kfree_skb(skb);
1072 return NET_XMIT_DROP;
1073 }
1074
1075 ndesc = DIV_ROUND_UP(skb->len, sizeof(struct tx_desc));
1076 spin_lock(&q->sendq.lock);
1077
1078 if (unlikely(q->full)) {
1079 skb->priority = ndesc; /* save for restart */
1080 __skb_queue_tail(&q->sendq, skb);
1081 spin_unlock(&q->sendq.lock);
1082 return NET_XMIT_CN;
1083 }
1084
1085 wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx];
1086 inline_tx_skb(skb, &q->q, wr);
1087
1088 txq_advance(&q->q, ndesc);
1089 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES))
1090 ctrlq_check_stop(q, wr);
1091
1092 ring_tx_db(q->adap, &q->q, ndesc);
1093 spin_unlock(&q->sendq.lock);
1094
1095 kfree_skb(skb);
1096 return NET_XMIT_SUCCESS;
1097}
1098
1099/**
1100 * restart_ctrlq - restart a suspended control queue
1101 * @data: the control queue to restart
1102 *
1103 * Resumes transmission on a suspended Tx control queue.
1104 */
1105static void restart_ctrlq(unsigned long data)
1106{
1107 struct sk_buff *skb;
1108 unsigned int written = 0;
1109 struct sge_ctrl_txq *q = (struct sge_ctrl_txq *)data;
1110
1111 spin_lock(&q->sendq.lock);
1112 reclaim_completed_tx_imm(&q->q);
1113 BUG_ON(txq_avail(&q->q) < TXQ_STOP_THRES); /* q should be empty */
1114
1115 while ((skb = __skb_dequeue(&q->sendq)) != NULL) {
1116 struct fw_wr_hdr *wr;
1117 unsigned int ndesc = skb->priority; /* previously saved */
1118
1119 /*
1120 * Write descriptors and free skbs outside the lock to limit
1121 * wait times. q->full is still set so new skbs will be queued.
1122 */
1123 spin_unlock(&q->sendq.lock);
1124
1125 wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx];
1126 inline_tx_skb(skb, &q->q, wr);
1127 kfree_skb(skb);
1128
1129 written += ndesc;
1130 txq_advance(&q->q, ndesc);
1131 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) {
1132 unsigned long old = q->q.stops;
1133
1134 ctrlq_check_stop(q, wr);
1135 if (q->q.stops != old) { /* suspended anew */
1136 spin_lock(&q->sendq.lock);
1137 goto ringdb;
1138 }
1139 }
1140 if (written > 16) {
1141 ring_tx_db(q->adap, &q->q, written);
1142 written = 0;
1143 }
1144 spin_lock(&q->sendq.lock);
1145 }
1146 q->full = 0;
1147ringdb: if (written)
1148 ring_tx_db(q->adap, &q->q, written);
1149 spin_unlock(&q->sendq.lock);
1150}
1151
1152/**
1153 * t4_mgmt_tx - send a management message
1154 * @adap: the adapter
1155 * @skb: the packet containing the management message
1156 *
1157 * Send a management message through control queue 0.
1158 */
1159int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb)
1160{
1161 int ret;
1162
1163 local_bh_disable();
1164 ret = ctrl_xmit(&adap->sge.ctrlq[0], skb);
1165 local_bh_enable();
1166 return ret;
1167}
1168
1169/**
1170 * is_ofld_imm - check whether a packet can be sent as immediate data
1171 * @skb: the packet
1172 *
1173 * Returns true if a packet can be sent as an offload WR with immediate
1174 * data. We currently use the same limit as for Ethernet packets.
1175 */
1176static inline int is_ofld_imm(const struct sk_buff *skb)
1177{
1178 return skb->len <= MAX_IMM_TX_PKT_LEN;
1179}
1180
1181/**
1182 * calc_tx_flits_ofld - calculate # of flits for an offload packet
1183 * @skb: the packet
1184 *
1185 * Returns the number of flits needed for the given offload packet.
1186 * These packets are already fully constructed and no additional headers
1187 * will be added.
1188 */
1189static inline unsigned int calc_tx_flits_ofld(const struct sk_buff *skb)
1190{
1191 unsigned int flits, cnt;
1192
1193 if (is_ofld_imm(skb))
1194 return DIV_ROUND_UP(skb->len, 8);
1195
1196 flits = skb_transport_offset(skb) / 8U; /* headers */
1197 cnt = skb_shinfo(skb)->nr_frags;
1198 if (skb->tail != skb->transport_header)
1199 cnt++;
1200 return flits + sgl_len(cnt);
1201}
1202
1203/**
1204 * txq_stop_maperr - stop a Tx queue due to I/O MMU exhaustion
1205 * @adap: the adapter
1206 * @q: the queue to stop
1207 *
1208 * Mark a Tx queue stopped due to I/O MMU exhaustion and resulting
1209 * inability to map packets. A periodic timer attempts to restart
1210 * queues so marked.
1211 */
1212static void txq_stop_maperr(struct sge_ofld_txq *q)
1213{
1214 q->mapping_err++;
1215 q->q.stops++;
1216 set_bit(q->q.cntxt_id, q->adap->sge.txq_maperr);
1217}
1218
1219/**
1220 * ofldtxq_stop - stop an offload Tx queue that has become full
1221 * @q: the queue to stop
1222 * @skb: the packet causing the queue to become full
1223 *
1224 * Stops an offload Tx queue that has become full and modifies the packet
1225 * being written to request a wakeup.
1226 */
1227static void ofldtxq_stop(struct sge_ofld_txq *q, struct sk_buff *skb)
1228{
1229 struct fw_wr_hdr *wr = (struct fw_wr_hdr *)skb->data;
1230
1231 wr->lo |= htonl(FW_WR_EQUEQ | FW_WR_EQUIQ);
1232 q->q.stops++;
1233 q->full = 1;
1234}
1235
1236/**
1237 * service_ofldq - restart a suspended offload queue
1238 * @q: the offload queue
1239 *
1240 * Services an offload Tx queue by moving packets from its packet queue
1241 * to the HW Tx ring. The function starts and ends with the queue locked.
1242 */
1243static void service_ofldq(struct sge_ofld_txq *q)
1244{
1245 u64 *pos;
1246 int credits;
1247 struct sk_buff *skb;
1248 unsigned int written = 0;
1249 unsigned int flits, ndesc;
1250
1251 while ((skb = skb_peek(&q->sendq)) != NULL && !q->full) {
1252 /*
1253 * We drop the lock but leave skb on sendq, thus retaining
1254 * exclusive access to the state of the queue.
1255 */
1256 spin_unlock(&q->sendq.lock);
1257
1258 reclaim_completed_tx(q->adap, &q->q, false);
1259
1260 flits = skb->priority; /* previously saved */
1261 ndesc = flits_to_desc(flits);
1262 credits = txq_avail(&q->q) - ndesc;
1263 BUG_ON(credits < 0);
1264 if (unlikely(credits < TXQ_STOP_THRES))
1265 ofldtxq_stop(q, skb);
1266
1267 pos = (u64 *)&q->q.desc[q->q.pidx];
1268 if (is_ofld_imm(skb))
1269 inline_tx_skb(skb, &q->q, pos);
1270 else if (map_skb(q->adap->pdev_dev, skb,
1271 (dma_addr_t *)skb->head)) {
1272 txq_stop_maperr(q);
1273 spin_lock(&q->sendq.lock);
1274 break;
1275 } else {
1276 int last_desc, hdr_len = skb_transport_offset(skb);
1277
1278 memcpy(pos, skb->data, hdr_len);
1279 write_sgl(skb, &q->q, (void *)pos + hdr_len,
1280 pos + flits, hdr_len,
1281 (dma_addr_t *)skb->head);
1282#ifdef CONFIG_NEED_DMA_MAP_STATE
1283 skb->dev = q->adap->port[0];
1284 skb->destructor = deferred_unmap_destructor;
1285#endif
1286 last_desc = q->q.pidx + ndesc - 1;
1287 if (last_desc >= q->q.size)
1288 last_desc -= q->q.size;
1289 q->q.sdesc[last_desc].skb = skb;
1290 }
1291
1292 txq_advance(&q->q, ndesc);
1293 written += ndesc;
1294 if (unlikely(written > 32)) {
1295 ring_tx_db(q->adap, &q->q, written);
1296 written = 0;
1297 }
1298
1299 spin_lock(&q->sendq.lock);
1300 __skb_unlink(skb, &q->sendq);
1301 if (is_ofld_imm(skb))
1302 kfree_skb(skb);
1303 }
1304 if (likely(written))
1305 ring_tx_db(q->adap, &q->q, written);
1306}
1307
1308/**
1309 * ofld_xmit - send a packet through an offload queue
1310 * @q: the Tx offload queue
1311 * @skb: the packet
1312 *
1313 * Send an offload packet through an SGE offload queue.
1314 */
1315static int ofld_xmit(struct sge_ofld_txq *q, struct sk_buff *skb)
1316{
1317 skb->priority = calc_tx_flits_ofld(skb); /* save for restart */
1318 spin_lock(&q->sendq.lock);
1319 __skb_queue_tail(&q->sendq, skb);
1320 if (q->sendq.qlen == 1)
1321 service_ofldq(q);
1322 spin_unlock(&q->sendq.lock);
1323 return NET_XMIT_SUCCESS;
1324}
1325
1326/**
1327 * restart_ofldq - restart a suspended offload queue
1328 * @data: the offload queue to restart
1329 *
1330 * Resumes transmission on a suspended Tx offload queue.
1331 */
1332static void restart_ofldq(unsigned long data)
1333{
1334 struct sge_ofld_txq *q = (struct sge_ofld_txq *)data;
1335
1336 spin_lock(&q->sendq.lock);
1337 q->full = 0; /* the queue actually is completely empty now */
1338 service_ofldq(q);
1339 spin_unlock(&q->sendq.lock);
1340}
1341
1342/**
1343 * skb_txq - return the Tx queue an offload packet should use
1344 * @skb: the packet
1345 *
1346 * Returns the Tx queue an offload packet should use as indicated by bits
1347 * 1-15 in the packet's queue_mapping.
1348 */
1349static inline unsigned int skb_txq(const struct sk_buff *skb)
1350{
1351 return skb->queue_mapping >> 1;
1352}
1353
1354/**
1355 * is_ctrl_pkt - return whether an offload packet is a control packet
1356 * @skb: the packet
1357 *
1358 * Returns whether an offload packet should use an OFLD or a CTRL
1359 * Tx queue as indicated by bit 0 in the packet's queue_mapping.
1360 */
1361static inline unsigned int is_ctrl_pkt(const struct sk_buff *skb)
1362{
1363 return skb->queue_mapping & 1;
1364}
1365
1366static inline int ofld_send(struct adapter *adap, struct sk_buff *skb)
1367{
1368 unsigned int idx = skb_txq(skb);
1369
1370 if (unlikely(is_ctrl_pkt(skb)))
1371 return ctrl_xmit(&adap->sge.ctrlq[idx], skb);
1372 return ofld_xmit(&adap->sge.ofldtxq[idx], skb);
1373}
1374
1375/**
1376 * t4_ofld_send - send an offload packet
1377 * @adap: the adapter
1378 * @skb: the packet
1379 *
1380 * Sends an offload packet. We use the packet queue_mapping to select the
1381 * appropriate Tx queue as follows: bit 0 indicates whether the packet
1382 * should be sent as regular or control, bits 1-15 select the queue.
1383 */
1384int t4_ofld_send(struct adapter *adap, struct sk_buff *skb)
1385{
1386 int ret;
1387
1388 local_bh_disable();
1389 ret = ofld_send(adap, skb);
1390 local_bh_enable();
1391 return ret;
1392}
1393
1394/**
1395 * cxgb4_ofld_send - send an offload packet
1396 * @dev: the net device
1397 * @skb: the packet
1398 *
1399 * Sends an offload packet. This is an exported version of @t4_ofld_send,
1400 * intended for ULDs.
1401 */
1402int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb)
1403{
1404 return t4_ofld_send(netdev2adap(dev), skb);
1405}
1406EXPORT_SYMBOL(cxgb4_ofld_send);
1407
1408static inline void copy_frags(struct skb_shared_info *ssi,
1409 const struct pkt_gl *gl, unsigned int offset)
1410{
1411 unsigned int n;
1412
1413 /* usually there's just one frag */
1414 ssi->frags[0].page = gl->frags[0].page;
1415 ssi->frags[0].page_offset = gl->frags[0].page_offset + offset;
1416 ssi->frags[0].size = gl->frags[0].size - offset;
1417 ssi->nr_frags = gl->nfrags;
1418 n = gl->nfrags - 1;
1419 if (n)
1420 memcpy(&ssi->frags[1], &gl->frags[1], n * sizeof(skb_frag_t));
1421
1422 /* get a reference to the last page, we don't own it */
1423 get_page(gl->frags[n].page);
1424}
1425
1426/**
1427 * cxgb4_pktgl_to_skb - build an sk_buff from a packet gather list
1428 * @gl: the gather list
1429 * @skb_len: size of sk_buff main body if it carries fragments
1430 * @pull_len: amount of data to move to the sk_buff's main body
1431 *
1432 * Builds an sk_buff from the given packet gather list. Returns the
1433 * sk_buff or %NULL if sk_buff allocation failed.
1434 */
1435struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl,
1436 unsigned int skb_len, unsigned int pull_len)
1437{
1438 struct sk_buff *skb;
1439
1440 /*
1441 * Below we rely on RX_COPY_THRES being less than the smallest Rx buffer
1442 * size, which is expected since buffers are at least PAGE_SIZEd.
1443 * In this case packets up to RX_COPY_THRES have only one fragment.
1444 */
1445 if (gl->tot_len <= RX_COPY_THRES) {
1446 skb = dev_alloc_skb(gl->tot_len);
1447 if (unlikely(!skb))
1448 goto out;
1449 __skb_put(skb, gl->tot_len);
1450 skb_copy_to_linear_data(skb, gl->va, gl->tot_len);
1451 } else {
1452 skb = dev_alloc_skb(skb_len);
1453 if (unlikely(!skb))
1454 goto out;
1455 __skb_put(skb, pull_len);
1456 skb_copy_to_linear_data(skb, gl->va, pull_len);
1457
1458 copy_frags(skb_shinfo(skb), gl, pull_len);
1459 skb->len = gl->tot_len;
1460 skb->data_len = skb->len - pull_len;
1461 skb->truesize += skb->data_len;
1462 }
1463out: return skb;
1464}
1465EXPORT_SYMBOL(cxgb4_pktgl_to_skb);
1466
1467/**
1468 * t4_pktgl_free - free a packet gather list
1469 * @gl: the gather list
1470 *
1471 * Releases the pages of a packet gather list. We do not own the last
1472 * page on the list and do not free it.
1473 */
1474static void t4_pktgl_free(const struct pkt_gl *gl)
1475{
1476 int n;
1477 const skb_frag_t *p;
1478
1479 for (p = gl->frags, n = gl->nfrags - 1; n--; p++)
1480 put_page(p->page);
1481}
1482
1483/*
1484 * Process an MPS trace packet. Give it an unused protocol number so it won't
1485 * be delivered to anyone and send it to the stack for capture.
1486 */
1487static noinline int handle_trace_pkt(struct adapter *adap,
1488 const struct pkt_gl *gl)
1489{
1490 struct sk_buff *skb;
1491 struct cpl_trace_pkt *p;
1492
1493 skb = cxgb4_pktgl_to_skb(gl, RX_PULL_LEN, RX_PULL_LEN);
1494 if (unlikely(!skb)) {
1495 t4_pktgl_free(gl);
1496 return 0;
1497 }
1498
1499 p = (struct cpl_trace_pkt *)skb->data;
1500 __skb_pull(skb, sizeof(*p));
1501 skb_reset_mac_header(skb);
1502 skb->protocol = htons(0xffff);
1503 skb->dev = adap->port[0];
1504 netif_receive_skb(skb);
1505 return 0;
1506}
1507
1508static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl,
1509 const struct cpl_rx_pkt *pkt)
1510{
1511 int ret;
1512 struct sk_buff *skb;
1513
1514 skb = napi_get_frags(&rxq->rspq.napi);
1515 if (unlikely(!skb)) {
1516 t4_pktgl_free(gl);
1517 rxq->stats.rx_drops++;
1518 return;
1519 }
1520
1521 copy_frags(skb_shinfo(skb), gl, RX_PKT_PAD);
1522 skb->len = gl->tot_len - RX_PKT_PAD;
1523 skb->data_len = skb->len;
1524 skb->truesize += skb->data_len;
1525 skb->ip_summed = CHECKSUM_UNNECESSARY;
1526 skb_record_rx_queue(skb, rxq->rspq.idx);
1527 if (rxq->rspq.netdev->features & NETIF_F_RXHASH)
1528 skb->rxhash = (__force u32)pkt->rsshdr.hash_val;
1529
1530 if (unlikely(pkt->vlan_ex)) {
1531 struct port_info *pi = netdev_priv(rxq->rspq.netdev);
1532 struct vlan_group *grp = pi->vlan_grp;
1533
1534 rxq->stats.vlan_ex++;
1535 if (likely(grp)) {
1536 ret = vlan_gro_frags(&rxq->rspq.napi, grp,
1537 ntohs(pkt->vlan));
1538 goto stats;
1539 }
1540 }
1541 ret = napi_gro_frags(&rxq->rspq.napi);
1542stats: if (ret == GRO_HELD)
1543 rxq->stats.lro_pkts++;
1544 else if (ret == GRO_MERGED || ret == GRO_MERGED_FREE)
1545 rxq->stats.lro_merged++;
1546 rxq->stats.pkts++;
1547 rxq->stats.rx_cso++;
1548}
1549
1550/**
1551 * t4_ethrx_handler - process an ingress ethernet packet
1552 * @q: the response queue that received the packet
1553 * @rsp: the response queue descriptor holding the RX_PKT message
1554 * @si: the gather list of packet fragments
1555 *
1556 * Process an ingress ethernet packet and deliver it to the stack.
1557 */
1558int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1559 const struct pkt_gl *si)
1560{
1561 bool csum_ok;
1562 struct sk_buff *skb;
1563 struct port_info *pi;
1564 const struct cpl_rx_pkt *pkt;
1565 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
1566
1567 if (unlikely(*(u8 *)rsp == CPL_TRACE_PKT))
1568 return handle_trace_pkt(q->adap, si);
1569
1570 pkt = (const struct cpl_rx_pkt *)rsp;
1571 csum_ok = pkt->csum_calc && !pkt->err_vec;
1572 if ((pkt->l2info & htonl(RXF_TCP)) &&
1573 (q->netdev->features & NETIF_F_GRO) && csum_ok && !pkt->ip_frag) {
1574 do_gro(rxq, si, pkt);
1575 return 0;
1576 }
1577
1578 skb = cxgb4_pktgl_to_skb(si, RX_PKT_SKB_LEN, RX_PULL_LEN);
1579 if (unlikely(!skb)) {
1580 t4_pktgl_free(si);
1581 rxq->stats.rx_drops++;
1582 return 0;
1583 }
1584
1585 __skb_pull(skb, RX_PKT_PAD); /* remove ethernet header padding */
1586 skb->protocol = eth_type_trans(skb, q->netdev);
1587 skb_record_rx_queue(skb, q->idx);
1588 if (skb->dev->features & NETIF_F_RXHASH)
1589 skb->rxhash = (__force u32)pkt->rsshdr.hash_val;
1590
1591 pi = netdev_priv(skb->dev);
1592 rxq->stats.pkts++;
1593
1594 if (csum_ok && (pi->rx_offload & RX_CSO) &&
1595 (pkt->l2info & htonl(RXF_UDP | RXF_TCP))) {
1596 if (!pkt->ip_frag)
1597 skb->ip_summed = CHECKSUM_UNNECESSARY;
1598 else {
1599 __sum16 c = (__force __sum16)pkt->csum;
1600 skb->csum = csum_unfold(c);
1601 skb->ip_summed = CHECKSUM_COMPLETE;
1602 }
1603 rxq->stats.rx_cso++;
1604 } else
1605 skb->ip_summed = CHECKSUM_NONE;
1606
1607 if (unlikely(pkt->vlan_ex)) {
1608 struct vlan_group *grp = pi->vlan_grp;
1609
1610 rxq->stats.vlan_ex++;
1611 if (likely(grp))
1612 vlan_hwaccel_receive_skb(skb, grp, ntohs(pkt->vlan));
1613 else
1614 dev_kfree_skb_any(skb);
1615 } else
1616 netif_receive_skb(skb);
1617
1618 return 0;
1619}
1620
1621/**
1622 * restore_rx_bufs - put back a packet's Rx buffers
1623 * @si: the packet gather list
1624 * @q: the SGE free list
1625 * @frags: number of FL buffers to restore
1626 *
1627 * Puts back on an FL the Rx buffers associated with @si. The buffers
1628 * have already been unmapped and are left unmapped, we mark them so to
1629 * prevent further unmapping attempts.
1630 *
1631 * This function undoes a series of @unmap_rx_buf calls when we find out
1632 * that the current packet can't be processed right away afterall and we
1633 * need to come back to it later. This is a very rare event and there's
1634 * no effort to make this particularly efficient.
1635 */
1636static void restore_rx_bufs(const struct pkt_gl *si, struct sge_fl *q,
1637 int frags)
1638{
1639 struct rx_sw_desc *d;
1640
1641 while (frags--) {
1642 if (q->cidx == 0)
1643 q->cidx = q->size - 1;
1644 else
1645 q->cidx--;
1646 d = &q->sdesc[q->cidx];
1647 d->page = si->frags[frags].page;
1648 d->dma_addr |= RX_UNMAPPED_BUF;
1649 q->avail++;
1650 }
1651}
1652
1653/**
1654 * is_new_response - check if a response is newly written
1655 * @r: the response descriptor
1656 * @q: the response queue
1657 *
1658 * Returns true if a response descriptor contains a yet unprocessed
1659 * response.
1660 */
1661static inline bool is_new_response(const struct rsp_ctrl *r,
1662 const struct sge_rspq *q)
1663{
1664 return RSPD_GEN(r->type_gen) == q->gen;
1665}
1666
1667/**
1668 * rspq_next - advance to the next entry in a response queue
1669 * @q: the queue
1670 *
1671 * Updates the state of a response queue to advance it to the next entry.
1672 */
1673static inline void rspq_next(struct sge_rspq *q)
1674{
1675 q->cur_desc = (void *)q->cur_desc + q->iqe_len;
1676 if (unlikely(++q->cidx == q->size)) {
1677 q->cidx = 0;
1678 q->gen ^= 1;
1679 q->cur_desc = q->desc;
1680 }
1681}
1682
1683/**
1684 * process_responses - process responses from an SGE response queue
1685 * @q: the ingress queue to process
1686 * @budget: how many responses can be processed in this round
1687 *
1688 * Process responses from an SGE response queue up to the supplied budget.
1689 * Responses include received packets as well as control messages from FW
1690 * or HW.
1691 *
1692 * Additionally choose the interrupt holdoff time for the next interrupt
1693 * on this queue. If the system is under memory shortage use a fairly
1694 * long delay to help recovery.
1695 */
1696static int process_responses(struct sge_rspq *q, int budget)
1697{
1698 int ret, rsp_type;
1699 int budget_left = budget;
1700 const struct rsp_ctrl *rc;
1701 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
1702
1703 while (likely(budget_left)) {
1704 rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc));
1705 if (!is_new_response(rc, q))
1706 break;
1707
1708 rmb();
1709 rsp_type = RSPD_TYPE(rc->type_gen);
1710 if (likely(rsp_type == RSP_TYPE_FLBUF)) {
1711 skb_frag_t *fp;
1712 struct pkt_gl si;
1713 const struct rx_sw_desc *rsd;
1714 u32 len = ntohl(rc->pldbuflen_qid), bufsz, frags;
1715
1716 if (len & RSPD_NEWBUF) {
1717 if (likely(q->offset > 0)) {
1718 free_rx_bufs(q->adap, &rxq->fl, 1);
1719 q->offset = 0;
1720 }
1721 len &= RSPD_LEN;
1722 }
1723 si.tot_len = len;
1724
1725 /* gather packet fragments */
1726 for (frags = 0, fp = si.frags; ; frags++, fp++) {
1727 rsd = &rxq->fl.sdesc[rxq->fl.cidx];
1728 bufsz = get_buf_size(rsd);
1729 fp->page = rsd->page;
1730 fp->page_offset = q->offset;
1731 fp->size = min(bufsz, len);
1732 len -= fp->size;
1733 if (!len)
1734 break;
1735 unmap_rx_buf(q->adap, &rxq->fl);
1736 }
1737
1738 /*
1739 * Last buffer remains mapped so explicitly make it
1740 * coherent for CPU access.
1741 */
1742 dma_sync_single_for_cpu(q->adap->pdev_dev,
1743 get_buf_addr(rsd),
1744 fp->size, DMA_FROM_DEVICE);
1745
1746 si.va = page_address(si.frags[0].page) +
1747 si.frags[0].page_offset;
1748 prefetch(si.va);
1749
1750 si.nfrags = frags + 1;
1751 ret = q->handler(q, q->cur_desc, &si);
1752 if (likely(ret == 0))
1753 q->offset += ALIGN(fp->size, FL_ALIGN);
1754 else
1755 restore_rx_bufs(&si, &rxq->fl, frags);
1756 } else if (likely(rsp_type == RSP_TYPE_CPL)) {
1757 ret = q->handler(q, q->cur_desc, NULL);
1758 } else {
1759 ret = q->handler(q, (const __be64 *)rc, CXGB4_MSG_AN);
1760 }
1761
1762 if (unlikely(ret)) {
1763 /* couldn't process descriptor, back off for recovery */
1764 q->next_intr_params = QINTR_TIMER_IDX(NOMEM_TMR_IDX);
1765 break;
1766 }
1767
1768 rspq_next(q);
1769 budget_left--;
1770 }
1771
1772 if (q->offset >= 0 && rxq->fl.size - rxq->fl.avail >= 16)
1773 __refill_fl(q->adap, &rxq->fl);
1774 return budget - budget_left;
1775}
1776
1777/**
1778 * napi_rx_handler - the NAPI handler for Rx processing
1779 * @napi: the napi instance
1780 * @budget: how many packets we can process in this round
1781 *
1782 * Handler for new data events when using NAPI. This does not need any
1783 * locking or protection from interrupts as data interrupts are off at
1784 * this point and other adapter interrupts do not interfere (the latter
1785 * in not a concern at all with MSI-X as non-data interrupts then have
1786 * a separate handler).
1787 */
1788static int napi_rx_handler(struct napi_struct *napi, int budget)
1789{
1790 unsigned int params;
1791 struct sge_rspq *q = container_of(napi, struct sge_rspq, napi);
1792 int work_done = process_responses(q, budget);
1793
1794 if (likely(work_done < budget)) {
1795 napi_complete(napi);
1796 params = q->next_intr_params;
1797 q->next_intr_params = q->intr_params;
1798 } else
1799 params = QINTR_TIMER_IDX(7);
1800
1801 t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS), CIDXINC(work_done) |
1802 INGRESSQID((u32)q->cntxt_id) | SEINTARM(params));
1803 return work_done;
1804}
1805
1806/*
1807 * The MSI-X interrupt handler for an SGE response queue.
1808 */
1809irqreturn_t t4_sge_intr_msix(int irq, void *cookie)
1810{
1811 struct sge_rspq *q = cookie;
1812
1813 napi_schedule(&q->napi);
1814 return IRQ_HANDLED;
1815}
1816
1817/*
1818 * Process the indirect interrupt entries in the interrupt queue and kick off
1819 * NAPI for each queue that has generated an entry.
1820 */
1821static unsigned int process_intrq(struct adapter *adap)
1822{
1823 unsigned int credits;
1824 const struct rsp_ctrl *rc;
1825 struct sge_rspq *q = &adap->sge.intrq;
1826
1827 spin_lock(&adap->sge.intrq_lock);
1828 for (credits = 0; ; credits++) {
1829 rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc));
1830 if (!is_new_response(rc, q))
1831 break;
1832
1833 rmb();
1834 if (RSPD_TYPE(rc->type_gen) == RSP_TYPE_INTR) {
1835 unsigned int qid = ntohl(rc->pldbuflen_qid);
1836
1837 napi_schedule(&adap->sge.ingr_map[qid]->napi);
1838 }
1839
1840 rspq_next(q);
1841 }
1842
1843 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS), CIDXINC(credits) |
1844 INGRESSQID(q->cntxt_id) | SEINTARM(q->intr_params));
1845 spin_unlock(&adap->sge.intrq_lock);
1846 return credits;
1847}
1848
1849/*
1850 * The MSI interrupt handler, which handles data events from SGE response queues
1851 * as well as error and other async events as they all use the same MSI vector.
1852 */
1853static irqreturn_t t4_intr_msi(int irq, void *cookie)
1854{
1855 struct adapter *adap = cookie;
1856
1857 t4_slow_intr_handler(adap);
1858 process_intrq(adap);
1859 return IRQ_HANDLED;
1860}
1861
1862/*
1863 * Interrupt handler for legacy INTx interrupts.
1864 * Handles data events from SGE response queues as well as error and other
1865 * async events as they all use the same interrupt line.
1866 */
1867static irqreturn_t t4_intr_intx(int irq, void *cookie)
1868{
1869 struct adapter *adap = cookie;
1870
1871 t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI), 0);
1872 if (t4_slow_intr_handler(adap) | process_intrq(adap))
1873 return IRQ_HANDLED;
1874 return IRQ_NONE; /* probably shared interrupt */
1875}
1876
1877/**
1878 * t4_intr_handler - select the top-level interrupt handler
1879 * @adap: the adapter
1880 *
1881 * Selects the top-level interrupt handler based on the type of interrupts
1882 * (MSI-X, MSI, or INTx).
1883 */
1884irq_handler_t t4_intr_handler(struct adapter *adap)
1885{
1886 if (adap->flags & USING_MSIX)
1887 return t4_sge_intr_msix;
1888 if (adap->flags & USING_MSI)
1889 return t4_intr_msi;
1890 return t4_intr_intx;
1891}
1892
1893static void sge_rx_timer_cb(unsigned long data)
1894{
1895 unsigned long m;
1896 unsigned int i, cnt[2];
1897 struct adapter *adap = (struct adapter *)data;
1898 struct sge *s = &adap->sge;
1899
1900 for (i = 0; i < ARRAY_SIZE(s->starving_fl); i++)
1901 for (m = s->starving_fl[i]; m; m &= m - 1) {
1902 struct sge_eth_rxq *rxq;
1903 unsigned int id = __ffs(m) + i * BITS_PER_LONG;
1904 struct sge_fl *fl = s->egr_map[id];
1905
1906 clear_bit(id, s->starving_fl);
1907 smp_mb__after_clear_bit();
1908
1909 if (fl_starving(fl)) {
1910 rxq = container_of(fl, struct sge_eth_rxq, fl);
1911 if (napi_reschedule(&rxq->rspq.napi))
1912 fl->starving++;
1913 else
1914 set_bit(id, s->starving_fl);
1915 }
1916 }
1917
1918 t4_write_reg(adap, SGE_DEBUG_INDEX, 13);
1919 cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH);
1920 cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
1921
1922 for (i = 0; i < 2; i++)
1923 if (cnt[i] >= s->starve_thres) {
1924 if (s->idma_state[i] || cnt[i] == 0xffffffff)
1925 continue;
1926 s->idma_state[i] = 1;
1927 t4_write_reg(adap, SGE_DEBUG_INDEX, 11);
1928 m = t4_read_reg(adap, SGE_DEBUG_DATA_LOW) >> (i * 16);
1929 dev_warn(adap->pdev_dev,
1930 "SGE idma%u starvation detected for "
1931 "queue %lu\n", i, m & 0xffff);
1932 } else if (s->idma_state[i])
1933 s->idma_state[i] = 0;
1934
1935 mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD);
1936}
1937
1938static void sge_tx_timer_cb(unsigned long data)
1939{
1940 unsigned long m;
1941 unsigned int i, budget;
1942 struct adapter *adap = (struct adapter *)data;
1943 struct sge *s = &adap->sge;
1944
1945 for (i = 0; i < ARRAY_SIZE(s->txq_maperr); i++)
1946 for (m = s->txq_maperr[i]; m; m &= m - 1) {
1947 unsigned long id = __ffs(m) + i * BITS_PER_LONG;
1948 struct sge_ofld_txq *txq = s->egr_map[id];
1949
1950 clear_bit(id, s->txq_maperr);
1951 tasklet_schedule(&txq->qresume_tsk);
1952 }
1953
1954 budget = MAX_TIMER_TX_RECLAIM;
1955 i = s->ethtxq_rover;
1956 do {
1957 struct sge_eth_txq *q = &s->ethtxq[i];
1958
1959 if (q->q.in_use &&
1960 time_after_eq(jiffies, q->txq->trans_start + HZ / 100) &&
1961 __netif_tx_trylock(q->txq)) {
1962 int avail = reclaimable(&q->q);
1963
1964 if (avail) {
1965 if (avail > budget)
1966 avail = budget;
1967
1968 free_tx_desc(adap, &q->q, avail, true);
1969 q->q.in_use -= avail;
1970 budget -= avail;
1971 }
1972 __netif_tx_unlock(q->txq);
1973 }
1974
1975 if (++i >= s->ethqsets)
1976 i = 0;
1977 } while (budget && i != s->ethtxq_rover);
1978 s->ethtxq_rover = i;
1979 mod_timer(&s->tx_timer, jiffies + (budget ? TX_QCHECK_PERIOD : 2));
1980}
1981
1982int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1983 struct net_device *dev, int intr_idx,
1984 struct sge_fl *fl, rspq_handler_t hnd)
1985{
1986 int ret, flsz = 0;
1987 struct fw_iq_cmd c;
1988 struct port_info *pi = netdev_priv(dev);
1989
1990 /* Size needs to be multiple of 16, including status entry. */
1991 iq->size = roundup(iq->size, 16);
1992
1993 iq->desc = alloc_ring(adap->pdev_dev, iq->size, iq->iqe_len, 0,
1994 &iq->phys_addr, NULL, 0);
1995 if (!iq->desc)
1996 return -ENOMEM;
1997
1998 memset(&c, 0, sizeof(c));
1999 c.op_to_vfn = htonl(FW_CMD_OP(FW_IQ_CMD) | FW_CMD_REQUEST |
2000 FW_CMD_WRITE | FW_CMD_EXEC |
2001 FW_IQ_CMD_PFN(0) | FW_IQ_CMD_VFN(0));
2002 c.alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC | FW_IQ_CMD_IQSTART(1) |
2003 FW_LEN16(c));
2004 c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2005 FW_IQ_CMD_IQASYNCH(fwevtq) | FW_IQ_CMD_VIID(pi->viid) |
2006 FW_IQ_CMD_IQANDST(intr_idx < 0) | FW_IQ_CMD_IQANUD(1) |
2007 FW_IQ_CMD_IQANDSTINDEX(intr_idx >= 0 ? intr_idx :
2008 -intr_idx - 1));
2009 c.iqdroprss_to_iqesize = htons(FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2010 FW_IQ_CMD_IQGTSMODE |
2011 FW_IQ_CMD_IQINTCNTTHRESH(iq->pktcnt_idx) |
2012 FW_IQ_CMD_IQESIZE(ilog2(iq->iqe_len) - 4));
2013 c.iqsize = htons(iq->size);
2014 c.iqaddr = cpu_to_be64(iq->phys_addr);
2015
2016 if (fl) {
2017 fl->size = roundup(fl->size, 8);
2018 fl->desc = alloc_ring(adap->pdev_dev, fl->size, sizeof(__be64),
2019 sizeof(struct rx_sw_desc), &fl->addr,
2020 &fl->sdesc, STAT_LEN);
2021 if (!fl->desc)
2022 goto fl_nomem;
2023
2024 flsz = fl->size / 8 + STAT_LEN / sizeof(struct tx_desc);
2025 c.iqns_to_fl0congen = htonl(FW_IQ_CMD_FL0PACKEN |
2026 FW_IQ_CMD_FL0PADEN);
2027 c.fl0dcaen_to_fl0cidxfthresh = htons(FW_IQ_CMD_FL0FBMIN(2) |
2028 FW_IQ_CMD_FL0FBMAX(3));
2029 c.fl0size = htons(flsz);
2030 c.fl0addr = cpu_to_be64(fl->addr);
2031 }
2032
2033 ret = t4_wr_mbox(adap, 0, &c, sizeof(c), &c);
2034 if (ret)
2035 goto err;
2036
2037 netif_napi_add(dev, &iq->napi, napi_rx_handler, 64);
2038 iq->cur_desc = iq->desc;
2039 iq->cidx = 0;
2040 iq->gen = 1;
2041 iq->next_intr_params = iq->intr_params;
2042 iq->cntxt_id = ntohs(c.iqid);
2043 iq->abs_id = ntohs(c.physiqid);
2044 iq->size--; /* subtract status entry */
2045 iq->adap = adap;
2046 iq->netdev = dev;
2047 iq->handler = hnd;
2048
2049 /* set offset to -1 to distinguish ingress queues without FL */
2050 iq->offset = fl ? 0 : -1;
2051
2052 adap->sge.ingr_map[iq->cntxt_id] = iq;
2053
2054 if (fl) {
2055 fl->cntxt_id = ntohs(c.fl0id);
2056 fl->avail = fl->pend_cred = 0;
2057 fl->pidx = fl->cidx = 0;
2058 fl->alloc_failed = fl->large_alloc_failed = fl->starving = 0;
2059 adap->sge.egr_map[fl->cntxt_id] = fl;
2060 refill_fl(adap, fl, fl_cap(fl), GFP_KERNEL);
2061 }
2062 return 0;
2063
2064fl_nomem:
2065 ret = -ENOMEM;
2066err:
2067 if (iq->desc) {
2068 dma_free_coherent(adap->pdev_dev, iq->size * iq->iqe_len,
2069 iq->desc, iq->phys_addr);
2070 iq->desc = NULL;
2071 }
2072 if (fl && fl->desc) {
2073 kfree(fl->sdesc);
2074 fl->sdesc = NULL;
2075 dma_free_coherent(adap->pdev_dev, flsz * sizeof(struct tx_desc),
2076 fl->desc, fl->addr);
2077 fl->desc = NULL;
2078 }
2079 return ret;
2080}
2081
2082static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id)
2083{
2084 q->in_use = 0;
2085 q->cidx = q->pidx = 0;
2086 q->stops = q->restarts = 0;
2087 q->stat = (void *)&q->desc[q->size];
2088 q->cntxt_id = id;
2089 adap->sge.egr_map[id] = q;
2090}
2091
2092int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
2093 struct net_device *dev, struct netdev_queue *netdevq,
2094 unsigned int iqid)
2095{
2096 int ret, nentries;
2097 struct fw_eq_eth_cmd c;
2098 struct port_info *pi = netdev_priv(dev);
2099
2100 /* Add status entries */
2101 nentries = txq->q.size + STAT_LEN / sizeof(struct tx_desc);
2102
2103 txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size,
2104 sizeof(struct tx_desc), sizeof(struct tx_sw_desc),
2105 &txq->q.phys_addr, &txq->q.sdesc, STAT_LEN);
2106 if (!txq->q.desc)
2107 return -ENOMEM;
2108
2109 memset(&c, 0, sizeof(c));
2110 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_ETH_CMD) | FW_CMD_REQUEST |
2111 FW_CMD_WRITE | FW_CMD_EXEC |
2112 FW_EQ_ETH_CMD_PFN(0) | FW_EQ_ETH_CMD_VFN(0));
2113 c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC |
2114 FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
2115 c.viid_pkd = htonl(FW_EQ_ETH_CMD_VIID(pi->viid));
2116 c.fetchszm_to_iqid = htonl(FW_EQ_ETH_CMD_HOSTFCMODE(2) |
2117 FW_EQ_ETH_CMD_PCIECHN(pi->tx_chan) |
2118 FW_EQ_ETH_CMD_IQID(iqid));
2119 c.dcaen_to_eqsize = htonl(FW_EQ_ETH_CMD_FBMIN(2) |
2120 FW_EQ_ETH_CMD_FBMAX(3) |
2121 FW_EQ_ETH_CMD_CIDXFTHRESH(5) |
2122 FW_EQ_ETH_CMD_EQSIZE(nentries));
2123 c.eqaddr = cpu_to_be64(txq->q.phys_addr);
2124
2125 ret = t4_wr_mbox(adap, 0, &c, sizeof(c), &c);
2126 if (ret) {
2127 kfree(txq->q.sdesc);
2128 txq->q.sdesc = NULL;
2129 dma_free_coherent(adap->pdev_dev,
2130 nentries * sizeof(struct tx_desc),
2131 txq->q.desc, txq->q.phys_addr);
2132 txq->q.desc = NULL;
2133 return ret;
2134 }
2135
2136 init_txq(adap, &txq->q, FW_EQ_ETH_CMD_EQID_GET(ntohl(c.eqid_pkd)));
2137 txq->txq = netdevq;
2138 txq->tso = txq->tx_cso = txq->vlan_ins = 0;
2139 txq->mapping_err = 0;
2140 return 0;
2141}
2142
2143int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
2144 struct net_device *dev, unsigned int iqid,
2145 unsigned int cmplqid)
2146{
2147 int ret, nentries;
2148 struct fw_eq_ctrl_cmd c;
2149 struct port_info *pi = netdev_priv(dev);
2150
2151 /* Add status entries */
2152 nentries = txq->q.size + STAT_LEN / sizeof(struct tx_desc);
2153
2154 txq->q.desc = alloc_ring(adap->pdev_dev, nentries,
2155 sizeof(struct tx_desc), 0, &txq->q.phys_addr,
2156 NULL, 0);
2157 if (!txq->q.desc)
2158 return -ENOMEM;
2159
2160 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST |
2161 FW_CMD_WRITE | FW_CMD_EXEC |
2162 FW_EQ_CTRL_CMD_PFN(0) | FW_EQ_CTRL_CMD_VFN(0));
2163 c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC |
2164 FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
2165 c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_CMPLIQID(cmplqid));
2166 c.physeqid_pkd = htonl(0);
2167 c.fetchszm_to_iqid = htonl(FW_EQ_CTRL_CMD_HOSTFCMODE(2) |
2168 FW_EQ_CTRL_CMD_PCIECHN(pi->tx_chan) |
2169 FW_EQ_CTRL_CMD_IQID(iqid));
2170 c.dcaen_to_eqsize = htonl(FW_EQ_CTRL_CMD_FBMIN(2) |
2171 FW_EQ_CTRL_CMD_FBMAX(3) |
2172 FW_EQ_CTRL_CMD_CIDXFTHRESH(5) |
2173 FW_EQ_CTRL_CMD_EQSIZE(nentries));
2174 c.eqaddr = cpu_to_be64(txq->q.phys_addr);
2175
2176 ret = t4_wr_mbox(adap, 0, &c, sizeof(c), &c);
2177 if (ret) {
2178 dma_free_coherent(adap->pdev_dev,
2179 nentries * sizeof(struct tx_desc),
2180 txq->q.desc, txq->q.phys_addr);
2181 txq->q.desc = NULL;
2182 return ret;
2183 }
2184
2185 init_txq(adap, &txq->q, FW_EQ_CTRL_CMD_EQID_GET(ntohl(c.cmpliqid_eqid)));
2186 txq->adap = adap;
2187 skb_queue_head_init(&txq->sendq);
2188 tasklet_init(&txq->qresume_tsk, restart_ctrlq, (unsigned long)txq);
2189 txq->full = 0;
2190 return 0;
2191}
2192
2193int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
2194 struct net_device *dev, unsigned int iqid)
2195{
2196 int ret, nentries;
2197 struct fw_eq_ofld_cmd c;
2198 struct port_info *pi = netdev_priv(dev);
2199
2200 /* Add status entries */
2201 nentries = txq->q.size + STAT_LEN / sizeof(struct tx_desc);
2202
2203 txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size,
2204 sizeof(struct tx_desc), sizeof(struct tx_sw_desc),
2205 &txq->q.phys_addr, &txq->q.sdesc, STAT_LEN);
2206 if (!txq->q.desc)
2207 return -ENOMEM;
2208
2209 memset(&c, 0, sizeof(c));
2210 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST |
2211 FW_CMD_WRITE | FW_CMD_EXEC |
2212 FW_EQ_OFLD_CMD_PFN(0) | FW_EQ_OFLD_CMD_VFN(0));
2213 c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC |
2214 FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
2215 c.fetchszm_to_iqid = htonl(FW_EQ_OFLD_CMD_HOSTFCMODE(2) |
2216 FW_EQ_OFLD_CMD_PCIECHN(pi->tx_chan) |
2217 FW_EQ_OFLD_CMD_IQID(iqid));
2218 c.dcaen_to_eqsize = htonl(FW_EQ_OFLD_CMD_FBMIN(2) |
2219 FW_EQ_OFLD_CMD_FBMAX(3) |
2220 FW_EQ_OFLD_CMD_CIDXFTHRESH(5) |
2221 FW_EQ_OFLD_CMD_EQSIZE(nentries));
2222 c.eqaddr = cpu_to_be64(txq->q.phys_addr);
2223
2224 ret = t4_wr_mbox(adap, 0, &c, sizeof(c), &c);
2225 if (ret) {
2226 kfree(txq->q.sdesc);
2227 txq->q.sdesc = NULL;
2228 dma_free_coherent(adap->pdev_dev,
2229 nentries * sizeof(struct tx_desc),
2230 txq->q.desc, txq->q.phys_addr);
2231 txq->q.desc = NULL;
2232 return ret;
2233 }
2234
2235 init_txq(adap, &txq->q, FW_EQ_OFLD_CMD_EQID_GET(ntohl(c.eqid_pkd)));
2236 txq->adap = adap;
2237 skb_queue_head_init(&txq->sendq);
2238 tasklet_init(&txq->qresume_tsk, restart_ofldq, (unsigned long)txq);
2239 txq->full = 0;
2240 txq->mapping_err = 0;
2241 return 0;
2242}
2243
2244static void free_txq(struct adapter *adap, struct sge_txq *q)
2245{
2246 dma_free_coherent(adap->pdev_dev,
2247 q->size * sizeof(struct tx_desc) + STAT_LEN,
2248 q->desc, q->phys_addr);
2249 q->cntxt_id = 0;
2250 q->sdesc = NULL;
2251 q->desc = NULL;
2252}
2253
2254static void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq,
2255 struct sge_fl *fl)
2256{
2257 unsigned int fl_id = fl ? fl->cntxt_id : 0xffff;
2258
2259 adap->sge.ingr_map[rq->cntxt_id] = NULL;
2260 t4_iq_free(adap, 0, 0, 0, FW_IQ_TYPE_FL_INT_CAP, rq->cntxt_id, fl_id,
2261 0xffff);
2262 dma_free_coherent(adap->pdev_dev, (rq->size + 1) * rq->iqe_len,
2263 rq->desc, rq->phys_addr);
2264 netif_napi_del(&rq->napi);
2265 rq->netdev = NULL;
2266 rq->cntxt_id = rq->abs_id = 0;
2267 rq->desc = NULL;
2268
2269 if (fl) {
2270 free_rx_bufs(adap, fl, fl->avail);
2271 dma_free_coherent(adap->pdev_dev, fl->size * 8 + STAT_LEN,
2272 fl->desc, fl->addr);
2273 kfree(fl->sdesc);
2274 fl->sdesc = NULL;
2275 fl->cntxt_id = 0;
2276 fl->desc = NULL;
2277 }
2278}
2279
2280/**
2281 * t4_free_sge_resources - free SGE resources
2282 * @adap: the adapter
2283 *
2284 * Frees resources used by the SGE queue sets.
2285 */
2286void t4_free_sge_resources(struct adapter *adap)
2287{
2288 int i;
2289 struct sge_eth_rxq *eq = adap->sge.ethrxq;
2290 struct sge_eth_txq *etq = adap->sge.ethtxq;
2291 struct sge_ofld_rxq *oq = adap->sge.ofldrxq;
2292
2293 /* clean up Ethernet Tx/Rx queues */
2294 for (i = 0; i < adap->sge.ethqsets; i++, eq++, etq++) {
2295 if (eq->rspq.desc)
2296 free_rspq_fl(adap, &eq->rspq, &eq->fl);
2297 if (etq->q.desc) {
2298 t4_eth_eq_free(adap, 0, 0, 0, etq->q.cntxt_id);
2299 free_tx_desc(adap, &etq->q, etq->q.in_use, true);
2300 kfree(etq->q.sdesc);
2301 free_txq(adap, &etq->q);
2302 }
2303 }
2304
2305 /* clean up RDMA and iSCSI Rx queues */
2306 for (i = 0; i < adap->sge.ofldqsets; i++, oq++) {
2307 if (oq->rspq.desc)
2308 free_rspq_fl(adap, &oq->rspq, &oq->fl);
2309 }
2310 for (i = 0, oq = adap->sge.rdmarxq; i < adap->sge.rdmaqs; i++, oq++) {
2311 if (oq->rspq.desc)
2312 free_rspq_fl(adap, &oq->rspq, &oq->fl);
2313 }
2314
2315 /* clean up offload Tx queues */
2316 for (i = 0; i < ARRAY_SIZE(adap->sge.ofldtxq); i++) {
2317 struct sge_ofld_txq *q = &adap->sge.ofldtxq[i];
2318
2319 if (q->q.desc) {
2320 tasklet_kill(&q->qresume_tsk);
2321 t4_ofld_eq_free(adap, 0, 0, 0, q->q.cntxt_id);
2322 free_tx_desc(adap, &q->q, q->q.in_use, false);
2323 kfree(q->q.sdesc);
2324 __skb_queue_purge(&q->sendq);
2325 free_txq(adap, &q->q);
2326 }
2327 }
2328
2329 /* clean up control Tx queues */
2330 for (i = 0; i < ARRAY_SIZE(adap->sge.ctrlq); i++) {
2331 struct sge_ctrl_txq *cq = &adap->sge.ctrlq[i];
2332
2333 if (cq->q.desc) {
2334 tasklet_kill(&cq->qresume_tsk);
2335 t4_ctrl_eq_free(adap, 0, 0, 0, cq->q.cntxt_id);
2336 __skb_queue_purge(&cq->sendq);
2337 free_txq(adap, &cq->q);
2338 }
2339 }
2340
2341 if (adap->sge.fw_evtq.desc)
2342 free_rspq_fl(adap, &adap->sge.fw_evtq, NULL);
2343
2344 if (adap->sge.intrq.desc)
2345 free_rspq_fl(adap, &adap->sge.intrq, NULL);
2346
2347 /* clear the reverse egress queue map */
2348 memset(adap->sge.egr_map, 0, sizeof(adap->sge.egr_map));
2349}
2350
2351void t4_sge_start(struct adapter *adap)
2352{
2353 adap->sge.ethtxq_rover = 0;
2354 mod_timer(&adap->sge.rx_timer, jiffies + RX_QCHECK_PERIOD);
2355 mod_timer(&adap->sge.tx_timer, jiffies + TX_QCHECK_PERIOD);
2356}
2357
2358/**
2359 * t4_sge_stop - disable SGE operation
2360 * @adap: the adapter
2361 *
2362 * Stop tasklets and timers associated with the DMA engine. Note that
2363 * this is effective only if measures have been taken to disable any HW
2364 * events that may restart them.
2365 */
2366void t4_sge_stop(struct adapter *adap)
2367{
2368 int i;
2369 struct sge *s = &adap->sge;
2370
2371 if (in_interrupt()) /* actions below require waiting */
2372 return;
2373
2374 if (s->rx_timer.function)
2375 del_timer_sync(&s->rx_timer);
2376 if (s->tx_timer.function)
2377 del_timer_sync(&s->tx_timer);
2378
2379 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++) {
2380 struct sge_ofld_txq *q = &s->ofldtxq[i];
2381
2382 if (q->q.desc)
2383 tasklet_kill(&q->qresume_tsk);
2384 }
2385 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) {
2386 struct sge_ctrl_txq *cq = &s->ctrlq[i];
2387
2388 if (cq->q.desc)
2389 tasklet_kill(&cq->qresume_tsk);
2390 }
2391}
2392
2393/**
2394 * t4_sge_init - initialize SGE
2395 * @adap: the adapter
2396 *
2397 * Performs SGE initialization needed every time after a chip reset.
2398 * We do not initialize any of the queues here, instead the driver
2399 * top-level must request them individually.
2400 */
2401void t4_sge_init(struct adapter *adap)
2402{
2403 struct sge *s = &adap->sge;
2404 unsigned int fl_align_log = ilog2(FL_ALIGN);
2405
2406 t4_set_reg_field(adap, SGE_CONTROL, PKTSHIFT_MASK |
2407 INGPADBOUNDARY_MASK | EGRSTATUSPAGESIZE,
2408 INGPADBOUNDARY(fl_align_log - 5) | PKTSHIFT(2) |
2409 RXPKTCPLMODE |
2410 (STAT_LEN == 128 ? EGRSTATUSPAGESIZE : 0));
2411 t4_set_reg_field(adap, SGE_HOST_PAGE_SIZE, HOSTPAGESIZEPF0_MASK,
2412 HOSTPAGESIZEPF0(PAGE_SHIFT - 10));
2413 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0, PAGE_SIZE);
2414#if FL_PG_ORDER > 0
2415 t4_write_reg(adap, SGE_FL_BUFFER_SIZE1, PAGE_SIZE << FL_PG_ORDER);
2416#endif
2417 t4_write_reg(adap, SGE_INGRESS_RX_THRESHOLD,
2418 THRESHOLD_0(s->counter_val[0]) |
2419 THRESHOLD_1(s->counter_val[1]) |
2420 THRESHOLD_2(s->counter_val[2]) |
2421 THRESHOLD_3(s->counter_val[3]));
2422 t4_write_reg(adap, SGE_TIMER_VALUE_0_AND_1,
2423 TIMERVALUE0(us_to_core_ticks(adap, s->timer_val[0])) |
2424 TIMERVALUE1(us_to_core_ticks(adap, s->timer_val[1])));
2425 t4_write_reg(adap, SGE_TIMER_VALUE_2_AND_3,
2426 TIMERVALUE0(us_to_core_ticks(adap, s->timer_val[2])) |
2427 TIMERVALUE1(us_to_core_ticks(adap, s->timer_val[3])));
2428 t4_write_reg(adap, SGE_TIMER_VALUE_4_AND_5,
2429 TIMERVALUE0(us_to_core_ticks(adap, s->timer_val[4])) |
2430 TIMERVALUE1(us_to_core_ticks(adap, s->timer_val[5])));
2431 setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adap);
2432 setup_timer(&s->tx_timer, sge_tx_timer_cb, (unsigned long)adap);
2433 s->starve_thres = core_ticks_per_usec(adap) * 1000000; /* 1 s */
2434 s->idma_state[0] = s->idma_state[1] = 0;
2435 spin_lock_init(&s->intrq_lock);
2436}
diff --git a/drivers/net/cxgb4/t4_hw.c b/drivers/net/cxgb4/t4_hw.c
new file mode 100644
index 000000000000..2923dd43523d
--- /dev/null
+++ b/drivers/net/cxgb4/t4_hw.c
@@ -0,0 +1,3147 @@
1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/init.h>
36#include <linux/delay.h>
37#include "cxgb4.h"
38#include "t4_regs.h"
39#include "t4fw_api.h"
40
41/**
42 * t4_wait_op_done_val - wait until an operation is completed
43 * @adapter: the adapter performing the operation
44 * @reg: the register to check for completion
45 * @mask: a single-bit field within @reg that indicates completion
46 * @polarity: the value of the field when the operation is completed
47 * @attempts: number of check iterations
48 * @delay: delay in usecs between iterations
49 * @valp: where to store the value of the register at completion time
50 *
51 * Wait until an operation is completed by checking a bit in a register
52 * up to @attempts times. If @valp is not NULL the value of the register
53 * at the time it indicated completion is stored there. Returns 0 if the
54 * operation completes and -EAGAIN otherwise.
55 */
56static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
57 int polarity, int attempts, int delay, u32 *valp)
58{
59 while (1) {
60 u32 val = t4_read_reg(adapter, reg);
61
62 if (!!(val & mask) == polarity) {
63 if (valp)
64 *valp = val;
65 return 0;
66 }
67 if (--attempts == 0)
68 return -EAGAIN;
69 if (delay)
70 udelay(delay);
71 }
72}
73
74static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
75 int polarity, int attempts, int delay)
76{
77 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
78 delay, NULL);
79}
80
81/**
82 * t4_set_reg_field - set a register field to a value
83 * @adapter: the adapter to program
84 * @addr: the register address
85 * @mask: specifies the portion of the register to modify
86 * @val: the new value for the register field
87 *
88 * Sets a register field specified by the supplied mask to the
89 * given value.
90 */
91void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
92 u32 val)
93{
94 u32 v = t4_read_reg(adapter, addr) & ~mask;
95
96 t4_write_reg(adapter, addr, v | val);
97 (void) t4_read_reg(adapter, addr); /* flush */
98}
99
100/**
101 * t4_read_indirect - read indirectly addressed registers
102 * @adap: the adapter
103 * @addr_reg: register holding the indirect address
104 * @data_reg: register holding the value of the indirect register
105 * @vals: where the read register values are stored
106 * @nregs: how many indirect registers to read
107 * @start_idx: index of first indirect register to read
108 *
109 * Reads registers that are accessed indirectly through an address/data
110 * register pair.
111 */
112static void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
113 unsigned int data_reg, u32 *vals,
114 unsigned int nregs, unsigned int start_idx)
115{
116 while (nregs--) {
117 t4_write_reg(adap, addr_reg, start_idx);
118 *vals++ = t4_read_reg(adap, data_reg);
119 start_idx++;
120 }
121}
122
123#if 0
124/**
125 * t4_write_indirect - write indirectly addressed registers
126 * @adap: the adapter
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
132 *
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
135 */
136static void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
139{
140 while (nregs--) {
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
143 }
144}
145#endif
146
147/*
148 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
149 */
150static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
151 u32 mbox_addr)
152{
153 for ( ; nflit; nflit--, mbox_addr += 8)
154 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
155}
156
157/*
158 * Handle a FW assertion reported in a mailbox.
159 */
160static void fw_asrt(struct adapter *adap, u32 mbox_addr)
161{
162 struct fw_debug_cmd asrt;
163
164 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
165 dev_alert(adap->pdev_dev,
166 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
167 asrt.u.assert.filename_0_7, ntohl(asrt.u.assert.line),
168 ntohl(asrt.u.assert.x), ntohl(asrt.u.assert.y));
169}
170
171static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
172{
173 dev_err(adap->pdev_dev,
174 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
175 (unsigned long long)t4_read_reg64(adap, data_reg),
176 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
177 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
178 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
179 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
180 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
181 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
182 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
183}
184
185/**
186 * t4_wr_mbox_meat - send a command to FW through the given mailbox
187 * @adap: the adapter
188 * @mbox: index of the mailbox to use
189 * @cmd: the command to write
190 * @size: command length in bytes
191 * @rpl: where to optionally store the reply
192 * @sleep_ok: if true we may sleep while awaiting command completion
193 *
194 * Sends the given command to FW through the selected mailbox and waits
195 * for the FW to execute the command. If @rpl is not %NULL it is used to
196 * store the FW's reply to the command. The command and its optional
197 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
198 * to respond. @sleep_ok determines whether we may sleep while awaiting
199 * the response. If sleeping is allowed we use progressive backoff
200 * otherwise we spin.
201 *
202 * The return value is 0 on success or a negative errno on failure. A
203 * failure can happen either because we are not able to execute the
204 * command or FW executes it but signals an error. In the latter case
205 * the return value is the error code indicated by FW (negated).
206 */
207int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
208 void *rpl, bool sleep_ok)
209{
210 static int delay[] = {
211 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
212 };
213
214 u32 v;
215 u64 res;
216 int i, ms, delay_idx;
217 const __be64 *p = cmd;
218 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA);
219 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL);
220
221 if ((size & 15) || size > MBOX_LEN)
222 return -EINVAL;
223
224 v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
225 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
226 v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
227
228 if (v != MBOX_OWNER_DRV)
229 return v ? -EBUSY : -ETIMEDOUT;
230
231 for (i = 0; i < size; i += 8)
232 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
233
234 t4_write_reg(adap, ctl_reg, MBMSGVALID | MBOWNER(MBOX_OWNER_FW));
235 t4_read_reg(adap, ctl_reg); /* flush write */
236
237 delay_idx = 0;
238 ms = delay[0];
239
240 for (i = 0; i < FW_CMD_MAX_TIMEOUT; i += ms) {
241 if (sleep_ok) {
242 ms = delay[delay_idx]; /* last element may repeat */
243 if (delay_idx < ARRAY_SIZE(delay) - 1)
244 delay_idx++;
245 msleep(ms);
246 } else
247 mdelay(ms);
248
249 v = t4_read_reg(adap, ctl_reg);
250 if (MBOWNER_GET(v) == MBOX_OWNER_DRV) {
251 if (!(v & MBMSGVALID)) {
252 t4_write_reg(adap, ctl_reg, 0);
253 continue;
254 }
255
256 res = t4_read_reg64(adap, data_reg);
257 if (FW_CMD_OP_GET(res >> 32) == FW_DEBUG_CMD) {
258 fw_asrt(adap, data_reg);
259 res = FW_CMD_RETVAL(EIO);
260 } else if (rpl)
261 get_mbox_rpl(adap, rpl, size / 8, data_reg);
262
263 if (FW_CMD_RETVAL_GET((int)res))
264 dump_mbox(adap, mbox, data_reg);
265 t4_write_reg(adap, ctl_reg, 0);
266 return -FW_CMD_RETVAL_GET((int)res);
267 }
268 }
269
270 dump_mbox(adap, mbox, data_reg);
271 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
272 *(const u8 *)cmd, mbox);
273 return -ETIMEDOUT;
274}
275
276/**
277 * t4_mc_read - read from MC through backdoor accesses
278 * @adap: the adapter
279 * @addr: address of first byte requested
280 * @data: 64 bytes of data containing the requested address
281 * @ecc: where to store the corresponding 64-bit ECC word
282 *
283 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
284 * that covers the requested address @addr. If @parity is not %NULL it
285 * is assigned the 64-bit ECC word for the read data.
286 */
287int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *ecc)
288{
289 int i;
290
291 if (t4_read_reg(adap, MC_BIST_CMD) & START_BIST)
292 return -EBUSY;
293 t4_write_reg(adap, MC_BIST_CMD_ADDR, addr & ~0x3fU);
294 t4_write_reg(adap, MC_BIST_CMD_LEN, 64);
295 t4_write_reg(adap, MC_BIST_DATA_PATTERN, 0xc);
296 t4_write_reg(adap, MC_BIST_CMD, BIST_OPCODE(1) | START_BIST |
297 BIST_CMD_GAP(1));
298 i = t4_wait_op_done(adap, MC_BIST_CMD, START_BIST, 0, 10, 1);
299 if (i)
300 return i;
301
302#define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA, i)
303
304 for (i = 15; i >= 0; i--)
305 *data++ = htonl(t4_read_reg(adap, MC_DATA(i)));
306 if (ecc)
307 *ecc = t4_read_reg64(adap, MC_DATA(16));
308#undef MC_DATA
309 return 0;
310}
311
312/**
313 * t4_edc_read - read from EDC through backdoor accesses
314 * @adap: the adapter
315 * @idx: which EDC to access
316 * @addr: address of first byte requested
317 * @data: 64 bytes of data containing the requested address
318 * @ecc: where to store the corresponding 64-bit ECC word
319 *
320 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
321 * that covers the requested address @addr. If @parity is not %NULL it
322 * is assigned the 64-bit ECC word for the read data.
323 */
324int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
325{
326 int i;
327
328 idx *= EDC_STRIDE;
329 if (t4_read_reg(adap, EDC_BIST_CMD + idx) & START_BIST)
330 return -EBUSY;
331 t4_write_reg(adap, EDC_BIST_CMD_ADDR + idx, addr & ~0x3fU);
332 t4_write_reg(adap, EDC_BIST_CMD_LEN + idx, 64);
333 t4_write_reg(adap, EDC_BIST_DATA_PATTERN + idx, 0xc);
334 t4_write_reg(adap, EDC_BIST_CMD + idx,
335 BIST_OPCODE(1) | BIST_CMD_GAP(1) | START_BIST);
336 i = t4_wait_op_done(adap, EDC_BIST_CMD + idx, START_BIST, 0, 10, 1);
337 if (i)
338 return i;
339
340#define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA, i) + idx)
341
342 for (i = 15; i >= 0; i--)
343 *data++ = htonl(t4_read_reg(adap, EDC_DATA(i)));
344 if (ecc)
345 *ecc = t4_read_reg64(adap, EDC_DATA(16));
346#undef EDC_DATA
347 return 0;
348}
349
350/*
351 * Partial EEPROM Vital Product Data structure. Includes only the ID and
352 * VPD-R header.
353 */
354struct t4_vpd_hdr {
355 u8 id_tag;
356 u8 id_len[2];
357 u8 id_data[ID_LEN];
358 u8 vpdr_tag;
359 u8 vpdr_len[2];
360};
361
362#define EEPROM_STAT_ADDR 0x7bfc
363#define VPD_BASE 0
364#define VPD_LEN 512
365
366/**
367 * t4_seeprom_wp - enable/disable EEPROM write protection
368 * @adapter: the adapter
369 * @enable: whether to enable or disable write protection
370 *
371 * Enables or disables write protection on the serial EEPROM.
372 */
373int t4_seeprom_wp(struct adapter *adapter, bool enable)
374{
375 unsigned int v = enable ? 0xc : 0;
376 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
377 return ret < 0 ? ret : 0;
378}
379
380/**
381 * get_vpd_params - read VPD parameters from VPD EEPROM
382 * @adapter: adapter to read
383 * @p: where to store the parameters
384 *
385 * Reads card parameters stored in VPD EEPROM.
386 */
387static int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
388{
389 int i, ret;
390 int ec, sn, v2;
391 u8 vpd[VPD_LEN], csum;
392 unsigned int vpdr_len;
393 const struct t4_vpd_hdr *v;
394
395 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(vpd), vpd);
396 if (ret < 0)
397 return ret;
398
399 v = (const struct t4_vpd_hdr *)vpd;
400 vpdr_len = pci_vpd_lrdt_size(&v->vpdr_tag);
401 if (vpdr_len + sizeof(struct t4_vpd_hdr) > VPD_LEN) {
402 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
403 return -EINVAL;
404 }
405
406#define FIND_VPD_KW(var, name) do { \
407 var = pci_vpd_find_info_keyword(&v->id_tag, sizeof(struct t4_vpd_hdr), \
408 vpdr_len, name); \
409 if (var < 0) { \
410 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
411 return -EINVAL; \
412 } \
413 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
414} while (0)
415
416 FIND_VPD_KW(i, "RV");
417 for (csum = 0; i >= 0; i--)
418 csum += vpd[i];
419
420 if (csum) {
421 dev_err(adapter->pdev_dev,
422 "corrupted VPD EEPROM, actual csum %u\n", csum);
423 return -EINVAL;
424 }
425
426 FIND_VPD_KW(ec, "EC");
427 FIND_VPD_KW(sn, "SN");
428 FIND_VPD_KW(v2, "V2");
429#undef FIND_VPD_KW
430
431 p->cclk = simple_strtoul(vpd + v2, NULL, 10);
432 memcpy(p->id, v->id_data, ID_LEN);
433 strim(p->id);
434 memcpy(p->ec, vpd + ec, EC_LEN);
435 strim(p->ec);
436 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
437 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
438 strim(p->sn);
439 return 0;
440}
441
442/* serial flash and firmware constants */
443enum {
444 SF_ATTEMPTS = 10, /* max retries for SF operations */
445
446 /* flash command opcodes */
447 SF_PROG_PAGE = 2, /* program page */
448 SF_WR_DISABLE = 4, /* disable writes */
449 SF_RD_STATUS = 5, /* read status register */
450 SF_WR_ENABLE = 6, /* enable writes */
451 SF_RD_DATA_FAST = 0xb, /* read flash */
452 SF_ERASE_SECTOR = 0xd8, /* erase sector */
453
454 FW_START_SEC = 8, /* first flash sector for FW */
455 FW_END_SEC = 15, /* last flash sector for FW */
456 FW_IMG_START = FW_START_SEC * SF_SEC_SIZE,
457 FW_MAX_SIZE = (FW_END_SEC - FW_START_SEC + 1) * SF_SEC_SIZE,
458};
459
460/**
461 * sf1_read - read data from the serial flash
462 * @adapter: the adapter
463 * @byte_cnt: number of bytes to read
464 * @cont: whether another operation will be chained
465 * @lock: whether to lock SF for PL access only
466 * @valp: where to store the read data
467 *
468 * Reads up to 4 bytes of data from the serial flash. The location of
469 * the read needs to be specified prior to calling this by issuing the
470 * appropriate commands to the serial flash.
471 */
472static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
473 int lock, u32 *valp)
474{
475 int ret;
476
477 if (!byte_cnt || byte_cnt > 4)
478 return -EINVAL;
479 if (t4_read_reg(adapter, SF_OP) & BUSY)
480 return -EBUSY;
481 cont = cont ? SF_CONT : 0;
482 lock = lock ? SF_LOCK : 0;
483 t4_write_reg(adapter, SF_OP, lock | cont | BYTECNT(byte_cnt - 1));
484 ret = t4_wait_op_done(adapter, SF_OP, BUSY, 0, SF_ATTEMPTS, 5);
485 if (!ret)
486 *valp = t4_read_reg(adapter, SF_DATA);
487 return ret;
488}
489
490/**
491 * sf1_write - write data to the serial flash
492 * @adapter: the adapter
493 * @byte_cnt: number of bytes to write
494 * @cont: whether another operation will be chained
495 * @lock: whether to lock SF for PL access only
496 * @val: value to write
497 *
498 * Writes up to 4 bytes of data to the serial flash. The location of
499 * the write needs to be specified prior to calling this by issuing the
500 * appropriate commands to the serial flash.
501 */
502static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
503 int lock, u32 val)
504{
505 if (!byte_cnt || byte_cnt > 4)
506 return -EINVAL;
507 if (t4_read_reg(adapter, SF_OP) & BUSY)
508 return -EBUSY;
509 cont = cont ? SF_CONT : 0;
510 lock = lock ? SF_LOCK : 0;
511 t4_write_reg(adapter, SF_DATA, val);
512 t4_write_reg(adapter, SF_OP, lock |
513 cont | BYTECNT(byte_cnt - 1) | OP_WR);
514 return t4_wait_op_done(adapter, SF_OP, BUSY, 0, SF_ATTEMPTS, 5);
515}
516
517/**
518 * flash_wait_op - wait for a flash operation to complete
519 * @adapter: the adapter
520 * @attempts: max number of polls of the status register
521 * @delay: delay between polls in ms
522 *
523 * Wait for a flash operation to complete by polling the status register.
524 */
525static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
526{
527 int ret;
528 u32 status;
529
530 while (1) {
531 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
532 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
533 return ret;
534 if (!(status & 1))
535 return 0;
536 if (--attempts == 0)
537 return -EAGAIN;
538 if (delay)
539 msleep(delay);
540 }
541}
542
543/**
544 * t4_read_flash - read words from serial flash
545 * @adapter: the adapter
546 * @addr: the start address for the read
547 * @nwords: how many 32-bit words to read
548 * @data: where to store the read data
549 * @byte_oriented: whether to store data as bytes or as words
550 *
551 * Read the specified number of 32-bit words from the serial flash.
552 * If @byte_oriented is set the read data is stored as a byte array
553 * (i.e., big-endian), otherwise as 32-bit words in the platform's
554 * natural endianess.
555 */
556static int t4_read_flash(struct adapter *adapter, unsigned int addr,
557 unsigned int nwords, u32 *data, int byte_oriented)
558{
559 int ret;
560
561 if (addr + nwords * sizeof(u32) > SF_SIZE || (addr & 3))
562 return -EINVAL;
563
564 addr = swab32(addr) | SF_RD_DATA_FAST;
565
566 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
567 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
568 return ret;
569
570 for ( ; nwords; nwords--, data++) {
571 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
572 if (nwords == 1)
573 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
574 if (ret)
575 return ret;
576 if (byte_oriented)
577 *data = htonl(*data);
578 }
579 return 0;
580}
581
582/**
583 * t4_write_flash - write up to a page of data to the serial flash
584 * @adapter: the adapter
585 * @addr: the start address to write
586 * @n: length of data to write in bytes
587 * @data: the data to write
588 *
589 * Writes up to a page of data (256 bytes) to the serial flash starting
590 * at the given address. All the data must be written to the same page.
591 */
592static int t4_write_flash(struct adapter *adapter, unsigned int addr,
593 unsigned int n, const u8 *data)
594{
595 int ret;
596 u32 buf[64];
597 unsigned int i, c, left, val, offset = addr & 0xff;
598
599 if (addr >= SF_SIZE || offset + n > SF_PAGE_SIZE)
600 return -EINVAL;
601
602 val = swab32(addr) | SF_PROG_PAGE;
603
604 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
605 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
606 goto unlock;
607
608 for (left = n; left; left -= c) {
609 c = min(left, 4U);
610 for (val = 0, i = 0; i < c; ++i)
611 val = (val << 8) + *data++;
612
613 ret = sf1_write(adapter, c, c != left, 1, val);
614 if (ret)
615 goto unlock;
616 }
617 ret = flash_wait_op(adapter, 5, 1);
618 if (ret)
619 goto unlock;
620
621 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
622
623 /* Read the page to verify the write succeeded */
624 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
625 if (ret)
626 return ret;
627
628 if (memcmp(data - n, (u8 *)buf + offset, n)) {
629 dev_err(adapter->pdev_dev,
630 "failed to correctly write the flash page at %#x\n",
631 addr);
632 return -EIO;
633 }
634 return 0;
635
636unlock:
637 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
638 return ret;
639}
640
641/**
642 * get_fw_version - read the firmware version
643 * @adapter: the adapter
644 * @vers: where to place the version
645 *
646 * Reads the FW version from flash.
647 */
648static int get_fw_version(struct adapter *adapter, u32 *vers)
649{
650 return t4_read_flash(adapter,
651 FW_IMG_START + offsetof(struct fw_hdr, fw_ver), 1,
652 vers, 0);
653}
654
655/**
656 * get_tp_version - read the TP microcode version
657 * @adapter: the adapter
658 * @vers: where to place the version
659 *
660 * Reads the TP microcode version from flash.
661 */
662static int get_tp_version(struct adapter *adapter, u32 *vers)
663{
664 return t4_read_flash(adapter, FW_IMG_START + offsetof(struct fw_hdr,
665 tp_microcode_ver),
666 1, vers, 0);
667}
668
669/**
670 * t4_check_fw_version - check if the FW is compatible with this driver
671 * @adapter: the adapter
672 *
673 * Checks if an adapter's FW is compatible with the driver. Returns 0
674 * if there's exact match, a negative error if the version could not be
675 * read or there's a major version mismatch, and a positive value if the
676 * expected major version is found but there's a minor version mismatch.
677 */
678int t4_check_fw_version(struct adapter *adapter)
679{
680 u32 api_vers[2];
681 int ret, major, minor, micro;
682
683 ret = get_fw_version(adapter, &adapter->params.fw_vers);
684 if (!ret)
685 ret = get_tp_version(adapter, &adapter->params.tp_vers);
686 if (!ret)
687 ret = t4_read_flash(adapter,
688 FW_IMG_START + offsetof(struct fw_hdr, intfver_nic),
689 2, api_vers, 1);
690 if (ret)
691 return ret;
692
693 major = FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers);
694 minor = FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers);
695 micro = FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers);
696 memcpy(adapter->params.api_vers, api_vers,
697 sizeof(adapter->params.api_vers));
698
699 if (major != FW_VERSION_MAJOR) { /* major mismatch - fail */
700 dev_err(adapter->pdev_dev,
701 "card FW has major version %u, driver wants %u\n",
702 major, FW_VERSION_MAJOR);
703 return -EINVAL;
704 }
705
706 if (minor == FW_VERSION_MINOR && micro == FW_VERSION_MICRO)
707 return 0; /* perfect match */
708
709 /* Minor/micro version mismatch. Report it but often it's OK. */
710 return 1;
711}
712
713/**
714 * t4_flash_erase_sectors - erase a range of flash sectors
715 * @adapter: the adapter
716 * @start: the first sector to erase
717 * @end: the last sector to erase
718 *
719 * Erases the sectors in the given inclusive range.
720 */
721static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
722{
723 int ret = 0;
724
725 while (start <= end) {
726 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
727 (ret = sf1_write(adapter, 4, 0, 1,
728 SF_ERASE_SECTOR | (start << 8))) != 0 ||
729 (ret = flash_wait_op(adapter, 5, 500)) != 0) {
730 dev_err(adapter->pdev_dev,
731 "erase of flash sector %d failed, error %d\n",
732 start, ret);
733 break;
734 }
735 start++;
736 }
737 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
738 return ret;
739}
740
741/**
742 * t4_load_fw - download firmware
743 * @adap: the adapter
744 * @fw_data: the firmware image to write
745 * @size: image size
746 *
747 * Write the supplied firmware image to the card's serial flash.
748 */
749int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
750{
751 u32 csum;
752 int ret, addr;
753 unsigned int i;
754 u8 first_page[SF_PAGE_SIZE];
755 const u32 *p = (const u32 *)fw_data;
756 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
757
758 if (!size) {
759 dev_err(adap->pdev_dev, "FW image has no data\n");
760 return -EINVAL;
761 }
762 if (size & 511) {
763 dev_err(adap->pdev_dev,
764 "FW image size not multiple of 512 bytes\n");
765 return -EINVAL;
766 }
767 if (ntohs(hdr->len512) * 512 != size) {
768 dev_err(adap->pdev_dev,
769 "FW image size differs from size in FW header\n");
770 return -EINVAL;
771 }
772 if (size > FW_MAX_SIZE) {
773 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
774 FW_MAX_SIZE);
775 return -EFBIG;
776 }
777
778 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
779 csum += ntohl(p[i]);
780
781 if (csum != 0xffffffff) {
782 dev_err(adap->pdev_dev,
783 "corrupted firmware image, checksum %#x\n", csum);
784 return -EINVAL;
785 }
786
787 i = DIV_ROUND_UP(size, SF_SEC_SIZE); /* # of sectors spanned */
788 ret = t4_flash_erase_sectors(adap, FW_START_SEC, FW_START_SEC + i - 1);
789 if (ret)
790 goto out;
791
792 /*
793 * We write the correct version at the end so the driver can see a bad
794 * version if the FW write fails. Start by writing a copy of the
795 * first page with a bad version.
796 */
797 memcpy(first_page, fw_data, SF_PAGE_SIZE);
798 ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff);
799 ret = t4_write_flash(adap, FW_IMG_START, SF_PAGE_SIZE, first_page);
800 if (ret)
801 goto out;
802
803 addr = FW_IMG_START;
804 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
805 addr += SF_PAGE_SIZE;
806 fw_data += SF_PAGE_SIZE;
807 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
808 if (ret)
809 goto out;
810 }
811
812 ret = t4_write_flash(adap,
813 FW_IMG_START + offsetof(struct fw_hdr, fw_ver),
814 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
815out:
816 if (ret)
817 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
818 ret);
819 return ret;
820}
821
822#define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
823 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_ANEG)
824
825/**
826 * t4_link_start - apply link configuration to MAC/PHY
827 * @phy: the PHY to setup
828 * @mac: the MAC to setup
829 * @lc: the requested link configuration
830 *
831 * Set up a port's MAC and PHY according to a desired link configuration.
832 * - If the PHY can auto-negotiate first decide what to advertise, then
833 * enable/disable auto-negotiation as desired, and reset.
834 * - If the PHY does not auto-negotiate just reset it.
835 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
836 * otherwise do it later based on the outcome of auto-negotiation.
837 */
838int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
839 struct link_config *lc)
840{
841 struct fw_port_cmd c;
842 unsigned int fc = 0, mdi = FW_PORT_MDI(FW_PORT_MDI_AUTO);
843
844 lc->link_ok = 0;
845 if (lc->requested_fc & PAUSE_RX)
846 fc |= FW_PORT_CAP_FC_RX;
847 if (lc->requested_fc & PAUSE_TX)
848 fc |= FW_PORT_CAP_FC_TX;
849
850 memset(&c, 0, sizeof(c));
851 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST |
852 FW_CMD_EXEC | FW_PORT_CMD_PORTID(port));
853 c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
854 FW_LEN16(c));
855
856 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
857 c.u.l1cfg.rcap = htonl((lc->supported & ADVERT_MASK) | fc);
858 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
859 } else if (lc->autoneg == AUTONEG_DISABLE) {
860 c.u.l1cfg.rcap = htonl(lc->requested_speed | fc | mdi);
861 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
862 } else
863 c.u.l1cfg.rcap = htonl(lc->advertising | fc | mdi);
864
865 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
866}
867
868/**
869 * t4_restart_aneg - restart autonegotiation
870 * @adap: the adapter
871 * @mbox: mbox to use for the FW command
872 * @port: the port id
873 *
874 * Restarts autonegotiation for the selected port.
875 */
876int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
877{
878 struct fw_port_cmd c;
879
880 memset(&c, 0, sizeof(c));
881 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST |
882 FW_CMD_EXEC | FW_PORT_CMD_PORTID(port));
883 c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
884 FW_LEN16(c));
885 c.u.l1cfg.rcap = htonl(FW_PORT_CAP_ANEG);
886 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
887}
888
889/**
890 * t4_set_vlan_accel - configure HW VLAN extraction
891 * @adap: the adapter
892 * @ports: bitmap of adapter ports to operate on
893 * @on: enable (1) or disable (0) HW VLAN extraction
894 *
895 * Enables or disables HW extraction of VLAN tags for the ports specified
896 * by @ports. @ports is a bitmap with the ith bit designating the port
897 * associated with the ith adapter channel.
898 */
899void t4_set_vlan_accel(struct adapter *adap, unsigned int ports, int on)
900{
901 ports <<= VLANEXTENABLE_SHIFT;
902 t4_set_reg_field(adap, TP_OUT_CONFIG, ports, on ? ports : 0);
903}
904
905struct intr_info {
906 unsigned int mask; /* bits to check in interrupt status */
907 const char *msg; /* message to print or NULL */
908 short stat_idx; /* stat counter to increment or -1 */
909 unsigned short fatal; /* whether the condition reported is fatal */
910};
911
912/**
913 * t4_handle_intr_status - table driven interrupt handler
914 * @adapter: the adapter that generated the interrupt
915 * @reg: the interrupt status register to process
916 * @acts: table of interrupt actions
917 *
918 * A table driven interrupt handler that applies a set of masks to an
919 * interrupt status word and performs the corresponding actions if the
920 * interrupts described by the mask have occured. The actions include
921 * optionally emitting a warning or alert message. The table is terminated
922 * by an entry specifying mask 0. Returns the number of fatal interrupt
923 * conditions.
924 */
925static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
926 const struct intr_info *acts)
927{
928 int fatal = 0;
929 unsigned int mask = 0;
930 unsigned int status = t4_read_reg(adapter, reg);
931
932 for ( ; acts->mask; ++acts) {
933 if (!(status & acts->mask))
934 continue;
935 if (acts->fatal) {
936 fatal++;
937 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
938 status & acts->mask);
939 } else if (acts->msg && printk_ratelimit())
940 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
941 status & acts->mask);
942 mask |= acts->mask;
943 }
944 status &= mask;
945 if (status) /* clear processed interrupts */
946 t4_write_reg(adapter, reg, status);
947 return fatal;
948}
949
950/*
951 * Interrupt handler for the PCIE module.
952 */
953static void pcie_intr_handler(struct adapter *adapter)
954{
955 static struct intr_info sysbus_intr_info[] = {
956 { RNPP, "RXNP array parity error", -1, 1 },
957 { RPCP, "RXPC array parity error", -1, 1 },
958 { RCIP, "RXCIF array parity error", -1, 1 },
959 { RCCP, "Rx completions control array parity error", -1, 1 },
960 { RFTP, "RXFT array parity error", -1, 1 },
961 { 0 }
962 };
963 static struct intr_info pcie_port_intr_info[] = {
964 { TPCP, "TXPC array parity error", -1, 1 },
965 { TNPP, "TXNP array parity error", -1, 1 },
966 { TFTP, "TXFT array parity error", -1, 1 },
967 { TCAP, "TXCA array parity error", -1, 1 },
968 { TCIP, "TXCIF array parity error", -1, 1 },
969 { RCAP, "RXCA array parity error", -1, 1 },
970 { OTDD, "outbound request TLP discarded", -1, 1 },
971 { RDPE, "Rx data parity error", -1, 1 },
972 { TDUE, "Tx uncorrectable data error", -1, 1 },
973 { 0 }
974 };
975 static struct intr_info pcie_intr_info[] = {
976 { MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
977 { MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
978 { MSIDATAPERR, "MSI data parity error", -1, 1 },
979 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
980 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
981 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
982 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
983 { PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
984 { PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
985 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
986 { CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
987 { CREQPERR, "PCI CMD channel request parity error", -1, 1 },
988 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
989 { DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
990 { DREQPERR, "PCI DMA channel request parity error", -1, 1 },
991 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
992 { HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
993 { HREQPERR, "PCI HMA channel request parity error", -1, 1 },
994 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
995 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
996 { FIDPERR, "PCI FID parity error", -1, 1 },
997 { INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
998 { MATAGPERR, "PCI MA tag parity error", -1, 1 },
999 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
1000 { RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
1001 { RXWRPERR, "PCI Rx write parity error", -1, 1 },
1002 { RPLPERR, "PCI replay buffer parity error", -1, 1 },
1003 { PCIESINT, "PCI core secondary fault", -1, 1 },
1004 { PCIEPINT, "PCI core primary fault", -1, 1 },
1005 { UNXSPLCPLERR, "PCI unexpected split completion error", -1, 0 },
1006 { 0 }
1007 };
1008
1009 int fat;
1010
1011 fat = t4_handle_intr_status(adapter,
1012 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
1013 sysbus_intr_info) +
1014 t4_handle_intr_status(adapter,
1015 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
1016 pcie_port_intr_info) +
1017 t4_handle_intr_status(adapter, PCIE_INT_CAUSE, pcie_intr_info);
1018 if (fat)
1019 t4_fatal_err(adapter);
1020}
1021
1022/*
1023 * TP interrupt handler.
1024 */
1025static void tp_intr_handler(struct adapter *adapter)
1026{
1027 static struct intr_info tp_intr_info[] = {
1028 { 0x3fffffff, "TP parity error", -1, 1 },
1029 { FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
1030 { 0 }
1031 };
1032
1033 if (t4_handle_intr_status(adapter, TP_INT_CAUSE, tp_intr_info))
1034 t4_fatal_err(adapter);
1035}
1036
1037/*
1038 * SGE interrupt handler.
1039 */
1040static void sge_intr_handler(struct adapter *adapter)
1041{
1042 u64 v;
1043
1044 static struct intr_info sge_intr_info[] = {
1045 { ERR_CPL_EXCEED_IQE_SIZE,
1046 "SGE received CPL exceeding IQE size", -1, 1 },
1047 { ERR_INVALID_CIDX_INC,
1048 "SGE GTS CIDX increment too large", -1, 0 },
1049 { ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 },
1050 { ERR_DROPPED_DB, "SGE doorbell dropped", -1, 0 },
1051 { ERR_DATA_CPL_ON_HIGH_QID1 | ERR_DATA_CPL_ON_HIGH_QID0,
1052 "SGE IQID > 1023 received CPL for FL", -1, 0 },
1053 { ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1,
1054 0 },
1055 { ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1,
1056 0 },
1057 { ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1,
1058 0 },
1059 { ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1,
1060 0 },
1061 { ERR_ING_CTXT_PRIO,
1062 "SGE too many priority ingress contexts", -1, 0 },
1063 { ERR_EGR_CTXT_PRIO,
1064 "SGE too many priority egress contexts", -1, 0 },
1065 { INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 },
1066 { EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 },
1067 { 0 }
1068 };
1069
1070 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1) |
1071 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2) << 32);
1072 if (v) {
1073 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
1074 (unsigned long long)v);
1075 t4_write_reg(adapter, SGE_INT_CAUSE1, v);
1076 t4_write_reg(adapter, SGE_INT_CAUSE2, v >> 32);
1077 }
1078
1079 if (t4_handle_intr_status(adapter, SGE_INT_CAUSE3, sge_intr_info) ||
1080 v != 0)
1081 t4_fatal_err(adapter);
1082}
1083
1084/*
1085 * CIM interrupt handler.
1086 */
1087static void cim_intr_handler(struct adapter *adapter)
1088{
1089 static struct intr_info cim_intr_info[] = {
1090 { PREFDROPINT, "CIM control register prefetch drop", -1, 1 },
1091 { OBQPARERR, "CIM OBQ parity error", -1, 1 },
1092 { IBQPARERR, "CIM IBQ parity error", -1, 1 },
1093 { MBUPPARERR, "CIM mailbox uP parity error", -1, 1 },
1094 { MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 },
1095 { TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 },
1096 { TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 },
1097 { 0 }
1098 };
1099 static struct intr_info cim_upintr_info[] = {
1100 { RSVDSPACEINT, "CIM reserved space access", -1, 1 },
1101 { ILLTRANSINT, "CIM illegal transaction", -1, 1 },
1102 { ILLWRINT, "CIM illegal write", -1, 1 },
1103 { ILLRDINT, "CIM illegal read", -1, 1 },
1104 { ILLRDBEINT, "CIM illegal read BE", -1, 1 },
1105 { ILLWRBEINT, "CIM illegal write BE", -1, 1 },
1106 { SGLRDBOOTINT, "CIM single read from boot space", -1, 1 },
1107 { SGLWRBOOTINT, "CIM single write to boot space", -1, 1 },
1108 { BLKWRBOOTINT, "CIM block write to boot space", -1, 1 },
1109 { SGLRDFLASHINT, "CIM single read from flash space", -1, 1 },
1110 { SGLWRFLASHINT, "CIM single write to flash space", -1, 1 },
1111 { BLKWRFLASHINT, "CIM block write to flash space", -1, 1 },
1112 { SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 },
1113 { SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 },
1114 { BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 },
1115 { BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 },
1116 { SGLRDCTLINT , "CIM single read from CTL space", -1, 1 },
1117 { SGLWRCTLINT , "CIM single write to CTL space", -1, 1 },
1118 { BLKRDCTLINT , "CIM block read from CTL space", -1, 1 },
1119 { BLKWRCTLINT , "CIM block write to CTL space", -1, 1 },
1120 { SGLRDPLINT , "CIM single read from PL space", -1, 1 },
1121 { SGLWRPLINT , "CIM single write to PL space", -1, 1 },
1122 { BLKRDPLINT , "CIM block read from PL space", -1, 1 },
1123 { BLKWRPLINT , "CIM block write to PL space", -1, 1 },
1124 { REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 },
1125 { RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 },
1126 { TIMEOUTINT , "CIM PIF timeout", -1, 1 },
1127 { TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 },
1128 { 0 }
1129 };
1130
1131 int fat;
1132
1133 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE,
1134 cim_intr_info) +
1135 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE,
1136 cim_upintr_info);
1137 if (fat)
1138 t4_fatal_err(adapter);
1139}
1140
1141/*
1142 * ULP RX interrupt handler.
1143 */
1144static void ulprx_intr_handler(struct adapter *adapter)
1145{
1146 static struct intr_info ulprx_intr_info[] = {
1147 { 0x7fffff, "ULPRX parity error", -1, 1 },
1148 { 0 }
1149 };
1150
1151 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE, ulprx_intr_info))
1152 t4_fatal_err(adapter);
1153}
1154
1155/*
1156 * ULP TX interrupt handler.
1157 */
1158static void ulptx_intr_handler(struct adapter *adapter)
1159{
1160 static struct intr_info ulptx_intr_info[] = {
1161 { PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1,
1162 0 },
1163 { PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1,
1164 0 },
1165 { PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1,
1166 0 },
1167 { PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1,
1168 0 },
1169 { 0xfffffff, "ULPTX parity error", -1, 1 },
1170 { 0 }
1171 };
1172
1173 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE, ulptx_intr_info))
1174 t4_fatal_err(adapter);
1175}
1176
1177/*
1178 * PM TX interrupt handler.
1179 */
1180static void pmtx_intr_handler(struct adapter *adapter)
1181{
1182 static struct intr_info pmtx_intr_info[] = {
1183 { PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 },
1184 { PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 },
1185 { PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 },
1186 { ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 },
1187 { PMTX_FRAMING_ERROR, "PMTX framing error", -1, 1 },
1188 { OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 },
1189 { DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 1 },
1190 { ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 },
1191 { C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1},
1192 { 0 }
1193 };
1194
1195 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE, pmtx_intr_info))
1196 t4_fatal_err(adapter);
1197}
1198
1199/*
1200 * PM RX interrupt handler.
1201 */
1202static void pmrx_intr_handler(struct adapter *adapter)
1203{
1204 static struct intr_info pmrx_intr_info[] = {
1205 { ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 },
1206 { PMRX_FRAMING_ERROR, "PMRX framing error", -1, 1 },
1207 { OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 },
1208 { DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 1 },
1209 { IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 },
1210 { E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1},
1211 { 0 }
1212 };
1213
1214 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE, pmrx_intr_info))
1215 t4_fatal_err(adapter);
1216}
1217
1218/*
1219 * CPL switch interrupt handler.
1220 */
1221static void cplsw_intr_handler(struct adapter *adapter)
1222{
1223 static struct intr_info cplsw_intr_info[] = {
1224 { CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 },
1225 { CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 },
1226 { TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 },
1227 { SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 },
1228 { CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 },
1229 { ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 },
1230 { 0 }
1231 };
1232
1233 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE, cplsw_intr_info))
1234 t4_fatal_err(adapter);
1235}
1236
1237/*
1238 * LE interrupt handler.
1239 */
1240static void le_intr_handler(struct adapter *adap)
1241{
1242 static struct intr_info le_intr_info[] = {
1243 { LIPMISS, "LE LIP miss", -1, 0 },
1244 { LIP0, "LE 0 LIP error", -1, 0 },
1245 { PARITYERR, "LE parity error", -1, 1 },
1246 { UNKNOWNCMD, "LE unknown command", -1, 1 },
1247 { REQQPARERR, "LE request queue parity error", -1, 1 },
1248 { 0 }
1249 };
1250
1251 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE, le_intr_info))
1252 t4_fatal_err(adap);
1253}
1254
1255/*
1256 * MPS interrupt handler.
1257 */
1258static void mps_intr_handler(struct adapter *adapter)
1259{
1260 static struct intr_info mps_rx_intr_info[] = {
1261 { 0xffffff, "MPS Rx parity error", -1, 1 },
1262 { 0 }
1263 };
1264 static struct intr_info mps_tx_intr_info[] = {
1265 { TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 },
1266 { NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
1267 { TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 },
1268 { TXDESCFIFO, "MPS Tx desc FIFO parity error", -1, 1 },
1269 { BUBBLE, "MPS Tx underflow", -1, 1 },
1270 { SECNTERR, "MPS Tx SOP/EOP error", -1, 1 },
1271 { FRMERR, "MPS Tx framing error", -1, 1 },
1272 { 0 }
1273 };
1274 static struct intr_info mps_trc_intr_info[] = {
1275 { FILTMEM, "MPS TRC filter parity error", -1, 1 },
1276 { PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 },
1277 { MISCPERR, "MPS TRC misc parity error", -1, 1 },
1278 { 0 }
1279 };
1280 static struct intr_info mps_stat_sram_intr_info[] = {
1281 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
1282 { 0 }
1283 };
1284 static struct intr_info mps_stat_tx_intr_info[] = {
1285 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
1286 { 0 }
1287 };
1288 static struct intr_info mps_stat_rx_intr_info[] = {
1289 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
1290 { 0 }
1291 };
1292 static struct intr_info mps_cls_intr_info[] = {
1293 { MATCHSRAM, "MPS match SRAM parity error", -1, 1 },
1294 { MATCHTCAM, "MPS match TCAM parity error", -1, 1 },
1295 { HASHSRAM, "MPS hash SRAM parity error", -1, 1 },
1296 { 0 }
1297 };
1298
1299 int fat;
1300
1301 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE,
1302 mps_rx_intr_info) +
1303 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE,
1304 mps_tx_intr_info) +
1305 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE,
1306 mps_trc_intr_info) +
1307 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM,
1308 mps_stat_sram_intr_info) +
1309 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
1310 mps_stat_tx_intr_info) +
1311 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
1312 mps_stat_rx_intr_info) +
1313 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE,
1314 mps_cls_intr_info);
1315
1316 t4_write_reg(adapter, MPS_INT_CAUSE, CLSINT | TRCINT |
1317 RXINT | TXINT | STATINT);
1318 t4_read_reg(adapter, MPS_INT_CAUSE); /* flush */
1319 if (fat)
1320 t4_fatal_err(adapter);
1321}
1322
1323#define MEM_INT_MASK (PERR_INT_CAUSE | ECC_CE_INT_CAUSE | ECC_UE_INT_CAUSE)
1324
1325/*
1326 * EDC/MC interrupt handler.
1327 */
1328static void mem_intr_handler(struct adapter *adapter, int idx)
1329{
1330 static const char name[3][5] = { "EDC0", "EDC1", "MC" };
1331
1332 unsigned int addr, cnt_addr, v;
1333
1334 if (idx <= MEM_EDC1) {
1335 addr = EDC_REG(EDC_INT_CAUSE, idx);
1336 cnt_addr = EDC_REG(EDC_ECC_STATUS, idx);
1337 } else {
1338 addr = MC_INT_CAUSE;
1339 cnt_addr = MC_ECC_STATUS;
1340 }
1341
1342 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
1343 if (v & PERR_INT_CAUSE)
1344 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
1345 name[idx]);
1346 if (v & ECC_CE_INT_CAUSE) {
1347 u32 cnt = ECC_CECNT_GET(t4_read_reg(adapter, cnt_addr));
1348
1349 t4_write_reg(adapter, cnt_addr, ECC_CECNT_MASK);
1350 if (printk_ratelimit())
1351 dev_warn(adapter->pdev_dev,
1352 "%u %s correctable ECC data error%s\n",
1353 cnt, name[idx], cnt > 1 ? "s" : "");
1354 }
1355 if (v & ECC_UE_INT_CAUSE)
1356 dev_alert(adapter->pdev_dev,
1357 "%s uncorrectable ECC data error\n", name[idx]);
1358
1359 t4_write_reg(adapter, addr, v);
1360 if (v & (PERR_INT_CAUSE | ECC_UE_INT_CAUSE))
1361 t4_fatal_err(adapter);
1362}
1363
1364/*
1365 * MA interrupt handler.
1366 */
1367static void ma_intr_handler(struct adapter *adap)
1368{
1369 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE);
1370
1371 if (status & MEM_PERR_INT_CAUSE)
1372 dev_alert(adap->pdev_dev,
1373 "MA parity error, parity status %#x\n",
1374 t4_read_reg(adap, MA_PARITY_ERROR_STATUS));
1375 if (status & MEM_WRAP_INT_CAUSE) {
1376 v = t4_read_reg(adap, MA_INT_WRAP_STATUS);
1377 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
1378 "client %u to address %#x\n",
1379 MEM_WRAP_CLIENT_NUM_GET(v),
1380 MEM_WRAP_ADDRESS_GET(v) << 4);
1381 }
1382 t4_write_reg(adap, MA_INT_CAUSE, status);
1383 t4_fatal_err(adap);
1384}
1385
1386/*
1387 * SMB interrupt handler.
1388 */
1389static void smb_intr_handler(struct adapter *adap)
1390{
1391 static struct intr_info smb_intr_info[] = {
1392 { MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 },
1393 { MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 },
1394 { SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 },
1395 { 0 }
1396 };
1397
1398 if (t4_handle_intr_status(adap, SMB_INT_CAUSE, smb_intr_info))
1399 t4_fatal_err(adap);
1400}
1401
1402/*
1403 * NC-SI interrupt handler.
1404 */
1405static void ncsi_intr_handler(struct adapter *adap)
1406{
1407 static struct intr_info ncsi_intr_info[] = {
1408 { CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 },
1409 { MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 },
1410 { TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 },
1411 { RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 },
1412 { 0 }
1413 };
1414
1415 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE, ncsi_intr_info))
1416 t4_fatal_err(adap);
1417}
1418
1419/*
1420 * XGMAC interrupt handler.
1421 */
1422static void xgmac_intr_handler(struct adapter *adap, int port)
1423{
1424 u32 v = t4_read_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE));
1425
1426 v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR;
1427 if (!v)
1428 return;
1429
1430 if (v & TXFIFO_PRTY_ERR)
1431 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
1432 port);
1433 if (v & RXFIFO_PRTY_ERR)
1434 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
1435 port);
1436 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE), v);
1437 t4_fatal_err(adap);
1438}
1439
1440/*
1441 * PL interrupt handler.
1442 */
1443static void pl_intr_handler(struct adapter *adap)
1444{
1445 static struct intr_info pl_intr_info[] = {
1446 { FATALPERR, "T4 fatal parity error", -1, 1 },
1447 { PERRVFID, "PL VFID_MAP parity error", -1, 1 },
1448 { 0 }
1449 };
1450
1451 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE, pl_intr_info))
1452 t4_fatal_err(adap);
1453}
1454
1455#define PF_INTR_MASK (PFSW | PFCIM)
1456#define GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \
1457 EDC1 | LE | TP | MA | PM_TX | PM_RX | ULP_RX | \
1458 CPL_SWITCH | SGE | ULP_TX)
1459
1460/**
1461 * t4_slow_intr_handler - control path interrupt handler
1462 * @adapter: the adapter
1463 *
1464 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
1465 * The designation 'slow' is because it involves register reads, while
1466 * data interrupts typically don't involve any MMIOs.
1467 */
1468int t4_slow_intr_handler(struct adapter *adapter)
1469{
1470 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE);
1471
1472 if (!(cause & GLBL_INTR_MASK))
1473 return 0;
1474 if (cause & CIM)
1475 cim_intr_handler(adapter);
1476 if (cause & MPS)
1477 mps_intr_handler(adapter);
1478 if (cause & NCSI)
1479 ncsi_intr_handler(adapter);
1480 if (cause & PL)
1481 pl_intr_handler(adapter);
1482 if (cause & SMB)
1483 smb_intr_handler(adapter);
1484 if (cause & XGMAC0)
1485 xgmac_intr_handler(adapter, 0);
1486 if (cause & XGMAC1)
1487 xgmac_intr_handler(adapter, 1);
1488 if (cause & XGMAC_KR0)
1489 xgmac_intr_handler(adapter, 2);
1490 if (cause & XGMAC_KR1)
1491 xgmac_intr_handler(adapter, 3);
1492 if (cause & PCIE)
1493 pcie_intr_handler(adapter);
1494 if (cause & MC)
1495 mem_intr_handler(adapter, MEM_MC);
1496 if (cause & EDC0)
1497 mem_intr_handler(adapter, MEM_EDC0);
1498 if (cause & EDC1)
1499 mem_intr_handler(adapter, MEM_EDC1);
1500 if (cause & LE)
1501 le_intr_handler(adapter);
1502 if (cause & TP)
1503 tp_intr_handler(adapter);
1504 if (cause & MA)
1505 ma_intr_handler(adapter);
1506 if (cause & PM_TX)
1507 pmtx_intr_handler(adapter);
1508 if (cause & PM_RX)
1509 pmrx_intr_handler(adapter);
1510 if (cause & ULP_RX)
1511 ulprx_intr_handler(adapter);
1512 if (cause & CPL_SWITCH)
1513 cplsw_intr_handler(adapter);
1514 if (cause & SGE)
1515 sge_intr_handler(adapter);
1516 if (cause & ULP_TX)
1517 ulptx_intr_handler(adapter);
1518
1519 /* Clear the interrupts just processed for which we are the master. */
1520 t4_write_reg(adapter, PL_INT_CAUSE, cause & GLBL_INTR_MASK);
1521 (void) t4_read_reg(adapter, PL_INT_CAUSE); /* flush */
1522 return 1;
1523}
1524
1525/**
1526 * t4_intr_enable - enable interrupts
1527 * @adapter: the adapter whose interrupts should be enabled
1528 *
1529 * Enable PF-specific interrupts for the calling function and the top-level
1530 * interrupt concentrator for global interrupts. Interrupts are already
1531 * enabled at each module, here we just enable the roots of the interrupt
1532 * hierarchies.
1533 *
1534 * Note: this function should be called only when the driver manages
1535 * non PF-specific interrupts from the various HW modules. Only one PCI
1536 * function at a time should be doing this.
1537 */
1538void t4_intr_enable(struct adapter *adapter)
1539{
1540 u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));
1541
1542 t4_write_reg(adapter, SGE_INT_ENABLE3, ERR_CPL_EXCEED_IQE_SIZE |
1543 ERR_INVALID_CIDX_INC | ERR_CPL_OPCODE_0 |
1544 ERR_DROPPED_DB | ERR_DATA_CPL_ON_HIGH_QID1 |
1545 ERR_DATA_CPL_ON_HIGH_QID0 | ERR_BAD_DB_PIDX3 |
1546 ERR_BAD_DB_PIDX2 | ERR_BAD_DB_PIDX1 |
1547 ERR_BAD_DB_PIDX0 | ERR_ING_CTXT_PRIO |
1548 ERR_EGR_CTXT_PRIO | INGRESS_SIZE_ERR |
1549 EGRESS_SIZE_ERR);
1550 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), PF_INTR_MASK);
1551 t4_set_reg_field(adapter, PL_INT_MAP0, 0, 1 << pf);
1552}
1553
1554/**
1555 * t4_intr_disable - disable interrupts
1556 * @adapter: the adapter whose interrupts should be disabled
1557 *
1558 * Disable interrupts. We only disable the top-level interrupt
1559 * concentrators. The caller must be a PCI function managing global
1560 * interrupts.
1561 */
1562void t4_intr_disable(struct adapter *adapter)
1563{
1564 u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));
1565
1566 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), 0);
1567 t4_set_reg_field(adapter, PL_INT_MAP0, 1 << pf, 0);
1568}
1569
1570/**
1571 * t4_intr_clear - clear all interrupts
1572 * @adapter: the adapter whose interrupts should be cleared
1573 *
1574 * Clears all interrupts. The caller must be a PCI function managing
1575 * global interrupts.
1576 */
1577void t4_intr_clear(struct adapter *adapter)
1578{
1579 static const unsigned int cause_reg[] = {
1580 SGE_INT_CAUSE1, SGE_INT_CAUSE2, SGE_INT_CAUSE3,
1581 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
1582 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
1583 PCIE_NONFAT_ERR, PCIE_INT_CAUSE,
1584 MC_INT_CAUSE,
1585 MA_INT_WRAP_STATUS, MA_PARITY_ERROR_STATUS, MA_INT_CAUSE,
1586 EDC_INT_CAUSE, EDC_REG(EDC_INT_CAUSE, 1),
1587 CIM_HOST_INT_CAUSE, CIM_HOST_UPACC_INT_CAUSE,
1588 MYPF_REG(CIM_PF_HOST_INT_CAUSE),
1589 TP_INT_CAUSE,
1590 ULP_RX_INT_CAUSE, ULP_TX_INT_CAUSE,
1591 PM_RX_INT_CAUSE, PM_TX_INT_CAUSE,
1592 MPS_RX_PERR_INT_CAUSE,
1593 CPL_INTR_CAUSE,
1594 MYPF_REG(PL_PF_INT_CAUSE),
1595 PL_PL_INT_CAUSE,
1596 LE_DB_INT_CAUSE,
1597 };
1598
1599 unsigned int i;
1600
1601 for (i = 0; i < ARRAY_SIZE(cause_reg); ++i)
1602 t4_write_reg(adapter, cause_reg[i], 0xffffffff);
1603
1604 t4_write_reg(adapter, PL_INT_CAUSE, GLBL_INTR_MASK);
1605 (void) t4_read_reg(adapter, PL_INT_CAUSE); /* flush */
1606}
1607
1608/**
1609 * hash_mac_addr - return the hash value of a MAC address
1610 * @addr: the 48-bit Ethernet MAC address
1611 *
1612 * Hashes a MAC address according to the hash function used by HW inexact
1613 * (hash) address matching.
1614 */
1615static int hash_mac_addr(const u8 *addr)
1616{
1617 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1618 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1619 a ^= b;
1620 a ^= (a >> 12);
1621 a ^= (a >> 6);
1622 return a & 0x3f;
1623}
1624
1625/**
1626 * t4_config_rss_range - configure a portion of the RSS mapping table
1627 * @adapter: the adapter
1628 * @mbox: mbox to use for the FW command
1629 * @viid: virtual interface whose RSS subtable is to be written
1630 * @start: start entry in the table to write
1631 * @n: how many table entries to write
1632 * @rspq: values for the response queue lookup table
1633 * @nrspq: number of values in @rspq
1634 *
1635 * Programs the selected part of the VI's RSS mapping table with the
1636 * provided values. If @nrspq < @n the supplied values are used repeatedly
1637 * until the full table range is populated.
1638 *
1639 * The caller must ensure the values in @rspq are in the range allowed for
1640 * @viid.
1641 */
1642int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1643 int start, int n, const u16 *rspq, unsigned int nrspq)
1644{
1645 int ret;
1646 const u16 *rsp = rspq;
1647 const u16 *rsp_end = rspq + nrspq;
1648 struct fw_rss_ind_tbl_cmd cmd;
1649
1650 memset(&cmd, 0, sizeof(cmd));
1651 cmd.op_to_viid = htonl(FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
1652 FW_CMD_REQUEST | FW_CMD_WRITE |
1653 FW_RSS_IND_TBL_CMD_VIID(viid));
1654 cmd.retval_len16 = htonl(FW_LEN16(cmd));
1655
1656 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
1657 while (n > 0) {
1658 int nq = min(n, 32);
1659 __be32 *qp = &cmd.iq0_to_iq2;
1660
1661 cmd.niqid = htons(nq);
1662 cmd.startidx = htons(start);
1663
1664 start += nq;
1665 n -= nq;
1666
1667 while (nq > 0) {
1668 unsigned int v;
1669
1670 v = FW_RSS_IND_TBL_CMD_IQ0(*rsp);
1671 if (++rsp >= rsp_end)
1672 rsp = rspq;
1673 v |= FW_RSS_IND_TBL_CMD_IQ1(*rsp);
1674 if (++rsp >= rsp_end)
1675 rsp = rspq;
1676 v |= FW_RSS_IND_TBL_CMD_IQ2(*rsp);
1677 if (++rsp >= rsp_end)
1678 rsp = rspq;
1679
1680 *qp++ = htonl(v);
1681 nq -= 3;
1682 }
1683
1684 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
1685 if (ret)
1686 return ret;
1687 }
1688 return 0;
1689}
1690
1691/**
1692 * t4_config_glbl_rss - configure the global RSS mode
1693 * @adapter: the adapter
1694 * @mbox: mbox to use for the FW command
1695 * @mode: global RSS mode
1696 * @flags: mode-specific flags
1697 *
1698 * Sets the global RSS mode.
1699 */
1700int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1701 unsigned int flags)
1702{
1703 struct fw_rss_glb_config_cmd c;
1704
1705 memset(&c, 0, sizeof(c));
1706 c.op_to_write = htonl(FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
1707 FW_CMD_REQUEST | FW_CMD_WRITE);
1708 c.retval_len16 = htonl(FW_LEN16(c));
1709 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
1710 c.u.manual.mode_pkd = htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode));
1711 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
1712 c.u.basicvirtual.mode_pkd =
1713 htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode));
1714 c.u.basicvirtual.synmapen_to_hashtoeplitz = htonl(flags);
1715 } else
1716 return -EINVAL;
1717 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
1718}
1719
1720/* Read an RSS table row */
1721static int rd_rss_row(struct adapter *adap, int row, u32 *val)
1722{
1723 t4_write_reg(adap, TP_RSS_LKP_TABLE, 0xfff00000 | row);
1724 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE, LKPTBLROWVLD, 1,
1725 5, 0, val);
1726}
1727
1728/**
1729 * t4_read_rss - read the contents of the RSS mapping table
1730 * @adapter: the adapter
1731 * @map: holds the contents of the RSS mapping table
1732 *
1733 * Reads the contents of the RSS hash->queue mapping table.
1734 */
1735int t4_read_rss(struct adapter *adapter, u16 *map)
1736{
1737 u32 val;
1738 int i, ret;
1739
1740 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
1741 ret = rd_rss_row(adapter, i, &val);
1742 if (ret)
1743 return ret;
1744 *map++ = LKPTBLQUEUE0_GET(val);
1745 *map++ = LKPTBLQUEUE1_GET(val);
1746 }
1747 return 0;
1748}
1749
1750/**
1751 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
1752 * @adap: the adapter
1753 * @v4: holds the TCP/IP counter values
1754 * @v6: holds the TCP/IPv6 counter values
1755 *
1756 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
1757 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
1758 */
1759void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1760 struct tp_tcp_stats *v6)
1761{
1762 u32 val[TP_MIB_TCP_RXT_SEG_LO - TP_MIB_TCP_OUT_RST + 1];
1763
1764#define STAT_IDX(x) ((TP_MIB_TCP_##x) - TP_MIB_TCP_OUT_RST)
1765#define STAT(x) val[STAT_IDX(x)]
1766#define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
1767
1768 if (v4) {
1769 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val,
1770 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST);
1771 v4->tcpOutRsts = STAT(OUT_RST);
1772 v4->tcpInSegs = STAT64(IN_SEG);
1773 v4->tcpOutSegs = STAT64(OUT_SEG);
1774 v4->tcpRetransSegs = STAT64(RXT_SEG);
1775 }
1776 if (v6) {
1777 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val,
1778 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST);
1779 v6->tcpOutRsts = STAT(OUT_RST);
1780 v6->tcpInSegs = STAT64(IN_SEG);
1781 v6->tcpOutSegs = STAT64(OUT_SEG);
1782 v6->tcpRetransSegs = STAT64(RXT_SEG);
1783 }
1784#undef STAT64
1785#undef STAT
1786#undef STAT_IDX
1787}
1788
1789/**
1790 * t4_tp_get_err_stats - read TP's error MIB counters
1791 * @adap: the adapter
1792 * @st: holds the counter values
1793 *
1794 * Returns the values of TP's error counters.
1795 */
1796void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
1797{
1798 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, st->macInErrs,
1799 12, TP_MIB_MAC_IN_ERR_0);
1800 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, st->tnlCongDrops,
1801 8, TP_MIB_TNL_CNG_DROP_0);
1802 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, st->tnlTxDrops,
1803 4, TP_MIB_TNL_DROP_0);
1804 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, st->ofldVlanDrops,
1805 4, TP_MIB_OFD_VLN_DROP_0);
1806 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, st->tcp6InErrs,
1807 4, TP_MIB_TCP_V6IN_ERR_0);
1808 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, &st->ofldNoNeigh,
1809 2, TP_MIB_OFD_ARP_DROP);
1810}
1811
1812/**
1813 * t4_read_mtu_tbl - returns the values in the HW path MTU table
1814 * @adap: the adapter
1815 * @mtus: where to store the MTU values
1816 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
1817 *
1818 * Reads the HW path MTU table.
1819 */
1820void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
1821{
1822 u32 v;
1823 int i;
1824
1825 for (i = 0; i < NMTUS; ++i) {
1826 t4_write_reg(adap, TP_MTU_TABLE,
1827 MTUINDEX(0xff) | MTUVALUE(i));
1828 v = t4_read_reg(adap, TP_MTU_TABLE);
1829 mtus[i] = MTUVALUE_GET(v);
1830 if (mtu_log)
1831 mtu_log[i] = MTUWIDTH_GET(v);
1832 }
1833}
1834
1835/**
1836 * init_cong_ctrl - initialize congestion control parameters
1837 * @a: the alpha values for congestion control
1838 * @b: the beta values for congestion control
1839 *
1840 * Initialize the congestion control parameters.
1841 */
1842static void __devinit init_cong_ctrl(unsigned short *a, unsigned short *b)
1843{
1844 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
1845 a[9] = 2;
1846 a[10] = 3;
1847 a[11] = 4;
1848 a[12] = 5;
1849 a[13] = 6;
1850 a[14] = 7;
1851 a[15] = 8;
1852 a[16] = 9;
1853 a[17] = 10;
1854 a[18] = 14;
1855 a[19] = 17;
1856 a[20] = 21;
1857 a[21] = 25;
1858 a[22] = 30;
1859 a[23] = 35;
1860 a[24] = 45;
1861 a[25] = 60;
1862 a[26] = 80;
1863 a[27] = 100;
1864 a[28] = 200;
1865 a[29] = 300;
1866 a[30] = 400;
1867 a[31] = 500;
1868
1869 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
1870 b[9] = b[10] = 1;
1871 b[11] = b[12] = 2;
1872 b[13] = b[14] = b[15] = b[16] = 3;
1873 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
1874 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
1875 b[28] = b[29] = 6;
1876 b[30] = b[31] = 7;
1877}
1878
1879/* The minimum additive increment value for the congestion control table */
1880#define CC_MIN_INCR 2U
1881
1882/**
1883 * t4_load_mtus - write the MTU and congestion control HW tables
1884 * @adap: the adapter
1885 * @mtus: the values for the MTU table
1886 * @alpha: the values for the congestion control alpha parameter
1887 * @beta: the values for the congestion control beta parameter
1888 *
1889 * Write the HW MTU table with the supplied MTUs and the high-speed
1890 * congestion control table with the supplied alpha, beta, and MTUs.
1891 * We write the two tables together because the additive increments
1892 * depend on the MTUs.
1893 */
1894void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1895 const unsigned short *alpha, const unsigned short *beta)
1896{
1897 static const unsigned int avg_pkts[NCCTRL_WIN] = {
1898 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
1899 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
1900 28672, 40960, 57344, 81920, 114688, 163840, 229376
1901 };
1902
1903 unsigned int i, w;
1904
1905 for (i = 0; i < NMTUS; ++i) {
1906 unsigned int mtu = mtus[i];
1907 unsigned int log2 = fls(mtu);
1908
1909 if (!(mtu & ((1 << log2) >> 2))) /* round */
1910 log2--;
1911 t4_write_reg(adap, TP_MTU_TABLE, MTUINDEX(i) |
1912 MTUWIDTH(log2) | MTUVALUE(mtu));
1913
1914 for (w = 0; w < NCCTRL_WIN; ++w) {
1915 unsigned int inc;
1916
1917 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
1918 CC_MIN_INCR);
1919
1920 t4_write_reg(adap, TP_CCTRL_TABLE, (i << 21) |
1921 (w << 16) | (beta[w] << 13) | inc);
1922 }
1923 }
1924}
1925
1926/**
1927 * t4_set_trace_filter - configure one of the tracing filters
1928 * @adap: the adapter
1929 * @tp: the desired trace filter parameters
1930 * @idx: which filter to configure
1931 * @enable: whether to enable or disable the filter
1932 *
1933 * Configures one of the tracing filters available in HW. If @enable is
1934 * %0 @tp is not examined and may be %NULL.
1935 */
1936int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
1937 int idx, int enable)
1938{
1939 int i, ofst = idx * 4;
1940 u32 data_reg, mask_reg, cfg;
1941 u32 multitrc = TRCMULTIFILTER;
1942
1943 if (!enable) {
1944 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A + ofst, 0);
1945 goto out;
1946 }
1947
1948 if (tp->port > 11 || tp->invert > 1 || tp->skip_len > 0x1f ||
1949 tp->skip_ofst > 0x1f || tp->min_len > 0x1ff ||
1950 tp->snap_len > 9600 || (idx && tp->snap_len > 256))
1951 return -EINVAL;
1952
1953 if (tp->snap_len > 256) { /* must be tracer 0 */
1954 if ((t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A + 4) |
1955 t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A + 8) |
1956 t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A + 12)) & TFEN)
1957 return -EINVAL; /* other tracers are enabled */
1958 multitrc = 0;
1959 } else if (idx) {
1960 i = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B);
1961 if (TFCAPTUREMAX_GET(i) > 256 &&
1962 (t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A) & TFEN))
1963 return -EINVAL;
1964 }
1965
1966 /* stop the tracer we'll be changing */
1967 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A + ofst, 0);
1968
1969 /* disable tracing globally if running in the wrong single/multi mode */
1970 cfg = t4_read_reg(adap, MPS_TRC_CFG);
1971 if ((cfg & TRCEN) && multitrc != (cfg & TRCMULTIFILTER)) {
1972 t4_write_reg(adap, MPS_TRC_CFG, cfg ^ TRCEN);
1973 t4_read_reg(adap, MPS_TRC_CFG); /* flush */
1974 msleep(1);
1975 if (!(t4_read_reg(adap, MPS_TRC_CFG) & TRCFIFOEMPTY))
1976 return -ETIMEDOUT;
1977 }
1978 /*
1979 * At this point either the tracing is enabled and in the right mode or
1980 * disabled.
1981 */
1982
1983 idx *= (MPS_TRC_FILTER1_MATCH - MPS_TRC_FILTER0_MATCH);
1984 data_reg = MPS_TRC_FILTER0_MATCH + idx;
1985 mask_reg = MPS_TRC_FILTER0_DONT_CARE + idx;
1986
1987 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
1988 t4_write_reg(adap, data_reg, tp->data[i]);
1989 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
1990 }
1991 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B + ofst,
1992 TFCAPTUREMAX(tp->snap_len) |
1993 TFMINPKTSIZE(tp->min_len));
1994 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A + ofst,
1995 TFOFFSET(tp->skip_ofst) | TFLENGTH(tp->skip_len) |
1996 TFPORT(tp->port) | TFEN |
1997 (tp->invert ? TFINVERTMATCH : 0));
1998
1999 cfg &= ~TRCMULTIFILTER;
2000 t4_write_reg(adap, MPS_TRC_CFG, cfg | TRCEN | multitrc);
2001out: t4_read_reg(adap, MPS_TRC_CFG); /* flush */
2002 return 0;
2003}
2004
2005/**
2006 * t4_get_trace_filter - query one of the tracing filters
2007 * @adap: the adapter
2008 * @tp: the current trace filter parameters
2009 * @idx: which trace filter to query
2010 * @enabled: non-zero if the filter is enabled
2011 *
2012 * Returns the current settings of one of the HW tracing filters.
2013 */
2014void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
2015 int *enabled)
2016{
2017 u32 ctla, ctlb;
2018 int i, ofst = idx * 4;
2019 u32 data_reg, mask_reg;
2020
2021 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A + ofst);
2022 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B + ofst);
2023
2024 *enabled = !!(ctla & TFEN);
2025 tp->snap_len = TFCAPTUREMAX_GET(ctlb);
2026 tp->min_len = TFMINPKTSIZE_GET(ctlb);
2027 tp->skip_ofst = TFOFFSET_GET(ctla);
2028 tp->skip_len = TFLENGTH_GET(ctla);
2029 tp->invert = !!(ctla & TFINVERTMATCH);
2030 tp->port = TFPORT_GET(ctla);
2031
2032 ofst = (MPS_TRC_FILTER1_MATCH - MPS_TRC_FILTER0_MATCH) * idx;
2033 data_reg = MPS_TRC_FILTER0_MATCH + ofst;
2034 mask_reg = MPS_TRC_FILTER0_DONT_CARE + ofst;
2035
2036 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
2037 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
2038 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
2039 }
2040}
2041
2042/**
2043 * get_mps_bg_map - return the buffer groups associated with a port
2044 * @adap: the adapter
2045 * @idx: the port index
2046 *
2047 * Returns a bitmap indicating which MPS buffer groups are associated
2048 * with the given port. Bit i is set if buffer group i is used by the
2049 * port.
2050 */
2051static unsigned int get_mps_bg_map(struct adapter *adap, int idx)
2052{
2053 u32 n = NUMPORTS_GET(t4_read_reg(adap, MPS_CMN_CTL));
2054
2055 if (n == 0)
2056 return idx == 0 ? 0xf : 0;
2057 if (n == 1)
2058 return idx < 2 ? (3 << (2 * idx)) : 0;
2059 return 1 << idx;
2060}
2061
2062/**
2063 * t4_get_port_stats - collect port statistics
2064 * @adap: the adapter
2065 * @idx: the port index
2066 * @p: the stats structure to fill
2067 *
2068 * Collect statistics related to the given port from HW.
2069 */
2070void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2071{
2072 u32 bgmap = get_mps_bg_map(adap, idx);
2073
2074#define GET_STAT(name) \
2075 t4_read_reg64(adap, PORT_REG(idx, MPS_PORT_STAT_##name##_L))
2076#define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
2077
2078 p->tx_octets = GET_STAT(TX_PORT_BYTES);
2079 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
2080 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
2081 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
2082 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
2083 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
2084 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
2085 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
2086 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
2087 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
2088 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
2089 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2090 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
2091 p->tx_drop = GET_STAT(TX_PORT_DROP);
2092 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
2093 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
2094 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
2095 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
2096 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
2097 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
2098 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
2099 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
2100 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
2101
2102 p->rx_octets = GET_STAT(RX_PORT_BYTES);
2103 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
2104 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
2105 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
2106 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
2107 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
2108 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2109 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
2110 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
2111 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
2112 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
2113 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
2114 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
2115 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
2116 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
2117 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
2118 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
2119 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
2120 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
2121 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
2122 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
2123 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
2124 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
2125 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
2126 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
2127 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
2128 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
2129
2130 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
2131 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
2132 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
2133 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
2134 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
2135 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
2136 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
2137 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
2138
2139#undef GET_STAT
2140#undef GET_STAT_COM
2141}
2142
2143/**
2144 * t4_get_lb_stats - collect loopback port statistics
2145 * @adap: the adapter
2146 * @idx: the loopback port index
2147 * @p: the stats structure to fill
2148 *
2149 * Return HW statistics for the given loopback port.
2150 */
2151void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
2152{
2153 u32 bgmap = get_mps_bg_map(adap, idx);
2154
2155#define GET_STAT(name) \
2156 t4_read_reg64(adap, PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L))
2157#define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
2158
2159 p->octets = GET_STAT(BYTES);
2160 p->frames = GET_STAT(FRAMES);
2161 p->bcast_frames = GET_STAT(BCAST);
2162 p->mcast_frames = GET_STAT(MCAST);
2163 p->ucast_frames = GET_STAT(UCAST);
2164 p->error_frames = GET_STAT(ERROR);
2165
2166 p->frames_64 = GET_STAT(64B);
2167 p->frames_65_127 = GET_STAT(65B_127B);
2168 p->frames_128_255 = GET_STAT(128B_255B);
2169 p->frames_256_511 = GET_STAT(256B_511B);
2170 p->frames_512_1023 = GET_STAT(512B_1023B);
2171 p->frames_1024_1518 = GET_STAT(1024B_1518B);
2172 p->frames_1519_max = GET_STAT(1519B_MAX);
2173 p->drop = t4_read_reg(adap, PORT_REG(idx,
2174 MPS_PORT_STAT_LB_PORT_DROP_FRAMES));
2175
2176 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
2177 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
2178 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
2179 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
2180 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
2181 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
2182 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
2183 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
2184
2185#undef GET_STAT
2186#undef GET_STAT_COM
2187}
2188
2189/**
2190 * t4_wol_magic_enable - enable/disable magic packet WoL
2191 * @adap: the adapter
2192 * @port: the physical port index
2193 * @addr: MAC address expected in magic packets, %NULL to disable
2194 *
2195 * Enables/disables magic packet wake-on-LAN for the selected port.
2196 */
2197void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
2198 const u8 *addr)
2199{
2200 if (addr) {
2201 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO),
2202 (addr[2] << 24) | (addr[3] << 16) |
2203 (addr[4] << 8) | addr[5]);
2204 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI),
2205 (addr[0] << 8) | addr[1]);
2206 }
2207 t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), MAGICEN,
2208 addr ? MAGICEN : 0);
2209}
2210
2211/**
2212 * t4_wol_pat_enable - enable/disable pattern-based WoL
2213 * @adap: the adapter
2214 * @port: the physical port index
2215 * @map: bitmap of which HW pattern filters to set
2216 * @mask0: byte mask for bytes 0-63 of a packet
2217 * @mask1: byte mask for bytes 64-127 of a packet
2218 * @crc: Ethernet CRC for selected bytes
2219 * @enable: enable/disable switch
2220 *
2221 * Sets the pattern filters indicated in @map to mask out the bytes
2222 * specified in @mask0/@mask1 in received packets and compare the CRC of
2223 * the resulting packet against @crc. If @enable is %true pattern-based
2224 * WoL is enabled, otherwise disabled.
2225 */
2226int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
2227 u64 mask0, u64 mask1, unsigned int crc, bool enable)
2228{
2229 int i;
2230
2231 if (!enable) {
2232 t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2),
2233 PATEN, 0);
2234 return 0;
2235 }
2236 if (map > 0xff)
2237 return -EINVAL;
2238
2239#define EPIO_REG(name) PORT_REG(port, XGMAC_PORT_EPIO_##name)
2240
2241 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
2242 t4_write_reg(adap, EPIO_REG(DATA2), mask1);
2243 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
2244
2245 for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
2246 if (!(map & 1))
2247 continue;
2248
2249 /* write byte masks */
2250 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
2251 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i) | EPIOWR);
2252 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
2253 if (t4_read_reg(adap, EPIO_REG(OP)) & BUSY)
2254 return -ETIMEDOUT;
2255
2256 /* write CRC */
2257 t4_write_reg(adap, EPIO_REG(DATA0), crc);
2258 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i + 32) | EPIOWR);
2259 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
2260 if (t4_read_reg(adap, EPIO_REG(OP)) & BUSY)
2261 return -ETIMEDOUT;
2262 }
2263#undef EPIO_REG
2264
2265 t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), 0, PATEN);
2266 return 0;
2267}
2268
2269#define INIT_CMD(var, cmd, rd_wr) do { \
2270 (var).op_to_write = htonl(FW_CMD_OP(FW_##cmd##_CMD) | \
2271 FW_CMD_REQUEST | FW_CMD_##rd_wr); \
2272 (var).retval_len16 = htonl(FW_LEN16(var)); \
2273} while (0)
2274
2275/**
2276 * t4_mdio_rd - read a PHY register through MDIO
2277 * @adap: the adapter
2278 * @mbox: mailbox to use for the FW command
2279 * @phy_addr: the PHY address
2280 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
2281 * @reg: the register to read
2282 * @valp: where to store the value
2283 *
2284 * Issues a FW command through the given mailbox to read a PHY register.
2285 */
2286int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2287 unsigned int mmd, unsigned int reg, u16 *valp)
2288{
2289 int ret;
2290 struct fw_ldst_cmd c;
2291
2292 memset(&c, 0, sizeof(c));
2293 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2294 FW_CMD_READ | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO));
2295 c.cycles_to_len16 = htonl(FW_LEN16(c));
2296 c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) |
2297 FW_LDST_CMD_MMD(mmd));
2298 c.u.mdio.raddr = htons(reg);
2299
2300 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2301 if (ret == 0)
2302 *valp = ntohs(c.u.mdio.rval);
2303 return ret;
2304}
2305
2306/**
2307 * t4_mdio_wr - write a PHY register through MDIO
2308 * @adap: the adapter
2309 * @mbox: mailbox to use for the FW command
2310 * @phy_addr: the PHY address
2311 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
2312 * @reg: the register to write
2313 * @valp: value to write
2314 *
2315 * Issues a FW command through the given mailbox to write a PHY register.
2316 */
2317int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2318 unsigned int mmd, unsigned int reg, u16 val)
2319{
2320 struct fw_ldst_cmd c;
2321
2322 memset(&c, 0, sizeof(c));
2323 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2324 FW_CMD_WRITE | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO));
2325 c.cycles_to_len16 = htonl(FW_LEN16(c));
2326 c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) |
2327 FW_LDST_CMD_MMD(mmd));
2328 c.u.mdio.raddr = htons(reg);
2329 c.u.mdio.rval = htons(val);
2330
2331 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2332}
2333
2334/**
2335 * t4_fw_hello - establish communication with FW
2336 * @adap: the adapter
2337 * @mbox: mailbox to use for the FW command
2338 * @evt_mbox: mailbox to receive async FW events
2339 * @master: specifies the caller's willingness to be the device master
2340 * @state: returns the current device state
2341 *
2342 * Issues a command to establish communication with FW.
2343 */
2344int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
2345 enum dev_master master, enum dev_state *state)
2346{
2347 int ret;
2348 struct fw_hello_cmd c;
2349
2350 INIT_CMD(c, HELLO, WRITE);
2351 c.err_to_mbasyncnot = htonl(
2352 FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
2353 FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
2354 FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox : 0xff) |
2355 FW_HELLO_CMD_MBASYNCNOT(evt_mbox));
2356
2357 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2358 if (ret == 0 && state) {
2359 u32 v = ntohl(c.err_to_mbasyncnot);
2360 if (v & FW_HELLO_CMD_INIT)
2361 *state = DEV_STATE_INIT;
2362 else if (v & FW_HELLO_CMD_ERR)
2363 *state = DEV_STATE_ERR;
2364 else
2365 *state = DEV_STATE_UNINIT;
2366 }
2367 return ret;
2368}
2369
2370/**
2371 * t4_fw_bye - end communication with FW
2372 * @adap: the adapter
2373 * @mbox: mailbox to use for the FW command
2374 *
2375 * Issues a command to terminate communication with FW.
2376 */
2377int t4_fw_bye(struct adapter *adap, unsigned int mbox)
2378{
2379 struct fw_bye_cmd c;
2380
2381 INIT_CMD(c, BYE, WRITE);
2382 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2383}
2384
2385/**
2386 * t4_init_cmd - ask FW to initialize the device
2387 * @adap: the adapter
2388 * @mbox: mailbox to use for the FW command
2389 *
2390 * Issues a command to FW to partially initialize the device. This
2391 * performs initialization that generally doesn't depend on user input.
2392 */
2393int t4_early_init(struct adapter *adap, unsigned int mbox)
2394{
2395 struct fw_initialize_cmd c;
2396
2397 INIT_CMD(c, INITIALIZE, WRITE);
2398 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2399}
2400
2401/**
2402 * t4_fw_reset - issue a reset to FW
2403 * @adap: the adapter
2404 * @mbox: mailbox to use for the FW command
2405 * @reset: specifies the type of reset to perform
2406 *
2407 * Issues a reset command of the specified type to FW.
2408 */
2409int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
2410{
2411 struct fw_reset_cmd c;
2412
2413 INIT_CMD(c, RESET, WRITE);
2414 c.val = htonl(reset);
2415 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2416}
2417
2418/**
2419 * t4_query_params - query FW or device parameters
2420 * @adap: the adapter
2421 * @mbox: mailbox to use for the FW command
2422 * @pf: the PF
2423 * @vf: the VF
2424 * @nparams: the number of parameters
2425 * @params: the parameter names
2426 * @val: the parameter values
2427 *
2428 * Reads the value of FW or device parameters. Up to 7 parameters can be
2429 * queried at once.
2430 */
2431int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
2432 unsigned int vf, unsigned int nparams, const u32 *params,
2433 u32 *val)
2434{
2435 int i, ret;
2436 struct fw_params_cmd c;
2437 __be32 *p = &c.param[0].mnem;
2438
2439 if (nparams > 7)
2440 return -EINVAL;
2441
2442 memset(&c, 0, sizeof(c));
2443 c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST |
2444 FW_CMD_READ | FW_PARAMS_CMD_PFN(pf) |
2445 FW_PARAMS_CMD_VFN(vf));
2446 c.retval_len16 = htonl(FW_LEN16(c));
2447 for (i = 0; i < nparams; i++, p += 2)
2448 *p = htonl(*params++);
2449
2450 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2451 if (ret == 0)
2452 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
2453 *val++ = ntohl(*p);
2454 return ret;
2455}
2456
2457/**
2458 * t4_set_params - sets FW or device parameters
2459 * @adap: the adapter
2460 * @mbox: mailbox to use for the FW command
2461 * @pf: the PF
2462 * @vf: the VF
2463 * @nparams: the number of parameters
2464 * @params: the parameter names
2465 * @val: the parameter values
2466 *
2467 * Sets the value of FW or device parameters. Up to 7 parameters can be
2468 * specified at once.
2469 */
2470int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
2471 unsigned int vf, unsigned int nparams, const u32 *params,
2472 const u32 *val)
2473{
2474 struct fw_params_cmd c;
2475 __be32 *p = &c.param[0].mnem;
2476
2477 if (nparams > 7)
2478 return -EINVAL;
2479
2480 memset(&c, 0, sizeof(c));
2481 c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST |
2482 FW_CMD_WRITE | FW_PARAMS_CMD_PFN(pf) |
2483 FW_PARAMS_CMD_VFN(vf));
2484 c.retval_len16 = htonl(FW_LEN16(c));
2485 while (nparams--) {
2486 *p++ = htonl(*params++);
2487 *p++ = htonl(*val++);
2488 }
2489
2490 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2491}
2492
2493/**
2494 * t4_cfg_pfvf - configure PF/VF resource limits
2495 * @adap: the adapter
2496 * @mbox: mailbox to use for the FW command
2497 * @pf: the PF being configured
2498 * @vf: the VF being configured
2499 * @txq: the max number of egress queues
2500 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
2501 * @rxqi: the max number of interrupt-capable ingress queues
2502 * @rxq: the max number of interruptless ingress queues
2503 * @tc: the PCI traffic class
2504 * @vi: the max number of virtual interfaces
2505 * @cmask: the channel access rights mask for the PF/VF
2506 * @pmask: the port access rights mask for the PF/VF
2507 * @nexact: the maximum number of exact MPS filters
2508 * @rcaps: read capabilities
2509 * @wxcaps: write/execute capabilities
2510 *
2511 * Configures resource limits and capabilities for a physical or virtual
2512 * function.
2513 */
2514int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
2515 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
2516 unsigned int rxqi, unsigned int rxq, unsigned int tc,
2517 unsigned int vi, unsigned int cmask, unsigned int pmask,
2518 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
2519{
2520 struct fw_pfvf_cmd c;
2521
2522 memset(&c, 0, sizeof(c));
2523 c.op_to_vfn = htonl(FW_CMD_OP(FW_PFVF_CMD) | FW_CMD_REQUEST |
2524 FW_CMD_WRITE | FW_PFVF_CMD_PFN(pf) |
2525 FW_PFVF_CMD_VFN(vf));
2526 c.retval_len16 = htonl(FW_LEN16(c));
2527 c.niqflint_niq = htonl(FW_PFVF_CMD_NIQFLINT(rxqi) |
2528 FW_PFVF_CMD_NIQ(rxq));
2529 c.cmask_to_neq = htonl(FW_PFVF_CMD_CMASK(cmask) |
2530 FW_PFVF_CMD_PMASK(pmask) |
2531 FW_PFVF_CMD_NEQ(txq));
2532 c.tc_to_nexactf = htonl(FW_PFVF_CMD_TC(tc) | FW_PFVF_CMD_NVI(vi) |
2533 FW_PFVF_CMD_NEXACTF(nexact));
2534 c.r_caps_to_nethctrl = htonl(FW_PFVF_CMD_R_CAPS(rcaps) |
2535 FW_PFVF_CMD_WX_CAPS(wxcaps) |
2536 FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
2537 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2538}
2539
2540/**
2541 * t4_alloc_vi - allocate a virtual interface
2542 * @adap: the adapter
2543 * @mbox: mailbox to use for the FW command
2544 * @port: physical port associated with the VI
2545 * @pf: the PF owning the VI
2546 * @vf: the VF owning the VI
2547 * @nmac: number of MAC addresses needed (1 to 5)
2548 * @mac: the MAC addresses of the VI
2549 * @rss_size: size of RSS table slice associated with this VI
2550 *
2551 * Allocates a virtual interface for the given physical port. If @mac is
2552 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
2553 * @mac should be large enough to hold @nmac Ethernet addresses, they are
2554 * stored consecutively so the space needed is @nmac * 6 bytes.
2555 * Returns a negative error number or the non-negative VI id.
2556 */
2557int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
2558 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
2559 unsigned int *rss_size)
2560{
2561 int ret;
2562 struct fw_vi_cmd c;
2563
2564 memset(&c, 0, sizeof(c));
2565 c.op_to_vfn = htonl(FW_CMD_OP(FW_VI_CMD) | FW_CMD_REQUEST |
2566 FW_CMD_WRITE | FW_CMD_EXEC |
2567 FW_VI_CMD_PFN(pf) | FW_VI_CMD_VFN(vf));
2568 c.alloc_to_len16 = htonl(FW_VI_CMD_ALLOC | FW_LEN16(c));
2569 c.portid_pkd = FW_VI_CMD_PORTID(port);
2570 c.nmac = nmac - 1;
2571
2572 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2573 if (ret)
2574 return ret;
2575
2576 if (mac) {
2577 memcpy(mac, c.mac, sizeof(c.mac));
2578 switch (nmac) {
2579 case 5:
2580 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
2581 case 4:
2582 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
2583 case 3:
2584 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
2585 case 2:
2586 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
2587 }
2588 }
2589 if (rss_size)
2590 *rss_size = FW_VI_CMD_RSSSIZE_GET(ntohs(c.rsssize_pkd));
2591 return ntohs(c.viid_pkd);
2592}
2593
2594/**
2595 * t4_free_vi - free a virtual interface
2596 * @adap: the adapter
2597 * @mbox: mailbox to use for the FW command
2598 * @pf: the PF owning the VI
2599 * @vf: the VF owning the VI
2600 * @viid: virtual interface identifiler
2601 *
2602 * Free a previously allocated virtual interface.
2603 */
2604int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
2605 unsigned int vf, unsigned int viid)
2606{
2607 struct fw_vi_cmd c;
2608
2609 memset(&c, 0, sizeof(c));
2610 c.op_to_vfn = htonl(FW_CMD_OP(FW_VI_CMD) | FW_CMD_REQUEST |
2611 FW_CMD_EXEC | FW_VI_CMD_PFN(pf) |
2612 FW_VI_CMD_VFN(vf));
2613 c.alloc_to_len16 = htonl(FW_VI_CMD_FREE | FW_LEN16(c));
2614 c.viid_pkd = htons(FW_VI_CMD_VIID(viid));
2615 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2616}
2617
2618/**
2619 * t4_set_rxmode - set Rx properties of a virtual interface
2620 * @adap: the adapter
2621 * @mbox: mailbox to use for the FW command
2622 * @viid: the VI id
2623 * @mtu: the new MTU or -1
2624 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
2625 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
2626 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
2627 * @sleep_ok: if true we may sleep while awaiting command completion
2628 *
2629 * Sets Rx properties of a virtual interface.
2630 */
2631int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
2632 int mtu, int promisc, int all_multi, int bcast, bool sleep_ok)
2633{
2634 struct fw_vi_rxmode_cmd c;
2635
2636 /* convert to FW values */
2637 if (mtu < 0)
2638 mtu = FW_RXMODE_MTU_NO_CHG;
2639 if (promisc < 0)
2640 promisc = FW_VI_RXMODE_CMD_PROMISCEN_MASK;
2641 if (all_multi < 0)
2642 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_MASK;
2643 if (bcast < 0)
2644 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_MASK;
2645
2646 memset(&c, 0, sizeof(c));
2647 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_RXMODE_CMD) | FW_CMD_REQUEST |
2648 FW_CMD_WRITE | FW_VI_RXMODE_CMD_VIID(viid));
2649 c.retval_len16 = htonl(FW_LEN16(c));
2650 c.mtu_to_broadcasten = htonl(FW_VI_RXMODE_CMD_MTU(mtu) |
2651 FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
2652 FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
2653 FW_VI_RXMODE_CMD_BROADCASTEN(bcast));
2654 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
2655}
2656
2657/**
2658 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
2659 * @adap: the adapter
2660 * @mbox: mailbox to use for the FW command
2661 * @viid: the VI id
2662 * @free: if true any existing filters for this VI id are first removed
2663 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
2664 * @addr: the MAC address(es)
2665 * @idx: where to store the index of each allocated filter
2666 * @hash: pointer to hash address filter bitmap
2667 * @sleep_ok: call is allowed to sleep
2668 *
2669 * Allocates an exact-match filter for each of the supplied addresses and
2670 * sets it to the corresponding address. If @idx is not %NULL it should
2671 * have at least @naddr entries, each of which will be set to the index of
2672 * the filter allocated for the corresponding MAC address. If a filter
2673 * could not be allocated for an address its index is set to 0xffff.
2674 * If @hash is not %NULL addresses that fail to allocate an exact filter
2675 * are hashed and update the hash filter bitmap pointed at by @hash.
2676 *
2677 * Returns a negative error number or the number of filters allocated.
2678 */
2679int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
2680 unsigned int viid, bool free, unsigned int naddr,
2681 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
2682{
2683 int i, ret;
2684 struct fw_vi_mac_cmd c;
2685 struct fw_vi_mac_exact *p;
2686
2687 if (naddr > 7)
2688 return -EINVAL;
2689
2690 memset(&c, 0, sizeof(c));
2691 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
2692 FW_CMD_WRITE | (free ? FW_CMD_EXEC : 0) |
2693 FW_VI_MAC_CMD_VIID(viid));
2694 c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_FREEMACS(free) |
2695 FW_CMD_LEN16((naddr + 2) / 2));
2696
2697 for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
2698 p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID |
2699 FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
2700 memcpy(p->macaddr, addr[i], sizeof(p->macaddr));
2701 }
2702
2703 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
2704 if (ret)
2705 return ret;
2706
2707 for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
2708 u16 index = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
2709
2710 if (idx)
2711 idx[i] = index >= NEXACT_MAC ? 0xffff : index;
2712 if (index < NEXACT_MAC)
2713 ret++;
2714 else if (hash)
2715 *hash |= (1 << hash_mac_addr(addr[i]));
2716 }
2717 return ret;
2718}
2719
2720/**
2721 * t4_change_mac - modifies the exact-match filter for a MAC address
2722 * @adap: the adapter
2723 * @mbox: mailbox to use for the FW command
2724 * @viid: the VI id
2725 * @idx: index of existing filter for old value of MAC address, or -1
2726 * @addr: the new MAC address value
2727 * @persist: whether a new MAC allocation should be persistent
2728 * @add_smt: if true also add the address to the HW SMT
2729 *
2730 * Modifies an exact-match filter and sets it to the new MAC address.
2731 * Note that in general it is not possible to modify the value of a given
2732 * filter so the generic way to modify an address filter is to free the one
2733 * being used by the old address value and allocate a new filter for the
2734 * new address value. @idx can be -1 if the address is a new addition.
2735 *
2736 * Returns a negative error number or the index of the filter with the new
2737 * MAC value.
2738 */
2739int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
2740 int idx, const u8 *addr, bool persist, bool add_smt)
2741{
2742 int ret, mode;
2743 struct fw_vi_mac_cmd c;
2744 struct fw_vi_mac_exact *p = c.u.exact;
2745
2746 if (idx < 0) /* new allocation */
2747 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
2748 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
2749
2750 memset(&c, 0, sizeof(c));
2751 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
2752 FW_CMD_WRITE | FW_VI_MAC_CMD_VIID(viid));
2753 c.freemacs_to_len16 = htonl(FW_CMD_LEN16(1));
2754 p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID |
2755 FW_VI_MAC_CMD_SMAC_RESULT(mode) |
2756 FW_VI_MAC_CMD_IDX(idx));
2757 memcpy(p->macaddr, addr, sizeof(p->macaddr));
2758
2759 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2760 if (ret == 0) {
2761 ret = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
2762 if (ret >= NEXACT_MAC)
2763 ret = -ENOMEM;
2764 }
2765 return ret;
2766}
2767
2768/**
2769 * t4_set_addr_hash - program the MAC inexact-match hash filter
2770 * @adap: the adapter
2771 * @mbox: mailbox to use for the FW command
2772 * @viid: the VI id
2773 * @ucast: whether the hash filter should also match unicast addresses
2774 * @vec: the value to be written to the hash filter
2775 * @sleep_ok: call is allowed to sleep
2776 *
2777 * Sets the 64-bit inexact-match hash filter for a virtual interface.
2778 */
2779int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
2780 bool ucast, u64 vec, bool sleep_ok)
2781{
2782 struct fw_vi_mac_cmd c;
2783
2784 memset(&c, 0, sizeof(c));
2785 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
2786 FW_CMD_WRITE | FW_VI_ENABLE_CMD_VIID(viid));
2787 c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_HASHVECEN |
2788 FW_VI_MAC_CMD_HASHUNIEN(ucast) |
2789 FW_CMD_LEN16(1));
2790 c.u.hash.hashvec = cpu_to_be64(vec);
2791 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
2792}
2793
2794/**
2795 * t4_enable_vi - enable/disable a virtual interface
2796 * @adap: the adapter
2797 * @mbox: mailbox to use for the FW command
2798 * @viid: the VI id
2799 * @rx_en: 1=enable Rx, 0=disable Rx
2800 * @tx_en: 1=enable Tx, 0=disable Tx
2801 *
2802 * Enables/disables a virtual interface.
2803 */
2804int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
2805 bool rx_en, bool tx_en)
2806{
2807 struct fw_vi_enable_cmd c;
2808
2809 memset(&c, 0, sizeof(c));
2810 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST |
2811 FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid));
2812 c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_IEN(rx_en) |
2813 FW_VI_ENABLE_CMD_EEN(tx_en) | FW_LEN16(c));
2814 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2815}
2816
2817/**
2818 * t4_identify_port - identify a VI's port by blinking its LED
2819 * @adap: the adapter
2820 * @mbox: mailbox to use for the FW command
2821 * @viid: the VI id
2822 * @nblinks: how many times to blink LED at 2.5 Hz
2823 *
2824 * Identifies a VI's port by blinking its LED.
2825 */
2826int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
2827 unsigned int nblinks)
2828{
2829 struct fw_vi_enable_cmd c;
2830
2831 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST |
2832 FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid));
2833 c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
2834 c.blinkdur = htons(nblinks);
2835 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2836}
2837
2838/**
2839 * t4_iq_start_stop - enable/disable an ingress queue and its FLs
2840 * @adap: the adapter
2841 * @mbox: mailbox to use for the FW command
2842 * @start: %true to enable the queues, %false to disable them
2843 * @pf: the PF owning the queues
2844 * @vf: the VF owning the queues
2845 * @iqid: ingress queue id
2846 * @fl0id: FL0 queue id or 0xffff if no attached FL0
2847 * @fl1id: FL1 queue id or 0xffff if no attached FL1
2848 *
2849 * Starts or stops an ingress queue and its associated FLs, if any.
2850 */
2851int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
2852 unsigned int pf, unsigned int vf, unsigned int iqid,
2853 unsigned int fl0id, unsigned int fl1id)
2854{
2855 struct fw_iq_cmd c;
2856
2857 memset(&c, 0, sizeof(c));
2858 c.op_to_vfn = htonl(FW_CMD_OP(FW_IQ_CMD) | FW_CMD_REQUEST |
2859 FW_CMD_EXEC | FW_IQ_CMD_PFN(pf) |
2860 FW_IQ_CMD_VFN(vf));
2861 c.alloc_to_len16 = htonl(FW_IQ_CMD_IQSTART(start) |
2862 FW_IQ_CMD_IQSTOP(!start) | FW_LEN16(c));
2863 c.iqid = htons(iqid);
2864 c.fl0id = htons(fl0id);
2865 c.fl1id = htons(fl1id);
2866 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2867}
2868
2869/**
2870 * t4_iq_free - free an ingress queue and its FLs
2871 * @adap: the adapter
2872 * @mbox: mailbox to use for the FW command
2873 * @pf: the PF owning the queues
2874 * @vf: the VF owning the queues
2875 * @iqtype: the ingress queue type
2876 * @iqid: ingress queue id
2877 * @fl0id: FL0 queue id or 0xffff if no attached FL0
2878 * @fl1id: FL1 queue id or 0xffff if no attached FL1
2879 *
2880 * Frees an ingress queue and its associated FLs, if any.
2881 */
2882int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
2883 unsigned int vf, unsigned int iqtype, unsigned int iqid,
2884 unsigned int fl0id, unsigned int fl1id)
2885{
2886 struct fw_iq_cmd c;
2887
2888 memset(&c, 0, sizeof(c));
2889 c.op_to_vfn = htonl(FW_CMD_OP(FW_IQ_CMD) | FW_CMD_REQUEST |
2890 FW_CMD_EXEC | FW_IQ_CMD_PFN(pf) |
2891 FW_IQ_CMD_VFN(vf));
2892 c.alloc_to_len16 = htonl(FW_IQ_CMD_FREE | FW_LEN16(c));
2893 c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE(iqtype));
2894 c.iqid = htons(iqid);
2895 c.fl0id = htons(fl0id);
2896 c.fl1id = htons(fl1id);
2897 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2898}
2899
2900/**
2901 * t4_eth_eq_free - free an Ethernet egress queue
2902 * @adap: the adapter
2903 * @mbox: mailbox to use for the FW command
2904 * @pf: the PF owning the queue
2905 * @vf: the VF owning the queue
2906 * @eqid: egress queue id
2907 *
2908 * Frees an Ethernet egress queue.
2909 */
2910int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
2911 unsigned int vf, unsigned int eqid)
2912{
2913 struct fw_eq_eth_cmd c;
2914
2915 memset(&c, 0, sizeof(c));
2916 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_ETH_CMD) | FW_CMD_REQUEST |
2917 FW_CMD_EXEC | FW_EQ_ETH_CMD_PFN(pf) |
2918 FW_EQ_ETH_CMD_VFN(vf));
2919 c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
2920 c.eqid_pkd = htonl(FW_EQ_ETH_CMD_EQID(eqid));
2921 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2922}
2923
2924/**
2925 * t4_ctrl_eq_free - free a control egress queue
2926 * @adap: the adapter
2927 * @mbox: mailbox to use for the FW command
2928 * @pf: the PF owning the queue
2929 * @vf: the VF owning the queue
2930 * @eqid: egress queue id
2931 *
2932 * Frees a control egress queue.
2933 */
2934int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
2935 unsigned int vf, unsigned int eqid)
2936{
2937 struct fw_eq_ctrl_cmd c;
2938
2939 memset(&c, 0, sizeof(c));
2940 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST |
2941 FW_CMD_EXEC | FW_EQ_CTRL_CMD_PFN(pf) |
2942 FW_EQ_CTRL_CMD_VFN(vf));
2943 c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
2944 c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_EQID(eqid));
2945 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2946}
2947
2948/**
2949 * t4_ofld_eq_free - free an offload egress queue
2950 * @adap: the adapter
2951 * @mbox: mailbox to use for the FW command
2952 * @pf: the PF owning the queue
2953 * @vf: the VF owning the queue
2954 * @eqid: egress queue id
2955 *
2956 * Frees a control egress queue.
2957 */
2958int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
2959 unsigned int vf, unsigned int eqid)
2960{
2961 struct fw_eq_ofld_cmd c;
2962
2963 memset(&c, 0, sizeof(c));
2964 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST |
2965 FW_CMD_EXEC | FW_EQ_OFLD_CMD_PFN(pf) |
2966 FW_EQ_OFLD_CMD_VFN(vf));
2967 c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
2968 c.eqid_pkd = htonl(FW_EQ_OFLD_CMD_EQID(eqid));
2969 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2970}
2971
2972/**
2973 * t4_handle_fw_rpl - process a FW reply message
2974 * @adap: the adapter
2975 * @rpl: start of the FW message
2976 *
2977 * Processes a FW message, such as link state change messages.
2978 */
2979int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
2980{
2981 u8 opcode = *(const u8 *)rpl;
2982
2983 if (opcode == FW_PORT_CMD) { /* link/module state change message */
2984 int speed = 0, fc = 0;
2985 const struct fw_port_cmd *p = (void *)rpl;
2986 int chan = FW_PORT_CMD_PORTID_GET(ntohl(p->op_to_portid));
2987 int port = adap->chan_map[chan];
2988 struct port_info *pi = adap2pinfo(adap, port);
2989 struct link_config *lc = &pi->link_cfg;
2990 u32 stat = ntohl(p->u.info.lstatus_to_modtype);
2991 int link_ok = (stat & FW_PORT_CMD_LSTATUS) != 0;
2992 u32 mod = FW_PORT_CMD_MODTYPE_GET(stat);
2993
2994 if (stat & FW_PORT_CMD_RXPAUSE)
2995 fc |= PAUSE_RX;
2996 if (stat & FW_PORT_CMD_TXPAUSE)
2997 fc |= PAUSE_TX;
2998 if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
2999 speed = SPEED_100;
3000 else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
3001 speed = SPEED_1000;
3002 else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
3003 speed = SPEED_10000;
3004
3005 if (link_ok != lc->link_ok || speed != lc->speed ||
3006 fc != lc->fc) { /* something changed */
3007 lc->link_ok = link_ok;
3008 lc->speed = speed;
3009 lc->fc = fc;
3010 t4_os_link_changed(adap, port, link_ok);
3011 }
3012 if (mod != pi->mod_type) {
3013 pi->mod_type = mod;
3014 t4_os_portmod_changed(adap, port);
3015 }
3016 }
3017 return 0;
3018}
3019
3020static void __devinit get_pci_mode(struct adapter *adapter,
3021 struct pci_params *p)
3022{
3023 u16 val;
3024 u32 pcie_cap = pci_pcie_cap(adapter->pdev);
3025
3026 if (pcie_cap) {
3027 pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA,
3028 &val);
3029 p->speed = val & PCI_EXP_LNKSTA_CLS;
3030 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
3031 }
3032}
3033
3034/**
3035 * init_link_config - initialize a link's SW state
3036 * @lc: structure holding the link state
3037 * @caps: link capabilities
3038 *
3039 * Initializes the SW state maintained for each link, including the link's
3040 * capabilities and default speed/flow-control/autonegotiation settings.
3041 */
3042static void __devinit init_link_config(struct link_config *lc,
3043 unsigned int caps)
3044{
3045 lc->supported = caps;
3046 lc->requested_speed = 0;
3047 lc->speed = 0;
3048 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
3049 if (lc->supported & FW_PORT_CAP_ANEG) {
3050 lc->advertising = lc->supported & ADVERT_MASK;
3051 lc->autoneg = AUTONEG_ENABLE;
3052 lc->requested_fc |= PAUSE_AUTONEG;
3053 } else {
3054 lc->advertising = 0;
3055 lc->autoneg = AUTONEG_DISABLE;
3056 }
3057}
3058
3059static int __devinit wait_dev_ready(struct adapter *adap)
3060{
3061 if (t4_read_reg(adap, PL_WHOAMI) != 0xffffffff)
3062 return 0;
3063 msleep(500);
3064 return t4_read_reg(adap, PL_WHOAMI) != 0xffffffff ? 0 : -EIO;
3065}
3066
3067/**
3068 * t4_prep_adapter - prepare SW and HW for operation
3069 * @adapter: the adapter
3070 * @reset: if true perform a HW reset
3071 *
3072 * Initialize adapter SW state for the various HW modules, set initial
3073 * values for some adapter tunables, take PHYs out of reset, and
3074 * initialize the MDIO interface.
3075 */
3076int __devinit t4_prep_adapter(struct adapter *adapter)
3077{
3078 int ret;
3079
3080 ret = wait_dev_ready(adapter);
3081 if (ret < 0)
3082 return ret;
3083
3084 get_pci_mode(adapter, &adapter->params.pci);
3085 adapter->params.rev = t4_read_reg(adapter, PL_REV);
3086
3087 ret = get_vpd_params(adapter, &adapter->params.vpd);
3088 if (ret < 0)
3089 return ret;
3090
3091 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3092
3093 /*
3094 * Default port for debugging in case we can't reach FW.
3095 */
3096 adapter->params.nports = 1;
3097 adapter->params.portvec = 1;
3098 return 0;
3099}
3100
3101int __devinit t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
3102{
3103 u8 addr[6];
3104 int ret, i, j = 0;
3105 struct fw_port_cmd c;
3106
3107 memset(&c, 0, sizeof(c));
3108
3109 for_each_port(adap, i) {
3110 unsigned int rss_size;
3111 struct port_info *p = adap2pinfo(adap, i);
3112
3113 while ((adap->params.portvec & (1 << j)) == 0)
3114 j++;
3115
3116 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) |
3117 FW_CMD_REQUEST | FW_CMD_READ |
3118 FW_PORT_CMD_PORTID(j));
3119 c.action_to_len16 = htonl(
3120 FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
3121 FW_LEN16(c));
3122 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3123 if (ret)
3124 return ret;
3125
3126 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
3127 if (ret < 0)
3128 return ret;
3129
3130 p->viid = ret;
3131 p->tx_chan = j;
3132 p->lport = j;
3133 p->rss_size = rss_size;
3134 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
3135 memcpy(adap->port[i]->perm_addr, addr, ETH_ALEN);
3136
3137 ret = ntohl(c.u.info.lstatus_to_modtype);
3138 p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP) ?
3139 FW_PORT_CMD_MDIOADDR_GET(ret) : -1;
3140 p->port_type = FW_PORT_CMD_PTYPE_GET(ret);
3141 p->mod_type = FW_PORT_CMD_MODTYPE_GET(ret);
3142
3143 init_link_config(&p->link_cfg, ntohs(c.u.info.pcap));
3144 j++;
3145 }
3146 return 0;
3147}
diff --git a/drivers/net/cxgb4/t4_hw.h b/drivers/net/cxgb4/t4_hw.h
new file mode 100644
index 000000000000..025623285c93
--- /dev/null
+++ b/drivers/net/cxgb4/t4_hw.h
@@ -0,0 +1,100 @@
1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __T4_HW_H
36#define __T4_HW_H
37
38#include <linux/types.h>
39
40enum {
41 NCHAN = 4, /* # of HW channels */
42 MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */
43 EEPROMSIZE = 17408, /* Serial EEPROM physical size */
44 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
45 RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */
46 TCB_SIZE = 128, /* TCB size */
47 NMTUS = 16, /* size of MTU table */
48 NCCTRL_WIN = 32, /* # of congestion control windows */
49 NEXACT_MAC = 336, /* # of exact MAC address filters */
50 L2T_SIZE = 4096, /* # of L2T entries */
51 MBOX_LEN = 64, /* mailbox size in bytes */
52 TRACE_LEN = 112, /* length of trace data and mask */
53 FILTER_OPT_LEN = 36, /* filter tuple width for optional components */
54 NWOL_PAT = 8, /* # of WoL patterns */
55 WOL_PAT_LEN = 128, /* length of WoL patterns */
56};
57
58enum {
59 SF_PAGE_SIZE = 256, /* serial flash page size */
60 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
61 SF_SIZE = SF_SEC_SIZE * 16, /* serial flash size */
62};
63
64enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
65
66enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */
67
68enum {
69 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
70 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
71 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
72};
73
74struct sge_qstat { /* data written to SGE queue status entries */
75 __be32 qid;
76 __be16 cidx;
77 __be16 pidx;
78};
79
80/*
81 * Structure for last 128 bits of response descriptors
82 */
83struct rsp_ctrl {
84 __be32 hdrbuflen_pidx;
85 __be32 pldbuflen_qid;
86 union {
87 u8 type_gen;
88 __be64 last_flit;
89 };
90};
91
92#define RSPD_NEWBUF 0x80000000U
93#define RSPD_LEN 0x7fffffffU
94
95#define RSPD_GEN(x) ((x) >> 7)
96#define RSPD_TYPE(x) (((x) >> 4) & 3)
97
98#define QINTR_CNT_EN 0x1
99#define QINTR_TIMER_IDX(x) ((x) << 1)
100#endif /* __T4_HW_H */
diff --git a/drivers/net/cxgb4/t4_msg.h b/drivers/net/cxgb4/t4_msg.h
new file mode 100644
index 000000000000..7a981b81afaf
--- /dev/null
+++ b/drivers/net/cxgb4/t4_msg.h
@@ -0,0 +1,665 @@
1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __T4_MSG_H
36#define __T4_MSG_H
37
38#include <linux/types.h>
39
40enum {
41 CPL_PASS_OPEN_REQ = 0x1,
42 CPL_PASS_ACCEPT_RPL = 0x2,
43 CPL_ACT_OPEN_REQ = 0x3,
44 CPL_SET_TCB_FIELD = 0x5,
45 CPL_GET_TCB = 0x6,
46 CPL_CLOSE_CON_REQ = 0x8,
47 CPL_CLOSE_LISTSRV_REQ = 0x9,
48 CPL_ABORT_REQ = 0xA,
49 CPL_ABORT_RPL = 0xB,
50 CPL_RX_DATA_ACK = 0xD,
51 CPL_TX_PKT = 0xE,
52 CPL_L2T_WRITE_REQ = 0x12,
53 CPL_TID_RELEASE = 0x1A,
54
55 CPL_CLOSE_LISTSRV_RPL = 0x20,
56 CPL_L2T_WRITE_RPL = 0x23,
57 CPL_PASS_OPEN_RPL = 0x24,
58 CPL_ACT_OPEN_RPL = 0x25,
59 CPL_PEER_CLOSE = 0x26,
60 CPL_ABORT_REQ_RSS = 0x2B,
61 CPL_ABORT_RPL_RSS = 0x2D,
62
63 CPL_CLOSE_CON_RPL = 0x32,
64 CPL_ISCSI_HDR = 0x33,
65 CPL_RDMA_CQE = 0x35,
66 CPL_RDMA_CQE_READ_RSP = 0x36,
67 CPL_RDMA_CQE_ERR = 0x37,
68 CPL_RX_DATA = 0x39,
69 CPL_SET_TCB_RPL = 0x3A,
70 CPL_RX_PKT = 0x3B,
71 CPL_RX_DDP_COMPLETE = 0x3F,
72
73 CPL_ACT_ESTABLISH = 0x40,
74 CPL_PASS_ESTABLISH = 0x41,
75 CPL_RX_DATA_DDP = 0x42,
76 CPL_PASS_ACCEPT_REQ = 0x44,
77
78 CPL_RDMA_READ_REQ = 0x60,
79
80 CPL_PASS_OPEN_REQ6 = 0x81,
81 CPL_ACT_OPEN_REQ6 = 0x83,
82
83 CPL_RDMA_TERMINATE = 0xA2,
84 CPL_RDMA_WRITE = 0xA4,
85 CPL_SGE_EGR_UPDATE = 0xA5,
86
87 CPL_TRACE_PKT = 0xB0,
88
89 CPL_FW4_MSG = 0xC0,
90 CPL_FW4_PLD = 0xC1,
91 CPL_FW4_ACK = 0xC3,
92
93 CPL_FW6_MSG = 0xE0,
94 CPL_FW6_PLD = 0xE1,
95 CPL_TX_PKT_LSO = 0xED,
96 CPL_TX_PKT_XT = 0xEE,
97
98 NUM_CPL_CMDS
99};
100
101enum CPL_error {
102 CPL_ERR_NONE = 0,
103 CPL_ERR_TCAM_FULL = 3,
104 CPL_ERR_BAD_LENGTH = 15,
105 CPL_ERR_BAD_ROUTE = 18,
106 CPL_ERR_CONN_RESET = 20,
107 CPL_ERR_CONN_EXIST_SYNRECV = 21,
108 CPL_ERR_CONN_EXIST = 22,
109 CPL_ERR_ARP_MISS = 23,
110 CPL_ERR_BAD_SYN = 24,
111 CPL_ERR_CONN_TIMEDOUT = 30,
112 CPL_ERR_XMIT_TIMEDOUT = 31,
113 CPL_ERR_PERSIST_TIMEDOUT = 32,
114 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
115 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
116 CPL_ERR_RTX_NEG_ADVICE = 35,
117 CPL_ERR_PERSIST_NEG_ADVICE = 36,
118 CPL_ERR_ABORT_FAILED = 42,
119 CPL_ERR_IWARP_FLM = 50,
120};
121
122enum {
123 ULP_MODE_NONE = 0,
124 ULP_MODE_ISCSI = 2,
125 ULP_MODE_RDMA = 4,
126 ULP_MODE_FCOE = 6,
127};
128
129enum {
130 ULP_CRC_HEADER = 1 << 0,
131 ULP_CRC_DATA = 1 << 1
132};
133
134enum {
135 CPL_ABORT_SEND_RST = 0,
136 CPL_ABORT_NO_RST,
137};
138
139enum { /* TX_PKT_XT checksum types */
140 TX_CSUM_TCP = 0,
141 TX_CSUM_UDP = 1,
142 TX_CSUM_CRC16 = 4,
143 TX_CSUM_CRC32 = 5,
144 TX_CSUM_CRC32C = 6,
145 TX_CSUM_FCOE = 7,
146 TX_CSUM_TCPIP = 8,
147 TX_CSUM_UDPIP = 9,
148 TX_CSUM_TCPIP6 = 10,
149 TX_CSUM_UDPIP6 = 11,
150 TX_CSUM_IP = 12,
151};
152
153union opcode_tid {
154 __be32 opcode_tid;
155 u8 opcode;
156};
157
158#define CPL_OPCODE(x) ((x) << 24)
159#define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE(opcode) | (tid))
160#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
161#define GET_TID(cmd) (ntohl(OPCODE_TID(cmd)) & 0xFFFFFF)
162
163/* partitioning of TID fields that also carry a queue id */
164#define GET_TID_TID(x) ((x) & 0x3fff)
165#define GET_TID_QID(x) (((x) >> 14) & 0x3ff)
166#define TID_QID(x) ((x) << 14)
167
168struct rss_header {
169 u8 opcode;
170#if defined(__LITTLE_ENDIAN_BITFIELD)
171 u8 channel:2;
172 u8 filter_hit:1;
173 u8 filter_tid:1;
174 u8 hash_type:2;
175 u8 ipv6:1;
176 u8 send2fw:1;
177#else
178 u8 send2fw:1;
179 u8 ipv6:1;
180 u8 hash_type:2;
181 u8 filter_tid:1;
182 u8 filter_hit:1;
183 u8 channel:2;
184#endif
185 __be16 qid;
186 __be32 hash_val;
187};
188
189struct work_request_hdr {
190 __be32 wr_hi;
191 __be32 wr_mid;
192 __be64 wr_lo;
193};
194
195#define WR_HDR struct work_request_hdr wr
196
197struct cpl_pass_open_req {
198 WR_HDR;
199 union opcode_tid ot;
200 __be16 local_port;
201 __be16 peer_port;
202 __be32 local_ip;
203 __be32 peer_ip;
204 __be64 opt0;
205#define TX_CHAN(x) ((x) << 2)
206#define DELACK(x) ((x) << 5)
207#define ULP_MODE(x) ((x) << 8)
208#define RCV_BUFSIZ(x) ((x) << 12)
209#define DSCP(x) ((x) << 22)
210#define SMAC_SEL(x) ((u64)(x) << 28)
211#define L2T_IDX(x) ((u64)(x) << 36)
212#define NAGLE(x) ((u64)(x) << 49)
213#define WND_SCALE(x) ((u64)(x) << 50)
214#define KEEP_ALIVE(x) ((u64)(x) << 54)
215#define MSS_IDX(x) ((u64)(x) << 60)
216 __be64 opt1;
217#define SYN_RSS_ENABLE (1 << 0)
218#define SYN_RSS_QUEUE(x) ((x) << 2)
219#define CONN_POLICY_ASK (1 << 22)
220};
221
222struct cpl_pass_open_req6 {
223 WR_HDR;
224 union opcode_tid ot;
225 __be16 local_port;
226 __be16 peer_port;
227 __be64 local_ip_hi;
228 __be64 local_ip_lo;
229 __be64 peer_ip_hi;
230 __be64 peer_ip_lo;
231 __be64 opt0;
232 __be64 opt1;
233};
234
235struct cpl_pass_open_rpl {
236 union opcode_tid ot;
237 u8 rsvd[3];
238 u8 status;
239};
240
241struct cpl_pass_accept_rpl {
242 WR_HDR;
243 union opcode_tid ot;
244 __be32 opt2;
245#define RSS_QUEUE(x) ((x) << 0)
246#define RSS_QUEUE_VALID (1 << 10)
247#define RX_COALESCE_VALID(x) ((x) << 11)
248#define RX_COALESCE(x) ((x) << 12)
249#define TX_QUEUE(x) ((x) << 23)
250#define RX_CHANNEL(x) ((x) << 26)
251#define WND_SCALE_EN(x) ((x) << 28)
252#define TSTAMPS_EN(x) ((x) << 29)
253#define SACK_EN(x) ((x) << 30)
254 __be64 opt0;
255};
256
257struct cpl_act_open_req {
258 WR_HDR;
259 union opcode_tid ot;
260 __be16 local_port;
261 __be16 peer_port;
262 __be32 local_ip;
263 __be32 peer_ip;
264 __be64 opt0;
265 __be32 params;
266 __be32 opt2;
267};
268
269struct cpl_act_open_req6 {
270 WR_HDR;
271 union opcode_tid ot;
272 __be16 local_port;
273 __be16 peer_port;
274 __be64 local_ip_hi;
275 __be64 local_ip_lo;
276 __be64 peer_ip_hi;
277 __be64 peer_ip_lo;
278 __be64 opt0;
279 __be32 params;
280 __be32 opt2;
281};
282
283struct cpl_act_open_rpl {
284 union opcode_tid ot;
285 __be32 atid_status;
286#define GET_AOPEN_STATUS(x) ((x) & 0xff)
287#define GET_AOPEN_ATID(x) (((x) >> 8) & 0xffffff)
288};
289
290struct cpl_pass_establish {
291 union opcode_tid ot;
292 __be32 rsvd;
293 __be32 tos_stid;
294#define GET_POPEN_TID(x) ((x) & 0xffffff)
295#define GET_POPEN_TOS(x) (((x) >> 24) & 0xff)
296 __be16 mac_idx;
297 __be16 tcp_opt;
298#define GET_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
299#define GET_TCPOPT_SACK(x) (((x) >> 6) & 1)
300#define GET_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
301#define GET_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
302#define GET_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
303 __be32 snd_isn;
304 __be32 rcv_isn;
305};
306
307struct cpl_act_establish {
308 union opcode_tid ot;
309 __be32 rsvd;
310 __be32 tos_atid;
311 __be16 mac_idx;
312 __be16 tcp_opt;
313 __be32 snd_isn;
314 __be32 rcv_isn;
315};
316
317struct cpl_get_tcb {
318 WR_HDR;
319 union opcode_tid ot;
320 __be16 reply_ctrl;
321#define QUEUENO(x) ((x) << 0)
322#define REPLY_CHAN(x) ((x) << 14)
323#define NO_REPLY(x) ((x) << 15)
324 __be16 cookie;
325};
326
327struct cpl_set_tcb_field {
328 WR_HDR;
329 union opcode_tid ot;
330 __be16 reply_ctrl;
331 __be16 word_cookie;
332#define TCB_WORD(x) ((x) << 0)
333#define TCB_COOKIE(x) ((x) << 5)
334 __be64 mask;
335 __be64 val;
336};
337
338struct cpl_set_tcb_rpl {
339 union opcode_tid ot;
340 __be16 rsvd;
341 u8 cookie;
342 u8 status;
343 __be64 oldval;
344};
345
346struct cpl_close_con_req {
347 WR_HDR;
348 union opcode_tid ot;
349 __be32 rsvd;
350};
351
352struct cpl_close_con_rpl {
353 union opcode_tid ot;
354 u8 rsvd[3];
355 u8 status;
356 __be32 snd_nxt;
357 __be32 rcv_nxt;
358};
359
360struct cpl_close_listsvr_req {
361 WR_HDR;
362 union opcode_tid ot;
363 __be16 reply_ctrl;
364#define LISTSVR_IPV6 (1 << 14)
365 __be16 rsvd;
366};
367
368struct cpl_close_listsvr_rpl {
369 union opcode_tid ot;
370 u8 rsvd[3];
371 u8 status;
372};
373
374struct cpl_abort_req_rss {
375 union opcode_tid ot;
376 u8 rsvd[3];
377 u8 status;
378};
379
380struct cpl_abort_req {
381 WR_HDR;
382 union opcode_tid ot;
383 __be32 rsvd0;
384 u8 rsvd1;
385 u8 cmd;
386 u8 rsvd2[6];
387};
388
389struct cpl_abort_rpl_rss {
390 union opcode_tid ot;
391 u8 rsvd[3];
392 u8 status;
393};
394
395struct cpl_abort_rpl {
396 WR_HDR;
397 union opcode_tid ot;
398 __be32 rsvd0;
399 u8 rsvd1;
400 u8 cmd;
401 u8 rsvd2[6];
402};
403
404struct cpl_peer_close {
405 union opcode_tid ot;
406 __be32 rcv_nxt;
407};
408
409struct cpl_tid_release {
410 WR_HDR;
411 union opcode_tid ot;
412 __be32 rsvd;
413};
414
415struct cpl_tx_pkt_core {
416 __be32 ctrl0;
417#define TXPKT_VF(x) ((x) << 0)
418#define TXPKT_PF(x) ((x) << 8)
419#define TXPKT_VF_VLD (1 << 11)
420#define TXPKT_OVLAN_IDX(x) ((x) << 12)
421#define TXPKT_INTF(x) ((x) << 16)
422#define TXPKT_INS_OVLAN (1 << 21)
423#define TXPKT_OPCODE(x) ((x) << 24)
424 __be16 pack;
425 __be16 len;
426 __be64 ctrl1;
427#define TXPKT_CSUM_END(x) ((x) << 12)
428#define TXPKT_CSUM_START(x) ((x) << 20)
429#define TXPKT_IPHDR_LEN(x) ((u64)(x) << 20)
430#define TXPKT_CSUM_LOC(x) ((u64)(x) << 30)
431#define TXPKT_ETHHDR_LEN(x) ((u64)(x) << 34)
432#define TXPKT_CSUM_TYPE(x) ((u64)(x) << 40)
433#define TXPKT_VLAN(x) ((u64)(x) << 44)
434#define TXPKT_VLAN_VLD (1ULL << 60)
435#define TXPKT_IPCSUM_DIS (1ULL << 62)
436#define TXPKT_L4CSUM_DIS (1ULL << 63)
437};
438
439struct cpl_tx_pkt {
440 WR_HDR;
441 struct cpl_tx_pkt_core c;
442};
443
444#define cpl_tx_pkt_xt cpl_tx_pkt
445
446struct cpl_tx_pkt_lso {
447 WR_HDR;
448 __be32 lso_ctrl;
449#define LSO_TCPHDR_LEN(x) ((x) << 0)
450#define LSO_IPHDR_LEN(x) ((x) << 4)
451#define LSO_ETHHDR_LEN(x) ((x) << 16)
452#define LSO_IPV6(x) ((x) << 20)
453#define LSO_LAST_SLICE (1 << 22)
454#define LSO_FIRST_SLICE (1 << 23)
455#define LSO_OPCODE(x) ((x) << 24)
456 __be16 ipid_ofst;
457 __be16 mss;
458 __be32 seqno_offset;
459 __be32 len;
460 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
461};
462
463struct cpl_iscsi_hdr {
464 union opcode_tid ot;
465 __be16 pdu_len_ddp;
466#define ISCSI_PDU_LEN(x) ((x) & 0x7FFF)
467#define ISCSI_DDP (1 << 15)
468 __be16 len;
469 __be32 seq;
470 __be16 urg;
471 u8 rsvd;
472 u8 status;
473};
474
475struct cpl_rx_data {
476 union opcode_tid ot;
477 __be16 rsvd;
478 __be16 len;
479 __be32 seq;
480 __be16 urg;
481#if defined(__LITTLE_ENDIAN_BITFIELD)
482 u8 dack_mode:2;
483 u8 psh:1;
484 u8 heartbeat:1;
485 u8 ddp_off:1;
486 u8 :3;
487#else
488 u8 :3;
489 u8 ddp_off:1;
490 u8 heartbeat:1;
491 u8 psh:1;
492 u8 dack_mode:2;
493#endif
494 u8 status;
495};
496
497struct cpl_rx_data_ack {
498 WR_HDR;
499 union opcode_tid ot;
500 __be32 credit_dack;
501#define RX_CREDITS(x) ((x) << 0)
502#define RX_FORCE_ACK(x) ((x) << 28)
503};
504
505struct cpl_rx_pkt {
506 struct rss_header rsshdr;
507 u8 opcode;
508#if defined(__LITTLE_ENDIAN_BITFIELD)
509 u8 iff:4;
510 u8 csum_calc:1;
511 u8 ipmi_pkt:1;
512 u8 vlan_ex:1;
513 u8 ip_frag:1;
514#else
515 u8 ip_frag:1;
516 u8 vlan_ex:1;
517 u8 ipmi_pkt:1;
518 u8 csum_calc:1;
519 u8 iff:4;
520#endif
521 __be16 csum;
522 __be16 vlan;
523 __be16 len;
524 __be32 l2info;
525#define RXF_UDP (1 << 22)
526#define RXF_TCP (1 << 23)
527 __be16 hdr_len;
528 __be16 err_vec;
529};
530
531struct cpl_trace_pkt {
532 u8 opcode;
533 u8 intf;
534#if defined(__LITTLE_ENDIAN_BITFIELD)
535 u8 runt:4;
536 u8 filter_hit:4;
537 u8 :6;
538 u8 err:1;
539 u8 trunc:1;
540#else
541 u8 filter_hit:4;
542 u8 runt:4;
543 u8 trunc:1;
544 u8 err:1;
545 u8 :6;
546#endif
547 __be16 rsvd;
548 __be16 len;
549 __be64 tstamp;
550};
551
552struct cpl_l2t_write_req {
553 WR_HDR;
554 union opcode_tid ot;
555 __be16 params;
556#define L2T_W_INFO(x) ((x) << 2)
557#define L2T_W_PORT(x) ((x) << 8)
558#define L2T_W_NOREPLY(x) ((x) << 15)
559 __be16 l2t_idx;
560 __be16 vlan;
561 u8 dst_mac[6];
562};
563
564struct cpl_l2t_write_rpl {
565 union opcode_tid ot;
566 u8 status;
567 u8 rsvd[3];
568};
569
570struct cpl_rdma_terminate {
571 union opcode_tid ot;
572 __be16 rsvd;
573 __be16 len;
574};
575
576struct cpl_sge_egr_update {
577 __be32 opcode_qid;
578#define EGR_QID(x) ((x) & 0x1FFFF)
579 __be16 cidx;
580 __be16 pidx;
581};
582
583struct cpl_fw4_pld {
584 u8 opcode;
585 u8 rsvd0[3];
586 u8 type;
587 u8 rsvd1;
588 __be16 len;
589 __be64 data;
590 __be64 rsvd2;
591};
592
593struct cpl_fw6_pld {
594 u8 opcode;
595 u8 rsvd[5];
596 __be16 len;
597 __be64 data[4];
598};
599
600struct cpl_fw4_msg {
601 u8 opcode;
602 u8 type;
603 __be16 rsvd0;
604 __be32 rsvd1;
605 __be64 data[2];
606};
607
608struct cpl_fw4_ack {
609 union opcode_tid ot;
610 u8 credits;
611 u8 rsvd0[2];
612 u8 seq_vld;
613 __be32 snd_nxt;
614 __be32 snd_una;
615 __be64 rsvd1;
616};
617
618struct cpl_fw6_msg {
619 u8 opcode;
620 u8 type;
621 __be16 rsvd0;
622 __be32 rsvd1;
623 __be64 data[4];
624};
625
626enum {
627 ULP_TX_MEM_READ = 2,
628 ULP_TX_MEM_WRITE = 3,
629 ULP_TX_PKT = 4
630};
631
632enum {
633 ULP_TX_SC_NOOP = 0x80,
634 ULP_TX_SC_IMM = 0x81,
635 ULP_TX_SC_DSGL = 0x82,
636 ULP_TX_SC_ISGL = 0x83
637};
638
639struct ulptx_sge_pair {
640 __be32 len[2];
641 __be64 addr[2];
642};
643
644struct ulptx_sgl {
645 __be32 cmd_nsge;
646#define ULPTX_CMD(x) ((x) << 24)
647#define ULPTX_NSGE(x) ((x) << 0)
648 __be32 len0;
649 __be64 addr0;
650 struct ulptx_sge_pair sge[0];
651};
652
653struct ulp_mem_io {
654 WR_HDR;
655 __be32 cmd;
656#define ULP_MEMIO_ORDER(x) ((x) << 23)
657 __be32 len16; /* command length */
658 __be32 dlen; /* data length in 32-byte units */
659#define ULP_MEMIO_DATA_LEN(x) ((x) << 0)
660 __be32 lock_addr;
661#define ULP_MEMIO_ADDR(x) ((x) << 0)
662#define ULP_MEMIO_LOCK(x) ((x) << 31)
663};
664
665#endif /* __T4_MSG_H */
diff --git a/drivers/net/cxgb4/t4_regs.h b/drivers/net/cxgb4/t4_regs.h
new file mode 100644
index 000000000000..5ed56483cbc2
--- /dev/null
+++ b/drivers/net/cxgb4/t4_regs.h
@@ -0,0 +1,878 @@
1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __T4_REGS_H
36#define __T4_REGS_H
37
38#define MYPF_BASE 0x1b000
39#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
40
41#define PF0_BASE 0x1e000
42#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
43
44#define PF_STRIDE 0x400
45#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
46#define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
47
48#define MYPORT_BASE 0x1c000
49#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
50
51#define PORT0_BASE 0x20000
52#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
53
54#define PORT_STRIDE 0x2000
55#define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
56#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
57
58#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
59#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
60
61#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
62#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
63#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
64#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
65
66#define SGE_PF_KDOORBELL 0x0
67#define QID_MASK 0xffff8000U
68#define QID_SHIFT 15
69#define QID(x) ((x) << QID_SHIFT)
70#define DBPRIO 0x00004000U
71#define PIDX_MASK 0x00003fffU
72#define PIDX_SHIFT 0
73#define PIDX(x) ((x) << PIDX_SHIFT)
74
75#define SGE_PF_GTS 0x4
76#define INGRESSQID_MASK 0xffff0000U
77#define INGRESSQID_SHIFT 16
78#define INGRESSQID(x) ((x) << INGRESSQID_SHIFT)
79#define TIMERREG_MASK 0x0000e000U
80#define TIMERREG_SHIFT 13
81#define TIMERREG(x) ((x) << TIMERREG_SHIFT)
82#define SEINTARM_MASK 0x00001000U
83#define SEINTARM_SHIFT 12
84#define SEINTARM(x) ((x) << SEINTARM_SHIFT)
85#define CIDXINC_MASK 0x00000fffU
86#define CIDXINC_SHIFT 0
87#define CIDXINC(x) ((x) << CIDXINC_SHIFT)
88
89#define SGE_CONTROL 0x1008
90#define DCASYSTYPE 0x00080000U
91#define RXPKTCPLMODE 0x00040000U
92#define EGRSTATUSPAGESIZE 0x00020000U
93#define PKTSHIFT_MASK 0x00001c00U
94#define PKTSHIFT_SHIFT 10
95#define PKTSHIFT(x) ((x) << PKTSHIFT_SHIFT)
96#define INGPCIEBOUNDARY_MASK 0x00000380U
97#define INGPCIEBOUNDARY_SHIFT 7
98#define INGPCIEBOUNDARY(x) ((x) << INGPCIEBOUNDARY_SHIFT)
99#define INGPADBOUNDARY_MASK 0x00000070U
100#define INGPADBOUNDARY_SHIFT 4
101#define INGPADBOUNDARY(x) ((x) << INGPADBOUNDARY_SHIFT)
102#define EGRPCIEBOUNDARY_MASK 0x0000000eU
103#define EGRPCIEBOUNDARY_SHIFT 1
104#define EGRPCIEBOUNDARY(x) ((x) << EGRPCIEBOUNDARY_SHIFT)
105#define GLOBALENABLE 0x00000001U
106
107#define SGE_HOST_PAGE_SIZE 0x100c
108#define HOSTPAGESIZEPF0_MASK 0x0000000fU
109#define HOSTPAGESIZEPF0_SHIFT 0
110#define HOSTPAGESIZEPF0(x) ((x) << HOSTPAGESIZEPF0_SHIFT)
111
112#define SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
113#define QUEUESPERPAGEPF0_MASK 0x0000000fU
114#define QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK)
115
116#define SGE_INT_CAUSE1 0x1024
117#define SGE_INT_CAUSE2 0x1030
118#define SGE_INT_CAUSE3 0x103c
119#define ERR_FLM_DBP 0x80000000U
120#define ERR_FLM_IDMA1 0x40000000U
121#define ERR_FLM_IDMA0 0x20000000U
122#define ERR_FLM_HINT 0x10000000U
123#define ERR_PCIE_ERROR3 0x08000000U
124#define ERR_PCIE_ERROR2 0x04000000U
125#define ERR_PCIE_ERROR1 0x02000000U
126#define ERR_PCIE_ERROR0 0x01000000U
127#define ERR_TIMER_ABOVE_MAX_QID 0x00800000U
128#define ERR_CPL_EXCEED_IQE_SIZE 0x00400000U
129#define ERR_INVALID_CIDX_INC 0x00200000U
130#define ERR_ITP_TIME_PAUSED 0x00100000U
131#define ERR_CPL_OPCODE_0 0x00080000U
132#define ERR_DROPPED_DB 0x00040000U
133#define ERR_DATA_CPL_ON_HIGH_QID1 0x00020000U
134#define ERR_DATA_CPL_ON_HIGH_QID0 0x00010000U
135#define ERR_BAD_DB_PIDX3 0x00008000U
136#define ERR_BAD_DB_PIDX2 0x00004000U
137#define ERR_BAD_DB_PIDX1 0x00002000U
138#define ERR_BAD_DB_PIDX0 0x00001000U
139#define ERR_ING_PCIE_CHAN 0x00000800U
140#define ERR_ING_CTXT_PRIO 0x00000400U
141#define ERR_EGR_CTXT_PRIO 0x00000200U
142#define DBFIFO_HP_INT 0x00000100U
143#define DBFIFO_LP_INT 0x00000080U
144#define REG_ADDRESS_ERR 0x00000040U
145#define INGRESS_SIZE_ERR 0x00000020U
146#define EGRESS_SIZE_ERR 0x00000010U
147#define ERR_INV_CTXT3 0x00000008U
148#define ERR_INV_CTXT2 0x00000004U
149#define ERR_INV_CTXT1 0x00000002U
150#define ERR_INV_CTXT0 0x00000001U
151
152#define SGE_INT_ENABLE3 0x1040
153#define SGE_FL_BUFFER_SIZE0 0x1044
154#define SGE_FL_BUFFER_SIZE1 0x1048
155#define SGE_INGRESS_RX_THRESHOLD 0x10a0
156#define THRESHOLD_0_MASK 0x3f000000U
157#define THRESHOLD_0_SHIFT 24
158#define THRESHOLD_0(x) ((x) << THRESHOLD_0_SHIFT)
159#define THRESHOLD_0_GET(x) (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT)
160#define THRESHOLD_1_MASK 0x003f0000U
161#define THRESHOLD_1_SHIFT 16
162#define THRESHOLD_1(x) ((x) << THRESHOLD_1_SHIFT)
163#define THRESHOLD_1_GET(x) (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT)
164#define THRESHOLD_2_MASK 0x00003f00U
165#define THRESHOLD_2_SHIFT 8
166#define THRESHOLD_2(x) ((x) << THRESHOLD_2_SHIFT)
167#define THRESHOLD_2_GET(x) (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT)
168#define THRESHOLD_3_MASK 0x0000003fU
169#define THRESHOLD_3_SHIFT 0
170#define THRESHOLD_3(x) ((x) << THRESHOLD_3_SHIFT)
171#define THRESHOLD_3_GET(x) (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT)
172
173#define SGE_TIMER_VALUE_0_AND_1 0x10b8
174#define TIMERVALUE0_MASK 0xffff0000U
175#define TIMERVALUE0_SHIFT 16
176#define TIMERVALUE0(x) ((x) << TIMERVALUE0_SHIFT)
177#define TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT)
178#define TIMERVALUE1_MASK 0x0000ffffU
179#define TIMERVALUE1_SHIFT 0
180#define TIMERVALUE1(x) ((x) << TIMERVALUE1_SHIFT)
181#define TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT)
182
183#define SGE_TIMER_VALUE_2_AND_3 0x10bc
184#define SGE_TIMER_VALUE_4_AND_5 0x10c0
185#define SGE_DEBUG_INDEX 0x10cc
186#define SGE_DEBUG_DATA_HIGH 0x10d0
187#define SGE_DEBUG_DATA_LOW 0x10d4
188#define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
189
190#define PCIE_PF_CLI 0x44
191#define PCIE_INT_CAUSE 0x3004
192#define UNXSPLCPLERR 0x20000000U
193#define PCIEPINT 0x10000000U
194#define PCIESINT 0x08000000U
195#define RPLPERR 0x04000000U
196#define RXWRPERR 0x02000000U
197#define RXCPLPERR 0x01000000U
198#define PIOTAGPERR 0x00800000U
199#define MATAGPERR 0x00400000U
200#define INTXCLRPERR 0x00200000U
201#define FIDPERR 0x00100000U
202#define CFGSNPPERR 0x00080000U
203#define HRSPPERR 0x00040000U
204#define HREQPERR 0x00020000U
205#define HCNTPERR 0x00010000U
206#define DRSPPERR 0x00008000U
207#define DREQPERR 0x00004000U
208#define DCNTPERR 0x00002000U
209#define CRSPPERR 0x00001000U
210#define CREQPERR 0x00000800U
211#define CCNTPERR 0x00000400U
212#define TARTAGPERR 0x00000200U
213#define PIOREQPERR 0x00000100U
214#define PIOCPLPERR 0x00000080U
215#define MSIXDIPERR 0x00000040U
216#define MSIXDATAPERR 0x00000020U
217#define MSIXADDRHPERR 0x00000010U
218#define MSIXADDRLPERR 0x00000008U
219#define MSIDATAPERR 0x00000004U
220#define MSIADDRHPERR 0x00000002U
221#define MSIADDRLPERR 0x00000001U
222
223#define PCIE_NONFAT_ERR 0x3010
224#define PCIE_MEM_ACCESS_BASE_WIN 0x3068
225#define PCIEOFST_MASK 0xfffffc00U
226#define BIR_MASK 0x00000300U
227#define BIR_SHIFT 8
228#define BIR(x) ((x) << BIR_SHIFT)
229#define WINDOW_MASK 0x000000ffU
230#define WINDOW_SHIFT 0
231#define WINDOW(x) ((x) << WINDOW_SHIFT)
232
233#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
234#define RNPP 0x80000000U
235#define RPCP 0x20000000U
236#define RCIP 0x08000000U
237#define RCCP 0x04000000U
238#define RFTP 0x00800000U
239#define PTRP 0x00100000U
240
241#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
242#define TPCP 0x40000000U
243#define TNPP 0x20000000U
244#define TFTP 0x10000000U
245#define TCAP 0x08000000U
246#define TCIP 0x04000000U
247#define RCAP 0x02000000U
248#define PLUP 0x00800000U
249#define PLDN 0x00400000U
250#define OTDD 0x00200000U
251#define GTRP 0x00100000U
252#define RDPE 0x00040000U
253#define TDCE 0x00020000U
254#define TDUE 0x00010000U
255
256#define MC_INT_CAUSE 0x7518
257#define ECC_UE_INT_CAUSE 0x00000004U
258#define ECC_CE_INT_CAUSE 0x00000002U
259#define PERR_INT_CAUSE 0x00000001U
260
261#define MC_ECC_STATUS 0x751c
262#define ECC_CECNT_MASK 0xffff0000U
263#define ECC_CECNT_SHIFT 16
264#define ECC_CECNT(x) ((x) << ECC_CECNT_SHIFT)
265#define ECC_CECNT_GET(x) (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT)
266#define ECC_UECNT_MASK 0x0000ffffU
267#define ECC_UECNT_SHIFT 0
268#define ECC_UECNT(x) ((x) << ECC_UECNT_SHIFT)
269#define ECC_UECNT_GET(x) (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT)
270
271#define MC_BIST_CMD 0x7600
272#define START_BIST 0x80000000U
273#define BIST_CMD_GAP_MASK 0x0000ff00U
274#define BIST_CMD_GAP_SHIFT 8
275#define BIST_CMD_GAP(x) ((x) << BIST_CMD_GAP_SHIFT)
276#define BIST_OPCODE_MASK 0x00000003U
277#define BIST_OPCODE_SHIFT 0
278#define BIST_OPCODE(x) ((x) << BIST_OPCODE_SHIFT)
279
280#define MC_BIST_CMD_ADDR 0x7604
281#define MC_BIST_CMD_LEN 0x7608
282#define MC_BIST_DATA_PATTERN 0x760c
283#define BIST_DATA_TYPE_MASK 0x0000000fU
284#define BIST_DATA_TYPE_SHIFT 0
285#define BIST_DATA_TYPE(x) ((x) << BIST_DATA_TYPE_SHIFT)
286
287#define MC_BIST_STATUS_RDATA 0x7688
288
289#define MA_EXT_MEMORY_BAR 0x77c8
290#define EXT_MEM_SIZE_MASK 0x00000fffU
291#define EXT_MEM_SIZE_SHIFT 0
292#define EXT_MEM_SIZE_GET(x) (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT)
293
294#define MA_TARGET_MEM_ENABLE 0x77d8
295#define EXT_MEM_ENABLE 0x00000004U
296#define EDRAM1_ENABLE 0x00000002U
297#define EDRAM0_ENABLE 0x00000001U
298
299#define MA_INT_CAUSE 0x77e0
300#define MEM_PERR_INT_CAUSE 0x00000002U
301#define MEM_WRAP_INT_CAUSE 0x00000001U
302
303#define MA_INT_WRAP_STATUS 0x77e4
304#define MEM_WRAP_ADDRESS_MASK 0xfffffff0U
305#define MEM_WRAP_ADDRESS_SHIFT 4
306#define MEM_WRAP_ADDRESS_GET(x) (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT)
307#define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU
308#define MEM_WRAP_CLIENT_NUM_SHIFT 0
309#define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT)
310
311#define MA_PARITY_ERROR_STATUS 0x77f4
312
313#define EDC_0_BASE_ADDR 0x7900
314
315#define EDC_BIST_CMD 0x7904
316#define EDC_BIST_CMD_ADDR 0x7908
317#define EDC_BIST_CMD_LEN 0x790c
318#define EDC_BIST_DATA_PATTERN 0x7910
319#define EDC_BIST_STATUS_RDATA 0x7928
320#define EDC_INT_CAUSE 0x7978
321#define ECC_UE_PAR 0x00000020U
322#define ECC_CE_PAR 0x00000010U
323#define PERR_PAR_CAUSE 0x00000008U
324
325#define EDC_ECC_STATUS 0x797c
326
327#define EDC_1_BASE_ADDR 0x7980
328
329#define CIM_PF_MAILBOX_DATA 0x240
330#define CIM_PF_MAILBOX_CTRL 0x280
331#define MBMSGVALID 0x00000008U
332#define MBINTREQ 0x00000004U
333#define MBOWNER_MASK 0x00000003U
334#define MBOWNER_SHIFT 0
335#define MBOWNER(x) ((x) << MBOWNER_SHIFT)
336#define MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT)
337
338#define CIM_PF_HOST_INT_CAUSE 0x28c
339#define MBMSGRDYINT 0x00080000U
340
341#define CIM_HOST_INT_CAUSE 0x7b2c
342#define TIEQOUTPARERRINT 0x00100000U
343#define TIEQINPARERRINT 0x00080000U
344#define MBHOSTPARERR 0x00040000U
345#define MBUPPARERR 0x00020000U
346#define IBQPARERR 0x0001f800U
347#define IBQTP0PARERR 0x00010000U
348#define IBQTP1PARERR 0x00008000U
349#define IBQULPPARERR 0x00004000U
350#define IBQSGELOPARERR 0x00002000U
351#define IBQSGEHIPARERR 0x00001000U
352#define IBQNCSIPARERR 0x00000800U
353#define OBQPARERR 0x000007e0U
354#define OBQULP0PARERR 0x00000400U
355#define OBQULP1PARERR 0x00000200U
356#define OBQULP2PARERR 0x00000100U
357#define OBQULP3PARERR 0x00000080U
358#define OBQSGEPARERR 0x00000040U
359#define OBQNCSIPARERR 0x00000020U
360#define PREFDROPINT 0x00000002U
361#define UPACCNONZERO 0x00000001U
362
363#define CIM_HOST_UPACC_INT_CAUSE 0x7b34
364#define EEPROMWRINT 0x40000000U
365#define TIMEOUTMAINT 0x20000000U
366#define TIMEOUTINT 0x10000000U
367#define RSPOVRLOOKUPINT 0x08000000U
368#define REQOVRLOOKUPINT 0x04000000U
369#define BLKWRPLINT 0x02000000U
370#define BLKRDPLINT 0x01000000U
371#define SGLWRPLINT 0x00800000U
372#define SGLRDPLINT 0x00400000U
373#define BLKWRCTLINT 0x00200000U
374#define BLKRDCTLINT 0x00100000U
375#define SGLWRCTLINT 0x00080000U
376#define SGLRDCTLINT 0x00040000U
377#define BLKWREEPROMINT 0x00020000U
378#define BLKRDEEPROMINT 0x00010000U
379#define SGLWREEPROMINT 0x00008000U
380#define SGLRDEEPROMINT 0x00004000U
381#define BLKWRFLASHINT 0x00002000U
382#define BLKRDFLASHINT 0x00001000U
383#define SGLWRFLASHINT 0x00000800U
384#define SGLRDFLASHINT 0x00000400U
385#define BLKWRBOOTINT 0x00000200U
386#define BLKRDBOOTINT 0x00000100U
387#define SGLWRBOOTINT 0x00000080U
388#define SGLRDBOOTINT 0x00000040U
389#define ILLWRBEINT 0x00000020U
390#define ILLRDBEINT 0x00000010U
391#define ILLRDINT 0x00000008U
392#define ILLWRINT 0x00000004U
393#define ILLTRANSINT 0x00000002U
394#define RSVDSPACEINT 0x00000001U
395
396#define TP_OUT_CONFIG 0x7d04
397#define VLANEXTENABLE_MASK 0x0000f000U
398#define VLANEXTENABLE_SHIFT 12
399
400#define TP_PARA_REG2 0x7d68
401#define MAXRXDATA_MASK 0xffff0000U
402#define MAXRXDATA_SHIFT 16
403#define MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT)
404
405#define TP_TIMER_RESOLUTION 0x7d90
406#define TIMERRESOLUTION_MASK 0x00ff0000U
407#define TIMERRESOLUTION_SHIFT 16
408#define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT)
409
410#define TP_SHIFT_CNT 0x7dc0
411
412#define TP_CCTRL_TABLE 0x7ddc
413#define TP_MTU_TABLE 0x7de4
414#define MTUINDEX_MASK 0xff000000U
415#define MTUINDEX_SHIFT 24
416#define MTUINDEX(x) ((x) << MTUINDEX_SHIFT)
417#define MTUWIDTH_MASK 0x000f0000U
418#define MTUWIDTH_SHIFT 16
419#define MTUWIDTH(x) ((x) << MTUWIDTH_SHIFT)
420#define MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT)
421#define MTUVALUE_MASK 0x00003fffU
422#define MTUVALUE_SHIFT 0
423#define MTUVALUE(x) ((x) << MTUVALUE_SHIFT)
424#define MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT)
425
426#define TP_RSS_LKP_TABLE 0x7dec
427#define LKPTBLROWVLD 0x80000000U
428#define LKPTBLQUEUE1_MASK 0x000ffc00U
429#define LKPTBLQUEUE1_SHIFT 10
430#define LKPTBLQUEUE1(x) ((x) << LKPTBLQUEUE1_SHIFT)
431#define LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT)
432#define LKPTBLQUEUE0_MASK 0x000003ffU
433#define LKPTBLQUEUE0_SHIFT 0
434#define LKPTBLQUEUE0(x) ((x) << LKPTBLQUEUE0_SHIFT)
435#define LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT)
436
437#define TP_PIO_ADDR 0x7e40
438#define TP_PIO_DATA 0x7e44
439#define TP_MIB_INDEX 0x7e50
440#define TP_MIB_DATA 0x7e54
441#define TP_INT_CAUSE 0x7e74
442#define FLMTXFLSTEMPTY 0x40000000U
443
444#define TP_INGRESS_CONFIG 0x141
445#define VNIC 0x00000800U
446#define CSUM_HAS_PSEUDO_HDR 0x00000400U
447#define RM_OVLAN 0x00000200U
448#define LOOKUPEVERYPKT 0x00000100U
449
450#define TP_MIB_MAC_IN_ERR_0 0x0
451#define TP_MIB_TCP_OUT_RST 0xc
452#define TP_MIB_TCP_IN_SEG_HI 0x10
453#define TP_MIB_TCP_IN_SEG_LO 0x11
454#define TP_MIB_TCP_OUT_SEG_HI 0x12
455#define TP_MIB_TCP_OUT_SEG_LO 0x13
456#define TP_MIB_TCP_RXT_SEG_HI 0x14
457#define TP_MIB_TCP_RXT_SEG_LO 0x15
458#define TP_MIB_TNL_CNG_DROP_0 0x18
459#define TP_MIB_TCP_V6IN_ERR_0 0x28
460#define TP_MIB_TCP_V6OUT_RST 0x2c
461#define TP_MIB_OFD_ARP_DROP 0x36
462#define TP_MIB_TNL_DROP_0 0x44
463#define TP_MIB_OFD_VLN_DROP_0 0x58
464
465#define ULP_TX_INT_CAUSE 0x8dcc
466#define PBL_BOUND_ERR_CH3 0x80000000U
467#define PBL_BOUND_ERR_CH2 0x40000000U
468#define PBL_BOUND_ERR_CH1 0x20000000U
469#define PBL_BOUND_ERR_CH0 0x10000000U
470
471#define PM_RX_INT_CAUSE 0x8fdc
472#define ZERO_E_CMD_ERROR 0x00400000U
473#define PMRX_FRAMING_ERROR 0x003ffff0U
474#define OCSPI_PAR_ERROR 0x00000008U
475#define DB_OPTIONS_PAR_ERROR 0x00000004U
476#define IESPI_PAR_ERROR 0x00000002U
477#define E_PCMD_PAR_ERROR 0x00000001U
478
479#define PM_TX_INT_CAUSE 0x8ffc
480#define PCMD_LEN_OVFL0 0x80000000U
481#define PCMD_LEN_OVFL1 0x40000000U
482#define PCMD_LEN_OVFL2 0x20000000U
483#define ZERO_C_CMD_ERROR 0x10000000U
484#define PMTX_FRAMING_ERROR 0x0ffffff0U
485#define OESPI_PAR_ERROR 0x00000008U
486#define ICSPI_PAR_ERROR 0x00000002U
487#define C_PCMD_PAR_ERROR 0x00000001U
488
489#define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
490#define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
491#define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
492#define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
493#define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
494#define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
495#define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
496#define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
497#define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
498#define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
499#define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
500#define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
501#define MPS_PORT_STAT_TX_PORT_64B_L 0x430
502#define MPS_PORT_STAT_TX_PORT_64B_H 0x434
503#define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
504#define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
505#define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
506#define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
507#define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
508#define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
509#define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
510#define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
511#define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
512#define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
513#define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
514#define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
515#define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
516#define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
517#define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
518#define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
519#define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
520#define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
521#define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
522#define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
523#define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
524#define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
525#define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
526#define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
527#define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
528#define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
529#define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
530#define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
531#define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
532#define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
533#define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
534#define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
535#define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
536#define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
537#define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
538#define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
539#define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
540#define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
541#define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
542#define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
543#define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
544#define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
545#define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
546#define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
547#define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
548#define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
549#define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
550#define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
551#define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
552#define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
553#define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
554#define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
555#define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
556#define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
557#define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
558#define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
559#define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
560#define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
561#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
562#define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
563#define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
564#define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
565#define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
566#define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
567#define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
568#define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
569#define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
570#define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
571#define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
572#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
573#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
574#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
575#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
576#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
577#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
578#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
579#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
580#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
581#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
582#define MPS_PORT_STAT_RX_PORT_64B_L 0x590
583#define MPS_PORT_STAT_RX_PORT_64B_H 0x594
584#define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
585#define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
586#define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
587#define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
588#define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
589#define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
590#define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
591#define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
592#define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
593#define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
594#define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
595#define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
596#define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
597#define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
598#define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
599#define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
600#define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
601#define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
602#define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
603#define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
604#define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
605#define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
606#define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
607#define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
608#define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
609#define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
610#define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
611#define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
612#define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
613#define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
614#define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
615#define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
616#define MPS_CMN_CTL 0x9000
617#define NUMPORTS_MASK 0x00000003U
618#define NUMPORTS_SHIFT 0
619#define NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT)
620
621#define MPS_INT_CAUSE 0x9008
622#define STATINT 0x00000020U
623#define TXINT 0x00000010U
624#define RXINT 0x00000008U
625#define TRCINT 0x00000004U
626#define CLSINT 0x00000002U
627#define PLINT 0x00000001U
628
629#define MPS_TX_INT_CAUSE 0x9408
630#define PORTERR 0x00010000U
631#define FRMERR 0x00008000U
632#define SECNTERR 0x00004000U
633#define BUBBLE 0x00002000U
634#define TXDESCFIFO 0x00001e00U
635#define TXDATAFIFO 0x000001e0U
636#define NCSIFIFO 0x00000010U
637#define TPFIFO 0x0000000fU
638
639#define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
640#define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
641#define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
642
643#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
644#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
645#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
646#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
647#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
648#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
649#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
650#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
651#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
652#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
653#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
654#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
655#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
656#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
657#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
658#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
659#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
660#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
661#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
662#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
663#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
664#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
665#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
666#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
667#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
668#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
669#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
670#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
671#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
672#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
673#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
674#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
675#define MPS_TRC_CFG 0x9800
676#define TRCFIFOEMPTY 0x00000010U
677#define TRCIGNOREDROPINPUT 0x00000008U
678#define TRCKEEPDUPLICATES 0x00000004U
679#define TRCEN 0x00000002U
680#define TRCMULTIFILTER 0x00000001U
681
682#define MPS_TRC_RSS_CONTROL 0x9808
683#define RSSCONTROL_MASK 0x00ff0000U
684#define RSSCONTROL_SHIFT 16
685#define RSSCONTROL(x) ((x) << RSSCONTROL_SHIFT)
686#define QUEUENUMBER_MASK 0x0000ffffU
687#define QUEUENUMBER_SHIFT 0
688#define QUEUENUMBER(x) ((x) << QUEUENUMBER_SHIFT)
689
690#define MPS_TRC_FILTER_MATCH_CTL_A 0x9810
691#define TFINVERTMATCH 0x01000000U
692#define TFPKTTOOLARGE 0x00800000U
693#define TFEN 0x00400000U
694#define TFPORT_MASK 0x003c0000U
695#define TFPORT_SHIFT 18
696#define TFPORT(x) ((x) << TFPORT_SHIFT)
697#define TFPORT_GET(x) (((x) & TFPORT_MASK) >> TFPORT_SHIFT)
698#define TFDROP 0x00020000U
699#define TFSOPEOPERR 0x00010000U
700#define TFLENGTH_MASK 0x00001f00U
701#define TFLENGTH_SHIFT 8
702#define TFLENGTH(x) ((x) << TFLENGTH_SHIFT)
703#define TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT)
704#define TFOFFSET_MASK 0x0000001fU
705#define TFOFFSET_SHIFT 0
706#define TFOFFSET(x) ((x) << TFOFFSET_SHIFT)
707#define TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT)
708
709#define MPS_TRC_FILTER_MATCH_CTL_B 0x9820
710#define TFMINPKTSIZE_MASK 0x01ff0000U
711#define TFMINPKTSIZE_SHIFT 16
712#define TFMINPKTSIZE(x) ((x) << TFMINPKTSIZE_SHIFT)
713#define TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT)
714#define TFCAPTUREMAX_MASK 0x00003fffU
715#define TFCAPTUREMAX_SHIFT 0
716#define TFCAPTUREMAX(x) ((x) << TFCAPTUREMAX_SHIFT)
717#define TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT)
718
719#define MPS_TRC_INT_CAUSE 0x985c
720#define MISCPERR 0x00000100U
721#define PKTFIFO 0x000000f0U
722#define FILTMEM 0x0000000fU
723
724#define MPS_TRC_FILTER0_MATCH 0x9c00
725#define MPS_TRC_FILTER0_DONT_CARE 0x9c80
726#define MPS_TRC_FILTER1_MATCH 0x9d00
727#define MPS_CLS_INT_CAUSE 0xd028
728#define PLERRENB 0x00000008U
729#define HASHSRAM 0x00000004U
730#define MATCHTCAM 0x00000002U
731#define MATCHSRAM 0x00000001U
732
733#define MPS_RX_PERR_INT_CAUSE 0x11074
734
735#define CPL_INTR_CAUSE 0x19054
736#define CIM_OP_MAP_PERR 0x00000020U
737#define CIM_OVFL_ERROR 0x00000010U
738#define TP_FRAMING_ERROR 0x00000008U
739#define SGE_FRAMING_ERROR 0x00000004U
740#define CIM_FRAMING_ERROR 0x00000002U
741#define ZERO_SWITCH_ERROR 0x00000001U
742
743#define SMB_INT_CAUSE 0x19090
744#define MSTTXFIFOPARINT 0x00200000U
745#define MSTRXFIFOPARINT 0x00100000U
746#define SLVFIFOPARINT 0x00080000U
747
748#define ULP_RX_INT_CAUSE 0x19158
749#define ULP_RX_ISCSI_TAGMASK 0x19164
750#define ULP_RX_ISCSI_PSZ 0x19168
751#define HPZ3_MASK 0x0f000000U
752#define HPZ3_SHIFT 24
753#define HPZ3(x) ((x) << HPZ3_SHIFT)
754#define HPZ2_MASK 0x000f0000U
755#define HPZ2_SHIFT 16
756#define HPZ2(x) ((x) << HPZ2_SHIFT)
757#define HPZ1_MASK 0x00000f00U
758#define HPZ1_SHIFT 8
759#define HPZ1(x) ((x) << HPZ1_SHIFT)
760#define HPZ0_MASK 0x0000000fU
761#define HPZ0_SHIFT 0
762#define HPZ0(x) ((x) << HPZ0_SHIFT)
763
764#define ULP_RX_TDDP_PSZ 0x19178
765
766#define SF_DATA 0x193f8
767#define SF_OP 0x193fc
768#define BUSY 0x80000000U
769#define SF_LOCK 0x00000010U
770#define SF_CONT 0x00000008U
771#define BYTECNT_MASK 0x00000006U
772#define BYTECNT_SHIFT 1
773#define BYTECNT(x) ((x) << BYTECNT_SHIFT)
774#define OP_WR 0x00000001U
775
776#define PL_PF_INT_CAUSE 0x3c0
777#define PFSW 0x00000008U
778#define PFSGE 0x00000004U
779#define PFCIM 0x00000002U
780#define PFMPS 0x00000001U
781
782#define PL_PF_INT_ENABLE 0x3c4
783#define PL_PF_CTL 0x3c8
784#define SWINT 0x00000001U
785
786#define PL_WHOAMI 0x19400
787#define SOURCEPF_MASK 0x00000700U
788#define SOURCEPF_SHIFT 8
789#define SOURCEPF(x) ((x) << SOURCEPF_SHIFT)
790#define SOURCEPF_GET(x) (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT)
791#define ISVF 0x00000080U
792#define VFID_MASK 0x0000007fU
793#define VFID_SHIFT 0
794#define VFID(x) ((x) << VFID_SHIFT)
795#define VFID_GET(x) (((x) & VFID_MASK) >> VFID_SHIFT)
796
797#define PL_INT_CAUSE 0x1940c
798#define ULP_TX 0x08000000U
799#define SGE 0x04000000U
800#define HMA 0x02000000U
801#define CPL_SWITCH 0x01000000U
802#define ULP_RX 0x00800000U
803#define PM_RX 0x00400000U
804#define PM_TX 0x00200000U
805#define MA 0x00100000U
806#define TP 0x00080000U
807#define LE 0x00040000U
808#define EDC1 0x00020000U
809#define EDC0 0x00010000U
810#define MC 0x00008000U
811#define PCIE 0x00004000U
812#define PMU 0x00002000U
813#define XGMAC_KR1 0x00001000U
814#define XGMAC_KR0 0x00000800U
815#define XGMAC1 0x00000400U
816#define XGMAC0 0x00000200U
817#define SMB 0x00000100U
818#define SF 0x00000080U
819#define PL 0x00000040U
820#define NCSI 0x00000020U
821#define MPS 0x00000010U
822#define MI 0x00000008U
823#define DBG 0x00000004U
824#define I2CM 0x00000002U
825#define CIM 0x00000001U
826
827#define PL_INT_MAP0 0x19414
828#define PL_RST 0x19428
829#define PIORST 0x00000002U
830#define PIORSTMODE 0x00000001U
831
832#define PL_PL_INT_CAUSE 0x19430
833#define FATALPERR 0x00000010U
834#define PERRVFID 0x00000001U
835
836#define PL_REV 0x1943c
837
838#define LE_DB_CONFIG 0x19c04
839#define HASHEN 0x00100000U
840
841#define LE_DB_SERVER_INDEX 0x19c18
842#define LE_DB_ACT_CNT_IPV4 0x19c20
843#define LE_DB_ACT_CNT_IPV6 0x19c24
844
845#define LE_DB_INT_CAUSE 0x19c3c
846#define REQQPARERR 0x00010000U
847#define UNKNOWNCMD 0x00008000U
848#define PARITYERR 0x00000040U
849#define LIPMISS 0x00000020U
850#define LIP0 0x00000010U
851
852#define LE_DB_TID_HASHBASE 0x19df8
853
854#define NCSI_INT_CAUSE 0x1a0d8
855#define CIM_DM_PRTY_ERR 0x00000100U
856#define MPS_DM_PRTY_ERR 0x00000080U
857#define TXFIFO_PRTY_ERR 0x00000002U
858#define RXFIFO_PRTY_ERR 0x00000001U
859
860#define XGMAC_PORT_CFG2 0x1018
861#define PATEN 0x00040000U
862#define MAGICEN 0x00020000U
863
864#define XGMAC_PORT_MAGIC_MACID_LO 0x1024
865#define XGMAC_PORT_MAGIC_MACID_HI 0x1028
866
867#define XGMAC_PORT_EPIO_DATA0 0x10c0
868#define XGMAC_PORT_EPIO_DATA1 0x10c4
869#define XGMAC_PORT_EPIO_DATA2 0x10c8
870#define XGMAC_PORT_EPIO_DATA3 0x10cc
871#define XGMAC_PORT_EPIO_OP 0x10d0
872#define EPIOWR 0x00000100U
873#define ADDRESS_MASK 0x000000ffU
874#define ADDRESS_SHIFT 0
875#define ADDRESS(x) ((x) << ADDRESS_SHIFT)
876
877#define XGMAC_PORT_INT_CAUSE 0x10dc
878#endif /* __T4_REGS_H */
diff --git a/drivers/net/cxgb4/t4fw_api.h b/drivers/net/cxgb4/t4fw_api.h
new file mode 100644
index 000000000000..3393d05a388a
--- /dev/null
+++ b/drivers/net/cxgb4/t4fw_api.h
@@ -0,0 +1,1580 @@
1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef _T4FW_INTERFACE_H_
36#define _T4FW_INTERFACE_H_
37
38#define FW_T4VF_SGE_BASE_ADDR 0x0000
39#define FW_T4VF_MPS_BASE_ADDR 0x0100
40#define FW_T4VF_PL_BASE_ADDR 0x0200
41#define FW_T4VF_MBDATA_BASE_ADDR 0x0240
42#define FW_T4VF_CIM_BASE_ADDR 0x0300
43
44enum fw_wr_opcodes {
45 FW_FILTER_WR = 0x02,
46 FW_ULPTX_WR = 0x04,
47 FW_TP_WR = 0x05,
48 FW_ETH_TX_PKT_WR = 0x08,
49 FW_FLOWC_WR = 0x0a,
50 FW_OFLD_TX_DATA_WR = 0x0b,
51 FW_CMD_WR = 0x10,
52 FW_ETH_TX_PKT_VM_WR = 0x11,
53 FW_RI_RES_WR = 0x0c,
54 FW_RI_INIT_WR = 0x0d,
55 FW_RI_RDMA_WRITE_WR = 0x14,
56 FW_RI_SEND_WR = 0x15,
57 FW_RI_RDMA_READ_WR = 0x16,
58 FW_RI_RECV_WR = 0x17,
59 FW_RI_BIND_MW_WR = 0x18,
60 FW_RI_FR_NSMR_WR = 0x19,
61 FW_RI_INV_LSTAG_WR = 0x1a,
62 FW_LASTC2E_WR = 0x40
63};
64
65struct fw_wr_hdr {
66 __be32 hi;
67 __be32 lo;
68};
69
70#define FW_WR_OP(x) ((x) << 24)
71#define FW_WR_ATOMIC(x) ((x) << 23)
72#define FW_WR_FLUSH(x) ((x) << 22)
73#define FW_WR_COMPL(x) ((x) << 21)
74#define FW_WR_IMMDLEN(x) ((x) << 0)
75
76#define FW_WR_EQUIQ (1U << 31)
77#define FW_WR_EQUEQ (1U << 30)
78#define FW_WR_FLOWID(x) ((x) << 8)
79#define FW_WR_LEN16(x) ((x) << 0)
80
81struct fw_ulptx_wr {
82 __be32 op_to_compl;
83 __be32 flowid_len16;
84 u64 cookie;
85};
86
87struct fw_tp_wr {
88 __be32 op_to_immdlen;
89 __be32 flowid_len16;
90 u64 cookie;
91};
92
93struct fw_eth_tx_pkt_wr {
94 __be32 op_immdlen;
95 __be32 equiq_to_len16;
96 __be64 r3;
97};
98
99enum fw_flowc_mnem {
100 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */
101 FW_FLOWC_MNEM_CH,
102 FW_FLOWC_MNEM_PORT,
103 FW_FLOWC_MNEM_IQID,
104 FW_FLOWC_MNEM_SNDNXT,
105 FW_FLOWC_MNEM_RCVNXT,
106 FW_FLOWC_MNEM_SNDBUF,
107 FW_FLOWC_MNEM_MSS,
108};
109
110struct fw_flowc_mnemval {
111 u8 mnemonic;
112 u8 r4[3];
113 __be32 val;
114};
115
116struct fw_flowc_wr {
117 __be32 op_to_nparams;
118#define FW_FLOWC_WR_NPARAMS(x) ((x) << 0)
119 __be32 flowid_len16;
120 struct fw_flowc_mnemval mnemval[0];
121};
122
123struct fw_ofld_tx_data_wr {
124 __be32 op_to_immdlen;
125 __be32 flowid_len16;
126 __be32 plen;
127 __be32 tunnel_to_proxy;
128#define FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << 19)
129#define FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << 18)
130#define FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << 17)
131#define FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << 16)
132#define FW_OFLD_TX_DATA_WR_MORE(x) ((x) << 15)
133#define FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << 14)
134#define FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << 10)
135#define FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) ((x) << 6)
136};
137
138struct fw_cmd_wr {
139 __be32 op_dma;
140#define FW_CMD_WR_DMA (1U << 17)
141 __be32 len16_pkd;
142 __be64 cookie_daddr;
143};
144
145struct fw_eth_tx_pkt_vm_wr {
146 __be32 op_immdlen;
147 __be32 equiq_to_len16;
148 __be32 r3[2];
149 u8 ethmacdst[6];
150 u8 ethmacsrc[6];
151 __be16 ethtype;
152 __be16 vlantci;
153};
154
155#define FW_CMD_MAX_TIMEOUT 3000
156
157enum fw_cmd_opcodes {
158 FW_LDST_CMD = 0x01,
159 FW_RESET_CMD = 0x03,
160 FW_HELLO_CMD = 0x04,
161 FW_BYE_CMD = 0x05,
162 FW_INITIALIZE_CMD = 0x06,
163 FW_CAPS_CONFIG_CMD = 0x07,
164 FW_PARAMS_CMD = 0x08,
165 FW_PFVF_CMD = 0x09,
166 FW_IQ_CMD = 0x10,
167 FW_EQ_MNGT_CMD = 0x11,
168 FW_EQ_ETH_CMD = 0x12,
169 FW_EQ_CTRL_CMD = 0x13,
170 FW_EQ_OFLD_CMD = 0x21,
171 FW_VI_CMD = 0x14,
172 FW_VI_MAC_CMD = 0x15,
173 FW_VI_RXMODE_CMD = 0x16,
174 FW_VI_ENABLE_CMD = 0x17,
175 FW_ACL_MAC_CMD = 0x18,
176 FW_ACL_VLAN_CMD = 0x19,
177 FW_VI_STATS_CMD = 0x1a,
178 FW_PORT_CMD = 0x1b,
179 FW_PORT_STATS_CMD = 0x1c,
180 FW_PORT_LB_STATS_CMD = 0x1d,
181 FW_PORT_TRACE_CMD = 0x1e,
182 FW_PORT_TRACE_MMAP_CMD = 0x1f,
183 FW_RSS_IND_TBL_CMD = 0x20,
184 FW_RSS_GLB_CONFIG_CMD = 0x22,
185 FW_RSS_VI_CONFIG_CMD = 0x23,
186 FW_LASTC2E_CMD = 0x40,
187 FW_ERROR_CMD = 0x80,
188 FW_DEBUG_CMD = 0x81,
189};
190
191enum fw_cmd_cap {
192 FW_CMD_CAP_PF = 0x01,
193 FW_CMD_CAP_DMAQ = 0x02,
194 FW_CMD_CAP_PORT = 0x04,
195 FW_CMD_CAP_PORTPROMISC = 0x08,
196 FW_CMD_CAP_PORTSTATS = 0x10,
197 FW_CMD_CAP_VF = 0x80,
198};
199
200/*
201 * Generic command header flit0
202 */
203struct fw_cmd_hdr {
204 __be32 hi;
205 __be32 lo;
206};
207
208#define FW_CMD_OP(x) ((x) << 24)
209#define FW_CMD_OP_GET(x) (((x) >> 24) & 0xff)
210#define FW_CMD_REQUEST (1U << 23)
211#define FW_CMD_READ (1U << 22)
212#define FW_CMD_WRITE (1U << 21)
213#define FW_CMD_EXEC (1U << 20)
214#define FW_CMD_RAMASK(x) ((x) << 20)
215#define FW_CMD_RETVAL(x) ((x) << 8)
216#define FW_CMD_RETVAL_GET(x) (((x) >> 8) & 0xff)
217#define FW_CMD_LEN16(x) ((x) << 0)
218
219enum fw_ldst_addrspc {
220 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
221 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
222 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
223 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
224 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
225 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
226 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
227 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
228 FW_LDST_ADDRSPC_MDIO = 0x0018,
229 FW_LDST_ADDRSPC_MPS = 0x0020,
230 FW_LDST_ADDRSPC_FUNC = 0x0028
231};
232
233enum fw_ldst_mps_fid {
234 FW_LDST_MPS_ATRB,
235 FW_LDST_MPS_RPLC
236};
237
238enum fw_ldst_func_access_ctl {
239 FW_LDST_FUNC_ACC_CTL_VIID,
240 FW_LDST_FUNC_ACC_CTL_FID
241};
242
243enum fw_ldst_func_mod_index {
244 FW_LDST_FUNC_MPS
245};
246
247struct fw_ldst_cmd {
248 __be32 op_to_addrspace;
249#define FW_LDST_CMD_ADDRSPACE(x) ((x) << 0)
250 __be32 cycles_to_len16;
251 union fw_ldst {
252 struct fw_ldst_addrval {
253 __be32 addr;
254 __be32 val;
255 } addrval;
256 struct fw_ldst_idctxt {
257 __be32 physid;
258 __be32 msg_pkd;
259 __be32 ctxt_data7;
260 __be32 ctxt_data6;
261 __be32 ctxt_data5;
262 __be32 ctxt_data4;
263 __be32 ctxt_data3;
264 __be32 ctxt_data2;
265 __be32 ctxt_data1;
266 __be32 ctxt_data0;
267 } idctxt;
268 struct fw_ldst_mdio {
269 __be16 paddr_mmd;
270 __be16 raddr;
271 __be16 vctl;
272 __be16 rval;
273 } mdio;
274 struct fw_ldst_mps {
275 __be16 fid_ctl;
276 __be16 rplcpf_pkd;
277 __be32 rplc127_96;
278 __be32 rplc95_64;
279 __be32 rplc63_32;
280 __be32 rplc31_0;
281 __be32 atrb;
282 __be16 vlan[16];
283 } mps;
284 struct fw_ldst_func {
285 u8 access_ctl;
286 u8 mod_index;
287 __be16 ctl_id;
288 __be32 offset;
289 __be64 data0;
290 __be64 data1;
291 } func;
292 } u;
293};
294
295#define FW_LDST_CMD_MSG(x) ((x) << 31)
296#define FW_LDST_CMD_PADDR(x) ((x) << 8)
297#define FW_LDST_CMD_MMD(x) ((x) << 0)
298#define FW_LDST_CMD_FID(x) ((x) << 15)
299#define FW_LDST_CMD_CTL(x) ((x) << 0)
300#define FW_LDST_CMD_RPLCPF(x) ((x) << 0)
301
302struct fw_reset_cmd {
303 __be32 op_to_write;
304 __be32 retval_len16;
305 __be32 val;
306 __be32 r3;
307};
308
309struct fw_hello_cmd {
310 __be32 op_to_write;
311 __be32 retval_len16;
312 __be32 err_to_mbasyncnot;
313#define FW_HELLO_CMD_ERR (1U << 31)
314#define FW_HELLO_CMD_INIT (1U << 30)
315#define FW_HELLO_CMD_MASTERDIS(x) ((x) << 29)
316#define FW_HELLO_CMD_MASTERFORCE(x) ((x) << 28)
317#define FW_HELLO_CMD_MBMASTER(x) ((x) << 24)
318#define FW_HELLO_CMD_MBASYNCNOT(x) ((x) << 20)
319 __be32 fwrev;
320};
321
322struct fw_bye_cmd {
323 __be32 op_to_write;
324 __be32 retval_len16;
325 __be64 r3;
326};
327
328struct fw_initialize_cmd {
329 __be32 op_to_write;
330 __be32 retval_len16;
331 __be64 r3;
332};
333
334enum fw_caps_config_hm {
335 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
336 FW_CAPS_CONFIG_HM_PL = 0x00000002,
337 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
338 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
339 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
340 FW_CAPS_CONFIG_HM_TP = 0x00000020,
341 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
342 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
343 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
344 FW_CAPS_CONFIG_HM_MC = 0x00000200,
345 FW_CAPS_CONFIG_HM_LE = 0x00000400,
346 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
347 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
348 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
349 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
350 FW_CAPS_CONFIG_HM_MI = 0x00008000,
351 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
352 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
353 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
354 FW_CAPS_CONFIG_HM_MA = 0x00080000,
355 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
356 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
357 FW_CAPS_CONFIG_HM_UART = 0x00400000,
358 FW_CAPS_CONFIG_HM_SF = 0x00800000,
359};
360
361enum fw_caps_config_nbm {
362 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
363 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
364};
365
366enum fw_caps_config_link {
367 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
368 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
369 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
370};
371
372enum fw_caps_config_switch {
373 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
374 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
375};
376
377enum fw_caps_config_nic {
378 FW_CAPS_CONFIG_NIC = 0x00000001,
379 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
380};
381
382enum fw_caps_config_ofld {
383 FW_CAPS_CONFIG_OFLD = 0x00000001,
384};
385
386enum fw_caps_config_rdma {
387 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
388 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
389};
390
391enum fw_caps_config_iscsi {
392 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
393 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
394 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
395 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
396};
397
398enum fw_caps_config_fcoe {
399 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
400 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
401};
402
403struct fw_caps_config_cmd {
404 __be32 op_to_write;
405 __be32 retval_len16;
406 __be32 r2;
407 __be32 hwmbitmap;
408 __be16 nbmcaps;
409 __be16 linkcaps;
410 __be16 switchcaps;
411 __be16 r3;
412 __be16 niccaps;
413 __be16 ofldcaps;
414 __be16 rdmacaps;
415 __be16 r4;
416 __be16 iscsicaps;
417 __be16 fcoecaps;
418 __be32 r5;
419 __be64 r6;
420};
421
422/*
423 * params command mnemonics
424 */
425enum fw_params_mnem {
426 FW_PARAMS_MNEM_DEV = 1, /* device params */
427 FW_PARAMS_MNEM_PFVF = 2, /* function params */
428 FW_PARAMS_MNEM_REG = 3, /* limited register access */
429 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
430 FW_PARAMS_MNEM_LAST
431};
432
433/*
434 * device parameters
435 */
436enum fw_params_param_dev {
437 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
438 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
439 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
440 * allocated by the device's
441 * Lookup Engine
442 */
443 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
444 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04,
445 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
446 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
447 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07,
448 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
449 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
450 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A
451};
452
453/*
454 * physical and virtual function parameters
455 */
456enum fw_params_param_pfvf {
457 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
458 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
459 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
460 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
461 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
462 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
463 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
464 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
465 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
466 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
467 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
468 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
469 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
470 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
471 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
472 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
473 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
474 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
475 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
476 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
477 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
478 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
479};
480
481/*
482 * dma queue parameters
483 */
484enum fw_params_param_dmaq {
485 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
486 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
487 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
488 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
489 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
490};
491
492#define FW_PARAMS_MNEM(x) ((x) << 24)
493#define FW_PARAMS_PARAM_X(x) ((x) << 16)
494#define FW_PARAMS_PARAM_Y(x) ((x) << 8)
495#define FW_PARAMS_PARAM_Z(x) ((x) << 0)
496#define FW_PARAMS_PARAM_XYZ(x) ((x) << 0)
497#define FW_PARAMS_PARAM_YZ(x) ((x) << 0)
498
499struct fw_params_cmd {
500 __be32 op_to_vfn;
501 __be32 retval_len16;
502 struct fw_params_param {
503 __be32 mnem;
504 __be32 val;
505 } param[7];
506};
507
508#define FW_PARAMS_CMD_PFN(x) ((x) << 8)
509#define FW_PARAMS_CMD_VFN(x) ((x) << 0)
510
511struct fw_pfvf_cmd {
512 __be32 op_to_vfn;
513 __be32 retval_len16;
514 __be32 niqflint_niq;
515 __be32 cmask_to_neq;
516 __be32 tc_to_nexactf;
517 __be32 r_caps_to_nethctrl;
518 __be16 nricq;
519 __be16 nriqp;
520 __be32 r4;
521};
522
523#define FW_PFVF_CMD_PFN(x) ((x) << 8)
524#define FW_PFVF_CMD_VFN(x) ((x) << 0)
525
526#define FW_PFVF_CMD_NIQFLINT(x) ((x) << 20)
527#define FW_PFVF_CMD_NIQFLINT_GET(x) (((x) >> 20) & 0xfff)
528
529#define FW_PFVF_CMD_NIQ(x) ((x) << 0)
530#define FW_PFVF_CMD_NIQ_GET(x) (((x) >> 0) & 0xfffff)
531
532#define FW_PFVF_CMD_CMASK(x) ((x) << 24)
533#define FW_PFVF_CMD_CMASK_GET(x) (((x) >> 24) & 0xf)
534
535#define FW_PFVF_CMD_PMASK(x) ((x) << 20)
536#define FW_PFVF_CMD_PMASK_GET(x) (((x) >> 20) & 0xf)
537
538#define FW_PFVF_CMD_NEQ(x) ((x) << 0)
539#define FW_PFVF_CMD_NEQ_GET(x) (((x) >> 0) & 0xfffff)
540
541#define FW_PFVF_CMD_TC(x) ((x) << 24)
542#define FW_PFVF_CMD_TC_GET(x) (((x) >> 24) & 0xff)
543
544#define FW_PFVF_CMD_NVI(x) ((x) << 16)
545#define FW_PFVF_CMD_NVI_GET(x) (((x) >> 16) & 0xff)
546
547#define FW_PFVF_CMD_NEXACTF(x) ((x) << 0)
548#define FW_PFVF_CMD_NEXACTF_GET(x) (((x) >> 0) & 0xffff)
549
550#define FW_PFVF_CMD_R_CAPS(x) ((x) << 24)
551#define FW_PFVF_CMD_R_CAPS_GET(x) (((x) >> 24) & 0xff)
552
553#define FW_PFVF_CMD_WX_CAPS(x) ((x) << 16)
554#define FW_PFVF_CMD_WX_CAPS_GET(x) (((x) >> 16) & 0xff)
555
556#define FW_PFVF_CMD_NETHCTRL(x) ((x) << 0)
557#define FW_PFVF_CMD_NETHCTRL_GET(x) (((x) >> 0) & 0xffff)
558
559enum fw_iq_type {
560 FW_IQ_TYPE_FL_INT_CAP,
561 FW_IQ_TYPE_NO_FL_INT_CAP
562};
563
564struct fw_iq_cmd {
565 __be32 op_to_vfn;
566 __be32 alloc_to_len16;
567 __be16 physiqid;
568 __be16 iqid;
569 __be16 fl0id;
570 __be16 fl1id;
571 __be32 type_to_iqandstindex;
572 __be16 iqdroprss_to_iqesize;
573 __be16 iqsize;
574 __be64 iqaddr;
575 __be32 iqns_to_fl0congen;
576 __be16 fl0dcaen_to_fl0cidxfthresh;
577 __be16 fl0size;
578 __be64 fl0addr;
579 __be32 fl1cngchmap_to_fl1congen;
580 __be16 fl1dcaen_to_fl1cidxfthresh;
581 __be16 fl1size;
582 __be64 fl1addr;
583};
584
585#define FW_IQ_CMD_PFN(x) ((x) << 8)
586#define FW_IQ_CMD_VFN(x) ((x) << 0)
587
588#define FW_IQ_CMD_ALLOC (1U << 31)
589#define FW_IQ_CMD_FREE (1U << 30)
590#define FW_IQ_CMD_MODIFY (1U << 29)
591#define FW_IQ_CMD_IQSTART(x) ((x) << 28)
592#define FW_IQ_CMD_IQSTOP(x) ((x) << 27)
593
594#define FW_IQ_CMD_TYPE(x) ((x) << 29)
595#define FW_IQ_CMD_IQASYNCH(x) ((x) << 28)
596#define FW_IQ_CMD_VIID(x) ((x) << 16)
597#define FW_IQ_CMD_IQANDST(x) ((x) << 15)
598#define FW_IQ_CMD_IQANUS(x) ((x) << 14)
599#define FW_IQ_CMD_IQANUD(x) ((x) << 12)
600#define FW_IQ_CMD_IQANDSTINDEX(x) ((x) << 0)
601
602#define FW_IQ_CMD_IQDROPRSS (1U << 15)
603#define FW_IQ_CMD_IQGTSMODE (1U << 14)
604#define FW_IQ_CMD_IQPCIECH(x) ((x) << 12)
605#define FW_IQ_CMD_IQDCAEN(x) ((x) << 11)
606#define FW_IQ_CMD_IQDCACPU(x) ((x) << 6)
607#define FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << 4)
608#define FW_IQ_CMD_IQO (1U << 3)
609#define FW_IQ_CMD_IQCPRIO(x) ((x) << 2)
610#define FW_IQ_CMD_IQESIZE(x) ((x) << 0)
611
612#define FW_IQ_CMD_IQNS(x) ((x) << 31)
613#define FW_IQ_CMD_IQRO(x) ((x) << 30)
614#define FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << 28)
615#define FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << 27)
616#define FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << 26)
617#define FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << 20)
618#define FW_IQ_CMD_FL0CACHELOCK(x) ((x) << 15)
619#define FW_IQ_CMD_FL0DBP(x) ((x) << 14)
620#define FW_IQ_CMD_FL0DATANS(x) ((x) << 13)
621#define FW_IQ_CMD_FL0DATARO(x) ((x) << 12)
622#define FW_IQ_CMD_FL0CONGCIF(x) ((x) << 11)
623#define FW_IQ_CMD_FL0ONCHIP(x) ((x) << 10)
624#define FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << 9)
625#define FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << 8)
626#define FW_IQ_CMD_FL0FETCHNS(x) ((x) << 7)
627#define FW_IQ_CMD_FL0FETCHRO(x) ((x) << 6)
628#define FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << 4)
629#define FW_IQ_CMD_FL0CPRIO(x) ((x) << 3)
630#define FW_IQ_CMD_FL0PADEN (1U << 2)
631#define FW_IQ_CMD_FL0PACKEN (1U << 1)
632#define FW_IQ_CMD_FL0CONGEN (1U << 0)
633
634#define FW_IQ_CMD_FL0DCAEN(x) ((x) << 15)
635#define FW_IQ_CMD_FL0DCACPU(x) ((x) << 10)
636#define FW_IQ_CMD_FL0FBMIN(x) ((x) << 7)
637#define FW_IQ_CMD_FL0FBMAX(x) ((x) << 4)
638#define FW_IQ_CMD_FL0CIDXFTHRESHO (1U << 3)
639#define FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << 0)
640
641#define FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << 20)
642#define FW_IQ_CMD_FL1CACHELOCK(x) ((x) << 15)
643#define FW_IQ_CMD_FL1DBP(x) ((x) << 14)
644#define FW_IQ_CMD_FL1DATANS(x) ((x) << 13)
645#define FW_IQ_CMD_FL1DATARO(x) ((x) << 12)
646#define FW_IQ_CMD_FL1CONGCIF(x) ((x) << 11)
647#define FW_IQ_CMD_FL1ONCHIP(x) ((x) << 10)
648#define FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << 9)
649#define FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << 8)
650#define FW_IQ_CMD_FL1FETCHNS(x) ((x) << 7)
651#define FW_IQ_CMD_FL1FETCHRO(x) ((x) << 6)
652#define FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << 4)
653#define FW_IQ_CMD_FL1CPRIO(x) ((x) << 3)
654#define FW_IQ_CMD_FL1PADEN (1U << 2)
655#define FW_IQ_CMD_FL1PACKEN (1U << 1)
656#define FW_IQ_CMD_FL1CONGEN (1U << 0)
657
658#define FW_IQ_CMD_FL1DCAEN(x) ((x) << 15)
659#define FW_IQ_CMD_FL1DCACPU(x) ((x) << 10)
660#define FW_IQ_CMD_FL1FBMIN(x) ((x) << 7)
661#define FW_IQ_CMD_FL1FBMAX(x) ((x) << 4)
662#define FW_IQ_CMD_FL1CIDXFTHRESHO (1U << 3)
663#define FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << 0)
664
665struct fw_eq_eth_cmd {
666 __be32 op_to_vfn;
667 __be32 alloc_to_len16;
668 __be32 eqid_pkd;
669 __be32 physeqid_pkd;
670 __be32 fetchszm_to_iqid;
671 __be32 dcaen_to_eqsize;
672 __be64 eqaddr;
673 __be32 viid_pkd;
674 __be32 r8_lo;
675 __be64 r9;
676};
677
678#define FW_EQ_ETH_CMD_PFN(x) ((x) << 8)
679#define FW_EQ_ETH_CMD_VFN(x) ((x) << 0)
680#define FW_EQ_ETH_CMD_ALLOC (1U << 31)
681#define FW_EQ_ETH_CMD_FREE (1U << 30)
682#define FW_EQ_ETH_CMD_MODIFY (1U << 29)
683#define FW_EQ_ETH_CMD_EQSTART (1U << 28)
684#define FW_EQ_ETH_CMD_EQSTOP (1U << 27)
685
686#define FW_EQ_ETH_CMD_EQID(x) ((x) << 0)
687#define FW_EQ_ETH_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
688#define FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << 0)
689
690#define FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << 26)
691#define FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << 25)
692#define FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << 24)
693#define FW_EQ_ETH_CMD_FETCHNS(x) ((x) << 23)
694#define FW_EQ_ETH_CMD_FETCHRO(x) ((x) << 22)
695#define FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << 20)
696#define FW_EQ_ETH_CMD_CPRIO(x) ((x) << 19)
697#define FW_EQ_ETH_CMD_ONCHIP(x) ((x) << 18)
698#define FW_EQ_ETH_CMD_PCIECHN(x) ((x) << 16)
699#define FW_EQ_ETH_CMD_IQID(x) ((x) << 0)
700
701#define FW_EQ_ETH_CMD_DCAEN(x) ((x) << 31)
702#define FW_EQ_ETH_CMD_DCACPU(x) ((x) << 26)
703#define FW_EQ_ETH_CMD_FBMIN(x) ((x) << 23)
704#define FW_EQ_ETH_CMD_FBMAX(x) ((x) << 20)
705#define FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << 19)
706#define FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << 16)
707#define FW_EQ_ETH_CMD_EQSIZE(x) ((x) << 0)
708
709#define FW_EQ_ETH_CMD_VIID(x) ((x) << 16)
710
711struct fw_eq_ctrl_cmd {
712 __be32 op_to_vfn;
713 __be32 alloc_to_len16;
714 __be32 cmpliqid_eqid;
715 __be32 physeqid_pkd;
716 __be32 fetchszm_to_iqid;
717 __be32 dcaen_to_eqsize;
718 __be64 eqaddr;
719};
720
721#define FW_EQ_CTRL_CMD_PFN(x) ((x) << 8)
722#define FW_EQ_CTRL_CMD_VFN(x) ((x) << 0)
723
724#define FW_EQ_CTRL_CMD_ALLOC (1U << 31)
725#define FW_EQ_CTRL_CMD_FREE (1U << 30)
726#define FW_EQ_CTRL_CMD_MODIFY (1U << 29)
727#define FW_EQ_CTRL_CMD_EQSTART (1U << 28)
728#define FW_EQ_CTRL_CMD_EQSTOP (1U << 27)
729
730#define FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << 20)
731#define FW_EQ_CTRL_CMD_EQID(x) ((x) << 0)
732#define FW_EQ_CTRL_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
733#define FW_EQ_CTRL_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
734
735#define FW_EQ_CTRL_CMD_FETCHSZM (1U << 26)
736#define FW_EQ_CTRL_CMD_STATUSPGNS (1U << 25)
737#define FW_EQ_CTRL_CMD_STATUSPGRO (1U << 24)
738#define FW_EQ_CTRL_CMD_FETCHNS (1U << 23)
739#define FW_EQ_CTRL_CMD_FETCHRO (1U << 22)
740#define FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << 20)
741#define FW_EQ_CTRL_CMD_CPRIO(x) ((x) << 19)
742#define FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << 18)
743#define FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << 16)
744#define FW_EQ_CTRL_CMD_IQID(x) ((x) << 0)
745
746#define FW_EQ_CTRL_CMD_DCAEN(x) ((x) << 31)
747#define FW_EQ_CTRL_CMD_DCACPU(x) ((x) << 26)
748#define FW_EQ_CTRL_CMD_FBMIN(x) ((x) << 23)
749#define FW_EQ_CTRL_CMD_FBMAX(x) ((x) << 20)
750#define FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) ((x) << 19)
751#define FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << 16)
752#define FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << 0)
753
754struct fw_eq_ofld_cmd {
755 __be32 op_to_vfn;
756 __be32 alloc_to_len16;
757 __be32 eqid_pkd;
758 __be32 physeqid_pkd;
759 __be32 fetchszm_to_iqid;
760 __be32 dcaen_to_eqsize;
761 __be64 eqaddr;
762};
763
764#define FW_EQ_OFLD_CMD_PFN(x) ((x) << 8)
765#define FW_EQ_OFLD_CMD_VFN(x) ((x) << 0)
766
767#define FW_EQ_OFLD_CMD_ALLOC (1U << 31)
768#define FW_EQ_OFLD_CMD_FREE (1U << 30)
769#define FW_EQ_OFLD_CMD_MODIFY (1U << 29)
770#define FW_EQ_OFLD_CMD_EQSTART (1U << 28)
771#define FW_EQ_OFLD_CMD_EQSTOP (1U << 27)
772
773#define FW_EQ_OFLD_CMD_EQID(x) ((x) << 0)
774#define FW_EQ_OFLD_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
775#define FW_EQ_OFLD_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
776
777#define FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << 26)
778#define FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << 25)
779#define FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << 24)
780#define FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << 23)
781#define FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << 22)
782#define FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << 20)
783#define FW_EQ_OFLD_CMD_CPRIO(x) ((x) << 19)
784#define FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << 18)
785#define FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << 16)
786#define FW_EQ_OFLD_CMD_IQID(x) ((x) << 0)
787
788#define FW_EQ_OFLD_CMD_DCAEN(x) ((x) << 31)
789#define FW_EQ_OFLD_CMD_DCACPU(x) ((x) << 26)
790#define FW_EQ_OFLD_CMD_FBMIN(x) ((x) << 23)
791#define FW_EQ_OFLD_CMD_FBMAX(x) ((x) << 20)
792#define FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) ((x) << 19)
793#define FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << 16)
794#define FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << 0)
795
796/*
797 * Macros for VIID parsing:
798 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
799 */
800#define FW_VIID_PFN_GET(x) (((x) >> 8) & 0x7)
801#define FW_VIID_VIVLD_GET(x) (((x) >> 7) & 0x1)
802#define FW_VIID_VIN_GET(x) (((x) >> 0) & 0x7F)
803
804struct fw_vi_cmd {
805 __be32 op_to_vfn;
806 __be32 alloc_to_len16;
807 __be16 viid_pkd;
808 u8 mac[6];
809 u8 portid_pkd;
810 u8 nmac;
811 u8 nmac0[6];
812 __be16 rsssize_pkd;
813 u8 nmac1[6];
814 __be16 r7;
815 u8 nmac2[6];
816 __be16 r8;
817 u8 nmac3[6];
818 __be64 r9;
819 __be64 r10;
820};
821
822#define FW_VI_CMD_PFN(x) ((x) << 8)
823#define FW_VI_CMD_VFN(x) ((x) << 0)
824#define FW_VI_CMD_ALLOC (1U << 31)
825#define FW_VI_CMD_FREE (1U << 30)
826#define FW_VI_CMD_VIID(x) ((x) << 0)
827#define FW_VI_CMD_PORTID(x) ((x) << 4)
828#define FW_VI_CMD_RSSSIZE_GET(x) (((x) >> 0) & 0x7ff)
829
830/* Special VI_MAC command index ids */
831#define FW_VI_MAC_ADD_MAC 0x3FF
832#define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
833#define FW_VI_MAC_MAC_BASED_FREE 0x3FD
834
835enum fw_vi_mac_smac {
836 FW_VI_MAC_MPS_TCAM_ENTRY,
837 FW_VI_MAC_MPS_TCAM_ONLY,
838 FW_VI_MAC_SMT_ONLY,
839 FW_VI_MAC_SMT_AND_MPSTCAM
840};
841
842enum fw_vi_mac_result {
843 FW_VI_MAC_R_SUCCESS,
844 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
845 FW_VI_MAC_R_SMAC_FAIL,
846 FW_VI_MAC_R_F_ACL_CHECK
847};
848
849struct fw_vi_mac_cmd {
850 __be32 op_to_viid;
851 __be32 freemacs_to_len16;
852 union fw_vi_mac {
853 struct fw_vi_mac_exact {
854 __be16 valid_to_idx;
855 u8 macaddr[6];
856 } exact[7];
857 struct fw_vi_mac_hash {
858 __be64 hashvec;
859 } hash;
860 } u;
861};
862
863#define FW_VI_MAC_CMD_VIID(x) ((x) << 0)
864#define FW_VI_MAC_CMD_FREEMACS(x) ((x) << 31)
865#define FW_VI_MAC_CMD_HASHVECEN (1U << 23)
866#define FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << 22)
867#define FW_VI_MAC_CMD_VALID (1U << 15)
868#define FW_VI_MAC_CMD_PRIO(x) ((x) << 12)
869#define FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << 10)
870#define FW_VI_MAC_CMD_SMAC_RESULT_GET(x) (((x) >> 10) & 0x3)
871#define FW_VI_MAC_CMD_IDX(x) ((x) << 0)
872#define FW_VI_MAC_CMD_IDX_GET(x) (((x) >> 0) & 0x3ff)
873
874#define FW_RXMODE_MTU_NO_CHG 65535
875
876struct fw_vi_rxmode_cmd {
877 __be32 op_to_viid;
878 __be32 retval_len16;
879 __be32 mtu_to_broadcasten;
880 __be32 r4_lo;
881};
882
883#define FW_VI_RXMODE_CMD_VIID(x) ((x) << 0)
884#define FW_VI_RXMODE_CMD_MTU(x) ((x) << 16)
885#define FW_VI_RXMODE_CMD_PROMISCEN_MASK 0x3
886#define FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << 14)
887#define FW_VI_RXMODE_CMD_ALLMULTIEN_MASK 0x3
888#define FW_VI_RXMODE_CMD_ALLMULTIEN(x) ((x) << 12)
889#define FW_VI_RXMODE_CMD_BROADCASTEN_MASK 0x3
890#define FW_VI_RXMODE_CMD_BROADCASTEN(x) ((x) << 10)
891
892struct fw_vi_enable_cmd {
893 __be32 op_to_viid;
894 __be32 ien_to_len16;
895 __be16 blinkdur;
896 __be16 r3;
897 __be32 r4;
898};
899
900#define FW_VI_ENABLE_CMD_VIID(x) ((x) << 0)
901#define FW_VI_ENABLE_CMD_IEN(x) ((x) << 31)
902#define FW_VI_ENABLE_CMD_EEN(x) ((x) << 30)
903#define FW_VI_ENABLE_CMD_LED (1U << 29)
904
905/* VI VF stats offset definitions */
906#define VI_VF_NUM_STATS 16
907enum fw_vi_stats_vf_index {
908 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
909 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
910 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
911 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
912 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
913 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
914 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
915 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
916 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
917 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
918 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
919 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
920 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
921 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
922 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
923 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
924};
925
926/* VI PF stats offset definitions */
927#define VI_PF_NUM_STATS 17
928enum fw_vi_stats_pf_index {
929 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
930 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
931 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
932 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
933 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
934 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
935 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
936 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
937 FW_VI_PF_STAT_RX_BYTES_IX,
938 FW_VI_PF_STAT_RX_FRAMES_IX,
939 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
940 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
941 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
942 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
943 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
944 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
945 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
946};
947
948struct fw_vi_stats_cmd {
949 __be32 op_to_viid;
950 __be32 retval_len16;
951 union fw_vi_stats {
952 struct fw_vi_stats_ctl {
953 __be16 nstats_ix;
954 __be16 r6;
955 __be32 r7;
956 __be64 stat0;
957 __be64 stat1;
958 __be64 stat2;
959 __be64 stat3;
960 __be64 stat4;
961 __be64 stat5;
962 } ctl;
963 struct fw_vi_stats_pf {
964 __be64 tx_bcast_bytes;
965 __be64 tx_bcast_frames;
966 __be64 tx_mcast_bytes;
967 __be64 tx_mcast_frames;
968 __be64 tx_ucast_bytes;
969 __be64 tx_ucast_frames;
970 __be64 tx_offload_bytes;
971 __be64 tx_offload_frames;
972 __be64 rx_pf_bytes;
973 __be64 rx_pf_frames;
974 __be64 rx_bcast_bytes;
975 __be64 rx_bcast_frames;
976 __be64 rx_mcast_bytes;
977 __be64 rx_mcast_frames;
978 __be64 rx_ucast_bytes;
979 __be64 rx_ucast_frames;
980 __be64 rx_err_frames;
981 } pf;
982 struct fw_vi_stats_vf {
983 __be64 tx_bcast_bytes;
984 __be64 tx_bcast_frames;
985 __be64 tx_mcast_bytes;
986 __be64 tx_mcast_frames;
987 __be64 tx_ucast_bytes;
988 __be64 tx_ucast_frames;
989 __be64 tx_drop_frames;
990 __be64 tx_offload_bytes;
991 __be64 tx_offload_frames;
992 __be64 rx_bcast_bytes;
993 __be64 rx_bcast_frames;
994 __be64 rx_mcast_bytes;
995 __be64 rx_mcast_frames;
996 __be64 rx_ucast_bytes;
997 __be64 rx_ucast_frames;
998 __be64 rx_err_frames;
999 } vf;
1000 } u;
1001};
1002
1003#define FW_VI_STATS_CMD_VIID(x) ((x) << 0)
1004#define FW_VI_STATS_CMD_NSTATS(x) ((x) << 12)
1005#define FW_VI_STATS_CMD_IX(x) ((x) << 0)
1006
1007struct fw_acl_mac_cmd {
1008 __be32 op_to_vfn;
1009 __be32 en_to_len16;
1010 u8 nmac;
1011 u8 r3[7];
1012 __be16 r4;
1013 u8 macaddr0[6];
1014 __be16 r5;
1015 u8 macaddr1[6];
1016 __be16 r6;
1017 u8 macaddr2[6];
1018 __be16 r7;
1019 u8 macaddr3[6];
1020};
1021
1022#define FW_ACL_MAC_CMD_PFN(x) ((x) << 8)
1023#define FW_ACL_MAC_CMD_VFN(x) ((x) << 0)
1024#define FW_ACL_MAC_CMD_EN(x) ((x) << 31)
1025
1026struct fw_acl_vlan_cmd {
1027 __be32 op_to_vfn;
1028 __be32 en_to_len16;
1029 u8 nvlan;
1030 u8 dropnovlan_fm;
1031 u8 r3_lo[6];
1032 __be16 vlanid[16];
1033};
1034
1035#define FW_ACL_VLAN_CMD_PFN(x) ((x) << 8)
1036#define FW_ACL_VLAN_CMD_VFN(x) ((x) << 0)
1037#define FW_ACL_VLAN_CMD_EN(x) ((x) << 31)
1038#define FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << 7)
1039#define FW_ACL_VLAN_CMD_FM(x) ((x) << 6)
1040
1041enum fw_port_cap {
1042 FW_PORT_CAP_SPEED_100M = 0x0001,
1043 FW_PORT_CAP_SPEED_1G = 0x0002,
1044 FW_PORT_CAP_SPEED_2_5G = 0x0004,
1045 FW_PORT_CAP_SPEED_10G = 0x0008,
1046 FW_PORT_CAP_SPEED_40G = 0x0010,
1047 FW_PORT_CAP_SPEED_100G = 0x0020,
1048 FW_PORT_CAP_FC_RX = 0x0040,
1049 FW_PORT_CAP_FC_TX = 0x0080,
1050 FW_PORT_CAP_ANEG = 0x0100,
1051 FW_PORT_CAP_MDI_0 = 0x0200,
1052 FW_PORT_CAP_MDI_1 = 0x0400,
1053 FW_PORT_CAP_BEAN = 0x0800,
1054 FW_PORT_CAP_PMA_LPBK = 0x1000,
1055 FW_PORT_CAP_PCS_LPBK = 0x2000,
1056 FW_PORT_CAP_PHYXS_LPBK = 0x4000,
1057 FW_PORT_CAP_FAR_END_LPBK = 0x8000,
1058};
1059
1060enum fw_port_mdi {
1061 FW_PORT_MDI_UNCHANGED,
1062 FW_PORT_MDI_AUTO,
1063 FW_PORT_MDI_F_STRAIGHT,
1064 FW_PORT_MDI_F_CROSSOVER
1065};
1066
1067#define FW_PORT_MDI(x) ((x) << 9)
1068
1069enum fw_port_action {
1070 FW_PORT_ACTION_L1_CFG = 0x0001,
1071 FW_PORT_ACTION_L2_CFG = 0x0002,
1072 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1073 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
1074 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
1075 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
1076 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
1077 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
1078 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
1079 FW_PORT_ACTION_L1_LPBK = 0x0021,
1080 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022,
1081 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023,
1082 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
1083 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
1084 FW_PORT_ACTION_PHY_RESET = 0x0040,
1085 FW_PORT_ACTION_PMA_RESET = 0x0041,
1086 FW_PORT_ACTION_PCS_RESET = 0x0042,
1087 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
1088 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
1089 FW_PORT_ACTION_AN_RESET = 0x0045
1090};
1091
1092enum fw_port_l2cfg_ctlbf {
1093 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
1094 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
1095 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
1096 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
1097 FW_PORT_L2_CTLBF_IVLAN = 0x10,
1098 FW_PORT_L2_CTLBF_TXIPG = 0x20
1099};
1100
1101enum fw_port_dcb_cfg {
1102 FW_PORT_DCB_CFG_PG = 0x01,
1103 FW_PORT_DCB_CFG_PFC = 0x02,
1104 FW_PORT_DCB_CFG_APPL = 0x04
1105};
1106
1107enum fw_port_dcb_cfg_rc {
1108 FW_PORT_DCB_CFG_SUCCESS = 0x0,
1109 FW_PORT_DCB_CFG_ERROR = 0x1
1110};
1111
1112struct fw_port_cmd {
1113 __be32 op_to_portid;
1114 __be32 action_to_len16;
1115 union fw_port {
1116 struct fw_port_l1cfg {
1117 __be32 rcap;
1118 __be32 r;
1119 } l1cfg;
1120 struct fw_port_l2cfg {
1121 __be16 ctlbf_to_ivlan0;
1122 __be16 ivlantype;
1123 __be32 txipg_pkd;
1124 __be16 ovlan0mask;
1125 __be16 ovlan0type;
1126 __be16 ovlan1mask;
1127 __be16 ovlan1type;
1128 __be16 ovlan2mask;
1129 __be16 ovlan2type;
1130 __be16 ovlan3mask;
1131 __be16 ovlan3type;
1132 } l2cfg;
1133 struct fw_port_info {
1134 __be32 lstatus_to_modtype;
1135 __be16 pcap;
1136 __be16 acap;
1137 } info;
1138 struct fw_port_ppp {
1139 __be32 pppen_to_ncsich;
1140 __be32 r11;
1141 } ppp;
1142 struct fw_port_dcb {
1143 __be16 cfg;
1144 u8 up_map;
1145 u8 sf_cfgrc;
1146 __be16 prot_ix;
1147 u8 pe7_to_pe0;
1148 u8 numTCPFCs;
1149 __be32 pgid0_to_pgid7;
1150 __be32 numTCs_oui;
1151 u8 pgpc[8];
1152 } dcb;
1153 } u;
1154};
1155
1156#define FW_PORT_CMD_READ (1U << 22)
1157
1158#define FW_PORT_CMD_PORTID(x) ((x) << 0)
1159#define FW_PORT_CMD_PORTID_GET(x) (((x) >> 0) & 0xf)
1160
1161#define FW_PORT_CMD_ACTION(x) ((x) << 16)
1162
1163#define FW_PORT_CMD_CTLBF(x) ((x) << 10)
1164#define FW_PORT_CMD_OVLAN3(x) ((x) << 7)
1165#define FW_PORT_CMD_OVLAN2(x) ((x) << 6)
1166#define FW_PORT_CMD_OVLAN1(x) ((x) << 5)
1167#define FW_PORT_CMD_OVLAN0(x) ((x) << 4)
1168#define FW_PORT_CMD_IVLAN0(x) ((x) << 3)
1169
1170#define FW_PORT_CMD_TXIPG(x) ((x) << 19)
1171
1172#define FW_PORT_CMD_LSTATUS (1U << 31)
1173#define FW_PORT_CMD_LSPEED(x) ((x) << 24)
1174#define FW_PORT_CMD_LSPEED_GET(x) (((x) >> 24) & 0x3f)
1175#define FW_PORT_CMD_TXPAUSE (1U << 23)
1176#define FW_PORT_CMD_RXPAUSE (1U << 22)
1177#define FW_PORT_CMD_MDIOCAP (1U << 21)
1178#define FW_PORT_CMD_MDIOADDR_GET(x) (((x) >> 16) & 0x1f)
1179#define FW_PORT_CMD_LPTXPAUSE (1U << 15)
1180#define FW_PORT_CMD_LPRXPAUSE (1U << 14)
1181#define FW_PORT_CMD_PTYPE_MASK 0x1f
1182#define FW_PORT_CMD_PTYPE_GET(x) (((x) >> 8) & FW_PORT_CMD_PTYPE_MASK)
1183#define FW_PORT_CMD_MODTYPE_MASK 0x1f
1184#define FW_PORT_CMD_MODTYPE_GET(x) (((x) >> 0) & FW_PORT_CMD_MODTYPE_MASK)
1185
1186#define FW_PORT_CMD_PPPEN(x) ((x) << 31)
1187#define FW_PORT_CMD_TPSRC(x) ((x) << 28)
1188#define FW_PORT_CMD_NCSISRC(x) ((x) << 24)
1189
1190#define FW_PORT_CMD_CH0(x) ((x) << 20)
1191#define FW_PORT_CMD_CH1(x) ((x) << 16)
1192#define FW_PORT_CMD_CH2(x) ((x) << 12)
1193#define FW_PORT_CMD_CH3(x) ((x) << 8)
1194#define FW_PORT_CMD_NCSICH(x) ((x) << 4)
1195
1196enum fw_port_type {
1197 FW_PORT_TYPE_FIBER,
1198 FW_PORT_TYPE_KX4,
1199 FW_PORT_TYPE_BT_SGMII,
1200 FW_PORT_TYPE_KX,
1201 FW_PORT_TYPE_BT_XAUI,
1202 FW_PORT_TYPE_KR,
1203 FW_PORT_TYPE_CX4,
1204 FW_PORT_TYPE_TWINAX,
1205
1206 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_MASK
1207};
1208
1209enum fw_port_module_type {
1210 FW_PORT_MOD_TYPE_NA,
1211 FW_PORT_MOD_TYPE_LR,
1212 FW_PORT_MOD_TYPE_SR,
1213 FW_PORT_MOD_TYPE_ER,
1214
1215 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK
1216};
1217
1218/* port stats */
1219#define FW_NUM_PORT_STATS 50
1220#define FW_NUM_PORT_TX_STATS 23
1221#define FW_NUM_PORT_RX_STATS 27
1222
1223enum fw_port_stats_tx_index {
1224 FW_STAT_TX_PORT_BYTES_IX,
1225 FW_STAT_TX_PORT_FRAMES_IX,
1226 FW_STAT_TX_PORT_BCAST_IX,
1227 FW_STAT_TX_PORT_MCAST_IX,
1228 FW_STAT_TX_PORT_UCAST_IX,
1229 FW_STAT_TX_PORT_ERROR_IX,
1230 FW_STAT_TX_PORT_64B_IX,
1231 FW_STAT_TX_PORT_65B_127B_IX,
1232 FW_STAT_TX_PORT_128B_255B_IX,
1233 FW_STAT_TX_PORT_256B_511B_IX,
1234 FW_STAT_TX_PORT_512B_1023B_IX,
1235 FW_STAT_TX_PORT_1024B_1518B_IX,
1236 FW_STAT_TX_PORT_1519B_MAX_IX,
1237 FW_STAT_TX_PORT_DROP_IX,
1238 FW_STAT_TX_PORT_PAUSE_IX,
1239 FW_STAT_TX_PORT_PPP0_IX,
1240 FW_STAT_TX_PORT_PPP1_IX,
1241 FW_STAT_TX_PORT_PPP2_IX,
1242 FW_STAT_TX_PORT_PPP3_IX,
1243 FW_STAT_TX_PORT_PPP4_IX,
1244 FW_STAT_TX_PORT_PPP5_IX,
1245 FW_STAT_TX_PORT_PPP6_IX,
1246 FW_STAT_TX_PORT_PPP7_IX
1247};
1248
1249enum fw_port_stat_rx_index {
1250 FW_STAT_RX_PORT_BYTES_IX,
1251 FW_STAT_RX_PORT_FRAMES_IX,
1252 FW_STAT_RX_PORT_BCAST_IX,
1253 FW_STAT_RX_PORT_MCAST_IX,
1254 FW_STAT_RX_PORT_UCAST_IX,
1255 FW_STAT_RX_PORT_MTU_ERROR_IX,
1256 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1257 FW_STAT_RX_PORT_CRC_ERROR_IX,
1258 FW_STAT_RX_PORT_LEN_ERROR_IX,
1259 FW_STAT_RX_PORT_SYM_ERROR_IX,
1260 FW_STAT_RX_PORT_64B_IX,
1261 FW_STAT_RX_PORT_65B_127B_IX,
1262 FW_STAT_RX_PORT_128B_255B_IX,
1263 FW_STAT_RX_PORT_256B_511B_IX,
1264 FW_STAT_RX_PORT_512B_1023B_IX,
1265 FW_STAT_RX_PORT_1024B_1518B_IX,
1266 FW_STAT_RX_PORT_1519B_MAX_IX,
1267 FW_STAT_RX_PORT_PAUSE_IX,
1268 FW_STAT_RX_PORT_PPP0_IX,
1269 FW_STAT_RX_PORT_PPP1_IX,
1270 FW_STAT_RX_PORT_PPP2_IX,
1271 FW_STAT_RX_PORT_PPP3_IX,
1272 FW_STAT_RX_PORT_PPP4_IX,
1273 FW_STAT_RX_PORT_PPP5_IX,
1274 FW_STAT_RX_PORT_PPP6_IX,
1275 FW_STAT_RX_PORT_PPP7_IX,
1276 FW_STAT_RX_PORT_LESS_64B_IX
1277};
1278
1279struct fw_port_stats_cmd {
1280 __be32 op_to_portid;
1281 __be32 retval_len16;
1282 union fw_port_stats {
1283 struct fw_port_stats_ctl {
1284 u8 nstats_bg_bm;
1285 u8 tx_ix;
1286 __be16 r6;
1287 __be32 r7;
1288 __be64 stat0;
1289 __be64 stat1;
1290 __be64 stat2;
1291 __be64 stat3;
1292 __be64 stat4;
1293 __be64 stat5;
1294 } ctl;
1295 struct fw_port_stats_all {
1296 __be64 tx_bytes;
1297 __be64 tx_frames;
1298 __be64 tx_bcast;
1299 __be64 tx_mcast;
1300 __be64 tx_ucast;
1301 __be64 tx_error;
1302 __be64 tx_64b;
1303 __be64 tx_65b_127b;
1304 __be64 tx_128b_255b;
1305 __be64 tx_256b_511b;
1306 __be64 tx_512b_1023b;
1307 __be64 tx_1024b_1518b;
1308 __be64 tx_1519b_max;
1309 __be64 tx_drop;
1310 __be64 tx_pause;
1311 __be64 tx_ppp0;
1312 __be64 tx_ppp1;
1313 __be64 tx_ppp2;
1314 __be64 tx_ppp3;
1315 __be64 tx_ppp4;
1316 __be64 tx_ppp5;
1317 __be64 tx_ppp6;
1318 __be64 tx_ppp7;
1319 __be64 rx_bytes;
1320 __be64 rx_frames;
1321 __be64 rx_bcast;
1322 __be64 rx_mcast;
1323 __be64 rx_ucast;
1324 __be64 rx_mtu_error;
1325 __be64 rx_mtu_crc_error;
1326 __be64 rx_crc_error;
1327 __be64 rx_len_error;
1328 __be64 rx_sym_error;
1329 __be64 rx_64b;
1330 __be64 rx_65b_127b;
1331 __be64 rx_128b_255b;
1332 __be64 rx_256b_511b;
1333 __be64 rx_512b_1023b;
1334 __be64 rx_1024b_1518b;
1335 __be64 rx_1519b_max;
1336 __be64 rx_pause;
1337 __be64 rx_ppp0;
1338 __be64 rx_ppp1;
1339 __be64 rx_ppp2;
1340 __be64 rx_ppp3;
1341 __be64 rx_ppp4;
1342 __be64 rx_ppp5;
1343 __be64 rx_ppp6;
1344 __be64 rx_ppp7;
1345 __be64 rx_less_64b;
1346 __be64 rx_bg_drop;
1347 __be64 rx_bg_trunc;
1348 } all;
1349 } u;
1350};
1351
1352#define FW_PORT_STATS_CMD_NSTATS(x) ((x) << 4)
1353#define FW_PORT_STATS_CMD_BG_BM(x) ((x) << 0)
1354#define FW_PORT_STATS_CMD_TX(x) ((x) << 7)
1355#define FW_PORT_STATS_CMD_IX(x) ((x) << 0)
1356
1357/* port loopback stats */
1358#define FW_NUM_LB_STATS 16
1359enum fw_port_lb_stats_index {
1360 FW_STAT_LB_PORT_BYTES_IX,
1361 FW_STAT_LB_PORT_FRAMES_IX,
1362 FW_STAT_LB_PORT_BCAST_IX,
1363 FW_STAT_LB_PORT_MCAST_IX,
1364 FW_STAT_LB_PORT_UCAST_IX,
1365 FW_STAT_LB_PORT_ERROR_IX,
1366 FW_STAT_LB_PORT_64B_IX,
1367 FW_STAT_LB_PORT_65B_127B_IX,
1368 FW_STAT_LB_PORT_128B_255B_IX,
1369 FW_STAT_LB_PORT_256B_511B_IX,
1370 FW_STAT_LB_PORT_512B_1023B_IX,
1371 FW_STAT_LB_PORT_1024B_1518B_IX,
1372 FW_STAT_LB_PORT_1519B_MAX_IX,
1373 FW_STAT_LB_PORT_DROP_FRAMES_IX
1374};
1375
1376struct fw_port_lb_stats_cmd {
1377 __be32 op_to_lbport;
1378 __be32 retval_len16;
1379 union fw_port_lb_stats {
1380 struct fw_port_lb_stats_ctl {
1381 u8 nstats_bg_bm;
1382 u8 ix_pkd;
1383 __be16 r6;
1384 __be32 r7;
1385 __be64 stat0;
1386 __be64 stat1;
1387 __be64 stat2;
1388 __be64 stat3;
1389 __be64 stat4;
1390 __be64 stat5;
1391 } ctl;
1392 struct fw_port_lb_stats_all {
1393 __be64 tx_bytes;
1394 __be64 tx_frames;
1395 __be64 tx_bcast;
1396 __be64 tx_mcast;
1397 __be64 tx_ucast;
1398 __be64 tx_error;
1399 __be64 tx_64b;
1400 __be64 tx_65b_127b;
1401 __be64 tx_128b_255b;
1402 __be64 tx_256b_511b;
1403 __be64 tx_512b_1023b;
1404 __be64 tx_1024b_1518b;
1405 __be64 tx_1519b_max;
1406 __be64 rx_lb_drop;
1407 __be64 rx_lb_trunc;
1408 } all;
1409 } u;
1410};
1411
1412#define FW_PORT_LB_STATS_CMD_LBPORT(x) ((x) << 0)
1413#define FW_PORT_LB_STATS_CMD_NSTATS(x) ((x) << 4)
1414#define FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << 0)
1415#define FW_PORT_LB_STATS_CMD_IX(x) ((x) << 0)
1416
1417struct fw_rss_ind_tbl_cmd {
1418 __be32 op_to_viid;
1419#define FW_RSS_IND_TBL_CMD_VIID(x) ((x) << 0)
1420 __be32 retval_len16;
1421 __be16 niqid;
1422 __be16 startidx;
1423 __be32 r3;
1424 __be32 iq0_to_iq2;
1425#define FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << 20)
1426#define FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << 10)
1427#define FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << 0)
1428 __be32 iq3_to_iq5;
1429 __be32 iq6_to_iq8;
1430 __be32 iq9_to_iq11;
1431 __be32 iq12_to_iq14;
1432 __be32 iq15_to_iq17;
1433 __be32 iq18_to_iq20;
1434 __be32 iq21_to_iq23;
1435 __be32 iq24_to_iq26;
1436 __be32 iq27_to_iq29;
1437 __be32 iq30_iq31;
1438 __be32 r15_lo;
1439};
1440
1441struct fw_rss_glb_config_cmd {
1442 __be32 op_to_write;
1443 __be32 retval_len16;
1444 union fw_rss_glb_config {
1445 struct fw_rss_glb_config_manual {
1446 __be32 mode_pkd;
1447 __be32 r3;
1448 __be64 r4;
1449 __be64 r5;
1450 } manual;
1451 struct fw_rss_glb_config_basicvirtual {
1452 __be32 mode_pkd;
1453 __be32 synmapen_to_hashtoeplitz;
1454#define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN (1U << 8)
1455#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 (1U << 7)
1456#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 (1U << 6)
1457#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 (1U << 5)
1458#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 (1U << 4)
1459#define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN (1U << 3)
1460#define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN (1U << 2)
1461#define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP (1U << 1)
1462#define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ (1U << 0)
1463 __be64 r8;
1464 __be64 r9;
1465 } basicvirtual;
1466 } u;
1467};
1468
1469#define FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << 28)
1470
1471#define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
1472#define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
1473
1474struct fw_rss_vi_config_cmd {
1475 __be32 op_to_viid;
1476#define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
1477 __be32 retval_len16;
1478 union fw_rss_vi_config {
1479 struct fw_rss_vi_config_manual {
1480 __be64 r3;
1481 __be64 r4;
1482 __be64 r5;
1483 } manual;
1484 struct fw_rss_vi_config_basicvirtual {
1485 __be32 r6;
1486 __be32 defaultq_to_ip4udpen;
1487#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) ((x) << 16)
1488#define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4)
1489#define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN (1U << 3)
1490#define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2)
1491#define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN (1U << 1)
1492#define FW_RSS_VI_CONFIG_CMD_IP4UDPEN (1U << 0)
1493 __be64 r9;
1494 __be64 r10;
1495 } basicvirtual;
1496 } u;
1497};
1498
1499enum fw_error_type {
1500 FW_ERROR_TYPE_EXCEPTION = 0x0,
1501 FW_ERROR_TYPE_HWMODULE = 0x1,
1502 FW_ERROR_TYPE_WR = 0x2,
1503 FW_ERROR_TYPE_ACL = 0x3,
1504};
1505
1506struct fw_error_cmd {
1507 __be32 op_to_type;
1508 __be32 len16_pkd;
1509 union fw_error {
1510 struct fw_error_exception {
1511 __be32 info[6];
1512 } exception;
1513 struct fw_error_hwmodule {
1514 __be32 regaddr;
1515 __be32 regval;
1516 } hwmodule;
1517 struct fw_error_wr {
1518 __be16 cidx;
1519 __be16 pfn_vfn;
1520 __be32 eqid;
1521 u8 wrhdr[16];
1522 } wr;
1523 struct fw_error_acl {
1524 __be16 cidx;
1525 __be16 pfn_vfn;
1526 __be32 eqid;
1527 __be16 mv_pkd;
1528 u8 val[6];
1529 __be64 r4;
1530 } acl;
1531 } u;
1532};
1533
1534struct fw_debug_cmd {
1535 __be32 op_type;
1536#define FW_DEBUG_CMD_TYPE_GET(x) ((x) & 0xff)
1537 __be32 len16_pkd;
1538 union fw_debug {
1539 struct fw_debug_assert {
1540 __be32 fcid;
1541 __be32 line;
1542 __be32 x;
1543 __be32 y;
1544 u8 filename_0_7[8];
1545 u8 filename_8_15[8];
1546 __be64 r3;
1547 } assert;
1548 struct fw_debug_prt {
1549 __be16 dprtstridx;
1550 __be16 r3[3];
1551 __be32 dprtstrparam0;
1552 __be32 dprtstrparam1;
1553 __be32 dprtstrparam2;
1554 __be32 dprtstrparam3;
1555 } prt;
1556 } u;
1557};
1558
1559struct fw_hdr {
1560 u8 ver;
1561 u8 reserved1;
1562 __be16 len512; /* bin length in units of 512-bytes */
1563 __be32 fw_ver; /* firmware version */
1564 __be32 tp_microcode_ver;
1565 u8 intfver_nic;
1566 u8 intfver_vnic;
1567 u8 intfver_ofld;
1568 u8 intfver_ri;
1569 u8 intfver_iscsipdu;
1570 u8 intfver_iscsi;
1571 u8 intfver_fcoe;
1572 u8 reserved2;
1573 __be32 reserved3[27];
1574};
1575
1576#define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff)
1577#define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff)
1578#define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff)
1579#define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff)
1580#endif /* _T4FW_INTERFACE_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 11:20:59 -0500