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-rw-r--r--drivers/net/cxgb4/cxgb4_main.c24
-rw-r--r--drivers/net/cxgb4/cxgb4_uld.h4
-rw-r--r--drivers/net/cxgb4/t4_regs.h1
-rw-r--r--drivers/net/cxgb4/t4fw_api.h2
4 files changed, 29 insertions, 2 deletions
diff --git a/drivers/net/cxgb4/cxgb4_main.c b/drivers/net/cxgb4/cxgb4_main.c
index 0af6d6750a9d..47e8936e69c3 100644
--- a/drivers/net/cxgb4/cxgb4_main.c
+++ b/drivers/net/cxgb4/cxgb4_main.c
@@ -2897,6 +2897,21 @@ static void setup_memwin(struct adapter *adap)
2897 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2), 2897 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
2898 (bar0 + MEMWIN2_BASE) | BIR(0) | 2898 (bar0 + MEMWIN2_BASE) | BIR(0) |
2899 WINDOW(ilog2(MEMWIN2_APERTURE) - 10)); 2899 WINDOW(ilog2(MEMWIN2_APERTURE) - 10));
2900 if (adap->vres.ocq.size) {
2901 unsigned int start, sz_kb;
2902
2903 start = pci_resource_start(adap->pdev, 2) +
2904 OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
2905 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
2906 t4_write_reg(adap,
2907 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),
2908 start | BIR(1) | WINDOW(ilog2(sz_kb)));
2909 t4_write_reg(adap,
2910 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),
2911 adap->vres.ocq.start);
2912 t4_read_reg(adap,
2913 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));
2914 }
2900} 2915}
2901 2916
2902static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) 2917static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
@@ -2954,7 +2969,6 @@ static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
2954 t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG); 2969 t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
2955 v = t4_read_reg(adap, TP_PIO_DATA); 2970 v = t4_read_reg(adap, TP_PIO_DATA);
2956 t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR); 2971 t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
2957 setup_memwin(adap);
2958 return 0; 2972 return 0;
2959} 2973}
2960 2974
@@ -3073,13 +3087,17 @@ static int adap_init0(struct adapter *adap)
3073 params[1] = FW_PARAM_PFVF(SQRQ_END); 3087 params[1] = FW_PARAM_PFVF(SQRQ_END);
3074 params[2] = FW_PARAM_PFVF(CQ_START); 3088 params[2] = FW_PARAM_PFVF(CQ_START);
3075 params[3] = FW_PARAM_PFVF(CQ_END); 3089 params[3] = FW_PARAM_PFVF(CQ_END);
3076 ret = t4_query_params(adap, 0, 0, 0, 4, params, val); 3090 params[4] = FW_PARAM_PFVF(OCQ_START);
3091 params[5] = FW_PARAM_PFVF(OCQ_END);
3092 ret = t4_query_params(adap, 0, 0, 0, 6, params, val);
3077 if (ret < 0) 3093 if (ret < 0)
3078 goto bye; 3094 goto bye;
3079 adap->vres.qp.start = val[0]; 3095 adap->vres.qp.start = val[0];
3080 adap->vres.qp.size = val[1] - val[0] + 1; 3096 adap->vres.qp.size = val[1] - val[0] + 1;
3081 adap->vres.cq.start = val[2]; 3097 adap->vres.cq.start = val[2];
3082 adap->vres.cq.size = val[3] - val[2] + 1; 3098 adap->vres.cq.size = val[3] - val[2] + 1;
3099 adap->vres.ocq.start = val[4];
3100 adap->vres.ocq.size = val[5] - val[4] + 1;
3083 } 3101 }
3084 if (c.iscsicaps) { 3102 if (c.iscsicaps) {
3085 params[0] = FW_PARAM_PFVF(ISCSI_START); 3103 params[0] = FW_PARAM_PFVF(ISCSI_START);
@@ -3139,6 +3157,7 @@ static int adap_init0(struct adapter *adap)
3139 } 3157 }
3140#endif 3158#endif
3141 3159
3160 setup_memwin(adap);
3142 return 0; 3161 return 0;
3143 3162
3144 /* 3163 /*
@@ -3221,6 +3240,7 @@ static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
3221 3240
3222 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 3241 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
3223 adap->params.b_wnd); 3242 adap->params.b_wnd);
3243 setup_memwin(adap);
3224 if (cxgb_up(adap)) 3244 if (cxgb_up(adap))
3225 return PCI_ERS_RESULT_DISCONNECT; 3245 return PCI_ERS_RESULT_DISCONNECT;
3226 return PCI_ERS_RESULT_RECOVERED; 3246 return PCI_ERS_RESULT_RECOVERED;
diff --git a/drivers/net/cxgb4/cxgb4_uld.h b/drivers/net/cxgb4/cxgb4_uld.h
index 0dc0866df1bf..85d74e751ce0 100644
--- a/drivers/net/cxgb4/cxgb4_uld.h
+++ b/drivers/net/cxgb4/cxgb4_uld.h
@@ -187,8 +187,12 @@ struct cxgb4_virt_res { /* virtualized HW resources */
187 struct cxgb4_range pbl; 187 struct cxgb4_range pbl;
188 struct cxgb4_range qp; 188 struct cxgb4_range qp;
189 struct cxgb4_range cq; 189 struct cxgb4_range cq;
190 struct cxgb4_range ocq;
190}; 191};
191 192
193#define OCQ_WIN_OFFSET(pdev, vres) \
194 (pci_resource_len((pdev), 2) - roundup_pow_of_two((vres)->ocq.size))
195
192/* 196/*
193 * Block of information the LLD provides to ULDs attaching to a device. 197 * Block of information the LLD provides to ULDs attaching to a device.
194 */ 198 */
diff --git a/drivers/net/cxgb4/t4_regs.h b/drivers/net/cxgb4/t4_regs.h
index bf21c148fb2b..0adc5bcec7c4 100644
--- a/drivers/net/cxgb4/t4_regs.h
+++ b/drivers/net/cxgb4/t4_regs.h
@@ -232,6 +232,7 @@
232#define WINDOW_MASK 0x000000ffU 232#define WINDOW_MASK 0x000000ffU
233#define WINDOW_SHIFT 0 233#define WINDOW_SHIFT 0
234#define WINDOW(x) ((x) << WINDOW_SHIFT) 234#define WINDOW(x) ((x) << WINDOW_SHIFT)
235#define PCIE_MEM_ACCESS_OFFSET 0x306c
235 236
236#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908 237#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
237#define RNPP 0x80000000U 238#define RNPP 0x80000000U
diff --git a/drivers/net/cxgb4/t4fw_api.h b/drivers/net/cxgb4/t4fw_api.h
index ca45df8954dd..0969f2fbc1b0 100644
--- a/drivers/net/cxgb4/t4fw_api.h
+++ b/drivers/net/cxgb4/t4fw_api.h
@@ -485,6 +485,8 @@ enum fw_params_param_pfvf {
485 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 485 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
486 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 486 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
487 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 487 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
488 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26,
489 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27,
488}; 490};
489 491
490/* 492/*