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path: root/drivers/net/cxgb3
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-rw-r--r--drivers/net/cxgb3/common.h4
-rw-r--r--drivers/net/cxgb3/regs.h4
-rw-r--r--drivers/net/cxgb3/t3_hw.c37
3 files changed, 27 insertions, 18 deletions
diff --git a/drivers/net/cxgb3/common.h b/drivers/net/cxgb3/common.h
index e83a360bcc9e..75b5ee61f45c 100644
--- a/drivers/net/cxgb3/common.h
+++ b/drivers/net/cxgb3/common.h
@@ -194,7 +194,7 @@ struct adapter_info {
194 unsigned char nports; /* # of ports */ 194 unsigned char nports; /* # of ports */
195 unsigned char phy_base_addr; /* MDIO PHY base address */ 195 unsigned char phy_base_addr; /* MDIO PHY base address */
196 unsigned int gpio_out; /* GPIO output settings */ 196 unsigned int gpio_out; /* GPIO output settings */
197 unsigned int gpio_intr; /* GPIO IRQ enable mask */ 197 unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */
198 unsigned long caps; /* adapter capabilities */ 198 unsigned long caps; /* adapter capabilities */
199 const struct mdio_ops *mdio_ops; /* MDIO operations */ 199 const struct mdio_ops *mdio_ops; /* MDIO operations */
200 const char *desc; /* product description */ 200 const char *desc; /* product description */
@@ -517,7 +517,7 @@ enum {
517 MAC_RXFIFO_SIZE = 32768 517 MAC_RXFIFO_SIZE = 32768
518}; 518};
519 519
520/* IEEE 802.3ae specified MDIO devices */ 520/* IEEE 802.3 specified MDIO devices */
521enum { 521enum {
522 MDIO_DEV_PMA_PMD = 1, 522 MDIO_DEV_PMA_PMD = 1,
523 MDIO_DEV_WIS = 2, 523 MDIO_DEV_WIS = 2,
diff --git a/drivers/net/cxgb3/regs.h b/drivers/net/cxgb3/regs.h
index 4bda27c551c9..a035d5c24442 100644
--- a/drivers/net/cxgb3/regs.h
+++ b/drivers/net/cxgb3/regs.h
@@ -573,6 +573,10 @@
573#define V_GPIO10(x) ((x) << S_GPIO10) 573#define V_GPIO10(x) ((x) << S_GPIO10)
574#define F_GPIO10 V_GPIO10(1U) 574#define F_GPIO10 V_GPIO10(1U)
575 575
576#define S_GPIO9 9
577#define V_GPIO9(x) ((x) << S_GPIO9)
578#define F_GPIO9 V_GPIO9(1U)
579
576#define S_GPIO7 7 580#define S_GPIO7 7
577#define V_GPIO7(x) ((x) << S_GPIO7) 581#define V_GPIO7(x) ((x) << S_GPIO7)
578#define F_GPIO7 V_GPIO7(1U) 582#define F_GPIO7 V_GPIO7(1U)
diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c
index f7ced324227d..bfce761156a1 100644
--- a/drivers/net/cxgb3/t3_hw.c
+++ b/drivers/net/cxgb3/t3_hw.c
@@ -445,24 +445,22 @@ int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex)
445static const struct adapter_info t3_adap_info[] = { 445static const struct adapter_info t3_adap_info[] = {
446 {2, 0, 446 {2, 0,
447 F_GPIO2_OEN | F_GPIO4_OEN | 447 F_GPIO2_OEN | F_GPIO4_OEN |
448 F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5, 448 F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0,
449 0,
450 &mi1_mdio_ops, "Chelsio PE9000"}, 449 &mi1_mdio_ops, "Chelsio PE9000"},
451 {2, 0, 450 {2, 0,
452 F_GPIO2_OEN | F_GPIO4_OEN | 451 F_GPIO2_OEN | F_GPIO4_OEN |
453 F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5, 452 F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0,
454 0,
455 &mi1_mdio_ops, "Chelsio T302"}, 453 &mi1_mdio_ops, "Chelsio T302"},
456 {1, 0, 454 {1, 0,
457 F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN | 455 F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN |
458 F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, 456 F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
459 0, SUPPORTED_10000baseT_Full | SUPPORTED_AUI, 457 { 0 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
460 &mi1_mdio_ext_ops, "Chelsio T310"}, 458 &mi1_mdio_ext_ops, "Chelsio T310"},
461 {2, 0, 459 {2, 0,
462 F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN | 460 F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN |
463 F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL | 461 F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL |
464 F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, 0, 462 F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
465 SUPPORTED_10000baseT_Full | SUPPORTED_AUI, 463 { S_GPIO9, S_GPIO3 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
466 &mi1_mdio_ext_ops, "Chelsio T320"}, 464 &mi1_mdio_ext_ops, "Chelsio T320"},
467}; 465};
468 466
@@ -1684,19 +1682,15 @@ static int mac_intr_handler(struct adapter *adap, unsigned int idx)
1684 */ 1682 */
1685int t3_phy_intr_handler(struct adapter *adapter) 1683int t3_phy_intr_handler(struct adapter *adapter)
1686{ 1684{
1687 u32 mask, gpi = adapter_info(adapter)->gpio_intr;
1688 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE); 1685 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);
1689 1686
1690 for_each_port(adapter, i) { 1687 for_each_port(adapter, i) {
1691 struct port_info *p = adap2pinfo(adapter, i); 1688 struct port_info *p = adap2pinfo(adapter, i);
1692 1689
1693 mask = gpi - (gpi & (gpi - 1));
1694 gpi -= mask;
1695
1696 if (!(p->phy.caps & SUPPORTED_IRQ)) 1690 if (!(p->phy.caps & SUPPORTED_IRQ))
1697 continue; 1691 continue;
1698 1692
1699 if (cause & mask) { 1693 if (cause & (1 << adapter_info(adapter)->gpio_intr[i])) {
1700 int phy_cause = p->phy.ops->intr_handler(&p->phy); 1694 int phy_cause = p->phy.ops->intr_handler(&p->phy);
1701 1695
1702 if (phy_cause & cphy_cause_link_change) 1696 if (phy_cause & cphy_cause_link_change)
@@ -1765,6 +1759,17 @@ int t3_slow_intr_handler(struct adapter *adapter)
1765 return 1; 1759 return 1;
1766} 1760}
1767 1761
1762static unsigned int calc_gpio_intr(struct adapter *adap)
1763{
1764 unsigned int i, gpi_intr = 0;
1765
1766 for_each_port(adap, i)
1767 if ((adap2pinfo(adap, i)->phy.caps & SUPPORTED_IRQ) &&
1768 adapter_info(adap)->gpio_intr[i])
1769 gpi_intr |= 1 << adapter_info(adap)->gpio_intr[i];
1770 return gpi_intr;
1771}
1772
1768/** 1773/**
1769 * t3_intr_enable - enable interrupts 1774 * t3_intr_enable - enable interrupts
1770 * @adapter: the adapter whose interrupts should be enabled 1775 * @adapter: the adapter whose interrupts should be enabled
@@ -1807,10 +1812,8 @@ void t3_intr_enable(struct adapter *adapter)
1807 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK); 1812 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK);
1808 } 1813 }
1809 1814
1810 t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW, 1815 t3_write_reg(adapter, A_T3DBG_INT_ENABLE, calc_gpio_intr(adapter));
1811 adapter_info(adapter)->gpio_intr); 1816
1812 t3_write_reg(adapter, A_T3DBG_INT_ENABLE,
1813 adapter_info(adapter)->gpio_intr);
1814 if (is_pcie(adapter)) 1817 if (is_pcie(adapter))
1815 t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK); 1818 t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK);
1816 else 1819 else
@@ -3331,6 +3334,8 @@ int t3_init_hw(struct adapter *adapter, u32 fw_params)
3331 init_hw_for_avail_ports(adapter, adapter->params.nports); 3334 init_hw_for_avail_ports(adapter, adapter->params.nports);
3332 t3_sge_init(adapter, &adapter->params.sge); 3335 t3_sge_init(adapter, &adapter->params.sge);
3333 3336
3337 t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW, calc_gpio_intr(adapter));
3338
3334 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params); 3339 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params);
3335 t3_write_reg(adapter, A_CIM_BOOT_CFG, 3340 t3_write_reg(adapter, A_CIM_BOOT_CFG,
3336 V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2)); 3341 V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2));