diff options
Diffstat (limited to 'drivers/net/cxgb3/t3_hw.c')
-rw-r--r-- | drivers/net/cxgb3/t3_hw.c | 131 |
1 files changed, 111 insertions, 20 deletions
diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c index dfdda4735bd8..6e5b4992f17e 100644 --- a/drivers/net/cxgb3/t3_hw.c +++ b/drivers/net/cxgb3/t3_hw.c | |||
@@ -62,7 +62,7 @@ int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, | |||
62 | return 0; | 62 | return 0; |
63 | } | 63 | } |
64 | if (--attempts == 0) | 64 | if (--attempts == 0) |
65 | return -EAGAIN; | 65 | return -EAGAIN; |
66 | if (delay) | 66 | if (delay) |
67 | udelay(delay); | 67 | udelay(delay); |
68 | } | 68 | } |
@@ -1263,7 +1263,13 @@ static int t3_handle_intr_status(struct adapter *adapter, unsigned int reg, | |||
1263 | return fatal; | 1263 | return fatal; |
1264 | } | 1264 | } |
1265 | 1265 | ||
1266 | #define SGE_INTR_MASK (F_RSPQDISABLED) | 1266 | #define SGE_INTR_MASK (F_RSPQDISABLED | \ |
1267 | F_UC_REQ_FRAMINGERROR | F_R_REQ_FRAMINGERROR | \ | ||
1268 | F_CPPARITYERROR | F_OCPARITYERROR | F_RCPARITYERROR | \ | ||
1269 | F_IRPARITYERROR | V_ITPARITYERROR(M_ITPARITYERROR) | \ | ||
1270 | V_FLPARITYERROR(M_FLPARITYERROR) | F_LODRBPARITYERROR | \ | ||
1271 | F_HIDRBPARITYERROR | F_LORCQPARITYERROR | \ | ||
1272 | F_HIRCQPARITYERROR) | ||
1267 | #define MC5_INTR_MASK (F_PARITYERR | F_ACTRGNFULL | F_UNKNOWNCMD | \ | 1273 | #define MC5_INTR_MASK (F_PARITYERR | F_ACTRGNFULL | F_UNKNOWNCMD | \ |
1268 | F_REQQPARERR | F_DISPQPARERR | F_DELACTEMPTY | \ | 1274 | F_REQQPARERR | F_DISPQPARERR | F_DELACTEMPTY | \ |
1269 | F_NFASRCHFAIL) | 1275 | F_NFASRCHFAIL) |
@@ -1280,16 +1286,23 @@ static int t3_handle_intr_status(struct adapter *adapter, unsigned int reg, | |||
1280 | #define PCIE_INTR_MASK (F_UNXSPLCPLERRR | F_UNXSPLCPLERRC | F_PCIE_PIOPARERR |\ | 1286 | #define PCIE_INTR_MASK (F_UNXSPLCPLERRR | F_UNXSPLCPLERRC | F_PCIE_PIOPARERR |\ |
1281 | F_PCIE_WFPARERR | F_PCIE_RFPARERR | F_PCIE_CFPARERR | \ | 1287 | F_PCIE_WFPARERR | F_PCIE_RFPARERR | F_PCIE_CFPARERR | \ |
1282 | /* V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR) | */ \ | 1288 | /* V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR) | */ \ |
1283 | V_BISTERR(M_BISTERR)) | 1289 | F_RETRYBUFPARERR | F_RETRYLUTPARERR | F_RXPARERR | \ |
1284 | #define ULPRX_INTR_MASK F_PARERR | 1290 | F_TXPARERR | V_BISTERR(M_BISTERR)) |
1285 | #define ULPTX_INTR_MASK 0 | 1291 | #define ULPRX_INTR_MASK (F_PARERRDATA | F_PARERRPCMD | F_ARBPF1PERR | \ |
1286 | #define CPLSW_INTR_MASK (F_TP_FRAMING_ERROR | \ | 1292 | F_ARBPF0PERR | F_ARBFPERR | F_PCMDMUXPERR | \ |
1293 | F_DATASELFRAMEERR1 | F_DATASELFRAMEERR0) | ||
1294 | #define ULPTX_INTR_MASK 0xfc | ||
1295 | #define CPLSW_INTR_MASK (F_CIM_OP_MAP_PERR | F_TP_FRAMING_ERROR | \ | ||
1287 | F_SGE_FRAMING_ERROR | F_CIM_FRAMING_ERROR | \ | 1296 | F_SGE_FRAMING_ERROR | F_CIM_FRAMING_ERROR | \ |
1288 | F_ZERO_SWITCH_ERROR) | 1297 | F_ZERO_SWITCH_ERROR) |
1289 | #define CIM_INTR_MASK (F_BLKWRPLINT | F_BLKRDPLINT | F_BLKWRCTLINT | \ | 1298 | #define CIM_INTR_MASK (F_BLKWRPLINT | F_BLKRDPLINT | F_BLKWRCTLINT | \ |
1290 | F_BLKRDCTLINT | F_BLKWRFLASHINT | F_BLKRDFLASHINT | \ | 1299 | F_BLKRDCTLINT | F_BLKWRFLASHINT | F_BLKRDFLASHINT | \ |
1291 | F_SGLWRFLASHINT | F_WRBLKFLASHINT | F_BLKWRBOOTINT | \ | 1300 | F_SGLWRFLASHINT | F_WRBLKFLASHINT | F_BLKWRBOOTINT | \ |
1292 | F_FLASHRANGEINT | F_SDRAMRANGEINT | F_RSVDSPACEINT) | 1301 | F_FLASHRANGEINT | F_SDRAMRANGEINT | F_RSVDSPACEINT | \ |
1302 | F_DRAMPARERR | F_ICACHEPARERR | F_DCACHEPARERR | \ | ||
1303 | F_OBQSGEPARERR | F_OBQULPHIPARERR | F_OBQULPLOPARERR | \ | ||
1304 | F_IBQSGELOPARERR | F_IBQSGEHIPARERR | F_IBQULPPARERR | \ | ||
1305 | F_IBQTPPARERR | F_ITAGPARERR | F_DTAGPARERR) | ||
1293 | #define PMTX_INTR_MASK (F_ZERO_C_CMD_ERROR | ICSPI_FRM_ERR | OESPI_FRM_ERR | \ | 1306 | #define PMTX_INTR_MASK (F_ZERO_C_CMD_ERROR | ICSPI_FRM_ERR | OESPI_FRM_ERR | \ |
1294 | V_ICSPI_PAR_ERROR(M_ICSPI_PAR_ERROR) | \ | 1307 | V_ICSPI_PAR_ERROR(M_ICSPI_PAR_ERROR) | \ |
1295 | V_OESPI_PAR_ERROR(M_OESPI_PAR_ERROR)) | 1308 | V_OESPI_PAR_ERROR(M_OESPI_PAR_ERROR)) |
@@ -1358,6 +1371,10 @@ static void pcie_intr_handler(struct adapter *adapter) | |||
1358 | {F_PCIE_CFPARERR, "PCI command FIFO parity error", -1, 1}, | 1371 | {F_PCIE_CFPARERR, "PCI command FIFO parity error", -1, 1}, |
1359 | {V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR), | 1372 | {V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR), |
1360 | "PCI MSI-X table/PBA parity error", -1, 1}, | 1373 | "PCI MSI-X table/PBA parity error", -1, 1}, |
1374 | {F_RETRYBUFPARERR, "PCI retry buffer parity error", -1, 1}, | ||
1375 | {F_RETRYLUTPARERR, "PCI retry LUT parity error", -1, 1}, | ||
1376 | {F_RXPARERR, "PCI Rx parity error", -1, 1}, | ||
1377 | {F_TXPARERR, "PCI Tx parity error", -1, 1}, | ||
1361 | {V_BISTERR(M_BISTERR), "PCI BIST error", -1, 1}, | 1378 | {V_BISTERR(M_BISTERR), "PCI BIST error", -1, 1}, |
1362 | {0} | 1379 | {0} |
1363 | }; | 1380 | }; |
@@ -1384,15 +1401,15 @@ static void tp_intr_handler(struct adapter *adapter) | |||
1384 | }; | 1401 | }; |
1385 | 1402 | ||
1386 | static struct intr_info tp_intr_info_t3c[] = { | 1403 | static struct intr_info tp_intr_info_t3c[] = { |
1387 | { 0x1ffffff, "TP parity error", -1, 1 }, | 1404 | {0x1fffffff, "TP parity error", -1, 1}, |
1388 | { F_FLMRXFLSTEMPTY, "TP out of Rx pages", -1, 1 }, | 1405 | {F_FLMRXFLSTEMPTY, "TP out of Rx pages", -1, 1}, |
1389 | { F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, | 1406 | {F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1}, |
1390 | { 0 } | 1407 | {0} |
1391 | }; | 1408 | }; |
1392 | 1409 | ||
1393 | if (t3_handle_intr_status(adapter, A_TP_INT_CAUSE, 0xffffffff, | 1410 | if (t3_handle_intr_status(adapter, A_TP_INT_CAUSE, 0xffffffff, |
1394 | adapter->params.rev < T3_REV_C ? | 1411 | adapter->params.rev < T3_REV_C ? |
1395 | tp_intr_info : tp_intr_info_t3c, NULL)) | 1412 | tp_intr_info : tp_intr_info_t3c, NULL)) |
1396 | t3_fatal_err(adapter); | 1413 | t3_fatal_err(adapter); |
1397 | } | 1414 | } |
1398 | 1415 | ||
@@ -1414,6 +1431,18 @@ static void cim_intr_handler(struct adapter *adapter) | |||
1414 | {F_BLKWRCTLINT, "CIM block write to CTL space", -1, 1}, | 1431 | {F_BLKWRCTLINT, "CIM block write to CTL space", -1, 1}, |
1415 | {F_BLKRDPLINT, "CIM block read from PL space", -1, 1}, | 1432 | {F_BLKRDPLINT, "CIM block read from PL space", -1, 1}, |
1416 | {F_BLKWRPLINT, "CIM block write to PL space", -1, 1}, | 1433 | {F_BLKWRPLINT, "CIM block write to PL space", -1, 1}, |
1434 | {F_DRAMPARERR, "CIM DRAM parity error", -1, 1}, | ||
1435 | {F_ICACHEPARERR, "CIM icache parity error", -1, 1}, | ||
1436 | {F_DCACHEPARERR, "CIM dcache parity error", -1, 1}, | ||
1437 | {F_OBQSGEPARERR, "CIM OBQ SGE parity error", -1, 1}, | ||
1438 | {F_OBQULPHIPARERR, "CIM OBQ ULPHI parity error", -1, 1}, | ||
1439 | {F_OBQULPLOPARERR, "CIM OBQ ULPLO parity error", -1, 1}, | ||
1440 | {F_IBQSGELOPARERR, "CIM IBQ SGELO parity error", -1, 1}, | ||
1441 | {F_IBQSGEHIPARERR, "CIM IBQ SGEHI parity error", -1, 1}, | ||
1442 | {F_IBQULPPARERR, "CIM IBQ ULP parity error", -1, 1}, | ||
1443 | {F_IBQTPPARERR, "CIM IBQ TP parity error", -1, 1}, | ||
1444 | {F_ITAGPARERR, "CIM itag parity error", -1, 1}, | ||
1445 | {F_DTAGPARERR, "CIM dtag parity error", -1, 1}, | ||
1417 | {0} | 1446 | {0} |
1418 | }; | 1447 | }; |
1419 | 1448 | ||
@@ -1428,7 +1457,14 @@ static void cim_intr_handler(struct adapter *adapter) | |||
1428 | static void ulprx_intr_handler(struct adapter *adapter) | 1457 | static void ulprx_intr_handler(struct adapter *adapter) |
1429 | { | 1458 | { |
1430 | static const struct intr_info ulprx_intr_info[] = { | 1459 | static const struct intr_info ulprx_intr_info[] = { |
1431 | {F_PARERR, "ULP RX parity error", -1, 1}, | 1460 | {F_PARERRDATA, "ULP RX data parity error", -1, 1}, |
1461 | {F_PARERRPCMD, "ULP RX command parity error", -1, 1}, | ||
1462 | {F_ARBPF1PERR, "ULP RX ArbPF1 parity error", -1, 1}, | ||
1463 | {F_ARBPF0PERR, "ULP RX ArbPF0 parity error", -1, 1}, | ||
1464 | {F_ARBFPERR, "ULP RX ArbF parity error", -1, 1}, | ||
1465 | {F_PCMDMUXPERR, "ULP RX PCMDMUX parity error", -1, 1}, | ||
1466 | {F_DATASELFRAMEERR1, "ULP RX frame error", -1, 1}, | ||
1467 | {F_DATASELFRAMEERR0, "ULP RX frame error", -1, 1}, | ||
1432 | {0} | 1468 | {0} |
1433 | }; | 1469 | }; |
1434 | 1470 | ||
@@ -1447,6 +1483,7 @@ static void ulptx_intr_handler(struct adapter *adapter) | |||
1447 | STAT_ULP_CH0_PBL_OOB, 0}, | 1483 | STAT_ULP_CH0_PBL_OOB, 0}, |
1448 | {F_PBL_BOUND_ERR_CH1, "ULP TX channel 1 PBL out of bounds", | 1484 | {F_PBL_BOUND_ERR_CH1, "ULP TX channel 1 PBL out of bounds", |
1449 | STAT_ULP_CH1_PBL_OOB, 0}, | 1485 | STAT_ULP_CH1_PBL_OOB, 0}, |
1486 | {0xfc, "ULP TX parity error", -1, 1}, | ||
1450 | {0} | 1487 | {0} |
1451 | }; | 1488 | }; |
1452 | 1489 | ||
@@ -1521,7 +1558,8 @@ static void pmrx_intr_handler(struct adapter *adapter) | |||
1521 | static void cplsw_intr_handler(struct adapter *adapter) | 1558 | static void cplsw_intr_handler(struct adapter *adapter) |
1522 | { | 1559 | { |
1523 | static const struct intr_info cplsw_intr_info[] = { | 1560 | static const struct intr_info cplsw_intr_info[] = { |
1524 | /* { F_CIM_OVFL_ERROR, "CPL switch CIM overflow", -1, 1 }, */ | 1561 | {F_CIM_OP_MAP_PERR, "CPL switch CIM parity error", -1, 1}, |
1562 | {F_CIM_OVFL_ERROR, "CPL switch CIM overflow", -1, 1}, | ||
1525 | {F_TP_FRAMING_ERROR, "CPL switch TP framing error", -1, 1}, | 1563 | {F_TP_FRAMING_ERROR, "CPL switch TP framing error", -1, 1}, |
1526 | {F_SGE_FRAMING_ERROR, "CPL switch SGE framing error", -1, 1}, | 1564 | {F_SGE_FRAMING_ERROR, "CPL switch SGE framing error", -1, 1}, |
1527 | {F_CIM_FRAMING_ERROR, "CPL switch CIM framing error", -1, 1}, | 1565 | {F_CIM_FRAMING_ERROR, "CPL switch CIM framing error", -1, 1}, |
@@ -1907,6 +1945,16 @@ static int t3_sge_write_context(struct adapter *adapter, unsigned int id, | |||
1907 | 0, SG_CONTEXT_CMD_ATTEMPTS, 1); | 1945 | 0, SG_CONTEXT_CMD_ATTEMPTS, 1); |
1908 | } | 1946 | } |
1909 | 1947 | ||
1948 | static int clear_sge_ctxt(struct adapter *adap, unsigned int id, | ||
1949 | unsigned int type) | ||
1950 | { | ||
1951 | t3_write_reg(adap, A_SG_CONTEXT_DATA0, 0); | ||
1952 | t3_write_reg(adap, A_SG_CONTEXT_DATA1, 0); | ||
1953 | t3_write_reg(adap, A_SG_CONTEXT_DATA2, 0); | ||
1954 | t3_write_reg(adap, A_SG_CONTEXT_DATA3, 0); | ||
1955 | return t3_sge_write_context(adap, id, type); | ||
1956 | } | ||
1957 | |||
1910 | /** | 1958 | /** |
1911 | * t3_sge_init_ecntxt - initialize an SGE egress context | 1959 | * t3_sge_init_ecntxt - initialize an SGE egress context |
1912 | * @adapter: the adapter to configure | 1960 | * @adapter: the adapter to configure |
@@ -2408,7 +2456,7 @@ static inline unsigned int pm_num_pages(unsigned int mem_size, | |||
2408 | t3_write_reg((adap), A_ ## reg, (start)); \ | 2456 | t3_write_reg((adap), A_ ## reg, (start)); \ |
2409 | start += size | 2457 | start += size |
2410 | 2458 | ||
2411 | /* | 2459 | /** |
2412 | * partition_mem - partition memory and configure TP memory settings | 2460 | * partition_mem - partition memory and configure TP memory settings |
2413 | * @adap: the adapter | 2461 | * @adap: the adapter |
2414 | * @p: the TP parameters | 2462 | * @p: the TP parameters |
@@ -2493,7 +2541,7 @@ static void tp_config(struct adapter *adap, const struct tp_params *p) | |||
2493 | V_AUTOSTATE2(1) | V_AUTOSTATE1(0) | | 2541 | V_AUTOSTATE2(1) | V_AUTOSTATE1(0) | |
2494 | V_BYTETHRESHOLD(16384) | V_MSSTHRESHOLD(2) | | 2542 | V_BYTETHRESHOLD(16384) | V_MSSTHRESHOLD(2) | |
2495 | F_AUTOCAREFUL | F_AUTOENABLE | V_DACK_MODE(1)); | 2543 | F_AUTOCAREFUL | F_AUTOENABLE | V_DACK_MODE(1)); |
2496 | t3_set_reg_field(adap, A_TP_IN_CONFIG, F_IPV6ENABLE | F_NICMODE, | 2544 | t3_set_reg_field(adap, A_TP_IN_CONFIG, F_RXFBARBPRIO | F_TXFBARBPRIO, |
2497 | F_IPV6ENABLE | F_NICMODE); | 2545 | F_IPV6ENABLE | F_NICMODE); |
2498 | t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814); | 2546 | t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814); |
2499 | t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105); | 2547 | t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105); |
@@ -2505,7 +2553,9 @@ static void tp_config(struct adapter *adap, const struct tp_params *p) | |||
2505 | F_ENABLEEPCMDAFULL, | 2553 | F_ENABLEEPCMDAFULL, |
2506 | F_ENABLEOCSPIFULL |F_TXDEFERENABLE | F_HEARBEATDACK | | 2554 | F_ENABLEOCSPIFULL |F_TXDEFERENABLE | F_HEARBEATDACK | |
2507 | F_TXCONGESTIONMODE | F_RXCONGESTIONMODE); | 2555 | F_TXCONGESTIONMODE | F_RXCONGESTIONMODE); |
2508 | t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL, 0); | 2556 | t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL, |
2557 | F_ENABLEIPV6RSS | F_ENABLENONOFDTNLSYN | | ||
2558 | F_ENABLEARPMISS | F_DISBLEDAPARBIT0); | ||
2509 | t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080); | 2559 | t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080); |
2510 | t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000); | 2560 | t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000); |
2511 | 2561 | ||
@@ -3212,7 +3262,8 @@ static void config_pcie(struct adapter *adap) | |||
3212 | V_REPLAYLMT(rpllmt)); | 3262 | V_REPLAYLMT(rpllmt)); |
3213 | 3263 | ||
3214 | t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff); | 3264 | t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff); |
3215 | t3_set_reg_field(adap, A_PCIE_CFG, F_PCIE_CLIDECEN, F_PCIE_CLIDECEN); | 3265 | t3_set_reg_field(adap, A_PCIE_CFG, 0, |
3266 | F_PCIE_DMASTOPEN | F_PCIE_CLIDECEN); | ||
3216 | } | 3267 | } |
3217 | 3268 | ||
3218 | /* | 3269 | /* |
@@ -3225,7 +3276,7 @@ static void config_pcie(struct adapter *adap) | |||
3225 | */ | 3276 | */ |
3226 | int t3_init_hw(struct adapter *adapter, u32 fw_params) | 3277 | int t3_init_hw(struct adapter *adapter, u32 fw_params) |
3227 | { | 3278 | { |
3228 | int err = -EIO, attempts = 100; | 3279 | int err = -EIO, attempts, i; |
3229 | const struct vpd_params *vpd = &adapter->params.vpd; | 3280 | const struct vpd_params *vpd = &adapter->params.vpd; |
3230 | 3281 | ||
3231 | if (adapter->params.rev > 0) | 3282 | if (adapter->params.rev > 0) |
@@ -3243,6 +3294,10 @@ int t3_init_hw(struct adapter *adapter, u32 fw_params) | |||
3243 | adapter->params.mc5.nfilters, | 3294 | adapter->params.mc5.nfilters, |
3244 | adapter->params.mc5.nroutes)) | 3295 | adapter->params.mc5.nroutes)) |
3245 | goto out_err; | 3296 | goto out_err; |
3297 | |||
3298 | for (i = 0; i < 32; i++) | ||
3299 | if (clear_sge_ctxt(adapter, i, F_CQ)) | ||
3300 | goto out_err; | ||
3246 | } | 3301 | } |
3247 | 3302 | ||
3248 | if (tp_init(adapter, &adapter->params.tp)) | 3303 | if (tp_init(adapter, &adapter->params.tp)) |
@@ -3258,7 +3313,8 @@ int t3_init_hw(struct adapter *adapter, u32 fw_params) | |||
3258 | if (is_pcie(adapter)) | 3313 | if (is_pcie(adapter)) |
3259 | config_pcie(adapter); | 3314 | config_pcie(adapter); |
3260 | else | 3315 | else |
3261 | t3_set_reg_field(adapter, A_PCIX_CFG, 0, F_CLIDECEN); | 3316 | t3_set_reg_field(adapter, A_PCIX_CFG, 0, |
3317 | F_DMASTOPEN | F_CLIDECEN); | ||
3262 | 3318 | ||
3263 | if (adapter->params.rev == T3_REV_C) | 3319 | if (adapter->params.rev == T3_REV_C) |
3264 | t3_set_reg_field(adapter, A_ULPTX_CONFIG, 0, | 3320 | t3_set_reg_field(adapter, A_ULPTX_CONFIG, 0, |
@@ -3275,6 +3331,7 @@ int t3_init_hw(struct adapter *adapter, u32 fw_params) | |||
3275 | V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2)); | 3331 | V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2)); |
3276 | t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */ | 3332 | t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */ |
3277 | 3333 | ||
3334 | attempts = 100; | ||
3278 | do { /* wait for uP to initialize */ | 3335 | do { /* wait for uP to initialize */ |
3279 | msleep(20); | 3336 | msleep(20); |
3280 | } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts); | 3337 | } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts); |
@@ -3409,6 +3466,7 @@ void early_hw_init(struct adapter *adapter, const struct adapter_info *ai) | |||
3409 | t3_write_reg(adapter, A_T3DBG_GPIO_EN, | 3466 | t3_write_reg(adapter, A_T3DBG_GPIO_EN, |
3410 | ai->gpio_out | F_GPIO0_OEN | F_GPIO0_OUT_VAL); | 3467 | ai->gpio_out | F_GPIO0_OEN | F_GPIO0_OUT_VAL); |
3411 | t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0); | 3468 | t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0); |
3469 | t3_write_reg(adapter, A_SG_OCO_BASE, V_BASE1(0xfff)); | ||
3412 | 3470 | ||
3413 | if (adapter->params.rev == 0 || !uses_xaui(adapter)) | 3471 | if (adapter->params.rev == 0 || !uses_xaui(adapter)) |
3414 | val |= F_ENRGMII; | 3472 | val |= F_ENRGMII; |
@@ -3458,6 +3516,36 @@ static int t3_reset_adapter(struct adapter *adapter) | |||
3458 | return 0; | 3516 | return 0; |
3459 | } | 3517 | } |
3460 | 3518 | ||
3519 | static int __devinit init_parity(struct adapter *adap) | ||
3520 | { | ||
3521 | int i, err, addr; | ||
3522 | |||
3523 | if (t3_read_reg(adap, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) | ||
3524 | return -EBUSY; | ||
3525 | |||
3526 | for (err = i = 0; !err && i < 16; i++) | ||
3527 | err = clear_sge_ctxt(adap, i, F_EGRESS); | ||
3528 | for (i = 0xfff0; !err && i <= 0xffff; i++) | ||
3529 | err = clear_sge_ctxt(adap, i, F_EGRESS); | ||
3530 | for (i = 0; !err && i < SGE_QSETS; i++) | ||
3531 | err = clear_sge_ctxt(adap, i, F_RESPONSEQ); | ||
3532 | if (err) | ||
3533 | return err; | ||
3534 | |||
3535 | t3_write_reg(adap, A_CIM_IBQ_DBG_DATA, 0); | ||
3536 | for (i = 0; i < 4; i++) | ||
3537 | for (addr = 0; addr <= M_IBQDBGADDR; addr++) { | ||
3538 | t3_write_reg(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGEN | | ||
3539 | F_IBQDBGWR | V_IBQDBGQID(i) | | ||
3540 | V_IBQDBGADDR(addr)); | ||
3541 | err = t3_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, | ||
3542 | F_IBQDBGBUSY, 0, 2, 1); | ||
3543 | if (err) | ||
3544 | return err; | ||
3545 | } | ||
3546 | return 0; | ||
3547 | } | ||
3548 | |||
3461 | /* | 3549 | /* |
3462 | * Initialize adapter SW state for the various HW modules, set initial values | 3550 | * Initialize adapter SW state for the various HW modules, set initial values |
3463 | * for some adapter tunables, take PHYs out of reset, and initialize the MDIO | 3551 | * for some adapter tunables, take PHYs out of reset, and initialize the MDIO |
@@ -3525,6 +3613,9 @@ int __devinit t3_prep_adapter(struct adapter *adapter, | |||
3525 | } | 3613 | } |
3526 | 3614 | ||
3527 | early_hw_init(adapter, ai); | 3615 | early_hw_init(adapter, ai); |
3616 | ret = init_parity(adapter); | ||
3617 | if (ret) | ||
3618 | return ret; | ||
3528 | 3619 | ||
3529 | for_each_port(adapter, i) { | 3620 | for_each_port(adapter, i) { |
3530 | u8 hw_addr[6]; | 3621 | u8 hw_addr[6]; |