diff options
Diffstat (limited to 'drivers/net/cxgb3/t3_hw.c')
-rw-r--r-- | drivers/net/cxgb3/t3_hw.c | 42 |
1 files changed, 23 insertions, 19 deletions
diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c index fb485d0a43d8..9e3591d7706f 100644 --- a/drivers/net/cxgb3/t3_hw.c +++ b/drivers/net/cxgb3/t3_hw.c | |||
@@ -921,7 +921,7 @@ static int t3_flash_erase_sectors(struct adapter *adapter, int start, int end) | |||
921 | /* | 921 | /* |
922 | * t3_load_fw - download firmware | 922 | * t3_load_fw - download firmware |
923 | * @adapter: the adapter | 923 | * @adapter: the adapter |
924 | * @fw_data: the firrware image to write | 924 | * @fw_data: the firmware image to write |
925 | * @size: image size | 925 | * @size: image size |
926 | * | 926 | * |
927 | * Write the supplied firmware image to the card's serial flash. | 927 | * Write the supplied firmware image to the card's serial flash. |
@@ -2362,7 +2362,7 @@ static void tp_config(struct adapter *adap, const struct tp_params *p) | |||
2362 | F_TCPCHECKSUMOFFLOAD | V_IPTTL(64)); | 2362 | F_TCPCHECKSUMOFFLOAD | V_IPTTL(64)); |
2363 | t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) | | 2363 | t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) | |
2364 | F_MTUENABLE | V_WINDOWSCALEMODE(1) | | 2364 | F_MTUENABLE | V_WINDOWSCALEMODE(1) | |
2365 | V_TIMESTAMPSMODE(1) | V_SACKMODE(1) | V_SACKRX(1)); | 2365 | V_TIMESTAMPSMODE(0) | V_SACKMODE(1) | V_SACKRX(1)); |
2366 | t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) | | 2366 | t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) | |
2367 | V_AUTOSTATE2(1) | V_AUTOSTATE1(0) | | 2367 | V_AUTOSTATE2(1) | V_AUTOSTATE1(0) | |
2368 | V_BYTETHRESHOLD(16384) | V_MSSTHRESHOLD(2) | | 2368 | V_BYTETHRESHOLD(16384) | V_MSSTHRESHOLD(2) | |
@@ -2371,16 +2371,18 @@ static void tp_config(struct adapter *adap, const struct tp_params *p) | |||
2371 | F_IPV6ENABLE | F_NICMODE); | 2371 | F_IPV6ENABLE | F_NICMODE); |
2372 | t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814); | 2372 | t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814); |
2373 | t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105); | 2373 | t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105); |
2374 | t3_set_reg_field(adap, A_TP_PARA_REG6, | 2374 | t3_set_reg_field(adap, A_TP_PARA_REG6, 0, |
2375 | adap->params.rev > 0 ? F_ENABLEESND : F_T3A_ENABLEESND, | 2375 | adap->params.rev > 0 ? F_ENABLEESND : |
2376 | 0); | 2376 | F_T3A_ENABLEESND); |
2377 | 2377 | ||
2378 | t3_set_reg_field(adap, A_TP_PC_CONFIG, | 2378 | t3_set_reg_field(adap, A_TP_PC_CONFIG, |
2379 | F_ENABLEEPCMDAFULL | F_ENABLEOCSPIFULL, | 2379 | F_ENABLEEPCMDAFULL, |
2380 | F_TXDEFERENABLE | F_HEARBEATDACK | F_TXCONGESTIONMODE | | 2380 | F_ENABLEOCSPIFULL |F_TXDEFERENABLE | F_HEARBEATDACK | |
2381 | F_RXCONGESTIONMODE); | 2381 | F_TXCONGESTIONMODE | F_RXCONGESTIONMODE); |
2382 | t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL, 0); | 2382 | t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL, 0); |
2383 | 2383 | t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080); | |
2384 | t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000); | ||
2385 | |||
2384 | if (adap->params.rev > 0) { | 2386 | if (adap->params.rev > 0) { |
2385 | tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE); | 2387 | tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE); |
2386 | t3_set_reg_field(adap, A_TP_PARA_REG3, F_TXPACEAUTO, | 2388 | t3_set_reg_field(adap, A_TP_PARA_REG3, F_TXPACEAUTO, |
@@ -2390,9 +2392,10 @@ static void tp_config(struct adapter *adap, const struct tp_params *p) | |||
2390 | } else | 2392 | } else |
2391 | t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED); | 2393 | t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED); |
2392 | 2394 | ||
2393 | t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0x12121212); | 2395 | t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0); |
2394 | t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0x12121212); | 2396 | t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0); |
2395 | t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0x1212); | 2397 | t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0); |
2398 | t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000); | ||
2396 | } | 2399 | } |
2397 | 2400 | ||
2398 | /* Desired TP timer resolution in usec */ | 2401 | /* Desired TP timer resolution in usec */ |
@@ -2468,6 +2471,7 @@ int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh) | |||
2468 | val |= F_RXCOALESCEENABLE; | 2471 | val |= F_RXCOALESCEENABLE; |
2469 | if (psh) | 2472 | if (psh) |
2470 | val |= F_RXCOALESCEPSHEN; | 2473 | val |= F_RXCOALESCEPSHEN; |
2474 | size = min(MAX_RX_COALESCING_LEN, size); | ||
2471 | t3_write_reg(adap, A_TP_PARA_REG2, V_RXCOALESCESIZE(size) | | 2475 | t3_write_reg(adap, A_TP_PARA_REG2, V_RXCOALESCESIZE(size) | |
2472 | V_MAXRXDATA(MAX_RX_COALESCING_LEN)); | 2476 | V_MAXRXDATA(MAX_RX_COALESCING_LEN)); |
2473 | } | 2477 | } |
@@ -2496,11 +2500,11 @@ static void __devinit init_mtus(unsigned short mtus[]) | |||
2496 | * it can accomodate max size TCP/IP headers when SACK and timestamps | 2500 | * it can accomodate max size TCP/IP headers when SACK and timestamps |
2497 | * are enabled and still have at least 8 bytes of payload. | 2501 | * are enabled and still have at least 8 bytes of payload. |
2498 | */ | 2502 | */ |
2499 | mtus[0] = 88; | 2503 | mtus[1] = 88; |
2500 | mtus[1] = 256; | 2504 | mtus[1] = 88; |
2501 | mtus[2] = 512; | 2505 | mtus[2] = 256; |
2502 | mtus[3] = 576; | 2506 | mtus[3] = 512; |
2503 | mtus[4] = 808; | 2507 | mtus[4] = 576; |
2504 | mtus[5] = 1024; | 2508 | mtus[5] = 1024; |
2505 | mtus[6] = 1280; | 2509 | mtus[6] = 1280; |
2506 | mtus[7] = 1492; | 2510 | mtus[7] = 1492; |
@@ -2802,7 +2806,7 @@ static void init_hw_for_avail_ports(struct adapter *adap, int nports) | |||
2802 | t3_set_reg_field(adap, A_ULPTX_CONFIG, F_CFG_RR_ARB, 0); | 2806 | t3_set_reg_field(adap, A_ULPTX_CONFIG, F_CFG_RR_ARB, 0); |
2803 | t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_TPTXPORT0EN | | 2807 | t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_TPTXPORT0EN | |
2804 | F_PORT0ACTIVE | F_ENFORCEPKT); | 2808 | F_PORT0ACTIVE | F_ENFORCEPKT); |
2805 | t3_write_reg(adap, A_PM1_TX_CFG, 0xc000c000); | 2809 | t3_write_reg(adap, A_PM1_TX_CFG, 0xffffffff); |
2806 | } else { | 2810 | } else { |
2807 | t3_set_reg_field(adap, A_ULPRX_CTL, 0, F_ROUND_ROBIN); | 2811 | t3_set_reg_field(adap, A_ULPRX_CTL, 0, F_ROUND_ROBIN); |
2808 | t3_set_reg_field(adap, A_ULPTX_CONFIG, 0, F_CFG_RR_ARB); | 2812 | t3_set_reg_field(adap, A_ULPTX_CONFIG, 0, F_CFG_RR_ARB); |
@@ -3097,7 +3101,7 @@ int t3_init_hw(struct adapter *adapter, u32 fw_params) | |||
3097 | else | 3101 | else |
3098 | t3_set_reg_field(adapter, A_PCIX_CFG, 0, F_CLIDECEN); | 3102 | t3_set_reg_field(adapter, A_PCIX_CFG, 0, F_CLIDECEN); |
3099 | 3103 | ||
3100 | t3_write_reg(adapter, A_PM1_RX_CFG, 0xf000f000); | 3104 | t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff); |
3101 | init_hw_for_avail_ports(adapter, adapter->params.nports); | 3105 | init_hw_for_avail_ports(adapter, adapter->params.nports); |
3102 | t3_sge_init(adapter, &adapter->params.sge); | 3106 | t3_sge_init(adapter, &adapter->params.sge); |
3103 | 3107 | ||