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path: root/drivers/net/cxgb3/regs.h
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Diffstat (limited to 'drivers/net/cxgb3/regs.h')
-rw-r--r--drivers/net/cxgb3/regs.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/net/cxgb3/regs.h b/drivers/net/cxgb3/regs.h
index 6e12bf4bc6cf..70e1961acee1 100644
--- a/drivers/net/cxgb3/regs.h
+++ b/drivers/net/cxgb3/regs.h
@@ -965,6 +965,12 @@
965#define V_LOCKTID(x) ((x) << S_LOCKTID) 965#define V_LOCKTID(x) ((x) << S_LOCKTID)
966#define F_LOCKTID V_LOCKTID(1U) 966#define F_LOCKTID V_LOCKTID(1U)
967 967
968#define S_TABLELATENCYDELTA 0
969#define M_TABLELATENCYDELTA 0xf
970#define V_TABLELATENCYDELTA(x) ((x) << S_TABLELATENCYDELTA)
971#define G_TABLELATENCYDELTA(x) \
972 (((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA)
973
968#define A_TP_PC_CONFIG2 0x34c 974#define A_TP_PC_CONFIG2 0x34c
969 975
970#define S_CHDRAFULL 4 976#define S_CHDRAFULL 4
@@ -1146,6 +1152,10 @@
1146#define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE) 1152#define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE)
1147#define F_RQFEEDBACKENABLE V_RQFEEDBACKENABLE(1U) 1153#define F_RQFEEDBACKENABLE V_RQFEEDBACKENABLE(1U)
1148 1154
1155#define S_HASHTOEPLITZ 2
1156#define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
1157#define F_HASHTOEPLITZ V_HASHTOEPLITZ(1U)
1158
1149#define S_DISABLE 0 1159#define S_DISABLE 0
1150 1160
1151#define A_TP_TM_PIO_ADDR 0x418 1161#define A_TP_TM_PIO_ADDR 0x418
@@ -1198,6 +1208,14 @@
1198 1208
1199#define A_TP_INT_ENABLE 0x470 1209#define A_TP_INT_ENABLE 0x470
1200 1210
1211#define S_FLMTXFLSTEMPTY 30
1212#define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY)
1213#define F_FLMTXFLSTEMPTY V_FLMTXFLSTEMPTY(1U)
1214
1215#define S_FLMRXFLSTEMPTY 29
1216#define V_FLMRXFLSTEMPTY(x) ((x) << S_FLMRXFLSTEMPTY)
1217#define F_FLMRXFLSTEMPTY V_FLMRXFLSTEMPTY(1U)
1218
1201#define A_TP_INT_CAUSE 0x474 1219#define A_TP_INT_CAUSE 0x474
1202 1220
1203#define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8 1221#define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
@@ -1291,6 +1309,10 @@
1291 1309
1292#define A_ULPTX_CONFIG 0x580 1310#define A_ULPTX_CONFIG 0x580
1293 1311
1312#define S_CFG_CQE_SOP_MASK 1
1313#define V_CFG_CQE_SOP_MASK(x) ((x) << S_CFG_CQE_SOP_MASK)
1314#define F_CFG_CQE_SOP_MASK V_CFG_CQE_SOP_MASK(1U)
1315
1294#define S_CFG_RR_ARB 0 1316#define S_CFG_RR_ARB 0
1295#define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB) 1317#define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB)
1296#define F_CFG_RR_ARB V_CFG_RR_ARB(1U) 1318#define F_CFG_RR_ARB V_CFG_RR_ARB(1U)