diff options
Diffstat (limited to 'drivers/net/cxgb3/ael1002.c')
-rw-r--r-- | drivers/net/cxgb3/ael1002.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/net/cxgb3/ael1002.c b/drivers/net/cxgb3/ael1002.c index 35cd36729155..2028da95afa1 100644 --- a/drivers/net/cxgb3/ael1002.c +++ b/drivers/net/cxgb3/ael1002.c | |||
@@ -292,7 +292,7 @@ unknown: | |||
292 | */ | 292 | */ |
293 | static int ael2005_setup_sr_edc(struct cphy *phy) | 293 | static int ael2005_setup_sr_edc(struct cphy *phy) |
294 | { | 294 | { |
295 | static struct reg_val regs[] = { | 295 | static const struct reg_val regs[] = { |
296 | { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x181 }, | 296 | { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x181 }, |
297 | { MDIO_MMD_PMAPMD, 0xc010, 0xffff, 0x448a }, | 297 | { MDIO_MMD_PMAPMD, 0xc010, 0xffff, 0x448a }, |
298 | { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5200 }, | 298 | { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5200 }, |
@@ -324,11 +324,11 @@ static int ael2005_setup_sr_edc(struct cphy *phy) | |||
324 | 324 | ||
325 | static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype) | 325 | static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype) |
326 | { | 326 | { |
327 | static struct reg_val regs[] = { | 327 | static const struct reg_val regs[] = { |
328 | { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5a00 }, | 328 | { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5a00 }, |
329 | { 0, 0, 0, 0 } | 329 | { 0, 0, 0, 0 } |
330 | }; | 330 | }; |
331 | static struct reg_val preemphasis[] = { | 331 | static const struct reg_val preemphasis[] = { |
332 | { MDIO_MMD_PMAPMD, 0xc014, 0xffff, 0xfe16 }, | 332 | { MDIO_MMD_PMAPMD, 0xc014, 0xffff, 0xfe16 }, |
333 | { MDIO_MMD_PMAPMD, 0xc015, 0xffff, 0xa000 }, | 333 | { MDIO_MMD_PMAPMD, 0xc015, 0xffff, 0xa000 }, |
334 | { 0, 0, 0, 0 } | 334 | { 0, 0, 0, 0 } |
@@ -393,7 +393,7 @@ static int ael2005_intr_clear(struct cphy *phy) | |||
393 | 393 | ||
394 | static int ael2005_reset(struct cphy *phy, int wait) | 394 | static int ael2005_reset(struct cphy *phy, int wait) |
395 | { | 395 | { |
396 | static struct reg_val regs0[] = { | 396 | static const struct reg_val regs0[] = { |
397 | { MDIO_MMD_PMAPMD, 0xc001, 0, 1 << 5 }, | 397 | { MDIO_MMD_PMAPMD, 0xc001, 0, 1 << 5 }, |
398 | { MDIO_MMD_PMAPMD, 0xc017, 0, 1 << 5 }, | 398 | { MDIO_MMD_PMAPMD, 0xc017, 0, 1 << 5 }, |
399 | { MDIO_MMD_PMAPMD, 0xc013, 0xffff, 0xf341 }, | 399 | { MDIO_MMD_PMAPMD, 0xc013, 0xffff, 0xf341 }, |
@@ -403,7 +403,7 @@ static int ael2005_reset(struct cphy *phy, int wait) | |||
403 | { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0 }, | 403 | { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0 }, |
404 | { 0, 0, 0, 0 } | 404 | { 0, 0, 0, 0 } |
405 | }; | 405 | }; |
406 | static struct reg_val regs1[] = { | 406 | static const struct reg_val regs1[] = { |
407 | { MDIO_MMD_PMAPMD, 0xca00, 0xffff, 0x0080 }, | 407 | { MDIO_MMD_PMAPMD, 0xca00, 0xffff, 0x0080 }, |
408 | { MDIO_MMD_PMAPMD, 0xca12, 0xffff, 0 }, | 408 | { MDIO_MMD_PMAPMD, 0xca12, 0xffff, 0 }, |
409 | { 0, 0, 0, 0 } | 409 | { 0, 0, 0, 0 } |
@@ -522,7 +522,7 @@ int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter, | |||
522 | */ | 522 | */ |
523 | static int ael2020_setup_sr_edc(struct cphy *phy) | 523 | static int ael2020_setup_sr_edc(struct cphy *phy) |
524 | { | 524 | { |
525 | static struct reg_val regs[] = { | 525 | static const struct reg_val regs[] = { |
526 | /* set CDR offset to 10 */ | 526 | /* set CDR offset to 10 */ |
527 | { MDIO_MMD_PMAPMD, 0xcc01, 0xffff, 0x488a }, | 527 | { MDIO_MMD_PMAPMD, 0xcc01, 0xffff, 0x488a }, |
528 | 528 | ||
@@ -551,20 +551,20 @@ static int ael2020_setup_sr_edc(struct cphy *phy) | |||
551 | static int ael2020_setup_twinax_edc(struct cphy *phy, int modtype) | 551 | static int ael2020_setup_twinax_edc(struct cphy *phy, int modtype) |
552 | { | 552 | { |
553 | /* set uC to 40MHz */ | 553 | /* set uC to 40MHz */ |
554 | static struct reg_val uCclock40MHz[] = { | 554 | static const struct reg_val uCclock40MHz[] = { |
555 | { MDIO_MMD_PMAPMD, 0xff28, 0xffff, 0x4001 }, | 555 | { MDIO_MMD_PMAPMD, 0xff28, 0xffff, 0x4001 }, |
556 | { MDIO_MMD_PMAPMD, 0xff2a, 0xffff, 0x0002 }, | 556 | { MDIO_MMD_PMAPMD, 0xff2a, 0xffff, 0x0002 }, |
557 | { 0, 0, 0, 0 } | 557 | { 0, 0, 0, 0 } |
558 | }; | 558 | }; |
559 | 559 | ||
560 | /* activate uC clock */ | 560 | /* activate uC clock */ |
561 | static struct reg_val uCclockActivate[] = { | 561 | static const struct reg_val uCclockActivate[] = { |
562 | { MDIO_MMD_PMAPMD, 0xd000, 0xffff, 0x5200 }, | 562 | { MDIO_MMD_PMAPMD, 0xd000, 0xffff, 0x5200 }, |
563 | { 0, 0, 0, 0 } | 563 | { 0, 0, 0, 0 } |
564 | }; | 564 | }; |
565 | 565 | ||
566 | /* set PC to start of SRAM and activate uC */ | 566 | /* set PC to start of SRAM and activate uC */ |
567 | static struct reg_val uCactivate[] = { | 567 | static const struct reg_val uCactivate[] = { |
568 | { MDIO_MMD_PMAPMD, 0xd080, 0xffff, 0x0100 }, | 568 | { MDIO_MMD_PMAPMD, 0xd080, 0xffff, 0x0100 }, |
569 | { MDIO_MMD_PMAPMD, 0xd092, 0xffff, 0x0000 }, | 569 | { MDIO_MMD_PMAPMD, 0xd092, 0xffff, 0x0000 }, |
570 | { 0, 0, 0, 0 } | 570 | { 0, 0, 0, 0 } |
@@ -624,7 +624,7 @@ static int ael2020_get_module_type(struct cphy *phy, int delay_ms) | |||
624 | */ | 624 | */ |
625 | static int ael2020_intr_enable(struct cphy *phy) | 625 | static int ael2020_intr_enable(struct cphy *phy) |
626 | { | 626 | { |
627 | struct reg_val regs[] = { | 627 | static const struct reg_val regs[] = { |
628 | /* output Module's Loss Of Signal (LOS) to LED */ | 628 | /* output Module's Loss Of Signal (LOS) to LED */ |
629 | { MDIO_MMD_PMAPMD, AEL2020_GPIO_CFG+AEL2020_GPIO_LSTAT, | 629 | { MDIO_MMD_PMAPMD, AEL2020_GPIO_CFG+AEL2020_GPIO_LSTAT, |
630 | 0xffff, 0x4 }, | 630 | 0xffff, 0x4 }, |
@@ -664,7 +664,7 @@ static int ael2020_intr_enable(struct cphy *phy) | |||
664 | */ | 664 | */ |
665 | static int ael2020_intr_disable(struct cphy *phy) | 665 | static int ael2020_intr_disable(struct cphy *phy) |
666 | { | 666 | { |
667 | struct reg_val regs[] = { | 667 | static const struct reg_val regs[] = { |
668 | /* reset "link status" LED to "off" */ | 668 | /* reset "link status" LED to "off" */ |
669 | { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL, | 669 | { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL, |
670 | 0xffff, 0xb << (AEL2020_GPIO_LSTAT*4) }, | 670 | 0xffff, 0xb << (AEL2020_GPIO_LSTAT*4) }, |
@@ -701,7 +701,7 @@ static int ael2020_intr_clear(struct cphy *phy) | |||
701 | return err ? err : t3_phy_lasi_intr_clear(phy); | 701 | return err ? err : t3_phy_lasi_intr_clear(phy); |
702 | } | 702 | } |
703 | 703 | ||
704 | static struct reg_val ael2020_reset_regs[] = { | 704 | static const struct reg_val ael2020_reset_regs[] = { |
705 | /* Erratum #2: CDRLOL asserted, causing PMA link down status */ | 705 | /* Erratum #2: CDRLOL asserted, causing PMA link down status */ |
706 | { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x3101 }, | 706 | { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x3101 }, |
707 | 707 | ||