diff options
Diffstat (limited to 'drivers/net/cnic_if.h')
-rw-r--r-- | drivers/net/cnic_if.h | 51 |
1 files changed, 36 insertions, 15 deletions
diff --git a/drivers/net/cnic_if.h b/drivers/net/cnic_if.h index 344c842d55ab..fdd8e46a9050 100644 --- a/drivers/net/cnic_if.h +++ b/drivers/net/cnic_if.h | |||
@@ -1,6 +1,6 @@ | |||
1 | /* cnic_if.h: Broadcom CNIC core network driver. | 1 | /* cnic_if.h: Broadcom CNIC core network driver. |
2 | * | 2 | * |
3 | * Copyright (c) 2006-2010 Broadcom Corporation | 3 | * Copyright (c) 2006-2011 Broadcom Corporation |
4 | * | 4 | * |
5 | * This program is free software; you can redistribute it and/or modify | 5 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License as published by | 6 | * it under the terms of the GNU General Public License as published by |
@@ -12,22 +12,31 @@ | |||
12 | #ifndef CNIC_IF_H | 12 | #ifndef CNIC_IF_H |
13 | #define CNIC_IF_H | 13 | #define CNIC_IF_H |
14 | 14 | ||
15 | #define CNIC_MODULE_VERSION "2.1.3" | 15 | #define CNIC_MODULE_VERSION "2.2.14" |
16 | #define CNIC_MODULE_RELDATE "June 24, 2010" | 16 | #define CNIC_MODULE_RELDATE "Mar 30, 2011" |
17 | 17 | ||
18 | #define CNIC_ULP_RDMA 0 | 18 | #define CNIC_ULP_RDMA 0 |
19 | #define CNIC_ULP_ISCSI 1 | 19 | #define CNIC_ULP_ISCSI 1 |
20 | #define CNIC_ULP_L4 2 | 20 | #define CNIC_ULP_FCOE 2 |
21 | #define MAX_CNIC_ULP_TYPE_EXT 2 | 21 | #define CNIC_ULP_L4 3 |
22 | #define MAX_CNIC_ULP_TYPE 3 | 22 | #define MAX_CNIC_ULP_TYPE_EXT 3 |
23 | #define MAX_CNIC_ULP_TYPE 4 | ||
23 | 24 | ||
24 | struct kwqe { | 25 | struct kwqe { |
25 | u32 kwqe_op_flag; | 26 | u32 kwqe_op_flag; |
26 | 27 | ||
28 | #define KWQE_QID_SHIFT 8 | ||
27 | #define KWQE_OPCODE_MASK 0x00ff0000 | 29 | #define KWQE_OPCODE_MASK 0x00ff0000 |
28 | #define KWQE_OPCODE_SHIFT 16 | 30 | #define KWQE_OPCODE_SHIFT 16 |
29 | #define KWQE_FLAGS_LAYER_SHIFT 28 | ||
30 | #define KWQE_OPCODE(x) ((x & KWQE_OPCODE_MASK) >> KWQE_OPCODE_SHIFT) | 31 | #define KWQE_OPCODE(x) ((x & KWQE_OPCODE_MASK) >> KWQE_OPCODE_SHIFT) |
32 | #define KWQE_LAYER_MASK 0x70000000 | ||
33 | #define KWQE_LAYER_SHIFT 28 | ||
34 | #define KWQE_FLAGS_LAYER_MASK_L2 (2<<28) | ||
35 | #define KWQE_FLAGS_LAYER_MASK_L3 (3<<28) | ||
36 | #define KWQE_FLAGS_LAYER_MASK_L4 (4<<28) | ||
37 | #define KWQE_FLAGS_LAYER_MASK_L5_RDMA (5<<28) | ||
38 | #define KWQE_FLAGS_LAYER_MASK_L5_ISCSI (6<<28) | ||
39 | #define KWQE_FLAGS_LAYER_MASK_L5_FCOE (7<<28) | ||
31 | 40 | ||
32 | u32 kwqe_info0; | 41 | u32 kwqe_info0; |
33 | u32 kwqe_info1; | 42 | u32 kwqe_info1; |
@@ -62,6 +71,7 @@ struct kcqe { | |||
62 | #define KCQE_FLAGS_LAYER_MASK_L4 (4<<28) | 71 | #define KCQE_FLAGS_LAYER_MASK_L4 (4<<28) |
63 | #define KCQE_FLAGS_LAYER_MASK_L5_RDMA (5<<28) | 72 | #define KCQE_FLAGS_LAYER_MASK_L5_RDMA (5<<28) |
64 | #define KCQE_FLAGS_LAYER_MASK_L5_ISCSI (6<<28) | 73 | #define KCQE_FLAGS_LAYER_MASK_L5_ISCSI (6<<28) |
74 | #define KCQE_FLAGS_LAYER_MASK_L5_FCOE (7<<28) | ||
65 | #define KCQE_FLAGS_NEXT (1<<31) | 75 | #define KCQE_FLAGS_NEXT (1<<31) |
66 | #define KCQE_FLAGS_OPCODE_MASK (0xff<<16) | 76 | #define KCQE_FLAGS_OPCODE_MASK (0xff<<16) |
67 | #define KCQE_FLAGS_OPCODE_SHIFT (16) | 77 | #define KCQE_FLAGS_OPCODE_SHIFT (16) |
@@ -75,23 +85,22 @@ struct kcqe { | |||
75 | #define CNIC_CTL_STOP_CMD 1 | 85 | #define CNIC_CTL_STOP_CMD 1 |
76 | #define CNIC_CTL_START_CMD 2 | 86 | #define CNIC_CTL_START_CMD 2 |
77 | #define CNIC_CTL_COMPLETION_CMD 3 | 87 | #define CNIC_CTL_COMPLETION_CMD 3 |
88 | #define CNIC_CTL_STOP_ISCSI_CMD 4 | ||
78 | 89 | ||
79 | #define DRV_CTL_IO_WR_CMD 0x101 | 90 | #define DRV_CTL_IO_WR_CMD 0x101 |
80 | #define DRV_CTL_IO_RD_CMD 0x102 | 91 | #define DRV_CTL_IO_RD_CMD 0x102 |
81 | #define DRV_CTL_CTX_WR_CMD 0x103 | 92 | #define DRV_CTL_CTX_WR_CMD 0x103 |
82 | #define DRV_CTL_CTXTBL_WR_CMD 0x104 | 93 | #define DRV_CTL_CTXTBL_WR_CMD 0x104 |
83 | #define DRV_CTL_COMPLETION_CMD 0x105 | 94 | #define DRV_CTL_RET_L5_SPQ_CREDIT_CMD 0x105 |
84 | #define DRV_CTL_START_L2_CMD 0x106 | 95 | #define DRV_CTL_START_L2_CMD 0x106 |
85 | #define DRV_CTL_STOP_L2_CMD 0x107 | 96 | #define DRV_CTL_STOP_L2_CMD 0x107 |
97 | #define DRV_CTL_RET_L2_SPQ_CREDIT_CMD 0x10c | ||
98 | #define DRV_CTL_ISCSI_STOPPED_CMD 0x10d | ||
86 | 99 | ||
87 | struct cnic_ctl_completion { | 100 | struct cnic_ctl_completion { |
88 | u32 cid; | 101 | u32 cid; |
89 | }; | 102 | }; |
90 | 103 | ||
91 | struct drv_ctl_completion { | ||
92 | u32 comp_count; | ||
93 | }; | ||
94 | |||
95 | struct cnic_ctl_info { | 104 | struct cnic_ctl_info { |
96 | int cmd; | 105 | int cmd; |
97 | union { | 106 | union { |
@@ -100,6 +109,10 @@ struct cnic_ctl_info { | |||
100 | } data; | 109 | } data; |
101 | }; | 110 | }; |
102 | 111 | ||
112 | struct drv_ctl_spq_credit { | ||
113 | u32 credit_count; | ||
114 | }; | ||
115 | |||
103 | struct drv_ctl_io { | 116 | struct drv_ctl_io { |
104 | u32 cid_addr; | 117 | u32 cid_addr; |
105 | u32 offset; | 118 | u32 offset; |
@@ -115,7 +128,7 @@ struct drv_ctl_l2_ring { | |||
115 | struct drv_ctl_info { | 128 | struct drv_ctl_info { |
116 | int cmd; | 129 | int cmd; |
117 | union { | 130 | union { |
118 | struct drv_ctl_completion comp; | 131 | struct drv_ctl_spq_credit credit; |
119 | struct drv_ctl_io io; | 132 | struct drv_ctl_io io; |
120 | struct drv_ctl_l2_ring ring; | 133 | struct drv_ctl_l2_ring ring; |
121 | char bytes[MAX_DRV_CTL_DATA]; | 134 | char bytes[MAX_DRV_CTL_DATA]; |
@@ -138,6 +151,7 @@ struct cnic_irq { | |||
138 | unsigned int vector; | 151 | unsigned int vector; |
139 | void *status_blk; | 152 | void *status_blk; |
140 | u32 status_blk_num; | 153 | u32 status_blk_num; |
154 | u32 status_blk_num2; | ||
141 | u32 irq_flags; | 155 | u32 irq_flags; |
142 | #define CNIC_IRQ_FL_MSIX 0x00000001 | 156 | #define CNIC_IRQ_FL_MSIX 0x00000001 |
143 | }; | 157 | }; |
@@ -147,11 +161,15 @@ struct cnic_eth_dev { | |||
147 | u32 drv_state; | 161 | u32 drv_state; |
148 | #define CNIC_DRV_STATE_REGD 0x00000001 | 162 | #define CNIC_DRV_STATE_REGD 0x00000001 |
149 | #define CNIC_DRV_STATE_USING_MSIX 0x00000002 | 163 | #define CNIC_DRV_STATE_USING_MSIX 0x00000002 |
164 | #define CNIC_DRV_STATE_NO_ISCSI_OOO 0x00000004 | ||
165 | #define CNIC_DRV_STATE_NO_ISCSI 0x00000008 | ||
166 | #define CNIC_DRV_STATE_NO_FCOE 0x00000010 | ||
150 | u32 chip_id; | 167 | u32 chip_id; |
151 | u32 max_kwqe_pending; | 168 | u32 max_kwqe_pending; |
152 | struct pci_dev *pdev; | 169 | struct pci_dev *pdev; |
153 | void __iomem *io_base; | 170 | void __iomem *io_base; |
154 | void __iomem *io_base2; | 171 | void __iomem *io_base2; |
172 | void *iro_arr; | ||
155 | 173 | ||
156 | u32 ctx_tbl_offset; | 174 | u32 ctx_tbl_offset; |
157 | u32 ctx_tbl_len; | 175 | u32 ctx_tbl_len; |
@@ -160,7 +178,10 @@ struct cnic_eth_dev { | |||
160 | u32 max_iscsi_conn; | 178 | u32 max_iscsi_conn; |
161 | u32 max_fcoe_conn; | 179 | u32 max_fcoe_conn; |
162 | u32 max_rdma_conn; | 180 | u32 max_rdma_conn; |
163 | u32 reserved0[2]; | 181 | u32 fcoe_init_cid; |
182 | u16 iscsi_l2_client_id; | ||
183 | u16 iscsi_l2_cid; | ||
184 | u8 iscsi_mac[ETH_ALEN]; | ||
164 | 185 | ||
165 | int num_irq; | 186 | int num_irq; |
166 | struct cnic_irq irq_arr[MAX_CNIC_VEC]; | 187 | struct cnic_irq irq_arr[MAX_CNIC_VEC]; |
@@ -296,7 +317,7 @@ struct cnic_ulp_ops { | |||
296 | void (*cm_abort_complete)(struct cnic_sock *); | 317 | void (*cm_abort_complete)(struct cnic_sock *); |
297 | void (*cm_remote_close)(struct cnic_sock *); | 318 | void (*cm_remote_close)(struct cnic_sock *); |
298 | void (*cm_remote_abort)(struct cnic_sock *); | 319 | void (*cm_remote_abort)(struct cnic_sock *); |
299 | void (*iscsi_nl_send_msg)(struct cnic_dev *dev, u32 msg_type, | 320 | int (*iscsi_nl_send_msg)(void *ulp_ctx, u32 msg_type, |
300 | char *data, u16 data_size); | 321 | char *data, u16 data_size); |
301 | struct module *owner; | 322 | struct module *owner; |
302 | atomic_t ref_count; | 323 | atomic_t ref_count; |