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-rw-r--r--drivers/net/chelsio/subr.c195
1 files changed, 134 insertions, 61 deletions
diff --git a/drivers/net/chelsio/subr.c b/drivers/net/chelsio/subr.c
index c2522cdfab37..56d1d15a8f96 100644
--- a/drivers/net/chelsio/subr.c
+++ b/drivers/net/chelsio/subr.c
@@ -322,9 +322,9 @@ static int mi1_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr,
322 322
323#if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR) 323#if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
324static struct mdio_ops mi1_mdio_ops = { 324static struct mdio_ops mi1_mdio_ops = {
325 mi1_mdio_init, 325 .init = mi1_mdio_init,
326 mi1_mdio_read, 326 .read = mi1_mdio_read,
327 mi1_mdio_write 327 .write = mi1_mdio_write
328}; 328};
329#endif 329#endif
330 330
@@ -378,9 +378,9 @@ static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
378} 378}
379 379
380static struct mdio_ops mi1_mdio_ext_ops = { 380static struct mdio_ops mi1_mdio_ext_ops = {
381 mi1_mdio_init, 381 .init = mi1_mdio_init,
382 mi1_mdio_ext_read, 382 .read = mi1_mdio_ext_read,
383 mi1_mdio_ext_write 383 .write = mi1_mdio_ext_write
384}; 384};
385 385
386enum { 386enum {
@@ -392,63 +392,136 @@ enum {
392 CH_BRD_N204_4CU, 392 CH_BRD_N204_4CU,
393}; 393};
394 394
395static struct board_info t1_board[] = { 395static const struct board_info t1_board[] = {
396 396 {
397{ CHBT_BOARD_CHT110, 1/*ports#*/, 397 .board = CHBT_BOARD_CHT110,
398 SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T1, 398 .port_number = 1,
399 CHBT_MAC_PM3393, CHBT_PHY_MY3126, 399 .caps = SUPPORTED_10000baseT_Full,
400 125000000/*clk-core*/, 150000000/*clk-mc3*/, 125000000/*clk-mc4*/, 400 .chip_term = CHBT_TERM_T1,
401 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/, 401 .chip_mac = CHBT_MAC_PM3393,
402 1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops, 402 .chip_phy = CHBT_PHY_MY3126,
403 &t1_my3126_ops, &mi1_mdio_ext_ops, 403 .clock_core = 125000000,
404 "Chelsio T110 1x10GBase-CX4 TOE" }, 404 .clock_mc3 = 150000000,
405 405 .clock_mc4 = 125000000,
406{ CHBT_BOARD_N110, 1/*ports#*/, 406 .espi_nports = 1,
407 SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1, 407 .clock_elmer0 = 44,
408 CHBT_MAC_PM3393, CHBT_PHY_88X2010, 408 .mdio_mdien = 1,
409 125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/, 409 .mdio_mdiinv = 1,
410 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/, 410 .mdio_mdc = 1,
411 0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops, 411 .mdio_phybaseaddr = 1,
412 &t1_mv88x201x_ops, &mi1_mdio_ext_ops, 412 .gmac = &t1_pm3393_ops,
413 "Chelsio N110 1x10GBaseX NIC" }, 413 .gphy = &t1_my3126_ops,
414 414 .mdio_ops = &mi1_mdio_ext_ops,
415{ CHBT_BOARD_N210, 1/*ports#*/, 415 .desc = "Chelsio T110 1x10GBase-CX4 TOE",
416 SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T2, 416 },
417 CHBT_MAC_PM3393, CHBT_PHY_88X2010, 417
418 125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/, 418 {
419 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/, 419 .board = CHBT_BOARD_N110,
420 0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops, 420 .port_number = 1,
421 &t1_mv88x201x_ops, &mi1_mdio_ext_ops, 421 .caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
422 "Chelsio N210 1x10GBaseX NIC" }, 422 .chip_term = CHBT_TERM_T1,
423 423 .chip_mac = CHBT_MAC_PM3393,
424{ CHBT_BOARD_CHT210, 1/*ports#*/, 424 .chip_phy = CHBT_PHY_88X2010,
425 SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2, 425 .clock_core = 125000000,
426 CHBT_MAC_PM3393, CHBT_PHY_88X2010, 426 .espi_nports = 1,
427 125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/, 427 .clock_elmer0 = 44,
428 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/, 428 .mdio_mdien = 0,
429 0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops, 429 .mdio_mdiinv = 0,
430 &t1_mv88x201x_ops, &mi1_mdio_ext_ops, 430 .mdio_mdc = 1,
431 "Chelsio T210 1x10GBaseX TOE" }, 431 .mdio_phybaseaddr = 0,
432 432 .gmac = &t1_pm3393_ops,
433{ CHBT_BOARD_CHT210, 1/*ports#*/, 433 .gphy = &t1_mv88x201x_ops,
434 SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2, 434 .mdio_ops = &mi1_mdio_ext_ops,
435 CHBT_MAC_PM3393, CHBT_PHY_MY3126, 435 .desc = "Chelsio N110 1x10GBaseX NIC",
436 125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/, 436 },
437 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/, 437
438 1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops, 438 {
439 &t1_my3126_ops, &mi1_mdio_ext_ops, 439 .board = CHBT_BOARD_N210,
440 "Chelsio T210 1x10GBase-CX4 TOE" }, 440 .port_number = 1,
441 .caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
442 .chip_term = CHBT_TERM_T2,
443 .chip_mac = CHBT_MAC_PM3393,
444 .chip_phy = CHBT_PHY_88X2010,
445 .clock_core = 125000000,
446 .espi_nports = 1,
447 .clock_elmer0 = 44,
448 .mdio_mdien = 0,
449 .mdio_mdiinv = 0,
450 .mdio_mdc = 1,
451 .mdio_phybaseaddr = 0,
452 .gmac = &t1_pm3393_ops,
453 .gphy = &t1_mv88x201x_ops,
454 .mdio_ops = &mi1_mdio_ext_ops,
455 .desc = "Chelsio N210 1x10GBaseX NIC",
456 },
457
458 {
459 .board = CHBT_BOARD_CHT210,
460 .port_number = 1,
461 .caps = SUPPORTED_10000baseT_Full,
462 .chip_term = CHBT_TERM_T2,
463 .chip_mac = CHBT_MAC_PM3393,
464 .chip_phy = CHBT_PHY_88X2010,
465 .clock_core = 125000000,
466 .clock_mc3 = 133000000,
467 .clock_mc4 = 125000000,
468 .espi_nports = 1,
469 .clock_elmer0 = 44,
470 .mdio_mdien = 0,
471 .mdio_mdiinv = 0,
472 .mdio_mdc = 1,
473 .mdio_phybaseaddr = 0,
474 .gmac = &t1_pm3393_ops,
475 .gphy = &t1_mv88x201x_ops,
476 .mdio_ops = &mi1_mdio_ext_ops,
477 .desc = "Chelsio T210 1x10GBaseX TOE",
478 },
479
480 {
481 .board = CHBT_BOARD_CHT210,
482 .port_number = 1,
483 .caps = SUPPORTED_10000baseT_Full,
484 .chip_term = CHBT_TERM_T2,
485 .chip_mac = CHBT_MAC_PM3393,
486 .chip_phy = CHBT_PHY_MY3126,
487 .clock_core = 125000000,
488 .clock_mc3 = 133000000,
489 .clock_mc4 = 125000000,
490 .espi_nports = 1,
491 .clock_elmer0 = 44,
492 .mdio_mdien = 1,
493 .mdio_mdiinv = 1,
494 .mdio_mdc = 1,
495 .mdio_phybaseaddr = 1,
496 .gmac = &t1_pm3393_ops,
497 .gphy = &t1_my3126_ops,
498 .mdio_ops = &mi1_mdio_ext_ops,
499 .desc = "Chelsio T210 1x10GBase-CX4 TOE",
500 },
441 501
442#ifdef CONFIG_CHELSIO_T1_1G 502#ifdef CONFIG_CHELSIO_T1_1G
443{ CHBT_BOARD_CHN204, 4/*ports#*/, 503 {
444 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | 504 .board = CHBT_BOARD_CHN204,
445 SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | 505 .port_number = 4,
446 SUPPORTED_PAUSE | SUPPORTED_TP /*caps*/, CHBT_TERM_T2, CHBT_MAC_VSC7321, CHBT_PHY_88E1111, 506 .caps = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
447 100000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/, 507 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
448 4/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/, 508 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
449 0/*mdiinv*/, 1/*mdc*/, 4/*phybaseaddr*/, &t1_vsc7326_ops, 509 SUPPORTED_PAUSE | SUPPORTED_TP,
450 &t1_mv88e1xxx_ops, &mi1_mdio_ops, 510 .chip_term = CHBT_TERM_T2,
451 "Chelsio N204 4x100/1000BaseT NIC" }, 511 .chip_mac = CHBT_MAC_VSC7321,
512 .chip_phy = CHBT_PHY_88E1111,
513 .clock_core = 100000000,
514 .espi_nports = 4,
515 .clock_elmer0 = 44,
516 .mdio_mdien = 0,
517 .mdio_mdiinv = 0,
518 .mdio_mdc = 0,
519 .mdio_phybaseaddr = 4,
520 .gmac = &t1_vsc7326_ops,
521 .gphy = &t1_mv88e1xxx_ops,
522 .mdio_ops = &mi1_mdio_ops,
523 .desc = "Chelsio N204 4x100/1000BaseT NIC",
524 },
452#endif 525#endif
453 526
454}; 527};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 17:00:04 -0500