diff options
Diffstat (limited to 'drivers/net/chelsio/pm3393.c')
-rw-r--r-- | drivers/net/chelsio/pm3393.c | 45 |
1 files changed, 20 insertions, 25 deletions
diff --git a/drivers/net/chelsio/pm3393.c b/drivers/net/chelsio/pm3393.c index 17bd20f60d99..04a1404fc65e 100644 --- a/drivers/net/chelsio/pm3393.c +++ b/drivers/net/chelsio/pm3393.c | |||
@@ -1,8 +1,8 @@ | |||
1 | /***************************************************************************** | 1 | /***************************************************************************** |
2 | * * | 2 | * * |
3 | * File: pm3393.c * | 3 | * File: pm3393.c * |
4 | * $Revision: 1.9 $ * | 4 | * $Revision: 1.16 $ * |
5 | * $Date: 2005/03/23 07:41:27 $ * | 5 | * $Date: 2005/05/14 00:59:32 $ * |
6 | * Description: * | 6 | * Description: * |
7 | * PMC/SIERRA (pm3393) MAC-PHY functionality. * | 7 | * PMC/SIERRA (pm3393) MAC-PHY functionality. * |
8 | * part of the Chelsio 10Gb Ethernet Driver. * | 8 | * part of the Chelsio 10Gb Ethernet Driver. * |
@@ -45,15 +45,19 @@ | |||
45 | 45 | ||
46 | /* 802.3ae 10Gb/s MDIO Manageable Device(MMD) | 46 | /* 802.3ae 10Gb/s MDIO Manageable Device(MMD) |
47 | */ | 47 | */ |
48 | #define MMD_RESERVED 0 | 48 | enum { |
49 | #define MMD_PMAPMD 1 | 49 | MMD_RESERVED, |
50 | #define MMD_WIS 2 | 50 | MMD_PMAPMD, |
51 | #define MMD_PCS 3 | 51 | MMD_WIS, |
52 | #define MMD_PHY_XGXS 4 /* XGMII Extender Sublayer */ | 52 | MMD_PCS, |
53 | #define MMD_DTE_XGXS 5 | 53 | MMD_PHY_XGXS, /* XGMII Extender Sublayer */ |
54 | MMD_DTE_XGXS, | ||
55 | }; | ||
54 | 56 | ||
55 | #define PHY_XGXS_CTRL_1 0 | 57 | enum { |
56 | #define PHY_XGXS_STATUS_1 1 | 58 | PHY_XGXS_CTRL_1, |
59 | PHY_XGXS_STATUS_1 | ||
60 | }; | ||
57 | 61 | ||
58 | #define OFFSET(REG_ADDR) (REG_ADDR << 2) | 62 | #define OFFSET(REG_ADDR) (REG_ADDR << 2) |
59 | 63 | ||
@@ -160,9 +164,9 @@ static int pm3393_interrupt_enable(struct cmac *cmac) | |||
160 | 0 /*SUNI1x10GEXP_BITMSK_TOP_INTE */ ); | 164 | 0 /*SUNI1x10GEXP_BITMSK_TOP_INTE */ ); |
161 | 165 | ||
162 | /* TERMINATOR - PL_INTERUPTS_EXT */ | 166 | /* TERMINATOR - PL_INTERUPTS_EXT */ |
163 | pl_intr = t1_read_reg_4(cmac->adapter, A_PL_ENABLE); | 167 | pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE); |
164 | pl_intr |= F_PL_INTR_EXT; | 168 | pl_intr |= F_PL_INTR_EXT; |
165 | t1_write_reg_4(cmac->adapter, A_PL_ENABLE, pl_intr); | 169 | writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE); |
166 | return 0; | 170 | return 0; |
167 | } | 171 | } |
168 | 172 | ||
@@ -242,9 +246,9 @@ static int pm3393_interrupt_clear(struct cmac *cmac) | |||
242 | 246 | ||
243 | /* TERMINATOR - PL_INTERUPTS_EXT | 247 | /* TERMINATOR - PL_INTERUPTS_EXT |
244 | */ | 248 | */ |
245 | pl_intr = t1_read_reg_4(cmac->adapter, A_PL_CAUSE); | 249 | pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE); |
246 | pl_intr |= F_PL_INTR_EXT; | 250 | pl_intr |= F_PL_INTR_EXT; |
247 | t1_write_reg_4(cmac->adapter, A_PL_CAUSE, pl_intr); | 251 | writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE); |
248 | 252 | ||
249 | return 0; | 253 | return 0; |
250 | } | 254 | } |
@@ -261,8 +265,6 @@ static int pm3393_interrupt_handler(struct cmac *cmac) | |||
261 | /* Read the master interrupt status register. */ | 265 | /* Read the master interrupt status register. */ |
262 | pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, | 266 | pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, |
263 | &master_intr_status); | 267 | &master_intr_status); |
264 | CH_DBG(cmac->adapter, INTR, "PM3393 intr cause 0x%x\n", | ||
265 | master_intr_status); | ||
266 | 268 | ||
267 | /* TBD XXX Lets just clear everything for now */ | 269 | /* TBD XXX Lets just clear everything for now */ |
268 | pm3393_interrupt_clear(cmac); | 270 | pm3393_interrupt_clear(cmac); |
@@ -703,10 +705,9 @@ static struct cmac *pm3393_mac_create(adapter_t *adapter, int index) | |||
703 | 705 | ||
704 | t1_tpi_write(adapter, OFFSET(0x3040), 0x0c32); /* # TXXG Config */ | 706 | t1_tpi_write(adapter, OFFSET(0x3040), 0x0c32); /* # TXXG Config */ |
705 | /* For T1 use timer based Mac flow control. */ | 707 | /* For T1 use timer based Mac flow control. */ |
706 | if (t1_is_T1B(adapter)) | 708 | t1_tpi_write(adapter, OFFSET(0x304d), 0x8000); |
707 | t1_tpi_write(adapter, OFFSET(0x304d), 0x8000); | ||
708 | t1_tpi_write(adapter, OFFSET(0x2040), 0x059c); /* # RXXG Config */ | 709 | t1_tpi_write(adapter, OFFSET(0x2040), 0x059c); /* # RXXG Config */ |
709 | t1_tpi_write(adapter, OFFSET(0x2049), 0x0000); /* # RXXG Cut Through */ | 710 | t1_tpi_write(adapter, OFFSET(0x2049), 0x0001); /* # RXXG Cut Through */ |
710 | t1_tpi_write(adapter, OFFSET(0x2070), 0x0000); /* # Disable promiscuous mode */ | 711 | t1_tpi_write(adapter, OFFSET(0x2070), 0x0000); /* # Disable promiscuous mode */ |
711 | 712 | ||
712 | /* Setup Exact Match Filter 0 to allow broadcast packets. | 713 | /* Setup Exact Match Filter 0 to allow broadcast packets. |
@@ -814,12 +815,6 @@ static int pm3393_mac_reset(adapter_t * adapter) | |||
814 | 815 | ||
815 | successful_reset = (is_pl4_reset_finished && !is_pl4_outof_lock | 816 | successful_reset = (is_pl4_reset_finished && !is_pl4_outof_lock |
816 | && is_xaui_mabc_pll_locked); | 817 | && is_xaui_mabc_pll_locked); |
817 | |||
818 | CH_DBG(adapter, HW, | ||
819 | "PM3393 HW reset %d: pl4_reset 0x%x, val 0x%x, " | ||
820 | "is_pl4_outof_lock 0x%x, xaui_locked 0x%x\n", | ||
821 | i, is_pl4_reset_finished, val, is_pl4_outof_lock, | ||
822 | is_xaui_mabc_pll_locked); | ||
823 | } | 818 | } |
824 | return successful_reset ? 0 : 1; | 819 | return successful_reset ? 0 : 1; |
825 | } | 820 | } |