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path: root/drivers/net/chelsio/mv88x201x.c
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Diffstat (limited to 'drivers/net/chelsio/mv88x201x.c')
-rw-r--r--drivers/net/chelsio/mv88x201x.c50
1 files changed, 26 insertions, 24 deletions
diff --git a/drivers/net/chelsio/mv88x201x.c b/drivers/net/chelsio/mv88x201x.c
index cd856041af34..f7136b2fd1e5 100644
--- a/drivers/net/chelsio/mv88x201x.c
+++ b/drivers/net/chelsio/mv88x201x.c
@@ -53,7 +53,7 @@ static int led_init(struct cphy *cphy)
53 * Writing these bits maps control to another 53 * Writing these bits maps control to another
54 * register. mmd(0x1) addr(0x7) 54 * register. mmd(0x1) addr(0x7)
55 */ 55 */
56 mdio_write(cphy, 0x3, 0x8304, 0xdddd); 56 cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8304, 0xdddd);
57 return 0; 57 return 0;
58} 58}
59 59
@@ -62,14 +62,14 @@ static int led_link(struct cphy *cphy, u32 do_enable)
62 u32 led = 0; 62 u32 led = 0;
63#define LINK_ENABLE_BIT 0x1 63#define LINK_ENABLE_BIT 0x1
64 64
65 mdio_read(cphy, 0x1, 0x7, &led); 65 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, &led);
66 66
67 if (do_enable & LINK_ENABLE_BIT) { 67 if (do_enable & LINK_ENABLE_BIT) {
68 led |= LINK_ENABLE_BIT; 68 led |= LINK_ENABLE_BIT;
69 mdio_write(cphy, 0x1, 0x7, led); 69 cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, led);
70 } else { 70 } else {
71 led &= ~LINK_ENABLE_BIT; 71 led &= ~LINK_ENABLE_BIT;
72 mdio_write(cphy, 0x1, 0x7, led); 72 cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, led);
73 } 73 }
74 return 0; 74 return 0;
75} 75}
@@ -86,7 +86,8 @@ static int mv88x201x_reset(struct cphy *cphy, int wait)
86static int mv88x201x_interrupt_enable(struct cphy *cphy) 86static int mv88x201x_interrupt_enable(struct cphy *cphy)
87{ 87{
88 /* Enable PHY LASI interrupts. */ 88 /* Enable PHY LASI interrupts. */
89 mdio_write(cphy, 0x1, 0x9002, 0x1); 89 cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
90 MDIO_PMA_LASI_LSALARM);
90 91
91 /* Enable Marvell interrupts through Elmer0. */ 92 /* Enable Marvell interrupts through Elmer0. */
92 if (t1_is_asic(cphy->adapter)) { 93 if (t1_is_asic(cphy->adapter)) {
@@ -102,7 +103,7 @@ static int mv88x201x_interrupt_enable(struct cphy *cphy)
102static int mv88x201x_interrupt_disable(struct cphy *cphy) 103static int mv88x201x_interrupt_disable(struct cphy *cphy)
103{ 104{
104 /* Disable PHY LASI interrupts. */ 105 /* Disable PHY LASI interrupts. */
105 mdio_write(cphy, 0x1, 0x9002, 0x0); 106 cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, 0x0);
106 107
107 /* Disable Marvell interrupts through Elmer0. */ 108 /* Disable Marvell interrupts through Elmer0. */
108 if (t1_is_asic(cphy->adapter)) { 109 if (t1_is_asic(cphy->adapter)) {
@@ -122,25 +123,25 @@ static int mv88x201x_interrupt_clear(struct cphy *cphy)
122 123
123#ifdef MV88x2010_LINK_STATUS_BUGS 124#ifdef MV88x2010_LINK_STATUS_BUGS
124 /* Required to read twice before clear takes affect. */ 125 /* Required to read twice before clear takes affect. */
125 mdio_read(cphy, 0x1, 0x9003, &val); 126 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val);
126 mdio_read(cphy, 0x1, 0x9004, &val); 127 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val);
127 mdio_read(cphy, 0x1, 0x9005, &val); 128 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);
128 129
129 /* Read this register after the others above it else 130 /* Read this register after the others above it else
130 * the register doesn't clear correctly. 131 * the register doesn't clear correctly.
131 */ 132 */
132 mdio_read(cphy, 0x1, 0x1, &val); 133 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
133#endif 134#endif
134 135
135 /* Clear link status. */ 136 /* Clear link status. */
136 mdio_read(cphy, 0x1, 0x1, &val); 137 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
137 /* Clear PHY LASI interrupts. */ 138 /* Clear PHY LASI interrupts. */
138 mdio_read(cphy, 0x1, 0x9005, &val); 139 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);
139 140
140#ifdef MV88x2010_LINK_STATUS_BUGS 141#ifdef MV88x2010_LINK_STATUS_BUGS
141 /* Do it again. */ 142 /* Do it again. */
142 mdio_read(cphy, 0x1, 0x9003, &val); 143 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val);
143 mdio_read(cphy, 0x1, 0x9004, &val); 144 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val);
144#endif 145#endif
145 146
146 /* Clear Marvell interrupts through Elmer0. */ 147 /* Clear Marvell interrupts through Elmer0. */
@@ -172,13 +173,12 @@ static int mv88x201x_get_link_status(struct cphy *cphy, int *link_ok,
172 int *speed, int *duplex, int *fc) 173 int *speed, int *duplex, int *fc)
173{ 174{
174 u32 val = 0; 175 u32 val = 0;
175#define LINK_STATUS_BIT 0x4
176 176
177 if (link_ok) { 177 if (link_ok) {
178 /* Read link status. */ 178 /* Read link status. */
179 mdio_read(cphy, 0x1, 0x1, &val); 179 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
180 val &= LINK_STATUS_BIT; 180 val &= MDIO_STAT1_LSTATUS;
181 *link_ok = (val == LINK_STATUS_BIT); 181 *link_ok = (val == MDIO_STAT1_LSTATUS);
182 /* Turn on/off Link LED */ 182 /* Turn on/off Link LED */
183 led_link(cphy, *link_ok); 183 led_link(cphy, *link_ok);
184 } 184 }
@@ -205,9 +205,11 @@ static struct cphy_ops mv88x201x_ops = {
205 .interrupt_handler = mv88x201x_interrupt_handler, 205 .interrupt_handler = mv88x201x_interrupt_handler,
206 .get_link_status = mv88x201x_get_link_status, 206 .get_link_status = mv88x201x_get_link_status,
207 .set_loopback = mv88x201x_set_loopback, 207 .set_loopback = mv88x201x_set_loopback,
208 .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
209 MDIO_DEVS_PHYXS | MDIO_DEVS_WIS),
208}; 210};
209 211
210static struct cphy *mv88x201x_phy_create(adapter_t *adapter, int phy_addr, 212static struct cphy *mv88x201x_phy_create(struct net_device *dev, int phy_addr,
211 const struct mdio_ops *mdio_ops) 213 const struct mdio_ops *mdio_ops)
212{ 214{
213 u32 val; 215 u32 val;
@@ -216,15 +218,15 @@ static struct cphy *mv88x201x_phy_create(adapter_t *adapter, int phy_addr,
216 if (!cphy) 218 if (!cphy)
217 return NULL; 219 return NULL;
218 220
219 cphy_init(cphy, adapter, phy_addr, &mv88x201x_ops, mdio_ops); 221 cphy_init(cphy, dev, phy_addr, &mv88x201x_ops, mdio_ops);
220 222
221 /* Commands the PHY to enable XFP's clock. */ 223 /* Commands the PHY to enable XFP's clock. */
222 mdio_read(cphy, 0x3, 0x8300, &val); 224 cphy_mdio_read(cphy, MDIO_MMD_PCS, 0x8300, &val);
223 mdio_write(cphy, 0x3, 0x8300, val | 1); 225 cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8300, val | 1);
224 226
225 /* Clear link status. Required because of a bug in the PHY. */ 227 /* Clear link status. Required because of a bug in the PHY. */
226 mdio_read(cphy, 0x1, 0x8, &val); 228 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT2, &val);
227 mdio_read(cphy, 0x3, 0x8, &val); 229 cphy_mdio_read(cphy, MDIO_MMD_PCS, MDIO_STAT2, &val);
228 230
229 /* Allows for Link,Ack LED turn on/off */ 231 /* Allows for Link,Ack LED turn on/off */
230 led_init(cphy); 232 led_init(cphy);