1 files changed, 64 insertions, 104 deletions

diff --git a/drivers/net/chelsio/espi.c b/drivers/net/chelsio/espi.c
index 7ec2dc7bafac..230642571c92 100644
--- a/drivers/net/chelsio/espi.c
+++ b/drivers/net/chelsio/espi.c
@@ -1,8 +1,8 @@
 /*****************************************************************************
  *                                                                           *
  * File: espi.c                                                              *
- * $Revision: 1.9 $                                                          *
- * $Date: 2005/03/23 07:41:27 $                                              *
+ * $Revision: 1.14 $                                                         *
+ * $Date: 2005/05/14 00:59:32 $                                              *
  * Description:                                                              *
  *  Ethernet SPI functionality.                                              *
  *  part of the Chelsio 10Gb Ethernet Driver.                                *
@@ -63,15 +63,16 @@ static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr,
 {
         int busy, attempts = TRICN_CMD_ATTEMPTS;
 
-        t1_write_reg_4(adapter, A_ESPI_CMD_ADDR, V_WRITE_DATA(wr_data) |
-                       V_REGISTER_OFFSET(reg_offset) |
-                       V_CHANNEL_ADDR(ch_addr) | V_MODULE_ADDR(module_addr) |
-                       V_BUNDLE_ADDR(bundle_addr) |
-                       V_SPI4_COMMAND(TRICN_CMD_WRITE));
-        t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0);
+        writel(V_WRITE_DATA(wr_data) |
+               V_REGISTER_OFFSET(reg_offset) |
+               V_CHANNEL_ADDR(ch_addr) | V_MODULE_ADDR(module_addr) |
+               V_BUNDLE_ADDR(bundle_addr) |
+               V_SPI4_COMMAND(TRICN_CMD_WRITE),
+               adapter->regs + A_ESPI_CMD_ADDR);
+        writel(0, adapter->regs + A_ESPI_GOSTAT);
 
         do {
-                busy = t1_read_reg_4(adapter, A_ESPI_GOSTAT) & F_ESPI_CMD_BUSY;
+                busy = readl(adapter->regs + A_ESPI_GOSTAT) & F_ESPI_CMD_BUSY;
         } while (busy && --attempts);
 
         if (busy)
@@ -99,12 +100,12 @@ static int tricn_init(adapter_t *adapter)
         /* 1 */
         timeout=1000;
         do {
-                stat = t1_read_reg_4(adapter, A_ESPI_RX_RESET);
+                stat = readl(adapter->regs + A_ESPI_RX_RESET);
                 is_ready = (stat & 0x4);
                 timeout--;
                 udelay(5);
         } while (!is_ready || (timeout==0));
-        t1_write_reg_4(adapter, A_ESPI_RX_RESET, 0x2);
+        writel(0x2, adapter->regs + A_ESPI_RX_RESET);
         if (timeout==0)
         {
                 CH_ERR("ESPI : ERROR : Timeout tricn_init() \n");
@@ -127,14 +128,14 @@ static int tricn_init(adapter_t *adapter)
         for (i=8; i<= 8; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xf1);
 
         /* 3 */
-        t1_write_reg_4(adapter, A_ESPI_RX_RESET, 0x3);
+        writel(0x3, adapter->regs + A_ESPI_RX_RESET);
 
         return 0;
 }
 
 void t1_espi_intr_enable(struct peespi *espi)
 {
-        u32 enable, pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE);
+        u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE);
 
         /*
          * Cannot enable ESPI interrupts on T1B because HW asserts the
@@ -144,28 +145,28 @@ void t1_espi_intr_enable(struct peespi *espi)
          * cannot be cleared (HW bug).
          */
         enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK;
-        t1_write_reg_4(espi->adapter, A_ESPI_INTR_ENABLE, enable);
-        t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr | F_PL_INTR_ESPI);
+        writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE);
+        writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
 }
 
 void t1_espi_intr_clear(struct peespi *espi)
 {
-        t1_write_reg_4(espi->adapter, A_ESPI_INTR_STATUS, 0xffffffff);
-        t1_write_reg_4(espi->adapter, A_PL_CAUSE, F_PL_INTR_ESPI);
+        writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS);
+        writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE);
 }
 
 void t1_espi_intr_disable(struct peespi *espi)
 {
-        u32 pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE);
+        u32 pl_intr = readl(espi->adapter->regs + A_PL_ENABLE);
 
-        t1_write_reg_4(espi->adapter, A_ESPI_INTR_ENABLE, 0);
-        t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr & ~F_PL_INTR_ESPI);
+        writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE);
+        writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
 }
 
 int t1_espi_intr_handler(struct peespi *espi)
 {
         u32 cnt;
-        u32 status = t1_read_reg_4(espi->adapter, A_ESPI_INTR_STATUS);
+        u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS);
 
         if (status & F_DIP4ERR)
                 espi->intr_cnt.DIP4_err++;
@@ -184,7 +185,7 @@ int t1_espi_intr_handler(struct peespi *espi)
                  * Must read the error count to clear the interrupt
                  * that it causes.
                  */
-                cnt = t1_read_reg_4(espi->adapter, A_ESPI_DIP2_ERR_COUNT);
+                cnt = readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
         }
 
         /*
@@ -193,68 +194,28 @@ int t1_espi_intr_handler(struct peespi *espi)
          */
         if (status && t1_is_T1B(espi->adapter))
                 status = 1;
-        t1_write_reg_4(espi->adapter, A_ESPI_INTR_STATUS, status);
+        writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS);
         return 0;
 }
 
-static void espi_setup_for_pm3393(adapter_t *adapter)
+const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi)
 {
-        u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200;
-
-        t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4);
-        t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f4);
-        t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4);
-        t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN3, 0x1f4);
-        t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x100);
-        t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, wmark);
-        t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 3);
-        t1_write_reg_4(adapter, A_ESPI_TRAIN, 0x08000008);
-        t1_write_reg_4(adapter, A_PORT_CONFIG,
-                       V_RX_NPORTS(1) | V_TX_NPORTS(1));
+    return &espi->intr_cnt;
 }
 
-static void espi_setup_for_vsc7321(adapter_t *adapter)
+static void espi_setup_for_pm3393(adapter_t *adapter)
 {
         u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200;
 
-        t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4);
-        t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f4);
-        t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4);
-        t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN3, 0x1f4);
-        t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x100);
-        t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, wmark);
-        t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 3);
-        t1_write_reg_4(adapter, A_ESPI_TRAIN, 0x08000008);
-        t1_write_reg_4(adapter, A_PORT_CONFIG,
-                       V_RX_NPORTS(1) | V_TX_NPORTS(1));
-}
-
-/*
- * Note that T1B requires at least 2 ports for IXF1010 due to a HW bug.
- */
-static void espi_setup_for_ixf1010(adapter_t *adapter, int nports)
-{
-        t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 1);
-        if (nports == 4) {
-                if (is_T2(adapter)) {
-                        t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK,
-                                0xf00);
-                        t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK,
-                                0x3c0);
-                } else {
-                        t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK,
-                               0x7ff);
-                        t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK,
-                               0x1ff);
-                }
-        } else {
-                t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK,
-                               0x1fff);
-                t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK,
-                               0x7ff);
-        }
-        t1_write_reg_4(adapter, A_PORT_CONFIG,
-                       V_RX_NPORTS(nports) | V_TX_NPORTS(nports));
+        writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);
+        writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1);
+        writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);
+        writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN3);
+        writel(0x100, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
+        writel(wmark, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
+        writel(3, adapter->regs + A_ESPI_CALENDAR_LENGTH);
+        writel(0x08000008, adapter->regs + A_ESPI_TRAIN);
+        writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG);
 }
 
 /* T2 Init part --  */
@@ -263,43 +224,42 @@ static void espi_setup_for_ixf1010(adapter_t *adapter, int nports)
 /* 3. Init TriCN Hard Macro */
 int t1_espi_init(struct peespi *espi, int mac_type, int nports)
 {
+        u32 cnt;
+
         u32 status_enable_extra = 0;
         adapter_t *adapter = espi->adapter;
-        u32 cnt;
         u32 status, burstval = 0x800100;
 
         /* Disable ESPI training.  MACs that can handle it enable it below. */
-        t1_write_reg_4(adapter, A_ESPI_TRAIN, 0);
+        writel(0, adapter->regs + A_ESPI_TRAIN);
 
         if (is_T2(adapter)) {
-                t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
-                               V_OUT_OF_SYNC_COUNT(4) |
-                               V_DIP2_PARITY_ERR_THRES(3) | V_DIP4_THRES(1));
+                writel(V_OUT_OF_SYNC_COUNT(4) |
+                       V_DIP2_PARITY_ERR_THRES(3) |
+                       V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL);
                 if (nports == 4) {
                         /* T204: maxburst1 = 0x40, maxburst2 = 0x20 */
                         burstval = 0x200040;
                 }
         }
-        t1_write_reg_4(adapter, A_ESPI_MAXBURST1_MAXBURST2, burstval);
+        writel(burstval, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
 
-        if (mac_type == CHBT_MAC_PM3393)
+        switch (mac_type) {
+        case CHBT_MAC_PM3393:
                 espi_setup_for_pm3393(adapter);
-        else if (mac_type == CHBT_MAC_VSC7321)
-                espi_setup_for_vsc7321(adapter);
-        else if (mac_type == CHBT_MAC_IXF1010) {
-                status_enable_extra = F_INTEL1010MODE;
-                espi_setup_for_ixf1010(adapter, nports);
-        } else
+                break;
+        default:
                 return -1;
+        }
 
         /*
          * Make sure any pending interrupts from the SPI are
          * Cleared before enabling the interrupt.
          */
-        t1_write_reg_4(espi->adapter, A_ESPI_INTR_ENABLE, ESPI_INTR_MASK);
-        status = t1_read_reg_4(espi->adapter, A_ESPI_INTR_STATUS);
+        writel(ESPI_INTR_MASK, espi->adapter->regs + A_ESPI_INTR_ENABLE);
+        status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS);
         if (status & F_DIP2PARITYERR) {
-                cnt = t1_read_reg_4(espi->adapter, A_ESPI_DIP2_ERR_COUNT);
+                cnt = readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
         }
 
         /*
@@ -308,10 +268,10 @@ int t1_espi_init(struct peespi *espi, int mac_type, int nports)
          */
         if (status && t1_is_T1B(espi->adapter))
                 status = 1;
-        t1_write_reg_4(espi->adapter, A_ESPI_INTR_STATUS, status);
+        writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS);
 
-        t1_write_reg_4(adapter, A_ESPI_FIFO_STATUS_ENABLE,
-                       status_enable_extra | F_RXSTATUSENABLE);
+        writel(status_enable_extra | F_RXSTATUSENABLE,
+               adapter->regs + A_ESPI_FIFO_STATUS_ENABLE);
 
         if (is_T2(adapter)) {
                 tricn_init(adapter);
@@ -319,10 +279,10 @@ int t1_espi_init(struct peespi *espi, int mac_type, int nports)
                  * Always position the control at the 1st port egress IN
                  * (sop,eop) counter to reduce PIOs for T/N210 workaround.
                  */
-                espi->misc_ctrl = (t1_read_reg_4(adapter, A_ESPI_MISC_CONTROL)
+                espi->misc_ctrl = (readl(adapter->regs + A_ESPI_MISC_CONTROL)
                                    & ~MON_MASK) | (F_MONITORED_DIRECTION
                                    | F_MONITORED_INTERFACE);
-                t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
+                writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
                 spin_lock_init(&espi->lock);
         }
 
@@ -354,15 +314,16 @@ void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val)
         spin_lock(&espi->lock);
         espi->misc_ctrl = (val & ~MON_MASK) |
                           (espi->misc_ctrl & MON_MASK);
-        t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
+        writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
         spin_unlock(&espi->lock);
 }
 
 u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait)
 {
-        struct peespi *espi = adapter->espi;
         u32 sel;
 
+        struct peespi *espi = adapter->espi;
+
         if (!is_T2(adapter))
                 return 0;
         sel = V_MONITORED_PORT_NUM((addr & 0x3c) >> 2);
@@ -373,14 +334,13 @@ u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait)
         else
                 spin_lock(&espi->lock);
         if ((sel != (espi->misc_ctrl & MON_MASK))) {
-                t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
-                               ((espi->misc_ctrl & ~MON_MASK) | sel));
-                sel = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3);
-                t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
-                               espi->misc_ctrl);
+                writel(((espi->misc_ctrl & ~MON_MASK) | sel),
+                       adapter->regs + A_ESPI_MISC_CONTROL);
+                sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
+                writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
         }
         else
-                sel = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3);
+                sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
         spin_unlock(&espi->lock);
         return sel;
 }