aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/cassini.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/cassini.h')
-rw-r--r--drivers/net/cassini.h766
1 files changed, 383 insertions, 383 deletions
diff --git a/drivers/net/cassini.h b/drivers/net/cassini.h
index ab55c7ee1012..a970804487c7 100644
--- a/drivers/net/cassini.h
+++ b/drivers/net/cassini.h
@@ -21,7 +21,7 @@
21 * 21 *
22 * vendor id: 0x108E (Sun Microsystems, Inc.) 22 * vendor id: 0x108E (Sun Microsystems, Inc.)
23 * device id: 0xabba (Cassini) 23 * device id: 0xabba (Cassini)
24 * revision ids: 0x01 = Cassini 24 * revision ids: 0x01 = Cassini
25 * 0x02 = Cassini rev 2 25 * 0x02 = Cassini rev 2
26 * 0x10 = Cassini+ 26 * 0x10 = Cassini+
27 * 0x11 = Cassini+ 0.2u 27 * 0x11 = Cassini+ 0.2u
@@ -46,16 +46,16 @@
46 * appear in cassini+. REG_MINUS_ addresses only appear in cassini. 46 * appear in cassini+. REG_MINUS_ addresses only appear in cassini.
47 */ 47 */
48#define CAS_ID_REV2 0x02 48#define CAS_ID_REV2 0x02
49#define CAS_ID_REVPLUS 0x10 49#define CAS_ID_REVPLUS 0x10
50#define CAS_ID_REVPLUS02u 0x11 50#define CAS_ID_REVPLUS02u 0x11
51#define CAS_ID_REVSATURNB2 0x30 51#define CAS_ID_REVSATURNB2 0x30
52 52
53/** global resources **/ 53/** global resources **/
54 54
55/* this register sets the weights for the weighted round robin arbiter. e.g., 55/* this register sets the weights for the weighted round robin arbiter. e.g.,
56 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit 56 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
57 * for its next turn to access the pci bus. 57 * for its next turn to access the pci bus.
58 * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8 58 * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8
59 * DEFAULT: 0x0, SIZE: 5 bits 59 * DEFAULT: 0x0, SIZE: 5 bits
60 */ 60 */
61#define REG_CAWR 0x0004 /* core arbitration weight */ 61#define REG_CAWR 0x0004 /* core arbitration weight */
@@ -66,8 +66,8 @@
66#define CAWR_RR_DIS 0x10 /* [4] */ 66#define CAWR_RR_DIS 0x10 /* [4] */
67 67
68/* if enabled, BIM can send bursts across PCI bus > cacheline size. burst 68/* if enabled, BIM can send bursts across PCI bus > cacheline size. burst
69 * sizes determined by length of packet or descriptor transfer and the 69 * sizes determined by length of packet or descriptor transfer and the
70 * max length allowed by the target. 70 * max length allowed by the target.
71 * DEFAULT: 0x0, SIZE: 1 bit 71 * DEFAULT: 0x0, SIZE: 1 bit
72 */ 72 */
73#define REG_INF_BURST 0x0008 /* infinite burst enable reg */ 73#define REG_INF_BURST 0x0008 /* infinite burst enable reg */
@@ -75,21 +75,21 @@
75 75
76/* top level interrupts [0-9] are auto-cleared to 0 when the status 76/* top level interrupts [0-9] are auto-cleared to 0 when the status
77 * register is read. second level interrupts [13 - 18] are cleared at 77 * register is read. second level interrupts [13 - 18] are cleared at
78 * the source. tx completion register 3 is replicated in [19 - 31] 78 * the source. tx completion register 3 is replicated in [19 - 31]
79 * DEFAULT: 0x00000000, SIZE: 29 bits 79 * DEFAULT: 0x00000000, SIZE: 29 bits
80 */ 80 */
81#define REG_INTR_STATUS 0x000C /* interrupt status register */ 81#define REG_INTR_STATUS 0x000C /* interrupt status register */
82#define INTR_TX_INTME 0x00000001 /* frame w/ INT ME desc bit set 82#define INTR_TX_INTME 0x00000001 /* frame w/ INT ME desc bit set
83 xferred from host queue to 83 xferred from host queue to
84 TX FIFO */ 84 TX FIFO */
85#define INTR_TX_ALL 0x00000002 /* all xmit frames xferred into 85#define INTR_TX_ALL 0x00000002 /* all xmit frames xferred into
86 TX FIFO. i.e., 86 TX FIFO. i.e.,
87 TX Kick == TX complete. if 87 TX Kick == TX complete. if
88 PACED_MODE set, then TX FIFO 88 PACED_MODE set, then TX FIFO
89 also empty */ 89 also empty */
90#define INTR_TX_DONE 0x00000004 /* any frame xferred into tx 90#define INTR_TX_DONE 0x00000004 /* any frame xferred into tx
91 FIFO */ 91 FIFO */
92#define INTR_TX_TAG_ERROR 0x00000008 /* TX FIFO tag framing 92#define INTR_TX_TAG_ERROR 0x00000008 /* TX FIFO tag framing
93 corrupted. FATAL ERROR */ 93 corrupted. FATAL ERROR */
94#define INTR_RX_DONE 0x00000010 /* at least 1 frame xferred 94#define INTR_RX_DONE 0x00000010 /* at least 1 frame xferred
95 from RX FIFO to host mem. 95 from RX FIFO to host mem.
@@ -98,18 +98,18 @@
98 intr blanking. */ 98 intr blanking. */
99#define INTR_RX_BUF_UNAVAIL 0x00000020 /* no more receive buffers. 99#define INTR_RX_BUF_UNAVAIL 0x00000020 /* no more receive buffers.
100 RX Kick == RX complete */ 100 RX Kick == RX complete */
101#define INTR_RX_TAG_ERROR 0x00000040 /* RX FIFO tag framing 101#define INTR_RX_TAG_ERROR 0x00000040 /* RX FIFO tag framing
102 corrupted. FATAL ERROR */ 102 corrupted. FATAL ERROR */
103#define INTR_RX_COMP_FULL 0x00000080 /* no more room in completion 103#define INTR_RX_COMP_FULL 0x00000080 /* no more room in completion
104 ring to post descriptors. 104 ring to post descriptors.
105 RX complete head incr to 105 RX complete head incr to
106 almost reach RX complete 106 almost reach RX complete
107 tail */ 107 tail */
108#define INTR_RX_BUF_AE 0x00000100 /* less than the 108#define INTR_RX_BUF_AE 0x00000100 /* less than the
109 programmable threshold # 109 programmable threshold #
110 of free descr avail for 110 of free descr avail for
111 hw use */ 111 hw use */
112#define INTR_RX_COMP_AF 0x00000200 /* less than the 112#define INTR_RX_COMP_AF 0x00000200 /* less than the
113 programmable threshold # 113 programmable threshold #
114 of descr spaces for hw 114 of descr spaces for hw
115 use in completion descr 115 use in completion descr
@@ -119,17 +119,17 @@
119 from fifo during DMA or 119 from fifo during DMA or
120 header parser provides TCP 120 header parser provides TCP
121 header and payload size > 121 header and payload size >
122 MAC packet size. 122 MAC packet size.
123 FATAL ERROR */ 123 FATAL ERROR */
124#define INTR_SUMMARY 0x00001000 /* summary interrupt bit. this 124#define INTR_SUMMARY 0x00001000 /* summary interrupt bit. this
125 bit will be set if an interrupt 125 bit will be set if an interrupt
126 generated on the pci bus. useful 126 generated on the pci bus. useful
127 when driver is polling for 127 when driver is polling for
128 interrupts */ 128 interrupts */
129#define INTR_PCS_STATUS 0x00002000 /* PCS interrupt status register */ 129#define INTR_PCS_STATUS 0x00002000 /* PCS interrupt status register */
130#define INTR_TX_MAC_STATUS 0x00004000 /* TX MAC status register has at 130#define INTR_TX_MAC_STATUS 0x00004000 /* TX MAC status register has at
131 least 1 unmasked interrupt set */ 131 least 1 unmasked interrupt set */
132#define INTR_RX_MAC_STATUS 0x00008000 /* RX MAC status register has at 132#define INTR_RX_MAC_STATUS 0x00008000 /* RX MAC status register has at
133 least 1 unmasked interrupt set */ 133 least 1 unmasked interrupt set */
134#define INTR_MAC_CTRL_STATUS 0x00010000 /* MAC control status register has 134#define INTR_MAC_CTRL_STATUS 0x00010000 /* MAC control status register has
135 at least 1 unmasked interrupt 135 at least 1 unmasked interrupt
@@ -137,9 +137,9 @@
137#define INTR_MIF_STATUS 0x00020000 /* MIF status register has at least 137#define INTR_MIF_STATUS 0x00020000 /* MIF status register has at least
138 1 unmasked interrupt set */ 138 1 unmasked interrupt set */
139#define INTR_PCI_ERROR_STATUS 0x00040000 /* PCI error status register in the 139#define INTR_PCI_ERROR_STATUS 0x00040000 /* PCI error status register in the
140 BIF has at least 1 unmasked 140 BIF has at least 1 unmasked
141 interrupt set */ 141 interrupt set */
142#define INTR_TX_COMP_3_MASK 0xFFF80000 /* mask for TX completion 142#define INTR_TX_COMP_3_MASK 0xFFF80000 /* mask for TX completion
143 3 reg data */ 143 3 reg data */
144#define INTR_TX_COMP_3_SHIFT 19 144#define INTR_TX_COMP_3_SHIFT 19
145#define INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \ 145#define INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \
@@ -149,7 +149,7 @@
149 INTR_MAC_CTRL_STATUS) 149 INTR_MAC_CTRL_STATUS)
150 150
151/* determines which status events will cause an interrupt. layout same 151/* determines which status events will cause an interrupt. layout same
152 * as REG_INTR_STATUS. 152 * as REG_INTR_STATUS.
153 * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits 153 * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits
154 */ 154 */
155#define REG_INTR_MASK 0x0010 /* Interrupt mask */ 155#define REG_INTR_MASK 0x0010 /* Interrupt mask */
@@ -158,18 +158,18 @@
158 * useful when driver is polling for interrupts. layout same as REG_INTR_MASK. 158 * useful when driver is polling for interrupts. layout same as REG_INTR_MASK.
159 * DEFAULT: 0x00000000, SIZE: 12 bits 159 * DEFAULT: 0x00000000, SIZE: 12 bits
160 */ 160 */
161#define REG_ALIAS_CLEAR 0x0014 /* alias clear mask 161#define REG_ALIAS_CLEAR 0x0014 /* alias clear mask
162 (used w/ status alias) */ 162 (used w/ status alias) */
163/* same as REG_INTR_STATUS except that only bits cleared are those selected by 163/* same as REG_INTR_STATUS except that only bits cleared are those selected by
164 * REG_ALIAS_CLEAR 164 * REG_ALIAS_CLEAR
165 * DEFAULT: 0x00000000, SIZE: 29 bits 165 * DEFAULT: 0x00000000, SIZE: 29 bits
166 */ 166 */
167#define REG_INTR_STATUS_ALIAS 0x001C /* interrupt status alias 167#define REG_INTR_STATUS_ALIAS 0x001C /* interrupt status alias
168 (selective clear) */ 168 (selective clear) */
169 169
170/* DEFAULT: 0x0, SIZE: 3 bits */ 170/* DEFAULT: 0x0, SIZE: 3 bits */
171#define REG_PCI_ERR_STATUS 0x1000 /* PCI error status */ 171#define REG_PCI_ERR_STATUS 0x1000 /* PCI error status */
172#define PCI_ERR_BADACK 0x01 /* reserved in Cassini+. 172#define PCI_ERR_BADACK 0x01 /* reserved in Cassini+.
173 set if no ACK64# during ABS64 cycle 173 set if no ACK64# during ABS64 cycle
174 in Cassini. */ 174 in Cassini. */
175#define PCI_ERR_DTRTO 0x02 /* delayed xaction timeout. set if 175#define PCI_ERR_DTRTO 0x02 /* delayed xaction timeout. set if
@@ -179,16 +179,16 @@
179 unused in Cassini. */ 179 unused in Cassini. */
180#define PCI_ERR_BIM_DMA_READ 0x10 /* BIM received 0 count DMA read req. 180#define PCI_ERR_BIM_DMA_READ 0x10 /* BIM received 0 count DMA read req.
181 unused in Cassini. */ 181 unused in Cassini. */
182#define PCI_ERR_BIM_DMA_TIMEOUT 0x20 /* BIM received 255 retries during 182#define PCI_ERR_BIM_DMA_TIMEOUT 0x20 /* BIM received 255 retries during
183 DMA. unused in cassini. */ 183 DMA. unused in cassini. */
184 184
185/* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event 185/* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event
186 * causes an interrupt to be generated. 186 * causes an interrupt to be generated.
187 * DEFAULT: 0x7, SIZE: 3 bits 187 * DEFAULT: 0x7, SIZE: 3 bits
188 */ 188 */
189#define REG_PCI_ERR_STATUS_MASK 0x1004 /* PCI Error status mask */ 189#define REG_PCI_ERR_STATUS_MASK 0x1004 /* PCI Error status mask */
190 190
191/* used to configure PCI related parameters that are not in PCI config space. 191/* used to configure PCI related parameters that are not in PCI config space.
192 * DEFAULT: 0bxx000, SIZE: 5 bits 192 * DEFAULT: 0bxx000, SIZE: 5 bits
193 */ 193 */
194#define REG_BIM_CFG 0x1008 /* BIM Configuration */ 194#define REG_BIM_CFG 0x1008 /* BIM Configuration */
@@ -201,7 +201,7 @@
201#define BIM_CFG_RMA_INTR_ENABLE 0x040 /* master abort intr enable */ 201#define BIM_CFG_RMA_INTR_ENABLE 0x040 /* master abort intr enable */
202#define BIM_CFG_RTA_INTR_ENABLE 0x080 /* target abort intr enable */ 202#define BIM_CFG_RTA_INTR_ENABLE 0x080 /* target abort intr enable */
203#define BIM_CFG_RESERVED2 0x100 /* reserved */ 203#define BIM_CFG_RESERVED2 0x100 /* reserved */
204#define BIM_CFG_BIM_DISABLE 0x200 /* stop BIM DMA. use before global 204#define BIM_CFG_BIM_DISABLE 0x200 /* stop BIM DMA. use before global
205 reset. reserved in Cassini. */ 205 reset. reserved in Cassini. */
206#define BIM_CFG_BIM_STATUS 0x400 /* (ro) 1 = BIM DMA suspended. 206#define BIM_CFG_BIM_STATUS 0x400 /* (ro) 1 = BIM DMA suspended.
207 reserved in Cassini. */ 207 reserved in Cassini. */
@@ -212,7 +212,7 @@
212#define REG_BIM_DIAG 0x100C /* BIM Diagnostic */ 212#define REG_BIM_DIAG 0x100C /* BIM Diagnostic */
213#define BIM_DIAG_MSTR_SM_MASK 0x3FFFFF00 /* PCI master controller state 213#define BIM_DIAG_MSTR_SM_MASK 0x3FFFFF00 /* PCI master controller state
214 machine bits [21:0] */ 214 machine bits [21:0] */
215#define BIM_DIAG_BRST_SM_MASK 0x7F /* PCI burst controller state 215#define BIM_DIAG_BRST_SM_MASK 0x7F /* PCI burst controller state
216 machine bits [6:0] */ 216 machine bits [6:0] */
217 217
218/* writing to SW_RESET_TX and SW_RESET_RX will issue a global 218/* writing to SW_RESET_TX and SW_RESET_RX will issue a global
@@ -224,14 +224,14 @@
224#define SW_RESET_RX 0x00000002 /* reset RX DMA engine. poll until 224#define SW_RESET_RX 0x00000002 /* reset RX DMA engine. poll until
225 cleared to 0. */ 225 cleared to 0. */
226#define SW_RESET_RSTOUT 0x00000004 /* force RSTOUT# pin active (low). 226#define SW_RESET_RSTOUT 0x00000004 /* force RSTOUT# pin active (low).
227 resets PHY and anything else 227 resets PHY and anything else
228 connected to RSTOUT#. RSTOUT# 228 connected to RSTOUT#. RSTOUT#
229 is also activated by local PCI 229 is also activated by local PCI
230 reset when hot-swap is being 230 reset when hot-swap is being
231 done. */ 231 done. */
232#define SW_RESET_BLOCK_PCS_SLINK 0x00000008 /* if a global reset is done with 232#define SW_RESET_BLOCK_PCS_SLINK 0x00000008 /* if a global reset is done with
233 this bit set, PCS and SLINK 233 this bit set, PCS and SLINK
234 modules won't be reset. 234 modules won't be reset.
235 i.e., link won't drop. */ 235 i.e., link won't drop. */
236#define SW_RESET_BREQ_SM_MASK 0x00007F00 /* breq state machine [6:0] */ 236#define SW_RESET_BREQ_SM_MASK 0x00007F00 /* breq state machine [6:0] */
237#define SW_RESET_PCIARB_SM_MASK 0x00070000 /* pci arbitration state bits: 237#define SW_RESET_PCIARB_SM_MASK 0x00070000 /* pci arbitration state bits:
@@ -252,7 +252,7 @@
252 0b01: AD_ACK_RX 252 0b01: AD_ACK_RX
253 0b10: AD_ACK_TX 253 0b10: AD_ACK_TX
254 0b11: AD_IDL_TX */ 254 0b11: AD_IDL_TX */
255#define SW_RESET_WRPCI_SM_MASK 0x06000000 /* write pci state bits 255#define SW_RESET_WRPCI_SM_MASK 0x06000000 /* write pci state bits
256 0b00: WR_PCI_WAT 256 0b00: WR_PCI_WAT
257 0b01: WR_PCI_RDY 257 0b01: WR_PCI_RDY
258 0b11: WR_PCI_ACK */ 258 0b11: WR_PCI_ACK */
@@ -268,7 +268,7 @@
268 * value written has both lower and upper 32-bit halves rotated to the right 268 * value written has both lower and upper 32-bit halves rotated to the right
269 * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF 269 * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF
270 */ 270 */
271#define REG_MINUS_BIM_DATAPATH_TEST 0x1018 /* Cassini: BIM datapath test 271#define REG_MINUS_BIM_DATAPATH_TEST 0x1018 /* Cassini: BIM datapath test
272 Cassini+: reserved */ 272 Cassini+: reserved */
273 273
274/* output enables are provided for each device's chip select and for the rest 274/* output enables are provided for each device's chip select and for the rest
@@ -276,12 +276,12 @@
276 * bits are connected to general purpus control/status bits. 276 * bits are connected to general purpus control/status bits.
277 * DEFAULT: 0x7 277 * DEFAULT: 0x7
278 */ 278 */
279#define REG_BIM_LOCAL_DEV_EN 0x1020 /* BIM local device 279#define REG_BIM_LOCAL_DEV_EN 0x1020 /* BIM local device
280 output EN. default: 0x7 */ 280 output EN. default: 0x7 */
281#define BIM_LOCAL_DEV_PAD 0x01 /* address bus, RW signal, and 281#define BIM_LOCAL_DEV_PAD 0x01 /* address bus, RW signal, and
282 OE signal output enable on the 282 OE signal output enable on the
283 local bus interface. these 283 local bus interface. these
284 are shared between both local 284 are shared between both local
285 bus devices. tristate when 0. */ 285 bus devices. tristate when 0. */
286#define BIM_LOCAL_DEV_PROM 0x02 /* PROM chip select */ 286#define BIM_LOCAL_DEV_PROM 0x02 /* PROM chip select */
287#define BIM_LOCAL_DEV_EXT 0x04 /* secondary local bus device chip 287#define BIM_LOCAL_DEV_EXT 0x04 /* secondary local bus device chip
@@ -291,8 +291,8 @@
291#define BIM_LOCAL_DEV_HW_RESET 0x20 /* internal hw reset. Cassini+ only. */ 291#define BIM_LOCAL_DEV_HW_RESET 0x20 /* internal hw reset. Cassini+ only. */
292 292
293/* access 24 entry BIM read and write buffers. put address in REG_BIM_BUFFER_ADDR 293/* access 24 entry BIM read and write buffers. put address in REG_BIM_BUFFER_ADDR
294 * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI. 294 * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI.
295 * _DATA_HI should be the last access of the sequence. 295 * _DATA_HI should be the last access of the sequence.
296 * DEFAULT: undefined 296 * DEFAULT: undefined
297 */ 297 */
298#define REG_BIM_BUFFER_ADDR 0x1024 /* BIM buffer address. for 298#define REG_BIM_BUFFER_ADDR 0x1024 /* BIM buffer address. for
@@ -304,10 +304,10 @@
304#define REG_BIM_BUFFER_DATA_LOW 0x1028 /* BIM buffer data low */ 304#define REG_BIM_BUFFER_DATA_LOW 0x1028 /* BIM buffer data low */
305#define REG_BIM_BUFFER_DATA_HI 0x102C /* BIM buffer data high */ 305#define REG_BIM_BUFFER_DATA_HI 0x102C /* BIM buffer data high */
306 306
307/* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer. 307/* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer.
308 * bit auto-clears when done with status read from _SUMMARY and _PASS bits. 308 * bit auto-clears when done with status read from _SUMMARY and _PASS bits.
309 */ 309 */
310#define REG_BIM_RAM_BIST 0x102C /* BIM RAM (read buffer) BIST 310#define REG_BIM_RAM_BIST 0x102C /* BIM RAM (read buffer) BIST
311 control/status */ 311 control/status */
312#define BIM_RAM_BIST_RD_START 0x01 /* start BIST for BIM read buffer */ 312#define BIM_RAM_BIST_RD_START 0x01 /* start BIST for BIM read buffer */
313#define BIM_RAM_BIST_WR_START 0x02 /* start BIST for BIM write buffer. 313#define BIM_RAM_BIST_WR_START 0x02 /* start BIST for BIM write buffer.
@@ -321,7 +321,7 @@
321#define BIM_RAM_BIST_RD_LOW_PASS 0x10 /* read low bank passes BIST */ 321#define BIM_RAM_BIST_RD_LOW_PASS 0x10 /* read low bank passes BIST */
322#define BIM_RAM_BIST_RD_HI_PASS 0x20 /* read high bank passes BIST */ 322#define BIM_RAM_BIST_RD_HI_PASS 0x20 /* read high bank passes BIST */
323#define BIM_RAM_BIST_WR_LOW_PASS 0x40 /* write low bank passes BIST. 323#define BIM_RAM_BIST_WR_LOW_PASS 0x40 /* write low bank passes BIST.
324 Cassini only. reserved in 324 Cassini only. reserved in
325 Cassini+. */ 325 Cassini+. */
326#define BIM_RAM_BIST_WR_HI_PASS 0x80 /* write high bank passes BIST. 326#define BIM_RAM_BIST_WR_HI_PASS 0x80 /* write high bank passes BIST.
327 Cassini only. reserved in 327 Cassini only. reserved in
@@ -333,7 +333,7 @@
333#define REG_BIM_DIAG_MUX 0x1030 /* BIM diagnostic probe mux 333#define REG_BIM_DIAG_MUX 0x1030 /* BIM diagnostic probe mux
334 select register */ 334 select register */
335 335
336/* enable probe monitoring mode and select data appearing on the P_A* bus. bit 336/* enable probe monitoring mode and select data appearing on the P_A* bus. bit
337 * values for _SEL_HI_MASK and _SEL_LOW_MASK: 337 * values for _SEL_HI_MASK and _SEL_LOW_MASK:
338 * 0x0: internal probe[7:0] (pci arb state, wtc empty w, wtc full w, wtc empty w, 338 * 0x0: internal probe[7:0] (pci arb state, wtc empty w, wtc full w, wtc empty w,
339 * wtc empty r, post pci) 339 * wtc empty r, post pci)
@@ -353,7 +353,7 @@
353 * 0xe: hp probe[7:0] 0xf: mac probe[7:0] 353 * 0xe: hp probe[7:0] 0xf: mac probe[7:0]
354 */ 354 */
355#define REG_PLUS_PROBE_MUX_SELECT 0x1034 /* Cassini+: PROBE MUX SELECT */ 355#define REG_PLUS_PROBE_MUX_SELECT 0x1034 /* Cassini+: PROBE MUX SELECT */
356#define PROBE_MUX_EN 0x80000000 /* allow probe signals to be 356#define PROBE_MUX_EN 0x80000000 /* allow probe signals to be
357 driven on local bus P_A[15:0] 357 driven on local bus P_A[15:0]
358 for debugging */ 358 for debugging */
359#define PROBE_MUX_SUB_MUX_MASK 0x0000FF00 /* select sub module probe signals: 359#define PROBE_MUX_SUB_MUX_MASK 0x0000FF00 /* select sub module probe signals:
@@ -362,28 +362,28 @@
362 0x30 = tx[1:0] 362 0x30 = tx[1:0]
363 0xC0 = hp[1:0] */ 363 0xC0 = hp[1:0] */
364#define PROBE_MUX_SEL_HI_MASK 0x000000F0 /* select which module to appear 364#define PROBE_MUX_SEL_HI_MASK 0x000000F0 /* select which module to appear
365 on P_A[15:8]. see above for 365 on P_A[15:8]. see above for
366 values. */ 366 values. */
367#define PROBE_MUX_SEL_LOW_MASK 0x0000000F /* select which module to appear 367#define PROBE_MUX_SEL_LOW_MASK 0x0000000F /* select which module to appear
368 on P_A[7:0]. see above for 368 on P_A[7:0]. see above for
369 values. */ 369 values. */
370 370
371/* values mean the same thing as REG_INTR_MASK excep that it's for INTB. 371/* values mean the same thing as REG_INTR_MASK excep that it's for INTB.
372 DEFAULT: 0x1F */ 372 DEFAULT: 0x1F */
373#define REG_PLUS_INTR_MASK_1 0x1038 /* Cassini+: interrupt mask 373#define REG_PLUS_INTR_MASK_1 0x1038 /* Cassini+: interrupt mask
374 register 2 for INTB */ 374 register 2 for INTB */
375#define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16) 375#define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16)
376/* bits correspond to both _MASK and _STATUS registers. _ALT corresponds to 376/* bits correspond to both _MASK and _STATUS registers. _ALT corresponds to
377 * all of the alternate (2-4) INTR registers while _1 corresponds to only 377 * all of the alternate (2-4) INTR registers while _1 corresponds to only
378 * _MASK_1 and _STATUS_1 registers. 378 * _MASK_1 and _STATUS_1 registers.
379 * DEFAULT: 0x7 for MASK registers, 0x0 for ALIAS_CLEAR registers 379 * DEFAULT: 0x7 for MASK registers, 0x0 for ALIAS_CLEAR registers
380 */ 380 */
381#define INTR_RX_DONE_ALT 0x01 381#define INTR_RX_DONE_ALT 0x01
382#define INTR_RX_COMP_FULL_ALT 0x02 382#define INTR_RX_COMP_FULL_ALT 0x02
383#define INTR_RX_COMP_AF_ALT 0x04 383#define INTR_RX_COMP_AF_ALT 0x04
384#define INTR_RX_BUF_UNAVAIL_1 0x08 384#define INTR_RX_BUF_UNAVAIL_1 0x08
385#define INTR_RX_BUF_AE_1 0x10 /* almost empty */ 385#define INTR_RX_BUF_AE_1 0x10 /* almost empty */
386#define INTRN_MASK_RX_EN 0x80 386#define INTRN_MASK_RX_EN 0x80
387#define INTRN_MASK_CLEAR_ALL (INTR_RX_DONE_ALT | \ 387#define INTRN_MASK_CLEAR_ALL (INTR_RX_DONE_ALT | \
388 INTR_RX_COMP_FULL_ALT | \ 388 INTR_RX_COMP_FULL_ALT | \
389 INTR_RX_COMP_AF_ALT | \ 389 INTR_RX_COMP_AF_ALT | \
@@ -399,7 +399,7 @@
399 register 2 for INTB */ 399 register 2 for INTB */
400#define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16) 400#define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16)
401 401
402#define REG_PLUS_INTR_STATUS_ALIAS_1 0x1044 /* Cassini+: interrupt status 402#define REG_PLUS_INTR_STATUS_ALIAS_1 0x1044 /* Cassini+: interrupt status
403 register alias 2 for INTB */ 403 register alias 2 for INTB */
404#define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16) 404#define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16)
405 405
@@ -411,18 +411,18 @@
411#define SATURN_PCFG_CLA 0x00000004 /* 1 = phy link100led */ 411#define SATURN_PCFG_CLA 0x00000004 /* 1 = phy link100led */
412#define SATURN_PCFG_LLA 0x00000008 /* 1 = phy link1000led */ 412#define SATURN_PCFG_LLA 0x00000008 /* 1 = phy link1000led */
413#define SATURN_PCFG_RLA 0x00000010 /* 1 = phy duplexled */ 413#define SATURN_PCFG_RLA 0x00000010 /* 1 = phy duplexled */
414#define SATURN_PCFG_PDS 0x00000020 /* phy debug mode. 414#define SATURN_PCFG_PDS 0x00000020 /* phy debug mode.
415 0 = normal */ 415 0 = normal */
416#define SATURN_PCFG_MTP 0x00000080 /* test point select */ 416#define SATURN_PCFG_MTP 0x00000080 /* test point select */
417#define SATURN_PCFG_GMO 0x00000100 /* GMII observe. 1 = 417#define SATURN_PCFG_GMO 0x00000100 /* GMII observe. 1 =
418 GMII on SERDES pins for 418 GMII on SERDES pins for
419 monitoring. */ 419 monitoring. */
420#define SATURN_PCFG_FSI 0x00000200 /* 1 = freeze serdes/gmii. all 420#define SATURN_PCFG_FSI 0x00000200 /* 1 = freeze serdes/gmii. all
421 pins configed as outputs. 421 pins configed as outputs.
422 for power saving when using 422 for power saving when using
423 internal phy. */ 423 internal phy. */
424#define SATURN_PCFG_LAD 0x00000800 /* 0 = mac core led ctrl 424#define SATURN_PCFG_LAD 0x00000800 /* 0 = mac core led ctrl
425 polarity from strapping 425 polarity from strapping
426 value. 426 value.
427 1 = mac core led ctrl 427 1 = mac core led ctrl
428 polarity active low. */ 428 polarity active low. */
@@ -433,26 +433,26 @@
433#define MAX_TX_RINGS (1 << MAX_TX_RINGS_SHIFT) 433#define MAX_TX_RINGS (1 << MAX_TX_RINGS_SHIFT)
434#define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1) 434#define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1)
435 435
436/* TX configuration. 436/* TX configuration.
437 * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8 437 * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8
438 * DEFAULT: 0x3F000001 438 * DEFAULT: 0x3F000001
439 */ 439 */
440#define REG_TX_CFG 0x2004 /* TX config */ 440#define REG_TX_CFG 0x2004 /* TX config */
441#define TX_CFG_DMA_EN 0x00000001 /* enable TX DMA. if cleared, DMA 441#define TX_CFG_DMA_EN 0x00000001 /* enable TX DMA. if cleared, DMA
442 will stop after xfer of current 442 will stop after xfer of current
443 buffer has been completed. */ 443 buffer has been completed. */
444#define TX_CFG_FIFO_PIO_SEL 0x00000002 /* TX DMA FIFO can be 444#define TX_CFG_FIFO_PIO_SEL 0x00000002 /* TX DMA FIFO can be
445 accessed w/ FIFO addr 445 accessed w/ FIFO addr
446 and data registers. 446 and data registers.
447 TX DMA should be 447 TX DMA should be
448 disabled. */ 448 disabled. */
449#define TX_CFG_DESC_RING0_MASK 0x0000003C /* # desc entries in 449#define TX_CFG_DESC_RING0_MASK 0x0000003C /* # desc entries in
450 ring 1. */ 450 ring 1. */
451#define TX_CFG_DESC_RING0_SHIFT 2 451#define TX_CFG_DESC_RING0_SHIFT 2
452#define TX_CFG_DESC_RINGN_MASK(a) (TX_CFG_DESC_RING0_MASK << (a)*4) 452#define TX_CFG_DESC_RINGN_MASK(a) (TX_CFG_DESC_RING0_MASK << (a)*4)
453#define TX_CFG_DESC_RINGN_SHIFT(a) (TX_CFG_DESC_RING0_SHIFT + (a)*4) 453#define TX_CFG_DESC_RINGN_SHIFT(a) (TX_CFG_DESC_RING0_SHIFT + (a)*4)
454#define TX_CFG_PACED_MODE 0x00100000 /* TX_ALL only set after 454#define TX_CFG_PACED_MODE 0x00100000 /* TX_ALL only set after
455 TX FIFO becomes empty. 455 TX FIFO becomes empty.
456 if 0, TX_ALL set 456 if 0, TX_ALL set
457 if descr queue empty. */ 457 if descr queue empty. */
458#define TX_CFG_DMA_RDPIPE_DIS 0x01000000 /* always set to 1 */ 458#define TX_CFG_DMA_RDPIPE_DIS 0x01000000 /* always set to 1 */
@@ -470,26 +470,26 @@
470 through Q4 */ 470 through Q4 */
471#define TX_CFG_INTR_COMPWB_DIS 0x20000000 /* disable pre-interrupt completion 471#define TX_CFG_INTR_COMPWB_DIS 0x20000000 /* disable pre-interrupt completion
472 writeback */ 472 writeback */
473#define TX_CFG_CTX_SEL_MASK 0xC0000000 /* selects tx test port 473#define TX_CFG_CTX_SEL_MASK 0xC0000000 /* selects tx test port
474 connection 474 connection
475 0b00: tx mac req, 475 0b00: tx mac req,
476 tx mac retry req, 476 tx mac retry req,
477 tx ack and tx tag. 477 tx ack and tx tag.
478 0b01: txdma rd req, 478 0b01: txdma rd req,
479 txdma rd ack, 479 txdma rd ack,
480 txdma rd rdy, 480 txdma rd rdy,
481 txdma rd type0 481 txdma rd type0
482 0b11: txdma wr req, 482 0b11: txdma wr req,
483 txdma wr ack, 483 txdma wr ack,
484 txdma wr rdy, 484 txdma wr rdy,
485 txdma wr xfr done. */ 485 txdma wr xfr done. */
486#define TX_CFG_CTX_SEL_SHIFT 30 486#define TX_CFG_CTX_SEL_SHIFT 30
487 487
488/* 11-bit counters that point to next location in FIFO to be loaded/retrieved. 488/* 11-bit counters that point to next location in FIFO to be loaded/retrieved.
489 * used for diagnostics only. 489 * used for diagnostics only.
490 */ 490 */
491#define REG_TX_FIFO_WRITE_PTR 0x2014 /* TX FIFO write pointer */ 491#define REG_TX_FIFO_WRITE_PTR 0x2014 /* TX FIFO write pointer */
492#define REG_TX_FIFO_SHADOW_WRITE_PTR 0x2018 /* TX FIFO shadow write 492#define REG_TX_FIFO_SHADOW_WRITE_PTR 0x2018 /* TX FIFO shadow write
493 pointer. temp hold reg. 493 pointer. temp hold reg.
494 diagnostics only. */ 494 diagnostics only. */
495#define REG_TX_FIFO_READ_PTR 0x201C /* TX FIFO read pointer */ 495#define REG_TX_FIFO_READ_PTR 0x201C /* TX FIFO read pointer */
@@ -509,7 +509,7 @@
509#define TX_SM_1_CACHE_MASK 0x03C00000 /* desc. prefetch cache controller 509#define TX_SM_1_CACHE_MASK 0x03C00000 /* desc. prefetch cache controller
510 state machine */ 510 state machine */
511#define TX_SM_1_CBQ_ARB_MASK 0xF8000000 /* CBQ arbiter state machine */ 511#define TX_SM_1_CBQ_ARB_MASK 0xF8000000 /* CBQ arbiter state machine */
512 512
513#define REG_TX_SM_2 0x202C /* TX state machine reg #2 */ 513#define REG_TX_SM_2 0x202C /* TX state machine reg #2 */
514#define TX_SM_2_COMP_WB_MASK 0x07 /* completion writeback sm */ 514#define TX_SM_2_COMP_WB_MASK 0x07 /* completion writeback sm */
515#define TX_SM_2_SUB_LOAD_MASK 0x38 /* sub load state machine */ 515#define TX_SM_2_SUB_LOAD_MASK 0x38 /* sub load state machine */
@@ -521,9 +521,9 @@
521#define REG_TX_DATA_PTR_LOW 0x2030 /* TX data pointer low */ 521#define REG_TX_DATA_PTR_LOW 0x2030 /* TX data pointer low */
522#define REG_TX_DATA_PTR_HI 0x2034 /* TX data pointer high */ 522#define REG_TX_DATA_PTR_HI 0x2034 /* TX data pointer high */
523 523
524/* 13 bit registers written by driver w/ descriptor value that follows 524/* 13 bit registers written by driver w/ descriptor value that follows
525 * last valid xmit descriptor. kick # and complete # values are used by 525 * last valid xmit descriptor. kick # and complete # values are used by
526 * the xmit dma engine to control tx descr fetching. if > 1 valid 526 * the xmit dma engine to control tx descr fetching. if > 1 valid
527 * tx descr is available within the cache line being read, cassini will 527 * tx descr is available within the cache line being read, cassini will
528 * internally cache up to 4 of them. 0 on reset. _KICK = rw, _COMP = ro. 528 * internally cache up to 4 of them. 0 on reset. _KICK = rw, _COMP = ro.
529 */ 529 */
@@ -532,12 +532,12 @@
532#define REG_TX_COMP0 0x2048 /* TX completion reg #1 */ 532#define REG_TX_COMP0 0x2048 /* TX completion reg #1 */
533#define REG_TX_COMPN(x) (REG_TX_COMP0 + (x)*4) 533#define REG_TX_COMPN(x) (REG_TX_COMP0 + (x)*4)
534 534
535/* values of TX_COMPLETE_1-4 are written. each completion register 535/* values of TX_COMPLETE_1-4 are written. each completion register
536 * is 2bytes in size and contiguous. 8B allocation w/ 8B alignment. 536 * is 2bytes in size and contiguous. 8B allocation w/ 8B alignment.
537 * NOTE: completion reg values are only written back prior to TX_INTME and 537 * NOTE: completion reg values are only written back prior to TX_INTME and
538 * TX_ALL interrupts. at all other times, the most up-to-date index values 538 * TX_ALL interrupts. at all other times, the most up-to-date index values
539 * should be obtained from the REG_TX_COMPLETE_# registers. 539 * should be obtained from the REG_TX_COMPLETE_# registers.
540 * here's the layout: 540 * here's the layout:
541 * offset from base addr completion # byte 541 * offset from base addr completion # byte
542 * 0 TX_COMPLETE_1_MSB 542 * 0 TX_COMPLETE_1_MSB
543 * 1 TX_COMPLETE_1_LSB 543 * 1 TX_COMPLETE_1_LSB
@@ -558,7 +558,7 @@
558#define TX_COMPWB_LSB_MASK 0x000000000000FF00ULL 558#define TX_COMPWB_LSB_MASK 0x000000000000FF00ULL
559#define TX_COMPWB_LSB_SHIFT 8 559#define TX_COMPWB_LSB_SHIFT 8
560#define TX_COMPWB_NEXT(x) ((x) >> 16) 560#define TX_COMPWB_NEXT(x) ((x) >> 16)
561 561
562/* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must 562/* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must
563 * be 2KB-aligned. */ 563 * be 2KB-aligned. */
564#define REG_TX_DB0_LOW 0x2060 /* TX descriptor base low #1 */ 564#define REG_TX_DB0_LOW 0x2060 /* TX descriptor base low #1 */
@@ -594,11 +594,11 @@
594#define REG_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO data high t0 */ 594#define REG_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO data high t0 */
595#define REG_TX_FIFO_SIZE 0x2118 /* (ro) TX FIFO size = 0x090 = 9KB */ 595#define REG_TX_FIFO_SIZE 0x2118 /* (ro) TX FIFO size = 0x090 = 9KB */
596 596
597/* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST 597/* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST
598 * passed for the specified memory 598 * passed for the specified memory
599 */ 599 */
600#define REG_TX_RAMBIST 0x211C /* TX RAMBIST control/status */ 600#define REG_TX_RAMBIST 0x211C /* TX RAMBIST control/status */
601#define TX_RAMBIST_STATE 0x01C0 /* progress state of RAMBIST 601#define TX_RAMBIST_STATE 0x01C0 /* progress state of RAMBIST
602 controller state machine */ 602 controller state machine */
603#define TX_RAMBIST_RAM33A_PASS 0x0020 /* RAM33A passed */ 603#define TX_RAMBIST_RAM33A_PASS 0x0020 /* RAM33A passed */
604#define TX_RAMBIST_RAM32A_PASS 0x0010 /* RAM32A passed */ 604#define TX_RAMBIST_RAM32A_PASS 0x0010 /* RAM32A passed */
@@ -612,33 +612,33 @@
612#define MAX_RX_DESC_RINGS 2 612#define MAX_RX_DESC_RINGS 2
613#define MAX_RX_COMP_RINGS 4 613#define MAX_RX_COMP_RINGS 4
614 614
615/* receive DMA channel configuration. default: 0x80910 615/* receive DMA channel configuration. default: 0x80910
616 * free ring size = (1 << n)*32 -> [32 - 8k] 616 * free ring size = (1 << n)*32 -> [32 - 8k]
617 * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9 617 * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9
618 * DEFAULT: 0x80910 618 * DEFAULT: 0x80910
619 */ 619 */
620#define REG_RX_CFG 0x4000 /* RX config */ 620#define REG_RX_CFG 0x4000 /* RX config */
621#define RX_CFG_DMA_EN 0x00000001 /* enable RX DMA. 0 stops 621#define RX_CFG_DMA_EN 0x00000001 /* enable RX DMA. 0 stops
622 channel as soon as current 622 channel as soon as current
623 frame xfer has completed. 623 frame xfer has completed.
624 driver should disable MAC 624 driver should disable MAC
625 for 200ms before disabling 625 for 200ms before disabling
626 RX */ 626 RX */
627#define RX_CFG_DESC_RING_MASK 0x0000001E /* # desc entries in RX 627#define RX_CFG_DESC_RING_MASK 0x0000001E /* # desc entries in RX
628 free desc ring. 628 free desc ring.
629 def: 0x8 = 8k */ 629 def: 0x8 = 8k */
630#define RX_CFG_DESC_RING_SHIFT 1 630#define RX_CFG_DESC_RING_SHIFT 1
631#define RX_CFG_COMP_RING_MASK 0x000001E0 /* # desc entries in RX complete 631#define RX_CFG_COMP_RING_MASK 0x000001E0 /* # desc entries in RX complete
632 ring. def: 0x8 = 32k */ 632 ring. def: 0x8 = 32k */
633#define RX_CFG_COMP_RING_SHIFT 5 633#define RX_CFG_COMP_RING_SHIFT 5
634#define RX_CFG_BATCH_DIS 0x00000200 /* disable receive desc 634#define RX_CFG_BATCH_DIS 0x00000200 /* disable receive desc
635 batching. def: 0x0 = 635 batching. def: 0x0 =
636 enabled */ 636 enabled */
637#define RX_CFG_SWIVEL_MASK 0x00001C00 /* byte offset of the 1st 637#define RX_CFG_SWIVEL_MASK 0x00001C00 /* byte offset of the 1st
638 data byte of the packet 638 data byte of the packet
639 w/in 8 byte boundares. 639 w/in 8 byte boundares.
640 this swivels the data 640 this swivels the data
641 DMA'ed to header 641 DMA'ed to header
642 buffers, jumbo buffers 642 buffers, jumbo buffers
643 when header split is not 643 when header split is not
644 requested and MTU sized 644 requested and MTU sized
@@ -647,17 +647,17 @@
647 647
648/* cassini+ only */ 648/* cassini+ only */
649#define RX_CFG_DESC_RING1_MASK 0x000F0000 /* # of desc entries in 649#define RX_CFG_DESC_RING1_MASK 0x000F0000 /* # of desc entries in
650 RX free desc ring 2. 650 RX free desc ring 2.
651 def: 0x8 = 8k */ 651 def: 0x8 = 8k */
652#define RX_CFG_DESC_RING1_SHIFT 16 652#define RX_CFG_DESC_RING1_SHIFT 16
653 653
654 654
655/* the page size register allows cassini chips to do the following with 655/* the page size register allows cassini chips to do the following with
656 * received data: 656 * received data:
657 * [--------------------------------------------------------------] page 657 * [--------------------------------------------------------------] page
658 * [off][buf1][pad][off][buf2][pad][off][buf3][pad][off][buf4][pad] 658 * [off][buf1][pad][off][buf2][pad][off][buf3][pad][off][buf4][pad]
659 * |--------------| = PAGE_SIZE_BUFFER_STRIDE 659 * |--------------| = PAGE_SIZE_BUFFER_STRIDE
660 * page = PAGE_SIZE 660 * page = PAGE_SIZE
661 * offset = PAGE_SIZE_MTU_OFF 661 * offset = PAGE_SIZE_MTU_OFF
662 * for the above example, MTU_BUFFER_COUNT = 4. 662 * for the above example, MTU_BUFFER_COUNT = 4.
663 * NOTE: as is apparent, you need to ensure that the following holds: 663 * NOTE: as is apparent, you need to ensure that the following holds:
@@ -667,20 +667,20 @@
667#define REG_RX_PAGE_SIZE 0x4004 /* RX page size */ 667#define REG_RX_PAGE_SIZE 0x4004 /* RX page size */
668#define RX_PAGE_SIZE_MASK 0x00000003 /* size of pages pointed to 668#define RX_PAGE_SIZE_MASK 0x00000003 /* size of pages pointed to
669 by receive descriptors. 669 by receive descriptors.
670 if jumbo buffers are 670 if jumbo buffers are
671 supported the page size 671 supported the page size
672 should not be < 8k. 672 should not be < 8k.
673 0b00 = 2k, 0b01 = 4k 673 0b00 = 2k, 0b01 = 4k
674 0b10 = 8k, 0b11 = 16k 674 0b10 = 8k, 0b11 = 16k
675 DEFAULT: 8k */ 675 DEFAULT: 8k */
676#define RX_PAGE_SIZE_SHIFT 0 676#define RX_PAGE_SIZE_SHIFT 0
677#define RX_PAGE_SIZE_MTU_COUNT_MASK 0x00007800 /* # of MTU buffers the hw 677#define RX_PAGE_SIZE_MTU_COUNT_MASK 0x00007800 /* # of MTU buffers the hw
678 packs into a page. 678 packs into a page.
679 DEFAULT: 4 */ 679 DEFAULT: 4 */
680#define RX_PAGE_SIZE_MTU_COUNT_SHIFT 11 680#define RX_PAGE_SIZE_MTU_COUNT_SHIFT 11
681#define RX_PAGE_SIZE_MTU_STRIDE_MASK 0x18000000 /* # of bytes that separate 681#define RX_PAGE_SIZE_MTU_STRIDE_MASK 0x18000000 /* # of bytes that separate
682 each MTU buffer + 682 each MTU buffer +
683 offset from each 683 offset from each
684 other. 684 other.
685 0b00 = 1k, 0b01 = 2k 685 0b00 = 1k, 0b01 = 2k
686 0b10 = 4k, 0b11 = 8k 686 0b10 = 4k, 0b11 = 8k
@@ -688,24 +688,24 @@
688#define RX_PAGE_SIZE_MTU_STRIDE_SHIFT 27 688#define RX_PAGE_SIZE_MTU_STRIDE_SHIFT 27
689#define RX_PAGE_SIZE_MTU_OFF_MASK 0xC0000000 /* offset in each page that 689#define RX_PAGE_SIZE_MTU_OFF_MASK 0xC0000000 /* offset in each page that
690 hw writes the MTU buffer 690 hw writes the MTU buffer
691 into. 691 into.
692 0b00 = 0, 692 0b00 = 0,
693 0b01 = 64 bytes 693 0b01 = 64 bytes
694 0b10 = 96, 0b11 = 128 694 0b10 = 96, 0b11 = 128
695 DEFAULT: 0x1 */ 695 DEFAULT: 0x1 */
696#define RX_PAGE_SIZE_MTU_OFF_SHIFT 30 696#define RX_PAGE_SIZE_MTU_OFF_SHIFT 30
697 697
698/* 11-bit counter points to next location in RX FIFO to be loaded/read. 698/* 11-bit counter points to next location in RX FIFO to be loaded/read.
699 * shadow write pointers enable retries in case of early receive aborts. 699 * shadow write pointers enable retries in case of early receive aborts.
700 * DEFAULT: 0x0. generated on 64-bit boundaries. 700 * DEFAULT: 0x0. generated on 64-bit boundaries.
701 */ 701 */
702#define REG_RX_FIFO_WRITE_PTR 0x4008 /* RX FIFO write pointer */ 702#define REG_RX_FIFO_WRITE_PTR 0x4008 /* RX FIFO write pointer */
703#define REG_RX_FIFO_READ_PTR 0x400C /* RX FIFO read pointer */ 703#define REG_RX_FIFO_READ_PTR 0x400C /* RX FIFO read pointer */
704#define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR 0x4010 /* RX IPP FIFO shadow write 704#define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR 0x4010 /* RX IPP FIFO shadow write
705 pointer */ 705 pointer */
706#define REG_RX_IPP_FIFO_SHADOW_READ_PTR 0x4014 /* RX IPP FIFO shadow read 706#define REG_RX_IPP_FIFO_SHADOW_READ_PTR 0x4014 /* RX IPP FIFO shadow read
707 pointer */ 707 pointer */
708#define REG_RX_IPP_FIFO_READ_PTR 0x400C /* RX IPP FIFO read 708#define REG_RX_IPP_FIFO_READ_PTR 0x400C /* RX IPP FIFO read
709 pointer. (8-bit counter) */ 709 pointer. (8-bit counter) */
710 710
711/* current state of RX DMA state engines + other info 711/* current state of RX DMA state engines + other info
@@ -738,7 +738,7 @@
738 0x2 = wait xon 738 0x2 = wait xon
739 0x3 = wait xon ack */ 739 0x3 = wait xon ack */
740#define RX_DEBUG_DATA_STATE_MASK 0x000001E00 /* unload data state machine 740#define RX_DEBUG_DATA_STATE_MASK 0x000001E00 /* unload data state machine
741 states: 741 states:
742 0x0 = idle data 742 0x0 = idle data
743 0x1 = header begin 743 0x1 = header begin
744 0x2 = xfer header 744 0x2 = xfer header
@@ -747,7 +747,7 @@
747 0x5 = xfer mtu 747 0x5 = xfer mtu
748 0x6 = xfer mtu ld 748 0x6 = xfer mtu ld
749 0x7 = jumbo begin 749 0x7 = jumbo begin
750 0x8 = xfer jumbo 750 0x8 = xfer jumbo
751 0x9 = xfer jumbo ld 751 0x9 = xfer jumbo ld
752 0xa = reas begin 752 0xa = reas begin
753 0xb = xfer reas 753 0xb = xfer reas
@@ -776,15 +776,15 @@
776 * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg 776 * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg
777 * XON PAUSE uses a pause time of 0. granularity of threshold is 64bytes. 777 * XON PAUSE uses a pause time of 0. granularity of threshold is 64bytes.
778 * PAUSE thresholds defined in terms of FIFO occupancy and may be translated 778 * PAUSE thresholds defined in terms of FIFO occupancy and may be translated
779 * into FIFO vacancy using RX_FIFO_SIZE. setting ON will trigger XON frames 779 * into FIFO vacancy using RX_FIFO_SIZE. setting ON will trigger XON frames
780 * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max 780 * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max
781 * value is is 0x6F. 781 * value is is 0x6F.
782 * DEFAULT: 0x00078 782 * DEFAULT: 0x00078
783 */ 783 */
784#define REG_RX_PAUSE_THRESH 0x4020 /* RX pause thresholds */ 784#define REG_RX_PAUSE_THRESH 0x4020 /* RX pause thresholds */
785#define RX_PAUSE_THRESH_QUANTUM 64 785#define RX_PAUSE_THRESH_QUANTUM 64
786#define RX_PAUSE_THRESH_OFF_MASK 0x000001FF /* XOFF PAUSE emitted when 786#define RX_PAUSE_THRESH_OFF_MASK 0x000001FF /* XOFF PAUSE emitted when
787 RX FIFO occupancy > 787 RX FIFO occupancy >
788 value*64B */ 788 value*64B */
789#define RX_PAUSE_THRESH_OFF_SHIFT 0 789#define RX_PAUSE_THRESH_OFF_SHIFT 0
790#define RX_PAUSE_THRESH_ON_MASK 0x001FF000 /* XON PAUSE emitted after 790#define RX_PAUSE_THRESH_ON_MASK 0x001FF000 /* XON PAUSE emitted after
@@ -797,9 +797,9 @@
797#define RX_PAUSE_THRESH_ON_SHIFT 12 797#define RX_PAUSE_THRESH_ON_SHIFT 12
798 798
799/* 13-bit register used to control RX desc fetching and intr generation. if 4+ 799/* 13-bit register used to control RX desc fetching and intr generation. if 4+
800 * valid RX descriptors are available, Cassini will read 4 at a time. 800 * valid RX descriptors are available, Cassini will read 4 at a time.
801 * writing N means that all desc up to *but* excluding N are available. N must 801 * writing N means that all desc up to *but* excluding N are available. N must
802 * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned. 802 * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned.
803 * DEFAULT: 0 on reset 803 * DEFAULT: 0 on reset
804 */ 804 */
805#define REG_RX_KICK 0x4024 /* RX kick reg */ 805#define REG_RX_KICK 0x4024 /* RX kick reg */
@@ -807,16 +807,16 @@
807/* 8KB aligned 64-bit pointer to the base of the RX free/completion rings. 807/* 8KB aligned 64-bit pointer to the base of the RX free/completion rings.
808 * lower 13 bits of the low register are hard-wired to 0. 808 * lower 13 bits of the low register are hard-wired to 0.
809 */ 809 */
810#define REG_RX_DB_LOW 0x4028 /* RX descriptor ring 810#define REG_RX_DB_LOW 0x4028 /* RX descriptor ring
811 base low */ 811 base low */
812#define REG_RX_DB_HI 0x402C /* RX descriptor ring 812#define REG_RX_DB_HI 0x402C /* RX descriptor ring
813 base hi */ 813 base hi */
814#define REG_RX_CB_LOW 0x4030 /* RX completion ring 814#define REG_RX_CB_LOW 0x4030 /* RX completion ring
815 base low */ 815 base low */
816#define REG_RX_CB_HI 0x4034 /* RX completion ring 816#define REG_RX_CB_HI 0x4034 /* RX completion ring
817 base hi */ 817 base hi */
818/* 13-bit register indicate desc used by cassini for receive frames. used 818/* 13-bit register indicate desc used by cassini for receive frames. used
819 * for diagnostic purposes. 819 * for diagnostic purposes.
820 * DEFAULT: 0 on reset 820 * DEFAULT: 0 on reset
821 */ 821 */
822#define REG_RX_COMP 0x4038 /* (ro) RX completion */ 822#define REG_RX_COMP 0x4038 /* (ro) RX completion */
@@ -837,9 +837,9 @@
837/* values used for receive interrupt blanking. loaded each time the ISR is read 837/* values used for receive interrupt blanking. loaded each time the ISR is read
838 * DEFAULT: 0x00000000 838 * DEFAULT: 0x00000000
839 */ 839 */
840#define REG_RX_BLANK 0x4044 /* RX blanking register 840#define REG_RX_BLANK 0x4044 /* RX blanking register
841 for ISR read */ 841 for ISR read */
842#define RX_BLANK_INTR_PKT_MASK 0x000001FF /* RX_DONE intr asserted if 842#define RX_BLANK_INTR_PKT_MASK 0x000001FF /* RX_DONE intr asserted if
843 this many sets of completion 843 this many sets of completion
844 writebacks (up to 2 packets) 844 writebacks (up to 2 packets)
845 occur since the last time 845 occur since the last time
@@ -849,33 +849,33 @@
849#define RX_BLANK_INTR_TIME_MASK 0x3FFFF000 /* RX_DONE interrupt asserted 849#define RX_BLANK_INTR_TIME_MASK 0x3FFFF000 /* RX_DONE interrupt asserted
850 if that many clocks were 850 if that many clocks were
851 counted since last time the 851 counted since last time the
852 ISR was read. 852 ISR was read.
853 each count is 512 core 853 each count is 512 core
854 clocks (125MHz). 0 = no 854 clocks (125MHz). 0 = no
855 time blanking */ 855 time blanking */
856#define RX_BLANK_INTR_TIME_SHIFT 12 856#define RX_BLANK_INTR_TIME_SHIFT 12
857 857
858/* values used for interrupt generation based on threshold values of how 858/* values used for interrupt generation based on threshold values of how
859 * many free desc and completion entries are available for hw use. 859 * many free desc and completion entries are available for hw use.
860 * DEFAULT: 0x00000000 860 * DEFAULT: 0x00000000
861 */ 861 */
862#define REG_RX_AE_THRESH 0x4048 /* RX almost empty 862#define REG_RX_AE_THRESH 0x4048 /* RX almost empty
863 thresholds */ 863 thresholds */
864#define RX_AE_THRESH_FREE_MASK 0x00001FFF /* RX_BUF_AE will be 864#define RX_AE_THRESH_FREE_MASK 0x00001FFF /* RX_BUF_AE will be
865 generated if # desc 865 generated if # desc
866 avail for hw use <= 866 avail for hw use <=
867 # */ 867 # */
868#define RX_AE_THRESH_FREE_SHIFT 0 868#define RX_AE_THRESH_FREE_SHIFT 0
869#define RX_AE_THRESH_COMP_MASK 0x0FFFE000 /* RX_COMP_AE will be 869#define RX_AE_THRESH_COMP_MASK 0x0FFFE000 /* RX_COMP_AE will be
870 generated if # of 870 generated if # of
871 completion entries 871 completion entries
872 avail for hw use <= 872 avail for hw use <=
873 # */ 873 # */
874#define RX_AE_THRESH_COMP_SHIFT 13 874#define RX_AE_THRESH_COMP_SHIFT 13
875 875
876/* probabilities for random early drop (RED) thresholds on a FIFO threshold 876/* probabilities for random early drop (RED) thresholds on a FIFO threshold
877 * basis. probability should increase when the FIFO level increases. control 877 * basis. probability should increase when the FIFO level increases. control
878 * packets are never dropped and not counted in stats. probability programmed 878 * packets are never dropped and not counted in stats. probability programmed
879 * on a 12.5% granularity. e.g., 0x1 = 1/8 packets dropped. 879 * on a 12.5% granularity. e.g., 0x1 = 1/8 packets dropped.
880 * DEFAULT: 0x00000000 880 * DEFAULT: 0x00000000
881 */ 881 */
@@ -885,8 +885,8 @@
885#define RX_RED_8K_10K_FIFO_MASK 0x00FF0000 /* 8KB < FIFO thresh < 10KB */ 885#define RX_RED_8K_10K_FIFO_MASK 0x00FF0000 /* 8KB < FIFO thresh < 10KB */
886#define RX_RED_10K_12K_FIFO_MASK 0xFF000000 /* 10KB < FIFO thresh < 12KB */ 886#define RX_RED_10K_12K_FIFO_MASK 0xFF000000 /* 10KB < FIFO thresh < 12KB */
887 887
888/* FIFO fullness levels for RX FIFO, RX control FIFO, and RX IPP FIFO. 888/* FIFO fullness levels for RX FIFO, RX control FIFO, and RX IPP FIFO.
889 * RX control FIFO = # of packets in RX FIFO. 889 * RX control FIFO = # of packets in RX FIFO.
890 * DEFAULT: 0x0 890 * DEFAULT: 0x0
891 */ 891 */
892#define REG_RX_FIFO_FULLNESS 0x4050 /* (ro) RX FIFO fullness */ 892#define REG_RX_FIFO_FULLNESS 0x4050 /* (ro) RX FIFO fullness */
@@ -895,12 +895,12 @@
895#define RX_FIFO_FULLNESS_RX_PKT_MASK 0x000000FF /* # packets in RX FIFO */ 895#define RX_FIFO_FULLNESS_RX_PKT_MASK 0x000000FF /* # packets in RX FIFO */
896#define REG_RX_IPP_PACKET_COUNT 0x4054 /* RX IPP packet counter */ 896#define REG_RX_IPP_PACKET_COUNT 0x4054 /* RX IPP packet counter */
897#define REG_RX_WORK_DMA_PTR_LOW 0x4058 /* RX working DMA ptr low */ 897#define REG_RX_WORK_DMA_PTR_LOW 0x4058 /* RX working DMA ptr low */
898#define REG_RX_WORK_DMA_PTR_HI 0x405C /* RX working DMA ptr 898#define REG_RX_WORK_DMA_PTR_HI 0x405C /* RX working DMA ptr
899 high */ 899 high */
900 900
901/* BIST testing ro RX FIFO, RX control FIFO, and RX IPP FIFO. only RX BIST 901/* BIST testing ro RX FIFO, RX control FIFO, and RX IPP FIFO. only RX BIST
902 * START/COMPLETE is writeable. START will clear when the BIST has completed 902 * START/COMPLETE is writeable. START will clear when the BIST has completed
903 * checking all 17 RAMS. 903 * checking all 17 RAMS.
904 * DEFAULT: 0bxxxx xxxxx xxxx xxxx xxxx x000 0000 0000 00x0 904 * DEFAULT: 0bxxxx xxxxx xxxx xxxx xxxx x000 0000 0000 00x0
905 */ 905 */
906#define REG_RX_BIST 0x4060 /* (ro) RX BIST */ 906#define REG_RX_BIST 0x4060 /* (ro) RX BIST */
@@ -923,41 +923,41 @@
923#define RX_BIST_REAS_27_PASS 0x00080000 /* RX Reas 27 passed */ 923#define RX_BIST_REAS_27_PASS 0x00080000 /* RX Reas 27 passed */
924#define RX_BIST_STATE_MASK 0x00078000 /* BIST state machine */ 924#define RX_BIST_STATE_MASK 0x00078000 /* BIST state machine */
925#define RX_BIST_SUMMARY 0x00000002 /* when BIST complete, 925#define RX_BIST_SUMMARY 0x00000002 /* when BIST complete,
926 summary pass bit 926 summary pass bit
927 contains AND of BIST 927 contains AND of BIST
928 results of all 16 928 results of all 16
929 RAMS */ 929 RAMS */
930#define RX_BIST_START 0x00000001 /* write 1 to start 930#define RX_BIST_START 0x00000001 /* write 1 to start
931 BIST. self clears 931 BIST. self clears
932 on completion. */ 932 on completion. */
933 933
934/* next location in RX CTRL FIFO that will be loaded w/ data from RX IPP/read 934/* next location in RX CTRL FIFO that will be loaded w/ data from RX IPP/read
935 * from to retrieve packet control info. 935 * from to retrieve packet control info.
936 * DEFAULT: 0 936 * DEFAULT: 0
937 */ 937 */
938#define REG_RX_CTRL_FIFO_WRITE_PTR 0x4064 /* (ro) RX control FIFO 938#define REG_RX_CTRL_FIFO_WRITE_PTR 0x4064 /* (ro) RX control FIFO
939 write ptr */ 939 write ptr */
940#define REG_RX_CTRL_FIFO_READ_PTR 0x4068 /* (ro) RX control FIFO read 940#define REG_RX_CTRL_FIFO_READ_PTR 0x4068 /* (ro) RX control FIFO read
941 ptr */ 941 ptr */
942 942
943/* receive interrupt blanking. loaded each time interrupt alias register is 943/* receive interrupt blanking. loaded each time interrupt alias register is
944 * read. 944 * read.
945 * DEFAULT: 0x0 945 * DEFAULT: 0x0
946 */ 946 */
947#define REG_RX_BLANK_ALIAS_READ 0x406C /* RX blanking register for 947#define REG_RX_BLANK_ALIAS_READ 0x406C /* RX blanking register for
948 alias read */ 948 alias read */
949#define RX_BAR_INTR_PACKET_MASK 0x000001FF /* assert RX_DONE if # 949#define RX_BAR_INTR_PACKET_MASK 0x000001FF /* assert RX_DONE if #
950 completion writebacks 950 completion writebacks
951 > # since last ISR 951 > # since last ISR
952 read. 0 = no 952 read. 0 = no
953 blanking. up to 2 953 blanking. up to 2
954 packets per 954 packets per
955 completion wb. */ 955 completion wb. */
956#define RX_BAR_INTR_TIME_MASK 0x3FFFF000 /* assert RX_DONE if # 956#define RX_BAR_INTR_TIME_MASK 0x3FFFF000 /* assert RX_DONE if #
957 clocks > # since last 957 clocks > # since last
958 ISR read. each count 958 ISR read. each count
959 is 512 core clocks 959 is 512 core clocks
960 (125MHz). 0 = no 960 (125MHz). 0 = no
961 blanking. */ 961 blanking. */
962 962
963/* diagnostic access to RX FIFO. 32 LSB accessed via DATA_LOW. 32 MSB accessed 963/* diagnostic access to RX FIFO. 32 LSB accessed via DATA_LOW. 32 MSB accessed
@@ -981,13 +981,13 @@
981 * should be last write access of the write sequence. 981 * should be last write access of the write sequence.
982 * DEFAULT: undefined 982 * DEFAULT: undefined
983 */ 983 */
984#define REG_RX_CTRL_FIFO_ADDR 0x4094 /* RX Control FIFO and 984#define REG_RX_CTRL_FIFO_ADDR 0x4094 /* RX Control FIFO and
985 Batching FIFO addr */ 985 Batching FIFO addr */
986#define REG_RX_CTRL_FIFO_DATA_LOW 0x4098 /* RX Control FIFO data 986#define REG_RX_CTRL_FIFO_DATA_LOW 0x4098 /* RX Control FIFO data
987 low */ 987 low */
988#define REG_RX_CTRL_FIFO_DATA_MID 0x409C /* RX Control FIFO data 988#define REG_RX_CTRL_FIFO_DATA_MID 0x409C /* RX Control FIFO data
989 mid */ 989 mid */
990#define REG_RX_CTRL_FIFO_DATA_HI 0x4100 /* RX Control FIFO data 990#define REG_RX_CTRL_FIFO_DATA_HI 0x4100 /* RX Control FIFO data
991 hi and flow id */ 991 hi and flow id */
992#define RX_CTRL_FIFO_DATA_HI_CTRL 0x0001 /* upper bit of ctrl word */ 992#define RX_CTRL_FIFO_DATA_HI_CTRL 0x0001 /* upper bit of ctrl word */
993#define RX_CTRL_FIFO_DATA_HI_FLOW_MASK 0x007E /* flow id */ 993#define RX_CTRL_FIFO_DATA_HI_FLOW_MASK 0x007E /* flow id */
@@ -1004,7 +1004,7 @@
1004 T1 */ 1004 T1 */
1005 1005
1006/* 64-bit pointer to receive data buffer in host memory used for headers and 1006/* 64-bit pointer to receive data buffer in host memory used for headers and
1007 * small packets. MSB in high register. loaded by DMA state machine and 1007 * small packets. MSB in high register. loaded by DMA state machine and
1008 * increments as DMA writes receive data. only 50 LSB are incremented. top 1008 * increments as DMA writes receive data. only 50 LSB are incremented. top
1009 * 13 bits taken from RX descriptor. 1009 * 13 bits taken from RX descriptor.
1010 * DEFAULT: undefined 1010 * DEFAULT: undefined
@@ -1013,17 +1013,17 @@
1013 low */ 1013 low */
1014#define REG_RX_HEADER_PAGE_PTR_HI 0x411C /* (ro) RX header page ptr 1014#define REG_RX_HEADER_PAGE_PTR_HI 0x411C /* (ro) RX header page ptr
1015 high */ 1015 high */
1016#define REG_RX_MTU_PAGE_PTR_LOW 0x4120 /* (ro) RX MTU page pointer 1016#define REG_RX_MTU_PAGE_PTR_LOW 0x4120 /* (ro) RX MTU page pointer
1017 low */ 1017 low */
1018#define REG_RX_MTU_PAGE_PTR_HI 0x4124 /* (ro) RX MTU page pointer 1018#define REG_RX_MTU_PAGE_PTR_HI 0x4124 /* (ro) RX MTU page pointer
1019 high */ 1019 high */
1020 1020
1021/* PIO diagnostic access to RX reassembly DMA Table RAM. 6-bit register holds 1021/* PIO diagnostic access to RX reassembly DMA Table RAM. 6-bit register holds
1022 * one of 64 79-bit locations in the RX Reassembly DMA table and the addr of 1022 * one of 64 79-bit locations in the RX Reassembly DMA table and the addr of
1023 * one of the 64 byte locations in the Batching table. LOW holds 32 LSB. 1023 * one of the 64 byte locations in the Batching table. LOW holds 32 LSB.
1024 * MID holds the next 32 LSB. HIGH holds the 15 MSB. RX_DMA_EN must be set 1024 * MID holds the next 32 LSB. HIGH holds the 15 MSB. RX_DMA_EN must be set
1025 * to 0 for PIO access. DATA_HIGH should be last write of write sequence. 1025 * to 0 for PIO access. DATA_HIGH should be last write of write sequence.
1026 * layout: 1026 * layout:
1027 * reassmbl ptr [78:15] | reassmbl index [14:1] | reassmbl entry valid [0] 1027 * reassmbl ptr [78:15] | reassmbl index [14:1] | reassmbl entry valid [0]
1028 * DEFAULT: undefined 1028 * DEFAULT: undefined
1029 */ 1029 */
@@ -1033,7 +1033,7 @@
1033 1033
1034#define REG_RX_TABLE_DATA_LOW 0x412C /* RX reassembly DMA table 1034#define REG_RX_TABLE_DATA_LOW 0x412C /* RX reassembly DMA table
1035 data low */ 1035 data low */
1036#define REG_RX_TABLE_DATA_MID 0x4130 /* RX reassembly DMA table 1036#define REG_RX_TABLE_DATA_MID 0x4130 /* RX reassembly DMA table
1037 data mid */ 1037 data mid */
1038#define REG_RX_TABLE_DATA_HI 0x4134 /* RX reassembly DMA table 1038#define REG_RX_TABLE_DATA_HI 0x4134 /* RX reassembly DMA table
1039 data high */ 1039 data high */
@@ -1053,11 +1053,11 @@
1053#define REG_PLUS_RX_CBN_LOW(x) (REG_PLUS_RX_CB1_LOW + 8*((x) - 1)) 1053#define REG_PLUS_RX_CBN_LOW(x) (REG_PLUS_RX_CB1_LOW + 8*((x) - 1))
1054#define REG_PLUS_RX_CBN_HI(x) (REG_PLUS_RX_CB1_HI + 8*((x) - 1)) 1054#define REG_PLUS_RX_CBN_HI(x) (REG_PLUS_RX_CB1_HI + 8*((x) - 1))
1055#define REG_PLUS_RX_KICK1 0x4220 /* RX Kick 2 register */ 1055#define REG_PLUS_RX_KICK1 0x4220 /* RX Kick 2 register */
1056#define REG_PLUS_RX_COMP1 0x4224 /* (ro) RX completion 2 1056#define REG_PLUS_RX_COMP1 0x4224 /* (ro) RX completion 2
1057 reg */ 1057 reg */
1058#define REG_PLUS_RX_COMP1_HEAD 0x4228 /* (ro) RX completion 2 1058#define REG_PLUS_RX_COMP1_HEAD 0x4228 /* (ro) RX completion 2
1059 head reg. 4 total. */ 1059 head reg. 4 total. */
1060#define REG_PLUS_RX_COMP1_TAIL 0x422C /* RX completion 2 1060#define REG_PLUS_RX_COMP1_TAIL 0x422C /* RX completion 2
1061 tail reg. 4 total. */ 1061 tail reg. 4 total. */
1062#define REG_PLUS_RX_COMPN_HEAD(x) (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1)) 1062#define REG_PLUS_RX_COMPN_HEAD(x) (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1))
1063#define REG_PLUS_RX_COMPN_TAIL(x) (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1)) 1063#define REG_PLUS_RX_COMPN_TAIL(x) (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1))
@@ -1068,13 +1068,13 @@
1068 1068
1069/** header parser registers **/ 1069/** header parser registers **/
1070 1070
1071/* RX parser configuration register. 1071/* RX parser configuration register.
1072 * DEFAULT: 0x1651004 1072 * DEFAULT: 0x1651004
1073 */ 1073 */
1074#define REG_HP_CFG 0x4140 /* header parser 1074#define REG_HP_CFG 0x4140 /* header parser
1075 configuration reg */ 1075 configuration reg */
1076#define HP_CFG_PARSE_EN 0x00000001 /* enab header parsing */ 1076#define HP_CFG_PARSE_EN 0x00000001 /* enab header parsing */
1077#define HP_CFG_NUM_CPU_MASK 0x000000FC /* # processors 1077#define HP_CFG_NUM_CPU_MASK 0x000000FC /* # processors
1078 0 = 64. 0x3f = 63 */ 1078 0 = 64. 0x3f = 63 */
1079#define HP_CFG_NUM_CPU_SHIFT 2 1079#define HP_CFG_NUM_CPU_SHIFT 2
1080#define HP_CFG_SYN_INC_MASK 0x00000100 /* SYN bit won't increment 1080#define HP_CFG_SYN_INC_MASK 0x00000100 /* SYN bit won't increment
@@ -1088,7 +1088,7 @@
1088/* access to RX Instruction RAM. 5-bit register/counter holds addr 1088/* access to RX Instruction RAM. 5-bit register/counter holds addr
1089 * of 39 bit entry to be read/written. 32 LSB in _DATA_LOW. 7 MSB in _DATA_HI. 1089 * of 39 bit entry to be read/written. 32 LSB in _DATA_LOW. 7 MSB in _DATA_HI.
1090 * RX_DMA_EN must be 0 for RX instr PIO access. DATA_HI should be last access 1090 * RX_DMA_EN must be 0 for RX instr PIO access. DATA_HI should be last access
1091 * of sequence. 1091 * of sequence.
1092 * DEFAULT: undefined 1092 * DEFAULT: undefined
1093 */ 1093 */
1094#define REG_HP_INSTR_RAM_ADDR 0x4144 /* HP instruction RAM 1094#define REG_HP_INSTR_RAM_ADDR 0x4144 /* HP instruction RAM
@@ -1104,7 +1104,7 @@
1104#define HP_INSTR_RAM_LOW_OUTEN_SHIFT 20 1104#define HP_INSTR_RAM_LOW_OUTEN_SHIFT 20
1105#define HP_INSTR_RAM_LOW_OUTARG_MASK 0xFFC00000 1105#define HP_INSTR_RAM_LOW_OUTARG_MASK 0xFFC00000
1106#define HP_INSTR_RAM_LOW_OUTARG_SHIFT 22 1106#define HP_INSTR_RAM_LOW_OUTARG_SHIFT 22
1107#define REG_HP_INSTR_RAM_DATA_MID 0x414C /* HP instruction RAM 1107#define REG_HP_INSTR_RAM_DATA_MID 0x414C /* HP instruction RAM
1108 data mid */ 1108 data mid */
1109#define HP_INSTR_RAM_MID_OUTARG_MASK 0x00000003 1109#define HP_INSTR_RAM_MID_OUTARG_MASK 0x00000003
1110#define HP_INSTR_RAM_MID_OUTARG_SHIFT 0 1110#define HP_INSTR_RAM_MID_OUTARG_SHIFT 0
@@ -1131,7 +1131,7 @@
1131 * 11-bit register. Data fills the LSB portion of bus if less than 32 bits. 1131 * 11-bit register. Data fills the LSB portion of bus if less than 32 bits.
1132 * DATA_RAM: write RAM_FDB_DATA with index to access DATA_RAM. 1132 * DATA_RAM: write RAM_FDB_DATA with index to access DATA_RAM.
1133 * RAM bytes = 4*(x - 1) + [3:0]. e.g., 0 -> [3:0], 31 -> [123:120] 1133 * RAM bytes = 4*(x - 1) + [3:0]. e.g., 0 -> [3:0], 31 -> [123:120]
1134 * FLOWDB: write DATA_RAM_FDB register and then read/write FDB1-12 to access 1134 * FLOWDB: write DATA_RAM_FDB register and then read/write FDB1-12 to access
1135 * flow database. 1135 * flow database.
1136 * RX_DMA_EN must be 0 for RX parser RAM PIO access. RX Parser RAM data reg 1136 * RX_DMA_EN must be 0 for RX parser RAM PIO access. RX Parser RAM data reg
1137 * should be the last write access of the write sequence. 1137 * should be the last write access of the write sequence.
@@ -1139,17 +1139,17 @@
1139 */ 1139 */
1140#define REG_HP_DATA_RAM_FDB_ADDR 0x4154 /* HP data and FDB 1140#define REG_HP_DATA_RAM_FDB_ADDR 0x4154 /* HP data and FDB
1141 RAM address */ 1141 RAM address */
1142#define HP_DATA_RAM_FDB_DATA_MASK 0x001F /* select 1 of 86 byte 1142#define HP_DATA_RAM_FDB_DATA_MASK 0x001F /* select 1 of 86 byte
1143 locations in header 1143 locations in header
1144 parser data ram to 1144 parser data ram to
1145 read/write */ 1145 read/write */
1146#define HP_DATA_RAM_FDB_FDB_MASK 0x3F00 /* 1 of 64 353-bit locations 1146#define HP_DATA_RAM_FDB_FDB_MASK 0x3F00 /* 1 of 64 353-bit locations
1147 in the flow database */ 1147 in the flow database */
1148#define REG_HP_DATA_RAM_DATA 0x4158 /* HP data RAM data */ 1148#define REG_HP_DATA_RAM_DATA 0x4158 /* HP data RAM data */
1149 1149
1150/* HP flow database registers: 1 - 12, 0x415C - 0x4188, 4 8-bit bytes 1150/* HP flow database registers: 1 - 12, 0x415C - 0x4188, 4 8-bit bytes
1151 * FLOW_DB(1) = IP_SA[127:96], FLOW_DB(2) = IP_SA[95:64] 1151 * FLOW_DB(1) = IP_SA[127:96], FLOW_DB(2) = IP_SA[95:64]
1152 * FLOW_DB(3) = IP_SA[63:32], FLOW_DB(4) = IP_SA[31:0] 1152 * FLOW_DB(3) = IP_SA[63:32], FLOW_DB(4) = IP_SA[31:0]
1153 * FLOW_DB(5) = IP_DA[127:96], FLOW_DB(6) = IP_DA[95:64] 1153 * FLOW_DB(5) = IP_DA[127:96], FLOW_DB(6) = IP_DA[95:64]
1154 * FLOW_DB(7) = IP_DA[63:32], FLOW_DB(8) = IP_DA[31:0] 1154 * FLOW_DB(7) = IP_DA[63:32], FLOW_DB(8) = IP_DA[31:0]
1155 * FLOW_DB(9) = {TCP_SP[15:0],TCP_DP[15:0]} 1155 * FLOW_DB(9) = {TCP_SP[15:0],TCP_DP[15:0]}
@@ -1159,7 +1159,7 @@
1159#define REG_HP_FLOW_DB0 0x415C /* HP flow database 1 reg */ 1159#define REG_HP_FLOW_DB0 0x415C /* HP flow database 1 reg */
1160#define REG_HP_FLOW_DBN(x) (REG_HP_FLOW_DB0 + (x)*4) 1160#define REG_HP_FLOW_DBN(x) (REG_HP_FLOW_DB0 + (x)*4)
1161 1161
1162/* diagnostics for RX Header Parser block. 1162/* diagnostics for RX Header Parser block.
1163 * ASUN: the header parser state machine register is used for diagnostics 1163 * ASUN: the header parser state machine register is used for diagnostics
1164 * purposes. however, the spec doesn't have any details on it. 1164 * purposes. however, the spec doesn't have any details on it.
1165 */ 1165 */
@@ -1167,7 +1167,7 @@
1167#define REG_HP_STATUS0 0x4190 /* (ro) HP status 1 */ 1167#define REG_HP_STATUS0 0x4190 /* (ro) HP status 1 */
1168#define HP_STATUS0_SAP_MASK 0xFFFF0000 /* SAP */ 1168#define HP_STATUS0_SAP_MASK 0xFFFF0000 /* SAP */
1169#define HP_STATUS0_L3_OFF_MASK 0x0000FE00 /* L3 offset */ 1169#define HP_STATUS0_L3_OFF_MASK 0x0000FE00 /* L3 offset */
1170#define HP_STATUS0_LB_CPUNUM_MASK 0x000001F8 /* load balancing CPU 1170#define HP_STATUS0_LB_CPUNUM_MASK 0x000001F8 /* load balancing CPU
1171 number */ 1171 number */
1172#define HP_STATUS0_HRP_OPCODE_MASK 0x00000007 /* HRP opcode */ 1172#define HP_STATUS0_HRP_OPCODE_MASK 0x00000007 /* HRP opcode */
1173 1173
@@ -1179,11 +1179,11 @@
1179 1179
1180#define REG_HP_STATUS2 0x4198 /* (ro) HP status 3 */ 1180#define REG_HP_STATUS2 0x4198 /* (ro) HP status 3 */
1181#define HP_STATUS2_ACCUR2_MASK 0xF0000000 /* accu R2[3:0] */ 1181#define HP_STATUS2_ACCUR2_MASK 0xF0000000 /* accu R2[3:0] */
1182#define HP_STATUS2_CSUM_OFF_MASK 0x07F00000 /* checksum start 1182#define HP_STATUS2_CSUM_OFF_MASK 0x07F00000 /* checksum start
1183 start offset */ 1183 start offset */
1184#define HP_STATUS2_ACCUR1_MASK 0x000FE000 /* accu R1 */ 1184#define HP_STATUS2_ACCUR1_MASK 0x000FE000 /* accu R1 */
1185#define HP_STATUS2_FORCE_DROP 0x00001000 /* force drop */ 1185#define HP_STATUS2_FORCE_DROP 0x00001000 /* force drop */
1186#define HP_STATUS2_BWO_REASSM 0x00000800 /* batching w/o 1186#define HP_STATUS2_BWO_REASSM 0x00000800 /* batching w/o
1187 reassembly */ 1187 reassembly */
1188#define HP_STATUS2_JH_SPLIT_EN 0x00000400 /* jumbo header split 1188#define HP_STATUS2_JH_SPLIT_EN 0x00000400 /* jumbo header split
1189 enable */ 1189 enable */
@@ -1191,9 +1191,9 @@
1191 check */ 1191 check */
1192#define HP_STATUS2_DATA_MASK_ZERO 0x00000100 /* mask of data length 1192#define HP_STATUS2_DATA_MASK_ZERO 0x00000100 /* mask of data length
1193 equal to zero */ 1193 equal to zero */
1194#define HP_STATUS2_FORCE_TCP_CHECK 0x00000080 /* force tcp payload 1194#define HP_STATUS2_FORCE_TCP_CHECK 0x00000080 /* force tcp payload
1195 chk */ 1195 chk */
1196#define HP_STATUS2_MASK_TCP_THRESH 0x00000040 /* mask of payload 1196#define HP_STATUS2_MASK_TCP_THRESH 0x00000040 /* mask of payload
1197 threshold */ 1197 threshold */
1198#define HP_STATUS2_NO_ASSIST 0x00000020 /* no assist */ 1198#define HP_STATUS2_NO_ASSIST 0x00000020 /* no assist */
1199#define HP_STATUS2_CTRL_PACKET_FLAG 0x00000010 /* control packet flag */ 1199#define HP_STATUS2_CTRL_PACKET_FLAG 0x00000010 /* control packet flag */
@@ -1214,7 +1214,7 @@
1214#define HP_RAM_BIST_HP_INSTR2_PASS 0x10000000 /* HP instr ram 2 */ 1214#define HP_RAM_BIST_HP_INSTR2_PASS 0x10000000 /* HP instr ram 2 */
1215#define HP_RAM_BIST_FDBM_AGE0_PASS 0x08000000 /* FDBM aging RAM0 */ 1215#define HP_RAM_BIST_FDBM_AGE0_PASS 0x08000000 /* FDBM aging RAM0 */
1216#define HP_RAM_BIST_FDBM_AGE1_PASS 0x04000000 /* FDBM aging RAM1 */ 1216#define HP_RAM_BIST_FDBM_AGE1_PASS 0x04000000 /* FDBM aging RAM1 */
1217#define HP_RAM_BIST_FDBM_FLOWID00_PASS 0x02000000 /* FDBM flowid RAM0 1217#define HP_RAM_BIST_FDBM_FLOWID00_PASS 0x02000000 /* FDBM flowid RAM0
1218 bank 0 */ 1218 bank 0 */
1219#define HP_RAM_BIST_FDBM_FLOWID10_PASS 0x01000000 /* FDBM flowid RAM1 1219#define HP_RAM_BIST_FDBM_FLOWID10_PASS 0x01000000 /* FDBM flowid RAM1
1220 bank 0 */ 1220 bank 0 */
@@ -1247,25 +1247,25 @@
1247/* execute a pause flow control frame transmission 1247/* execute a pause flow control frame transmission
1248 DEFAULT: 0x0XXXX */ 1248 DEFAULT: 0x0XXXX */
1249#define REG_MAC_SEND_PAUSE 0x6008 /* send pause command reg */ 1249#define REG_MAC_SEND_PAUSE 0x6008 /* send pause command reg */
1250#define MAC_SEND_PAUSE_TIME_MASK 0x0000FFFF /* value of pause time 1250#define MAC_SEND_PAUSE_TIME_MASK 0x0000FFFF /* value of pause time
1251 to be sent on network 1251 to be sent on network
1252 in units of slot 1252 in units of slot
1253 times */ 1253 times */
1254#define MAC_SEND_PAUSE_SEND 0x00010000 /* send pause flow ctrl 1254#define MAC_SEND_PAUSE_SEND 0x00010000 /* send pause flow ctrl
1255 frame on network */ 1255 frame on network */
1256 1256
1257/* bit set indicates that event occurred. auto-cleared when status register 1257/* bit set indicates that event occurred. auto-cleared when status register
1258 * is read and have corresponding mask bits in mask register. events will 1258 * is read and have corresponding mask bits in mask register. events will
1259 * trigger an interrupt if the corresponding mask bit is 0. 1259 * trigger an interrupt if the corresponding mask bit is 0.
1260 * status register default: 0x00000000 1260 * status register default: 0x00000000
1261 * mask register default = 0xFFFFFFFF on reset 1261 * mask register default = 0xFFFFFFFF on reset
1262 */ 1262 */
1263#define REG_MAC_TX_STATUS 0x6010 /* TX MAC status reg */ 1263#define REG_MAC_TX_STATUS 0x6010 /* TX MAC status reg */
1264#define MAC_TX_FRAME_XMIT 0x0001 /* successful frame 1264#define MAC_TX_FRAME_XMIT 0x0001 /* successful frame
1265 transmision */ 1265 transmision */
1266#define MAC_TX_UNDERRUN 0x0002 /* terminated frame 1266#define MAC_TX_UNDERRUN 0x0002 /* terminated frame
1267 transmission due to 1267 transmission due to
1268 data starvation in the 1268 data starvation in the
1269 xmit data path */ 1269 xmit data path */
1270#define MAC_TX_MAX_PACKET_ERR 0x0004 /* frame exceeds max allowed 1270#define MAC_TX_MAX_PACKET_ERR 0x0004 /* frame exceeds max allowed
1271 length passed to TX MAC 1271 length passed to TX MAC
@@ -1286,7 +1286,7 @@
1286#define REG_MAC_RX_STATUS 0x6014 /* RX MAC status reg */ 1286#define REG_MAC_RX_STATUS 0x6014 /* RX MAC status reg */
1287#define MAC_RX_FRAME_RECV 0x0001 /* successful receipt of 1287#define MAC_RX_FRAME_RECV 0x0001 /* successful receipt of
1288 a frame */ 1288 a frame */
1289#define MAC_RX_OVERFLOW 0x0002 /* dropped frame due to 1289#define MAC_RX_OVERFLOW 0x0002 /* dropped frame due to
1290 RX FIFO overflow */ 1290 RX FIFO overflow */
1291#define MAC_RX_FRAME_COUNT 0x0004 /* rollover of receive frame 1291#define MAC_RX_FRAME_COUNT 0x0004 /* rollover of receive frame
1292 counter */ 1292 counter */
@@ -1294,27 +1294,27 @@
1294 error counter */ 1294 error counter */
1295#define MAC_RX_CRC_ERR 0x0010 /* rollover of crc error 1295#define MAC_RX_CRC_ERR 0x0010 /* rollover of crc error
1296 counter */ 1296 counter */
1297#define MAC_RX_LEN_ERR 0x0020 /* rollover of length 1297#define MAC_RX_LEN_ERR 0x0020 /* rollover of length
1298 error counter */ 1298 error counter */
1299#define MAC_RX_VIOL_ERR 0x0040 /* rollover of code 1299#define MAC_RX_VIOL_ERR 0x0040 /* rollover of code
1300 violation error */ 1300 violation error */
1301 1301
1302/* DEFAULT: 0xXXXX0000 on reset */ 1302/* DEFAULT: 0xXXXX0000 on reset */
1303#define REG_MAC_CTRL_STATUS 0x6018 /* MAC control status reg */ 1303#define REG_MAC_CTRL_STATUS 0x6018 /* MAC control status reg */
1304#define MAC_CTRL_PAUSE_RECEIVED 0x00000001 /* successful 1304#define MAC_CTRL_PAUSE_RECEIVED 0x00000001 /* successful
1305 reception of a 1305 reception of a
1306 pause control 1306 pause control
1307 frame */ 1307 frame */
1308#define MAC_CTRL_PAUSE_STATE 0x00000002 /* MAC has made a 1308#define MAC_CTRL_PAUSE_STATE 0x00000002 /* MAC has made a
1309 transition from 1309 transition from
1310 "not paused" to 1310 "not paused" to
1311 "paused" */ 1311 "paused" */
1312#define MAC_CTRL_NOPAUSE_STATE 0x00000004 /* MAC has made a 1312#define MAC_CTRL_NOPAUSE_STATE 0x00000004 /* MAC has made a
1313 transition from 1313 transition from
1314 "paused" to "not 1314 "paused" to "not
1315 paused" */ 1315 paused" */
1316#define MAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time 1316#define MAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time
1317 operand that was 1317 operand that was
1318 received in the last 1318 received in the last
1319 pause flow control 1319 pause flow control
1320 frame */ 1320 frame */
@@ -1326,13 +1326,13 @@
1326/* layout identical to CTRL MAC[2:0] */ 1326/* layout identical to CTRL MAC[2:0] */
1327#define REG_MAC_CTRL_MASK 0x6028 /* MAC control mask reg */ 1327#define REG_MAC_CTRL_MASK 0x6028 /* MAC control mask reg */
1328 1328
1329/* to ensure proper operation, CFG_EN must be cleared to 0 and a delay 1329/* to ensure proper operation, CFG_EN must be cleared to 0 and a delay
1330 * imposed before writes to other bits in the TX_MAC_CFG register or any of 1330 * imposed before writes to other bits in the TX_MAC_CFG register or any of
1331 * the MAC parameters is performed. delay dependent upon time required to 1331 * the MAC parameters is performed. delay dependent upon time required to
1332 * transmit a maximum size frame (= MAC_FRAMESIZE_MAX*8/Mbps). e.g., 1332 * transmit a maximum size frame (= MAC_FRAMESIZE_MAX*8/Mbps). e.g.,
1333 * the delay for a 1518-byte frame on a 100Mbps network is 125us. 1333 * the delay for a 1518-byte frame on a 100Mbps network is 125us.
1334 * alternatively, just poll TX_CFG_EN until it reads back as 0. 1334 * alternatively, just poll TX_CFG_EN until it reads back as 0.
1335 * NOTE: on half-duplex 1Gbps, TX_CFG_CARRIER_EXTEND and 1335 * NOTE: on half-duplex 1Gbps, TX_CFG_CARRIER_EXTEND and
1336 * RX_CFG_CARRIER_EXTEND should be set and the SLOT_TIME register should 1336 * RX_CFG_CARRIER_EXTEND should be set and the SLOT_TIME register should
1337 * be 0x200 (slot time of 512 bytes) 1337 * be 0x200 (slot time of 512 bytes)
1338 */ 1338 */
@@ -1340,12 +1340,12 @@
1340#define MAC_TX_CFG_EN 0x0001 /* enable TX MAC. 0 will 1340#define MAC_TX_CFG_EN 0x0001 /* enable TX MAC. 0 will
1341 force TXMAC state 1341 force TXMAC state
1342 machine to remain in 1342 machine to remain in
1343 idle state or to 1343 idle state or to
1344 transition to idle state 1344 transition to idle state
1345 on completion of an 1345 on completion of an
1346 ongoing packet. */ 1346 ongoing packet. */
1347#define MAC_TX_CFG_IGNORE_CARRIER 0x0002 /* disable CSMA/CD deferral 1347#define MAC_TX_CFG_IGNORE_CARRIER 0x0002 /* disable CSMA/CD deferral
1348 process. set to 1 when 1348 process. set to 1 when
1349 full duplex and 0 when 1349 full duplex and 0 when
1350 half duplex */ 1350 half duplex */
1351#define MAC_TX_CFG_IGNORE_COLL 0x0004 /* disable CSMA/CD backoff 1351#define MAC_TX_CFG_IGNORE_COLL 0x0004 /* disable CSMA/CD backoff
@@ -1353,32 +1353,32 @@
1353 full duplex and 0 when 1353 full duplex and 0 when
1354 half duplex */ 1354 half duplex */
1355#define MAC_TX_CFG_IPG_EN 0x0008 /* enable extension of the 1355#define MAC_TX_CFG_IPG_EN 0x0008 /* enable extension of the
1356 Rx-to-TX IPG. after 1356 Rx-to-TX IPG. after
1357 receiving a frame, TX 1357 receiving a frame, TX
1358 MAC will reset its 1358 MAC will reset its
1359 deferral process to 1359 deferral process to
1360 carrier sense for the 1360 carrier sense for the
1361 amount of time = IPG0 + 1361 amount of time = IPG0 +
1362 IPG1 and commit to 1362 IPG1 and commit to
1363 transmission for time 1363 transmission for time
1364 specified in IPG2. when 1364 specified in IPG2. when
1365 0 or when xmitting frames 1365 0 or when xmitting frames
1366 back-to-pack (Tx-to-Tx 1366 back-to-pack (Tx-to-Tx
1367 IPG), TX MAC ignores 1367 IPG), TX MAC ignores
1368 IPG0 and will only use 1368 IPG0 and will only use
1369 IPG1 for deferral time. 1369 IPG1 for deferral time.
1370 IPG2 still used. */ 1370 IPG2 still used. */
1371#define MAC_TX_CFG_NEVER_GIVE_UP_EN 0x0010 /* TX MAC will not easily 1371#define MAC_TX_CFG_NEVER_GIVE_UP_EN 0x0010 /* TX MAC will not easily
1372 give up on frame 1372 give up on frame
1373 xmission. if backoff 1373 xmission. if backoff
1374 algorithm reaches the 1374 algorithm reaches the
1375 ATTEMPT_LIMIT, it will 1375 ATTEMPT_LIMIT, it will
1376 clear attempts counter 1376 clear attempts counter
1377 and continue trying to 1377 and continue trying to
1378 send the frame as 1378 send the frame as
1379 specified by 1379 specified by
1380 GIVE_UP_LIM. when 0, 1380 GIVE_UP_LIM. when 0,
1381 TX MAC will execute 1381 TX MAC will execute
1382 standard CSMA/CD prot. */ 1382 standard CSMA/CD prot. */
1383#define MAC_TX_CFG_NEVER_GIVE_UP_LIM 0x0020 /* when set, TX MAC will 1383#define MAC_TX_CFG_NEVER_GIVE_UP_LIM 0x0020 /* when set, TX MAC will
1384 continue to try to xmit 1384 continue to try to xmit
@@ -1386,13 +1386,13 @@
1386 0, TX MAC will continue 1386 0, TX MAC will continue
1387 to try xmitting until 1387 to try xmitting until
1388 successful or backoff 1388 successful or backoff
1389 algorithm reaches 1389 algorithm reaches
1390 ATTEMPT_LIMIT*16 */ 1390 ATTEMPT_LIMIT*16 */
1391#define MAC_TX_CFG_NO_BACKOFF 0x0040 /* modify CSMA/CD to disable 1391#define MAC_TX_CFG_NO_BACKOFF 0x0040 /* modify CSMA/CD to disable
1392 backoff algorithm. TX 1392 backoff algorithm. TX
1393 MAC will not back off 1393 MAC will not back off
1394 after a xmission attempt 1394 after a xmission attempt
1395 that resulted in a 1395 that resulted in a
1396 collision. */ 1396 collision. */
1397#define MAC_TX_CFG_SLOW_DOWN 0x0080 /* modify CSMA/CD so that 1397#define MAC_TX_CFG_SLOW_DOWN 0x0080 /* modify CSMA/CD so that
1398 deferral process is reset 1398 deferral process is reset
@@ -1408,11 +1408,11 @@
1408 packets. when clear, CRC 1408 packets. when clear, CRC
1409 generation is dependent 1409 generation is dependent
1410 upon NO_CRC bit in the 1410 upon NO_CRC bit in the
1411 xmit control word from 1411 xmit control word from
1412 TX DMA */ 1412 TX DMA */
1413#define MAC_TX_CFG_CARRIER_EXTEND 0x0200 /* enables xmit part of the 1413#define MAC_TX_CFG_CARRIER_EXTEND 0x0200 /* enables xmit part of the
1414 carrier extension 1414 carrier extension
1415 feature. this allows for 1415 feature. this allows for
1416 longer collision domains 1416 longer collision domains
1417 by extending the carrier 1417 by extending the carrier
1418 and collision window 1418 and collision window
@@ -1422,44 +1422,44 @@
1422 for half-duplex at 1Gbps, 1422 for half-duplex at 1Gbps,
1423 clear otherwise. */ 1423 clear otherwise. */
1424 1424
1425/* when CRC is not stripped, reassembly packets will not contain the CRC. 1425/* when CRC is not stripped, reassembly packets will not contain the CRC.
1426 * these will be stripped by HRP because it reassembles layer 4 data, and the 1426 * these will be stripped by HRP because it reassembles layer 4 data, and the
1427 * CRC is layer 2. however, non-reassembly packets will still contain the CRC 1427 * CRC is layer 2. however, non-reassembly packets will still contain the CRC
1428 * when passed to the host. to ensure proper operation, need to wait 3.2ms 1428 * when passed to the host. to ensure proper operation, need to wait 3.2ms
1429 * after clearing RX_CFG_EN before writing to any other RX MAC registers 1429 * after clearing RX_CFG_EN before writing to any other RX MAC registers
1430 * or other MAC parameters. alternatively, poll RX_CFG_EN until it clears 1430 * or other MAC parameters. alternatively, poll RX_CFG_EN until it clears
1431 * to 0. similary, HASH_FILTER_EN and ADDR_FILTER_EN have the same 1431 * to 0. similary, HASH_FILTER_EN and ADDR_FILTER_EN have the same
1432 * restrictions as CFG_EN. 1432 * restrictions as CFG_EN.
1433 */ 1433 */
1434#define REG_MAC_RX_CFG 0x6034 /* RX MAC config reg */ 1434#define REG_MAC_RX_CFG 0x6034 /* RX MAC config reg */
1435#define MAC_RX_CFG_EN 0x0001 /* enable RX MAC */ 1435#define MAC_RX_CFG_EN 0x0001 /* enable RX MAC */
1436#define MAC_RX_CFG_STRIP_PAD 0x0002 /* always program to 0. 1436#define MAC_RX_CFG_STRIP_PAD 0x0002 /* always program to 0.
1437 feature not supported */ 1437 feature not supported */
1438#define MAC_RX_CFG_STRIP_FCS 0x0004 /* RX MAC will strip the 1438#define MAC_RX_CFG_STRIP_FCS 0x0004 /* RX MAC will strip the
1439 last 4 bytes of a 1439 last 4 bytes of a
1440 received frame. */ 1440 received frame. */
1441#define MAC_RX_CFG_PROMISC_EN 0x0008 /* promiscuous mode */ 1441#define MAC_RX_CFG_PROMISC_EN 0x0008 /* promiscuous mode */
1442#define MAC_RX_CFG_PROMISC_GROUP_EN 0x0010 /* accept all valid 1442#define MAC_RX_CFG_PROMISC_GROUP_EN 0x0010 /* accept all valid
1443 multicast frames (group 1443 multicast frames (group
1444 bit in DA field set) */ 1444 bit in DA field set) */
1445#define MAC_RX_CFG_HASH_FILTER_EN 0x0020 /* use hash table to filter 1445#define MAC_RX_CFG_HASH_FILTER_EN 0x0020 /* use hash table to filter
1446 multicast addresses */ 1446 multicast addresses */
1447#define MAC_RX_CFG_ADDR_FILTER_EN 0x0040 /* cause RX MAC to use 1447#define MAC_RX_CFG_ADDR_FILTER_EN 0x0040 /* cause RX MAC to use
1448 address filtering regs 1448 address filtering regs
1449 to filter both unicast 1449 to filter both unicast
1450 and multicast 1450 and multicast
1451 addresses */ 1451 addresses */
1452#define MAC_RX_CFG_DISABLE_DISCARD 0x0080 /* pass errored frames to 1452#define MAC_RX_CFG_DISABLE_DISCARD 0x0080 /* pass errored frames to
1453 RX DMA by setting BAD 1453 RX DMA by setting BAD
1454 bit but not Abort bit 1454 bit but not Abort bit
1455 in the status. CRC, 1455 in the status. CRC,
1456 framing, and length errs 1456 framing, and length errs
1457 will not increment 1457 will not increment
1458 error counters. frames 1458 error counters. frames
1459 which don't match dest 1459 which don't match dest
1460 addr will be passed up 1460 addr will be passed up
1461 w/ BAD bit set. */ 1461 w/ BAD bit set. */
1462#define MAC_RX_CFG_CARRIER_EXTEND 0x0100 /* enable reception of 1462#define MAC_RX_CFG_CARRIER_EXTEND 0x0100 /* enable reception of
1463 packet bursts generated 1463 packet bursts generated
1464 by carrier extension 1464 by carrier extension
1465 with packet bursting 1465 with packet bursting
@@ -1468,18 +1468,18 @@
1468 1468
1469/* DEFAULT: 0x0 */ 1469/* DEFAULT: 0x0 */
1470#define REG_MAC_CTRL_CFG 0x6038 /* MAC control config reg */ 1470#define REG_MAC_CTRL_CFG 0x6038 /* MAC control config reg */
1471#define MAC_CTRL_CFG_SEND_PAUSE_EN 0x0001 /* respond to requests for 1471#define MAC_CTRL_CFG_SEND_PAUSE_EN 0x0001 /* respond to requests for
1472 sending pause flow ctrl 1472 sending pause flow ctrl
1473 frames */ 1473 frames */
1474#define MAC_CTRL_CFG_RECV_PAUSE_EN 0x0002 /* respond to received 1474#define MAC_CTRL_CFG_RECV_PAUSE_EN 0x0002 /* respond to received
1475 pause flow ctrl frames */ 1475 pause flow ctrl frames */
1476#define MAC_CTRL_CFG_PASS_CTRL 0x0004 /* pass valid MAC ctrl 1476#define MAC_CTRL_CFG_PASS_CTRL 0x0004 /* pass valid MAC ctrl
1477 packets to RX DMA */ 1477 packets to RX DMA */
1478 1478
1479/* to ensure proper operation, a global initialization sequence should be 1479/* to ensure proper operation, a global initialization sequence should be
1480 * performed when a loopback config is entered or exited. if programmed after 1480 * performed when a loopback config is entered or exited. if programmed after
1481 * a hw or global sw reset, RX/TX MAC software reset and initialization 1481 * a hw or global sw reset, RX/TX MAC software reset and initialization
1482 * should be done to ensure stable clocking. 1482 * should be done to ensure stable clocking.
1483 * DEFAULT: 0x0 1483 * DEFAULT: 0x0
1484 */ 1484 */
1485#define REG_MAC_XIF_CFG 0x603C /* XIF config reg */ 1485#define REG_MAC_XIF_CFG 0x603C /* XIF config reg */
@@ -1489,26 +1489,26 @@
1489 path to GMII recv data 1489 path to GMII recv data
1490 path. phy mode register 1490 path. phy mode register
1491 clock selection must be 1491 clock selection must be
1492 set to GMII mode and 1492 set to GMII mode and
1493 GMII_MODE should be set 1493 GMII_MODE should be set
1494 to 1. in loopback mode, 1494 to 1. in loopback mode,
1495 REFCLK will drive the 1495 REFCLK will drive the
1496 entire mac core. 0 for 1496 entire mac core. 0 for
1497 normal operation. */ 1497 normal operation. */
1498#define MAC_XIF_DISABLE_ECHO 0x0004 /* disables receive data 1498#define MAC_XIF_DISABLE_ECHO 0x0004 /* disables receive data
1499 path during packet 1499 path during packet
1500 xmission. clear to 0 1500 xmission. clear to 0
1501 in any full duplex mode, 1501 in any full duplex mode,
1502 in any loopback mode, 1502 in any loopback mode,
1503 or in half-duplex SERDES 1503 or in half-duplex SERDES
1504 or SLINK modes. set when 1504 or SLINK modes. set when
1505 in half-duplex when 1505 in half-duplex when
1506 using external phy. */ 1506 using external phy. */
1507#define MAC_XIF_GMII_MODE 0x0008 /* MAC operates with GMII 1507#define MAC_XIF_GMII_MODE 0x0008 /* MAC operates with GMII
1508 clocks and datapath */ 1508 clocks and datapath */
1509#define MAC_XIF_MII_BUFFER_OUTPUT_EN 0x0010 /* MII_BUF_EN pin. enable 1509#define MAC_XIF_MII_BUFFER_OUTPUT_EN 0x0010 /* MII_BUF_EN pin. enable
1510 external tristate buffer 1510 external tristate buffer
1511 on the MII receive 1511 on the MII receive
1512 bus. */ 1512 bus. */
1513#define MAC_XIF_LINK_LED 0x0020 /* LINKLED# active (low) */ 1513#define MAC_XIF_LINK_LED 0x0020 /* LINKLED# active (low) */
1514#define MAC_XIF_FDPLX_LED 0x0040 /* FDPLXLED# active (low) */ 1514#define MAC_XIF_FDPLX_LED 0x0040 /* FDPLXLED# active (low) */
@@ -1521,7 +1521,7 @@
1521 recommended: 0x04 */ 1521 recommended: 0x04 */
1522#define REG_MAC_SLOT_TIME 0x604C /* slot time reg 1522#define REG_MAC_SLOT_TIME 0x604C /* slot time reg
1523 recommended: 0x40 */ 1523 recommended: 0x40 */
1524#define REG_MAC_FRAMESIZE_MIN 0x6050 /* min frame size reg 1524#define REG_MAC_FRAMESIZE_MIN 0x6050 /* min frame size reg
1525 recommended: 0x40 */ 1525 recommended: 0x40 */
1526 1526
1527/* FRAMESIZE_MAX holds both the max frame size as well as the max burst size. 1527/* FRAMESIZE_MAX holds both the max frame size as well as the max burst size.
@@ -1536,39 +1536,39 @@
1536 preamble bytes that the 1536 preamble bytes that the
1537 TX MAC will xmit at the 1537 TX MAC will xmit at the
1538 beginning of each frame 1538 beginning of each frame
1539 value should be 2 or 1539 value should be 2 or
1540 greater. recommended 1540 greater. recommended
1541 value: 0x07 */ 1541 value: 0x07 */
1542#define REG_MAC_JAM_SIZE 0x605C /* jam size reg. duration 1542#define REG_MAC_JAM_SIZE 0x605C /* jam size reg. duration
1543 of jam in units of media 1543 of jam in units of media
1544 byte time. recommended 1544 byte time. recommended
1545 value: 0x04 */ 1545 value: 0x04 */
1546#define REG_MAC_ATTEMPT_LIMIT 0x6060 /* attempt limit reg. # 1546#define REG_MAC_ATTEMPT_LIMIT 0x6060 /* attempt limit reg. #
1547 of attempts TX MAC will 1547 of attempts TX MAC will
1548 make to xmit a frame 1548 make to xmit a frame
1549 before it resets its 1549 before it resets its
1550 attempts counter. after 1550 attempts counter. after
1551 the limit has been 1551 the limit has been
1552 reached, TX MAC may or 1552 reached, TX MAC may or
1553 may not drop the frame 1553 may not drop the frame
1554 dependent upon value 1554 dependent upon value
1555 in TX_MAC_CFG. 1555 in TX_MAC_CFG.
1556 recommended 1556 recommended
1557 value: 0x10 */ 1557 value: 0x10 */
1558#define REG_MAC_CTRL_TYPE 0x6064 /* MAC control type reg. 1558#define REG_MAC_CTRL_TYPE 0x6064 /* MAC control type reg.
1559 type field of a MAC 1559 type field of a MAC
1560 ctrl frame. recommended 1560 ctrl frame. recommended
1561 value: 0x8808 */ 1561 value: 0x8808 */
1562 1562
1563/* mac address registers: 0 - 44, 0x6080 - 0x6130, 4 8-bit bytes. 1563/* mac address registers: 0 - 44, 0x6080 - 0x6130, 4 8-bit bytes.
1564 * register contains comparison 1564 * register contains comparison
1565 * 0 16 MSB of primary MAC addr [47:32] of DA field 1565 * 0 16 MSB of primary MAC addr [47:32] of DA field
1566 * 1 16 middle bits "" [31:16] of DA field 1566 * 1 16 middle bits "" [31:16] of DA field
1567 * 2 16 LSB "" [15:0] of DA field 1567 * 2 16 LSB "" [15:0] of DA field
1568 * 3*x 16MSB of alt MAC addr 1-15 [47:32] of DA field 1568 * 3*x 16MSB of alt MAC addr 1-15 [47:32] of DA field
1569 * 4*x 16 middle bits "" [31:16] 1569 * 4*x 16 middle bits "" [31:16]
1570 * 5*x 16 LSB "" [15:0] 1570 * 5*x 16 LSB "" [15:0]
1571 * 42 16 MSB of MAC CTRL addr [47:32] of DA. 1571 * 42 16 MSB of MAC CTRL addr [47:32] of DA.
1572 * 43 16 middle bits "" [31:16] 1572 * 43 16 middle bits "" [31:16]
1573 * 44 16 LSB "" [15:0] 1573 * 44 16 LSB "" [15:0]
1574 * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames. 1574 * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames.
@@ -1586,39 +1586,39 @@
1586#define REG_MAC_ADDRN(x) (REG_MAC_ADDR0 + (x)*4) 1586#define REG_MAC_ADDRN(x) (REG_MAC_ADDR0 + (x)*4)
1587#define REG_MAC_ADDR_FILTER0 0x614C /* address filter 0 reg 1587#define REG_MAC_ADDR_FILTER0 0x614C /* address filter 0 reg
1588 [47:32] */ 1588 [47:32] */
1589#define REG_MAC_ADDR_FILTER1 0x6150 /* address filter 1 reg 1589#define REG_MAC_ADDR_FILTER1 0x6150 /* address filter 1 reg
1590 [31:16] */ 1590 [31:16] */
1591#define REG_MAC_ADDR_FILTER2 0x6154 /* address filter 2 reg 1591#define REG_MAC_ADDR_FILTER2 0x6154 /* address filter 2 reg
1592 [15:0] */ 1592 [15:0] */
1593#define REG_MAC_ADDR_FILTER2_1_MASK 0x6158 /* address filter 2 and 1 1593#define REG_MAC_ADDR_FILTER2_1_MASK 0x6158 /* address filter 2 and 1
1594 mask reg. 8-bit reg 1594 mask reg. 8-bit reg
1595 contains nibble mask for 1595 contains nibble mask for
1596 reg 2 and 1. */ 1596 reg 2 and 1. */
1597#define REG_MAC_ADDR_FILTER0_MASK 0x615C /* address filter 0 mask 1597#define REG_MAC_ADDR_FILTER0_MASK 0x615C /* address filter 0 mask
1598 reg */ 1598 reg */
1599 1599
1600/* hash table registers: 0 - 15, 0x6160 - 0x619C, 4 8-bit bytes 1600/* hash table registers: 0 - 15, 0x6160 - 0x619C, 4 8-bit bytes
1601 * 16-bit registers contain bits of the hash table. 1601 * 16-bit registers contain bits of the hash table.
1602 * reg x -> [16*(15 - x) + 15 : 16*(15 - x)]. 1602 * reg x -> [16*(15 - x) + 15 : 16*(15 - x)].
1603 * e.g., 15 -> [15:0], 0 -> [255:240] 1603 * e.g., 15 -> [15:0], 0 -> [255:240]
1604 */ 1604 */
1605#define REG_MAC_HASH_TABLE0 0x6160 /* hash table 0 reg */ 1605#define REG_MAC_HASH_TABLE0 0x6160 /* hash table 0 reg */
1606#define REG_MAC_HASH_TABLEN(x) (REG_MAC_HASH_TABLE0 + (x)*4) 1606#define REG_MAC_HASH_TABLEN(x) (REG_MAC_HASH_TABLE0 + (x)*4)
1607 1607
1608/* statistics registers. these registers generate an interrupt on 1608/* statistics registers. these registers generate an interrupt on
1609 * overflow. recommended initialization: 0x0000. most are 16-bits except 1609 * overflow. recommended initialization: 0x0000. most are 16-bits except
1610 * for PEAK_ATTEMPTS register which is 8 bits. 1610 * for PEAK_ATTEMPTS register which is 8 bits.
1611 */ 1611 */
1612#define REG_MAC_COLL_NORMAL 0x61A0 /* normal collision 1612#define REG_MAC_COLL_NORMAL 0x61A0 /* normal collision
1613 counter. */ 1613 counter. */
1614#define REG_MAC_COLL_FIRST 0x61A4 /* first attempt 1614#define REG_MAC_COLL_FIRST 0x61A4 /* first attempt
1615 successful collision 1615 successful collision
1616 counter */ 1616 counter */
1617#define REG_MAC_COLL_EXCESS 0x61A8 /* excessive collision 1617#define REG_MAC_COLL_EXCESS 0x61A8 /* excessive collision
1618 counter */ 1618 counter */
1619#define REG_MAC_COLL_LATE 0x61AC /* late collision counter */ 1619#define REG_MAC_COLL_LATE 0x61AC /* late collision counter */
1620#define REG_MAC_TIMER_DEFER 0x61B0 /* defer timer. time base 1620#define REG_MAC_TIMER_DEFER 0x61B0 /* defer timer. time base
1621 is the media byte 1621 is the media byte
1622 clock/256 */ 1622 clock/256 */
1623#define REG_MAC_ATTEMPTS_PEAK 0x61B4 /* peak attempts reg */ 1623#define REG_MAC_ATTEMPTS_PEAK 0x61B4 /* peak attempts reg */
1624#define REG_MAC_RECV_FRAME 0x61B8 /* receive frame counter */ 1624#define REG_MAC_RECV_FRAME 0x61B8 /* receive frame counter */
@@ -1633,13 +1633,13 @@
1633 10-bit register used as a 1633 10-bit register used as a
1634 seed for the random number 1634 seed for the random number
1635 generator for the CSMA/CD 1635 generator for the CSMA/CD
1636 backoff algorithm. only 1636 backoff algorithm. only
1637 programmed after power-on 1637 programmed after power-on
1638 reset and should be a 1638 reset and should be a
1639 random value which has a 1639 random value which has a
1640 high likelihood of being 1640 high likelihood of being
1641 unique for each MAC 1641 unique for each MAC
1642 attached to a network 1642 attached to a network
1643 segment (e.g., 10 LSB of 1643 segment (e.g., 10 LSB of
1644 MAC address) */ 1644 MAC address) */
1645 1645
@@ -1649,7 +1649,7 @@
1649 1649
1650/* 27-bit register has the current state for key state machines in the MAC */ 1650/* 27-bit register has the current state for key state machines in the MAC */
1651#define REG_MAC_STATE_MACHINE 0x61D0 /* (ro) state machine reg */ 1651#define REG_MAC_STATE_MACHINE 0x61D0 /* (ro) state machine reg */
1652#define MAC_SM_RLM_MASK 0x07800000 1652#define MAC_SM_RLM_MASK 0x07800000
1653#define MAC_SM_RLM_SHIFT 23 1653#define MAC_SM_RLM_SHIFT 23
1654#define MAC_SM_RX_FC_MASK 0x00700000 1654#define MAC_SM_RX_FC_MASK 0x00700000
1655#define MAC_SM_RX_FC_SHIFT 20 1655#define MAC_SM_RX_FC_SHIFT 20
@@ -1666,26 +1666,26 @@
1666#define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007 1666#define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007
1667#define MAC_SM_TX_FIFO_EMPTY_SHIFT 0 1667#define MAC_SM_TX_FIFO_EMPTY_SHIFT 0
1668 1668
1669/** MIF registers. the MIF can be programmed in either bit-bang or 1669/** MIF registers. the MIF can be programmed in either bit-bang or
1670 * frame mode. 1670 * frame mode.
1671 **/ 1671 **/
1672#define REG_MIF_BIT_BANG_CLOCK 0x6200 /* MIF bit-bang clock. 1672#define REG_MIF_BIT_BANG_CLOCK 0x6200 /* MIF bit-bang clock.
1673 1 -> 0 will generate a 1673 1 -> 0 will generate a
1674 rising edge. 0 -> 1 will 1674 rising edge. 0 -> 1 will
1675 generate a falling edge. */ 1675 generate a falling edge. */
1676#define REG_MIF_BIT_BANG_DATA 0x6204 /* MIF bit-bang data. 1-bit 1676#define REG_MIF_BIT_BANG_DATA 0x6204 /* MIF bit-bang data. 1-bit
1677 register generates data */ 1677 register generates data */
1678#define REG_MIF_BIT_BANG_OUTPUT_EN 0x6208 /* MIF bit-bang output 1678#define REG_MIF_BIT_BANG_OUTPUT_EN 0x6208 /* MIF bit-bang output
1679 enable. enable when 1679 enable. enable when
1680 xmitting data from MIF to 1680 xmitting data from MIF to
1681 transceiver. */ 1681 transceiver. */
1682 1682
1683/* 32-bit register serves as an instruction register when the MIF is 1683/* 32-bit register serves as an instruction register when the MIF is
1684 * programmed in frame mode. load this register w/ a valid instruction 1684 * programmed in frame mode. load this register w/ a valid instruction
1685 * (as per IEEE 802.3u MII spec). poll this register to check for instruction 1685 * (as per IEEE 802.3u MII spec). poll this register to check for instruction
1686 * execution completion. during a read operation, this register will also 1686 * execution completion. during a read operation, this register will also
1687 * contain the 16-bit data returned by the tranceiver. unless specified 1687 * contain the 16-bit data returned by the tranceiver. unless specified
1688 * otherwise, fields are considered "don't care" when polling for 1688 * otherwise, fields are considered "don't care" when polling for
1689 * completion. 1689 * completion.
1690 */ 1690 */
1691#define REG_MIF_FRAME 0x620C /* MIF frame/output reg */ 1691#define REG_MIF_FRAME 0x620C /* MIF frame/output reg */
@@ -1693,14 +1693,14 @@
1693 load w/ 01 when 1693 load w/ 01 when
1694 issuing an instr */ 1694 issuing an instr */
1695#define MIF_FRAME_ST 0x40000000 /* STart of frame */ 1695#define MIF_FRAME_ST 0x40000000 /* STart of frame */
1696#define MIF_FRAME_OPCODE_MASK 0x30000000 /* opcode. 01 for a 1696#define MIF_FRAME_OPCODE_MASK 0x30000000 /* opcode. 01 for a
1697 write. 10 for a 1697 write. 10 for a
1698 read */ 1698 read */
1699#define MIF_FRAME_OP_READ 0x20000000 /* read OPcode */ 1699#define MIF_FRAME_OP_READ 0x20000000 /* read OPcode */
1700#define MIF_FRAME_OP_WRITE 0x10000000 /* write OPcode */ 1700#define MIF_FRAME_OP_WRITE 0x10000000 /* write OPcode */
1701#define MIF_FRAME_PHY_ADDR_MASK 0x0F800000 /* phy address. when 1701#define MIF_FRAME_PHY_ADDR_MASK 0x0F800000 /* phy address. when
1702 issuing an instr, 1702 issuing an instr,
1703 this field should be 1703 this field should be
1704 loaded w/ the XCVR 1704 loaded w/ the XCVR
1705 addr */ 1705 addr */
1706#define MIF_FRAME_PHY_ADDR_SHIFT 23 1706#define MIF_FRAME_PHY_ADDR_SHIFT 23
@@ -1724,12 +1724,12 @@
1724 to be written in 1724 to be written in
1725 transceiver reg for a 1725 transceiver reg for a
1726 write. doesn't matter 1726 write. doesn't matter
1727 in a read. when 1727 in a read. when
1728 polling for 1728 polling for
1729 completion, field is 1729 completion, field is
1730 "don't care" for write 1730 "don't care" for write
1731 and 16-bit data 1731 and 16-bit data
1732 returned by the 1732 returned by the
1733 transceiver for a 1733 transceiver for a
1734 read (if valid bit 1734 read (if valid bit
1735 is set) */ 1735 is set) */
@@ -1748,16 +1748,16 @@
1748#define MIF_CFG_POLL_REG_SHIFT 3 1748#define MIF_CFG_POLL_REG_SHIFT 3
1749#define MIF_CFG_MDIO_0 0x0100 /* (ro) dual purpose. 1749#define MIF_CFG_MDIO_0 0x0100 /* (ro) dual purpose.
1750 when MDIO_0 is idle, 1750 when MDIO_0 is idle,
1751 1 -> tranceiver is 1751 1 -> tranceiver is
1752 connected to MDIO_0. 1752 connected to MDIO_0.
1753 when MIF is communicating 1753 when MIF is communicating
1754 w/ MDIO_0 in bit-bang 1754 w/ MDIO_0 in bit-bang
1755 mode, this bit indicates 1755 mode, this bit indicates
1756 the incoming bit stream 1756 the incoming bit stream
1757 during a read op */ 1757 during a read op */
1758#define MIF_CFG_MDIO_1 0x0200 /* (ro) dual purpose. 1758#define MIF_CFG_MDIO_1 0x0200 /* (ro) dual purpose.
1759 when MDIO_1 is idle, 1759 when MDIO_1 is idle,
1760 1 -> transceiver is 1760 1 -> transceiver is
1761 connected to MDIO_1. 1761 connected to MDIO_1.
1762 when MIF is communicating 1762 when MIF is communicating
1763 w/ MDIO_1 in bit-bang 1763 w/ MDIO_1 in bit-bang
@@ -1770,7 +1770,7 @@
1770 1770
1771/* 16-bit register used to determine which bits in the POLL_STATUS portion of 1771/* 16-bit register used to determine which bits in the POLL_STATUS portion of
1772 * the MIF_STATUS register will cause an interrupt. if a mask bit is 0, 1772 * the MIF_STATUS register will cause an interrupt. if a mask bit is 0,
1773 * corresponding bit of the POLL_STATUS will generate a MIF interrupt when 1773 * corresponding bit of the POLL_STATUS will generate a MIF interrupt when
1774 * set. DEFAULT: 0xFFFF 1774 * set. DEFAULT: 0xFFFF
1775 */ 1775 */
1776#define REG_MIF_MASK 0x6214 /* MIF mask reg */ 1776#define REG_MIF_MASK 0x6214 /* MIF mask reg */
@@ -1779,7 +1779,7 @@
1779#define REG_MIF_STATUS 0x6218 /* MIF status reg */ 1779#define REG_MIF_STATUS 0x6218 /* MIF status reg */
1780#define MIF_STATUS_POLL_DATA_MASK 0xFFFF0000 /* poll data contains 1780#define MIF_STATUS_POLL_DATA_MASK 0xFFFF0000 /* poll data contains
1781 the "latest image" 1781 the "latest image"
1782 update of the XCVR 1782 update of the XCVR
1783 reg being read */ 1783 reg being read */
1784#define MIF_STATUS_POLL_DATA_SHIFT 16 1784#define MIF_STATUS_POLL_DATA_SHIFT 16
1785#define MIF_STATUS_POLL_STATUS_MASK 0x0000FFFF /* poll status indicates 1785#define MIF_STATUS_POLL_STATUS_MASK 0x0000FFFF /* poll status indicates
@@ -1792,19 +1792,19 @@
1792 1792
1793/* 7-bit register has current state for all state machines in the MIF */ 1793/* 7-bit register has current state for all state machines in the MIF */
1794#define REG_MIF_STATE_MACHINE 0x621C /* MIF state machine reg */ 1794#define REG_MIF_STATE_MACHINE 0x621C /* MIF state machine reg */
1795#define MIF_SM_CONTROL_MASK 0x07 /* control state machine 1795#define MIF_SM_CONTROL_MASK 0x07 /* control state machine
1796 state */ 1796 state */
1797#define MIF_SM_EXECUTION_MASK 0x60 /* execution state machine 1797#define MIF_SM_EXECUTION_MASK 0x60 /* execution state machine
1798 state */ 1798 state */
1799 1799
1800/** PCS/Serialink. the following registers are equivalent to the standard 1800/** PCS/Serialink. the following registers are equivalent to the standard
1801 * MII management registers except that they're directly mapped in 1801 * MII management registers except that they're directly mapped in
1802 * Cassini's register space. 1802 * Cassini's register space.
1803 **/ 1803 **/
1804 1804
1805/* the auto-negotiation enable bit should be programmed the same at 1805/* the auto-negotiation enable bit should be programmed the same at
1806 * the link partner as in the local device to enable auto-negotiation to 1806 * the link partner as in the local device to enable auto-negotiation to
1807 * complete. when that bit is reprogrammed, auto-neg/manual config is 1807 * complete. when that bit is reprogrammed, auto-neg/manual config is
1808 * restarted automatically. 1808 * restarted automatically.
1809 * DEFAULT: 0x1040 1809 * DEFAULT: 0x1040
1810 */ 1810 */
@@ -1815,10 +1815,10 @@
1815 to MAC interface is 1815 to MAC interface is
1816 activated regardless 1816 activated regardless
1817 of activity */ 1817 of activity */
1818#define PCS_MII_CTRL_DUPLEX 0x0100 /* forced 0x0. PCS 1818#define PCS_MII_CTRL_DUPLEX 0x0100 /* forced 0x0. PCS
1819 behaviour same for 1819 behaviour same for
1820 half and full dplx */ 1820 half and full dplx */
1821#define PCS_MII_RESTART_AUTONEG 0x0200 /* self clearing. 1821#define PCS_MII_RESTART_AUTONEG 0x0200 /* self clearing.
1822 restart auto- 1822 restart auto-
1823 negotiation */ 1823 negotiation */
1824#define PCS_MII_ISOLATE 0x0400 /* read as 0. ignored 1824#define PCS_MII_ISOLATE 0x0400 /* read as 0. ignored
@@ -1829,10 +1829,10 @@
1829 through automatic 1829 through automatic
1830 link config before it 1830 link config before it
1831 can be used. when 0, 1831 can be used. when 0,
1832 link can be used 1832 link can be used
1833 w/out any link config 1833 w/out any link config
1834 phase */ 1834 phase */
1835#define PCS_MII_10_100_SEL 0x2000 /* read as 0. ignored on 1835#define PCS_MII_10_100_SEL 0x2000 /* read as 0. ignored on
1836 writes */ 1836 writes */
1837#define PCS_MII_RESET 0x8000 /* reset PCS. self-clears 1837#define PCS_MII_RESET 0x8000 /* reset PCS. self-clears
1838 when done */ 1838 when done */
@@ -1841,7 +1841,7 @@
1841#define REG_PCS_MII_STATUS 0x9004 /* PCS MII status reg */ 1841#define REG_PCS_MII_STATUS 0x9004 /* PCS MII status reg */
1842#define PCS_MII_STATUS_EXTEND_CAP 0x0001 /* reads 0 */ 1842#define PCS_MII_STATUS_EXTEND_CAP 0x0001 /* reads 0 */
1843#define PCS_MII_STATUS_JABBER_DETECT 0x0002 /* reads 0 */ 1843#define PCS_MII_STATUS_JABBER_DETECT 0x0002 /* reads 0 */
1844#define PCS_MII_STATUS_LINK_STATUS 0x0004 /* 1 -> link up. 1844#define PCS_MII_STATUS_LINK_STATUS 0x0004 /* 1 -> link up.
1845 0 -> link down. 0 is 1845 0 -> link down. 0 is
1846 latched so that 0 is 1846 latched so that 0 is
1847 kept until read. read 1847 kept until read. read
@@ -1853,7 +1853,7 @@
1853 from received link code 1853 from received link code
1854 word. only valid after 1854 word. only valid after
1855 auto-neg completed */ 1855 auto-neg completed */
1856#define PCS_MII_STATUS_AUTONEG_COMP 0x0020 /* 1 -> auto-negotiation 1856#define PCS_MII_STATUS_AUTONEG_COMP 0x0020 /* 1 -> auto-negotiation
1857 completed 1857 completed
1858 0 -> auto-negotiation not 1858 0 -> auto-negotiation not
1859 completed */ 1859 completed */
@@ -1862,7 +1862,7 @@
1862 a 1000 Base-X PHY. writes 1862 a 1000 Base-X PHY. writes
1863 to it are ignored */ 1863 to it are ignored */
1864 1864
1865/* used during auto-negotiation. 1865/* used during auto-negotiation.
1866 * DEFAULT: 0x00E0 1866 * DEFAULT: 0x00E0
1867 */ 1867 */
1868#define REG_PCS_MII_ADVERT 0x9008 /* PCS MII advertisement 1868#define REG_PCS_MII_ADVERT 0x9008 /* PCS MII advertisement
@@ -1873,7 +1873,7 @@
1873 1000 Base-X */ 1873 1000 Base-X */
1874#define PCS_MII_ADVERT_SYM_PAUSE 0x0080 /* advertise PAUSE 1874#define PCS_MII_ADVERT_SYM_PAUSE 0x0080 /* advertise PAUSE
1875 symmetric capability */ 1875 symmetric capability */
1876#define PCS_MII_ADVERT_ASYM_PAUSE 0x0100 /* advertises PAUSE 1876#define PCS_MII_ADVERT_ASYM_PAUSE 0x0100 /* advertises PAUSE
1877 asymmetric capability */ 1877 asymmetric capability */
1878#define PCS_MII_ADVERT_RF_MASK 0x3000 /* remote fault. write bit13 1878#define PCS_MII_ADVERT_RF_MASK 0x3000 /* remote fault. write bit13
1879 to optionally indicate to 1879 to optionally indicate to
@@ -1881,7 +1881,7 @@
1881 going off-line. bit12 will 1881 going off-line. bit12 will
1882 get set when signal 1882 get set when signal
1883 detect == FAIL and will 1883 detect == FAIL and will
1884 remain set until 1884 remain set until
1885 successful negotiation */ 1885 successful negotiation */
1886#define PCS_MII_ADVERT_ACK 0x4000 /* (ro) */ 1886#define PCS_MII_ADVERT_ACK 0x4000 /* (ro) */
1887#define PCS_MII_ADVERT_NEXT_PAGE 0x8000 /* (ro) forced 0x0 */ 1887#define PCS_MII_ADVERT_NEXT_PAGE 0x8000 /* (ro) forced 0x0 */
@@ -1905,7 +1905,7 @@
1905 0 when modifying 1905 0 when modifying
1906 PCS_MII_ADVERT */ 1906 PCS_MII_ADVERT */
1907#define PCS_CFG_SD_OVERRIDE 0x02 /* sets signal detect to 1907#define PCS_CFG_SD_OVERRIDE 0x02 /* sets signal detect to
1908 OK. bit is 1908 OK. bit is
1909 non-resettable */ 1909 non-resettable */
1910#define PCS_CFG_SD_ACTIVE_LOW 0x04 /* changes interpretation 1910#define PCS_CFG_SD_ACTIVE_LOW 0x04 /* changes interpretation
1911 of optical signal to make 1911 of optical signal to make
@@ -1914,23 +1914,23 @@
1914#define PCS_CFG_JITTER_STUDY_MASK 0x18 /* used to make jitter 1914#define PCS_CFG_JITTER_STUDY_MASK 0x18 /* used to make jitter
1915 measurements. a single 1915 measurements. a single
1916 code group is xmitted 1916 code group is xmitted
1917 regularly. 1917 regularly.
1918 0x0 = normal operation 1918 0x0 = normal operation
1919 0x1 = high freq test 1919 0x1 = high freq test
1920 pattern, D21.5 1920 pattern, D21.5
1921 0x2 = low freq test 1921 0x2 = low freq test
1922 pattern, K28.7 1922 pattern, K28.7
1923 0x3 = reserved */ 1923 0x3 = reserved */
1924#define PCS_CFG_10MS_TIMER_OVERRIDE 0x20 /* shortens 10-20ms auto- 1924#define PCS_CFG_10MS_TIMER_OVERRIDE 0x20 /* shortens 10-20ms auto-
1925 negotiation timer to 1925 negotiation timer to
1926 a few cycles for test 1926 a few cycles for test
1927 purposes */ 1927 purposes */
1928 1928
1929/* used for diagnostic purposes. bits 20-22 autoclear on read */ 1929/* used for diagnostic purposes. bits 20-22 autoclear on read */
1930#define REG_PCS_STATE_MACHINE 0x9014 /* (ro) PCS state machine 1930#define REG_PCS_STATE_MACHINE 0x9014 /* (ro) PCS state machine
1931 and diagnostic reg */ 1931 and diagnostic reg */
1932#define PCS_SM_TX_STATE_MASK 0x0000000F /* 0 and 1 indicate 1932#define PCS_SM_TX_STATE_MASK 0x0000000F /* 0 and 1 indicate
1933 xmission of idle. 1933 xmission of idle.
1934 otherwise, xmission of 1934 otherwise, xmission of
1935 a packet */ 1935 a packet */
1936#define PCS_SM_RX_STATE_MASK 0x000000F0 /* 0 indicates reception 1936#define PCS_SM_RX_STATE_MASK 0x000000F0 /* 0 indicates reception
@@ -1943,39 +1943,39 @@
1943 Config codes. cycling 1943 Config codes. cycling
1944 through 0-1 indicates 1944 through 0-1 indicates
1945 reception of idles */ 1945 reception of idles */
1946#define PCS_SM_LINK_STATE_MASK 0x0001E000 1946#define PCS_SM_LINK_STATE_MASK 0x0001E000
1947#define SM_LINK_STATE_UP 0x00016000 /* link state is up */ 1947#define SM_LINK_STATE_UP 0x00016000 /* link state is up */
1948 1948
1949#define PCS_SM_LOSS_LINK_C 0x00100000 /* loss of link due to 1949#define PCS_SM_LOSS_LINK_C 0x00100000 /* loss of link due to
1950 recept of Config 1950 recept of Config
1951 codes */ 1951 codes */
1952#define PCS_SM_LOSS_LINK_SYNC 0x00200000 /* loss of link due to 1952#define PCS_SM_LOSS_LINK_SYNC 0x00200000 /* loss of link due to
1953 loss of sync */ 1953 loss of sync */
1954#define PCS_SM_LOSS_SIGNAL_DETECT 0x00400000 /* signal detect goes 1954#define PCS_SM_LOSS_SIGNAL_DETECT 0x00400000 /* signal detect goes
1955 from OK to FAIL. bit29 1955 from OK to FAIL. bit29
1956 will also be set if 1956 will also be set if
1957 this is set */ 1957 this is set */
1958#define PCS_SM_NO_LINK_BREAKLINK 0x01000000 /* link not up due to 1958#define PCS_SM_NO_LINK_BREAKLINK 0x01000000 /* link not up due to
1959 receipt of breaklink 1959 receipt of breaklink
1960 C codes from partner. 1960 C codes from partner.
1961 C codes w/ 0 content 1961 C codes w/ 0 content
1962 received triggering 1962 received triggering
1963 start/restart of 1963 start/restart of
1964 autonegotiation. 1964 autonegotiation.
1965 should be sent for 1965 should be sent for
1966 no longer than 20ms */ 1966 no longer than 20ms */
1967#define PCS_SM_NO_LINK_SERDES 0x02000000 /* serdes being 1967#define PCS_SM_NO_LINK_SERDES 0x02000000 /* serdes being
1968 initialized. see serdes 1968 initialized. see serdes
1969 state reg */ 1969 state reg */
1970#define PCS_SM_NO_LINK_C 0x04000000 /* C codes not stable or 1970#define PCS_SM_NO_LINK_C 0x04000000 /* C codes not stable or
1971 not received */ 1971 not received */
1972#define PCS_SM_NO_LINK_SYNC 0x08000000 /* word sync not 1972#define PCS_SM_NO_LINK_SYNC 0x08000000 /* word sync not
1973 achieved */ 1973 achieved */
1974#define PCS_SM_NO_LINK_WAIT_C 0x10000000 /* waiting for C codes 1974#define PCS_SM_NO_LINK_WAIT_C 0x10000000 /* waiting for C codes
1975 w/ ack bit set */ 1975 w/ ack bit set */
1976#define PCS_SM_NO_LINK_NO_IDLE 0x20000000 /* link partner continues 1976#define PCS_SM_NO_LINK_NO_IDLE 0x20000000 /* link partner continues
1977 to send C codes 1977 to send C codes
1978 instead of idle 1978 instead of idle
1979 symbols or pkt data */ 1979 symbols or pkt data */
1980 1980
1981/* this register indicates interrupt changes in specific PCS MII status bits. 1981/* this register indicates interrupt changes in specific PCS MII status bits.
@@ -1991,21 +1991,21 @@
1991 * DEFAULT: none 1991 * DEFAULT: none
1992 */ 1992 */
1993#define REG_PCS_DATAPATH_MODE 0x9050 /* datapath mode reg */ 1993#define REG_PCS_DATAPATH_MODE 0x9050 /* datapath mode reg */
1994#define PCS_DATAPATH_MODE_MII 0x00 /* PCS is not used and 1994#define PCS_DATAPATH_MODE_MII 0x00 /* PCS is not used and
1995 MII/GMII is selected. 1995 MII/GMII is selected.
1996 selection between MII and 1996 selection between MII and
1997 GMII is controlled by 1997 GMII is controlled by
1998 XIF_CFG */ 1998 XIF_CFG */
1999#define PCS_DATAPATH_MODE_SERDES 0x02 /* PCS is used via the 1999#define PCS_DATAPATH_MODE_SERDES 0x02 /* PCS is used via the
2000 10-bit interface */ 2000 10-bit interface */
2001 2001
2002/* input to serdes chip or serialink block */ 2002/* input to serdes chip or serialink block */
2003#define REG_PCS_SERDES_CTRL 0x9054 /* serdes control reg */ 2003#define REG_PCS_SERDES_CTRL 0x9054 /* serdes control reg */
2004#define PCS_SERDES_CTRL_LOOPBACK 0x01 /* enable loopback on 2004#define PCS_SERDES_CTRL_LOOPBACK 0x01 /* enable loopback on
2005 serdes interface */ 2005 serdes interface */
2006#define PCS_SERDES_CTRL_SYNCD_EN 0x02 /* enable sync carrier 2006#define PCS_SERDES_CTRL_SYNCD_EN 0x02 /* enable sync carrier
2007 detection. should be 2007 detection. should be
2008 0x0 for normal 2008 0x0 for normal
2009 operation */ 2009 operation */
2010#define PCS_SERDES_CTRL_LOCKREF 0x04 /* frequency-lock RBC[0:1] 2010#define PCS_SERDES_CTRL_LOCKREF 0x04 /* frequency-lock RBC[0:1]
2011 to REFCLK when set. 2011 to REFCLK when set.
@@ -2014,28 +2014,28 @@
2014 serial data */ 2014 serial data */
2015 2015
2016/* multiplex test outputs into the PROM address (PA_3 through PA_0) pins. 2016/* multiplex test outputs into the PROM address (PA_3 through PA_0) pins.
2017 * should be 0x0 for normal operations. 2017 * should be 0x0 for normal operations.
2018 * 0b000 normal operation, PROM address[3:0] selected 2018 * 0b000 normal operation, PROM address[3:0] selected
2019 * 0b001 rxdma req, rxdma ack, rxdma ready, rxdma read 2019 * 0b001 rxdma req, rxdma ack, rxdma ready, rxdma read
2020 * 0b010 rxmac req, rx ack, rx tag, rx clk shared 2020 * 0b010 rxmac req, rx ack, rx tag, rx clk shared
2021 * 0b011 txmac req, tx ack, tx tag, tx retry req 2021 * 0b011 txmac req, tx ack, tx tag, tx retry req
2022 * 0b100 tx tp3, tx tp2, tx tp1, tx tp0 2022 * 0b100 tx tp3, tx tp2, tx tp1, tx tp0
2023 * 0b101 R period RX, R period TX, R period HP, R period BIM 2023 * 0b101 R period RX, R period TX, R period HP, R period BIM
2024 * DEFAULT: 0x0 2024 * DEFAULT: 0x0
2025 */ 2025 */
2026#define REG_PCS_SHARED_OUTPUT_SEL 0x9058 /* shared output select */ 2026#define REG_PCS_SHARED_OUTPUT_SEL 0x9058 /* shared output select */
2027#define PCS_SOS_PROM_ADDR_MASK 0x0007 2027#define PCS_SOS_PROM_ADDR_MASK 0x0007
2028 2028
2029/* used for diagnostics. this register indicates progress of the SERDES 2029/* used for diagnostics. this register indicates progress of the SERDES
2030 * boot up. 2030 * boot up.
2031 * 0b00 undergoing reset 2031 * 0b00 undergoing reset
2032 * 0b01 waiting 500us while lockrefn is asserted 2032 * 0b01 waiting 500us while lockrefn is asserted
2033 * 0b10 waiting for comma detect 2033 * 0b10 waiting for comma detect
2034 * 0b11 receive data is synchronized 2034 * 0b11 receive data is synchronized
2035 * DEFAULT: 0x0 2035 * DEFAULT: 0x0
2036 */ 2036 */
2037#define REG_PCS_SERDES_STATE 0x905C /* (ro) serdes state */ 2037#define REG_PCS_SERDES_STATE 0x905C /* (ro) serdes state */
2038#define PCS_SERDES_STATE_MASK 0x03 2038#define PCS_SERDES_STATE_MASK 0x03
2039 2039
2040/* used for diagnostics. indicates number of packets transmitted or received. 2040/* used for diagnostics. indicates number of packets transmitted or received.
2041 * counters rollover w/out generating an interrupt. 2041 * counters rollover w/out generating an interrupt.
@@ -2044,18 +2044,18 @@
2044#define REG_PCS_PACKET_COUNT 0x9060 /* (ro) PCS packet counter */ 2044#define REG_PCS_PACKET_COUNT 0x9060 /* (ro) PCS packet counter */
2045#define PCS_PACKET_COUNT_TX 0x000007FF /* pkts xmitted by PCS */ 2045#define PCS_PACKET_COUNT_TX 0x000007FF /* pkts xmitted by PCS */
2046#define PCS_PACKET_COUNT_RX 0x07FF0000 /* pkts recvd by PCS 2046#define PCS_PACKET_COUNT_RX 0x07FF0000 /* pkts recvd by PCS
2047 whether they 2047 whether they
2048 encountered an error 2048 encountered an error
2049 or not */ 2049 or not */
2050 2050
2051/** LocalBus Devices. the following provides run-time access to the 2051/** LocalBus Devices. the following provides run-time access to the
2052 * Cassini's PROM 2052 * Cassini's PROM
2053 ***/ 2053 ***/
2054#define REG_EXPANSION_ROM_RUN_START 0x100000 /* expansion rom run time 2054#define REG_EXPANSION_ROM_RUN_START 0x100000 /* expansion rom run time
2055 access */ 2055 access */
2056#define REG_EXPANSION_ROM_RUN_END 0x17FFFF 2056#define REG_EXPANSION_ROM_RUN_END 0x17FFFF
2057 2057
2058#define REG_SECOND_LOCALBUS_START 0x180000 /* secondary local bus 2058#define REG_SECOND_LOCALBUS_START 0x180000 /* secondary local bus
2059 device */ 2059 device */
2060#define REG_SECOND_LOCALBUS_END 0x1FFFFF 2060#define REG_SECOND_LOCALBUS_END 0x1FFFFF
2061 2061
@@ -2103,7 +2103,7 @@
2103#define CAS_MII_1000_EXTEND 0x0F 2103#define CAS_MII_1000_EXTEND 0x0F
2104 2104
2105#define CAS_BMSR_1000_EXTEND 0x0100 /* supports 1000Base-T extended status */ 2105#define CAS_BMSR_1000_EXTEND 0x0100 /* supports 1000Base-T extended status */
2106/* 2106/*
2107 * if autoneg is disabled, here's the table: 2107 * if autoneg is disabled, here's the table:
2108 * BMCR_SPEED100 = 100Mbps 2108 * BMCR_SPEED100 = 100Mbps
2109 * BMCR_SPEED1000 = 1000Mbps 2109 * BMCR_SPEED1000 = 1000Mbps
@@ -2145,7 +2145,7 @@ typedef struct cas_hp_inst {
2145 u8 outenab; /* output enable: 0 = not, 1 = if match 2145 u8 outenab; /* output enable: 0 = not, 1 = if match
2146 2 = if !match, 3 = always */ 2146 2 = if !match, 3 = always */
2147 u8 outshift; /* barrel shift right, 4 bits */ 2147 u8 outshift; /* barrel shift right, 4 bits */
2148 u16 outmask; 2148 u16 outmask;
2149} cas_hp_inst_t; 2149} cas_hp_inst_t;
2150 2150
2151/* comparison */ 2151/* comparison */
@@ -2232,9 +2232,9 @@ typedef struct cas_hp_inst {
2232 2232
2233#ifdef USE_HP_IP46TCP4 2233#ifdef USE_HP_IP46TCP4
2234static cas_hp_inst_t cas_prog_ip46tcp4tab[] = { 2234static cas_hp_inst_t cas_prog_ip46tcp4tab[] = {
2235 CAS_PROG_IP46TCP4_PREAMBLE, 2235 CAS_PROG_IP46TCP4_PREAMBLE,
2236 { "TCP seq", /* DADDR should point to dest port */ 2236 { "TCP seq", /* DADDR should point to dest port */
2237 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ, 2237 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ,
2238 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ 2238 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2239 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0, 2239 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2240 S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */ 2240 S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */
@@ -2263,7 +2263,7 @@ static cas_hp_inst_t cas_prog_ip46tcp4tab[] = {
2263static cas_hp_inst_t cas_prog_ip46tcp4nohttptab[] = { 2263static cas_hp_inst_t cas_prog_ip46tcp4nohttptab[] = {
2264 CAS_PROG_IP46TCP4_PREAMBLE, 2264 CAS_PROG_IP46TCP4_PREAMBLE,
2265 { "TCP seq", /* DADDR should point to dest port */ 2265 { "TCP seq", /* DADDR should point to dest port */
2266 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ, 2266 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ,
2267 0x081, 3, 0x0, 0xffff} , /* Load TCP seq # */ 2267 0x081, 3, 0x0, 0xffff} , /* Load TCP seq # */
2268 { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0, 2268 { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0,
2269 S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f, }, /* Load TCP flags */ 2269 S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f, }, /* Load TCP flags */
@@ -2328,7 +2328,7 @@ static cas_hp_inst_t cas_prog_ip4fragtab[] = {
2328 { "TCP seq", /* DADDR should point to dest port */ 2328 { "TCP seq", /* DADDR should point to dest port */
2329 0x0000, 0x0000, OP_EQ, 0, S3_TCPFG, 4, S3_TCPFG, LD_SEQ, 2329 0x0000, 0x0000, OP_EQ, 0, S3_TCPFG, 4, S3_TCPFG, LD_SEQ,
2330 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ 2330 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2331 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHL, 0, 2331 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHL, 0,
2332 S3_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */ 2332 S3_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */
2333 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHc, 0, S3_TCPHc, 2333 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHc, 0, S3_TCPHc,
2334 LD_R1, 0x205, 3, 0xB, 0xf000}, 2334 LD_R1, 0x205, 3, 0xB, 0xf000},
@@ -2338,7 +2338,7 @@ static cas_hp_inst_t cas_prog_ip4fragtab[] = {
2338 LD_FID, 0x103, 3, 0x0, 0xffff}, /* FID IP4 src+dst */ 2338 LD_FID, 0x103, 3, 0x0, 0xffff}, /* FID IP4 src+dst */
2339 { "IP4 frag offset", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF, 2339 { "IP4 frag offset", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF,
2340 LD_SEQ, 0x040, 1, 0xD, 0xfff8}, 2340 LD_SEQ, 0x040, 1, 0xD, 0xfff8},
2341 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2341 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2342 IM_CTL, 0x001, 3, 0x0, 0x0001}, 2342 IM_CTL, 0x001, 3, 0x0, 0x0001},
2343 { NULL }, 2343 { NULL },
2344}; 2344};
@@ -2356,11 +2356,11 @@ static cas_hp_inst_t cas_prog_ip46tcp4batchtab[] = {
2356 { "TCP seq", /* DADDR should point to dest port */ 2356 { "TCP seq", /* DADDR should point to dest port */
2357 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 0, S1_TCPFG, LD_SEQ, 2357 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 0, S1_TCPFG, LD_SEQ,
2358 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ 2358 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2359 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0, 2359 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2360 S1_TCPHL, ST_FLG, 0x000, 3, 0x0, 0x0000}, /* Load TCP flags */ 2360 S1_TCPHL, ST_FLG, 0x000, 3, 0x0, 0x0000}, /* Load TCP flags */
2361 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, 2361 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0,
2362 S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000}, 2362 S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000},
2363 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, 2363 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2364 S1_PCKT, IM_CTL, 0x040, 3, 0x0, 0xffff}, /* set batch bit */ 2364 S1_PCKT, IM_CTL, 0x040, 3, 0x0, 0xffff}, /* set batch bit */
2365 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2365 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2366 IM_CTL, 0x001, 3, 0x0, 0x0001}, 2366 IM_CTL, 0x001, 3, 0x0, 0x0001},
@@ -2381,7 +2381,7 @@ static cas_hp_inst_t cas_prog_ip46tcp4batchtab[] = {
2381static cas_hp_inst_t cas_prog_workaroundtab[] = { 2381static cas_hp_inst_t cas_prog_workaroundtab[] = {
2382 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, 2382 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0,
2383 S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000} , 2383 S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000} ,
2384 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, 2384 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2385 IM_CTL, 0x04a, 3, 0x0, 0xffff}, 2385 IM_CTL, 0x04a, 3, 0x0, 0xffff},
2386 { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023, 2386 { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023,
2387 CL_REG, 0x000, 0, 0x0, 0x0000}, 2387 CL_REG, 0x000, 0, 0x0, 0x0000},
@@ -2395,7 +2395,7 @@ static cas_hp_inst_t cas_prog_workaroundtab[] = {
2395 IM_SAP, 0x6AE, 3, 0x0, 0xffff}, 2395 IM_SAP, 0x6AE, 3, 0x0, 0xffff},
2396 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP, 2396 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP,
2397 LD_SUM, 0x00a, 1, 0x0, 0x0000}, 2397 LD_SUM, 0x00a, 1, 0x0, 0x0000},
2398 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP, 2398 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP,
2399 LD_LEN, 0x03e, 1, 0x0, 0xffff}, 2399 LD_LEN, 0x03e, 1, 0x0, 0xffff},
2400 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP, 2400 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP,
2401 LD_FID, 0x182, 3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ 2401 LD_FID, 0x182, 3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
@@ -2408,7 +2408,7 @@ static cas_hp_inst_t cas_prog_workaroundtab[] = {
2408 { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP, 2408 { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP,
2409 LD_LEN, 0x03f, 1, 0x0, 0xffff}, 2409 LD_LEN, 0x03f, 1, 0x0, 0xffff},
2410 { "TCP seq", /* DADDR should point to dest port */ 2410 { "TCP seq", /* DADDR should point to dest port */
2411 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ, 2411 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ,
2412 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ 2412 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2413 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0, 2413 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2414 S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */ 2414 S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */
@@ -2429,7 +2429,7 @@ static cas_hp_inst_t cas_prog_workaroundtab[] = {
2429 2429
2430#ifdef USE_HP_ENCRYPT 2430#ifdef USE_HP_ENCRYPT
2431static cas_hp_inst_t cas_prog_encryptiontab[] = { 2431static cas_hp_inst_t cas_prog_encryptiontab[] = {
2432 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, 2432 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0,
2433 S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000}, 2433 S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000},
2434 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, 2434 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2435 IM_CTL, 0x00a, 3, 0x0, 0xffff}, 2435 IM_CTL, 0x00a, 3, 0x0, 0xffff},
@@ -2439,19 +2439,19 @@ static cas_hp_inst_t cas_prog_encryptiontab[] = {
2439 00, 2439 00,
2440#endif 2440#endif
2441 { "CFI?", /* FIND CFI and If FIND go to CleanUP1 (ignore and send to host) */ 2441 { "CFI?", /* FIND CFI and If FIND go to CleanUP1 (ignore and send to host) */
2442 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023, 2442 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023,
2443 CL_REG, 0x000, 0, 0x0, 0x0000}, 2443 CL_REG, 0x000, 0, 0x0, 0x0000},
2444 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, 2444 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
2445 CL_REG, 0x000, 0, 0x0, 0x0000}, 2445 CL_REG, 0x000, 0, 0x0, 0x0000},
2446 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP, 2446 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP,
2447 CL_REG, 0x000, 0, 0x0, 0x0000}, 2447 CL_REG, 0x000, 0, 0x0, 0x0000},
2448 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, 2448 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
2449 CL_REG, 0x000, 0, 0x0, 0x0000}, 2449 CL_REG, 0x000, 0, 0x0, 0x0000},
2450 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, 2450 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
2451 LD_SAP, 0x100, 3, 0x0, 0xffff}, 2451 LD_SAP, 0x100, 3, 0x0, 0xffff},
2452 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP, 2452 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP,
2453 LD_SUM, 0x00a, 1, 0x0, 0x0000}, 2453 LD_SUM, 0x00a, 1, 0x0, 0x0000},
2454 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP, 2454 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP,
2455 LD_LEN, 0x03e, 1, 0x0, 0xffff}, 2455 LD_LEN, 0x03e, 1, 0x0, 0xffff},
2456 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_ESP4, 2456 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_ESP4,
2457 LD_FID, 0x182, 1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ 2457 LD_FID, 0x182, 1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
@@ -2459,9 +2459,9 @@ static cas_hp_inst_t cas_prog_encryptiontab[] = {
2459 LD_SUM, 0x015, 1, 0x0, 0x0000}, 2459 LD_SUM, 0x015, 1, 0x0, 0x0000},
2460 { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP, 2460 { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP,
2461 IM_R1, 0x128, 1, 0x0, 0xffff}, 2461 IM_R1, 0x128, 1, 0x0, 0xffff},
2462 { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP, 2462 { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP,
2463 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ 2463 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */
2464 { "TCP64?", 2464 { "TCP64?",
2465#if 0 2465#if 0
2466//@@@0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_ESP6, LD_LEN, 0x03f, 1, 0x0, 0xffff, 2466//@@@0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_ESP6, LD_LEN, 0x03f, 1, 0x0, 0xffff,
2467#endif 2467#endif
@@ -2472,10 +2472,10 @@ static cas_hp_inst_t cas_prog_encryptiontab[] = {
2472 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ 2472 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2473 { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0, 2473 { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0,
2474 S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f}, /* Load TCP flags */ 2474 S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f}, /* Load TCP flags */
2475 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc, 2475 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
2476 LD_R1, 0x205, 3, 0xB, 0xf000} , 2476 LD_R1, 0x205, 3, 0xB, 0xf000} ,
2477 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, 2477 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2478 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff}, 2478 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2479 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2, 2479 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2480 IM_CTL, 0x001, 3, 0x0, 0x0001}, 2480 IM_CTL, 0x001, 3, 0x0, 0x0001},
2481 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2481 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
@@ -2483,7 +2483,7 @@ static cas_hp_inst_t cas_prog_encryptiontab[] = {
2483 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2483 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2484 IM_CTL, 0x080, 3, 0x0, 0xffff}, 2484 IM_CTL, 0x080, 3, 0x0, 0xffff},
2485 { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2485 { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2486 IM_CTL, 0x044, 3, 0x0, 0xffff}, 2486 IM_CTL, 0x044, 3, 0x0, 0xffff},
2487 { "IPV4 ESP encrypted?", /* S1_ESP4 */ 2487 { "IPV4 ESP encrypted?", /* S1_ESP4 */
2488 0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH4, IM_CTL, 2488 0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH4, IM_CTL,
2489 0x021, 1, 0x0, 0xffff}, 2489 0x021, 1, 0x0, 0xffff},
@@ -4044,7 +4044,7 @@ cas_saturn_patch_t cas_saturn_patch[] = {
4044 * deal with that, i just allocate rings to create the desired 4044 * deal with that, i just allocate rings to create the desired
4045 * alignment. here are the constraints: 4045 * alignment. here are the constraints:
4046 * RX DESC and COMP rings must be 8KB aligned 4046 * RX DESC and COMP rings must be 8KB aligned
4047 * TX DESC must be 2KB aligned. 4047 * TX DESC must be 2KB aligned.
4048 * if you change the numbers, be cognizant of how the alignment will change 4048 * if you change the numbers, be cognizant of how the alignment will change
4049 * in INIT_BLOCK as well. 4049 * in INIT_BLOCK as well.
4050 */ 4050 */
@@ -4095,20 +4095,20 @@ cas_saturn_patch_t cas_saturn_patch[] = {
4095/* min is 2k, but we can't do jumbo frames unless it's at least 8k */ 4095/* min is 2k, but we can't do jumbo frames unless it's at least 8k */
4096#define CAS_MIN_PAGE_SHIFT 11 /* 2048 */ 4096#define CAS_MIN_PAGE_SHIFT 11 /* 2048 */
4097#define CAS_JUMBO_PAGE_SHIFT 13 /* 8192 */ 4097#define CAS_JUMBO_PAGE_SHIFT 13 /* 8192 */
4098#define CAS_MAX_PAGE_SHIFT 14 /* 16384 */ 4098#define CAS_MAX_PAGE_SHIFT 14 /* 16384 */
4099 4099
4100#define TX_DESC_BUFLEN_MASK 0x0000000000003FFFULL /* buffer length in 4100#define TX_DESC_BUFLEN_MASK 0x0000000000003FFFULL /* buffer length in
4101 bytes. 0 - 9256 */ 4101 bytes. 0 - 9256 */
4102#define TX_DESC_BUFLEN_SHIFT 0 4102#define TX_DESC_BUFLEN_SHIFT 0
4103#define TX_DESC_CSUM_START_MASK 0x00000000001F8000ULL /* checksum start. # 4103#define TX_DESC_CSUM_START_MASK 0x00000000001F8000ULL /* checksum start. #
4104 of bytes to be 4104 of bytes to be
4105 skipped before 4105 skipped before
4106 csum calc begins. 4106 csum calc begins.
4107 value must be 4107 value must be
4108 even */ 4108 even */
4109#define TX_DESC_CSUM_START_SHIFT 15 4109#define TX_DESC_CSUM_START_SHIFT 15
4110#define TX_DESC_CSUM_STUFF_MASK 0x000000001FE00000ULL /* checksum stuff. 4110#define TX_DESC_CSUM_STUFF_MASK 0x000000001FE00000ULL /* checksum stuff.
4111 byte offset w/in 4111 byte offset w/in
4112 the pkt for the 4112 the pkt for the
4113 1st csum byte. 4113 1st csum byte.
4114 must be > 8 */ 4114 must be > 8 */
@@ -4137,7 +4137,7 @@ struct cas_rx_desc {
4137 4137
4138/* received packets are put on the completion ring. */ 4138/* received packets are put on the completion ring. */
4139/* word 1 */ 4139/* word 1 */
4140#define RX_COMP1_DATA_SIZE_MASK 0x0000000007FFE000ULL 4140#define RX_COMP1_DATA_SIZE_MASK 0x0000000007FFE000ULL
4141#define RX_COMP1_DATA_SIZE_SHIFT 13 4141#define RX_COMP1_DATA_SIZE_SHIFT 13
4142#define RX_COMP1_DATA_OFF_MASK 0x000001FFF8000000ULL 4142#define RX_COMP1_DATA_OFF_MASK 0x000001FFF8000000ULL
4143#define RX_COMP1_DATA_OFF_SHIFT 27 4143#define RX_COMP1_DATA_OFF_SHIFT 27
@@ -4147,8 +4147,8 @@ struct cas_rx_desc {
4147#define RX_COMP1_SKIP_SHIFT 55 4147#define RX_COMP1_SKIP_SHIFT 55
4148#define RX_COMP1_RELEASE_NEXT 0x0200000000000000ULL 4148#define RX_COMP1_RELEASE_NEXT 0x0200000000000000ULL
4149#define RX_COMP1_SPLIT_PKT 0x0400000000000000ULL 4149#define RX_COMP1_SPLIT_PKT 0x0400000000000000ULL
4150#define RX_COMP1_RELEASE_FLOW 0x0800000000000000ULL 4150#define RX_COMP1_RELEASE_FLOW 0x0800000000000000ULL
4151#define RX_COMP1_RELEASE_DATA 0x1000000000000000ULL 4151#define RX_COMP1_RELEASE_DATA 0x1000000000000000ULL
4152#define RX_COMP1_RELEASE_HDR 0x2000000000000000ULL 4152#define RX_COMP1_RELEASE_HDR 0x2000000000000000ULL
4153#define RX_COMP1_TYPE_MASK 0xC000000000000000ULL 4153#define RX_COMP1_TYPE_MASK 0xC000000000000000ULL
4154#define RX_COMP1_TYPE_SHIFT 62 4154#define RX_COMP1_TYPE_SHIFT 62
@@ -4201,7 +4201,7 @@ struct cas_rx_desc {
4201 4201
4202/* we encode the following: ring/index/release. only 14 bits 4202/* we encode the following: ring/index/release. only 14 bits
4203 * are usable. 4203 * are usable.
4204 * NOTE: the encoding is dependent upon RX_DESC_RING_SIZE and 4204 * NOTE: the encoding is dependent upon RX_DESC_RING_SIZE and
4205 * MAX_RX_DESC_RINGS. */ 4205 * MAX_RX_DESC_RINGS. */
4206#define RX_INDEX_NUM_MASK 0x0000000000000FFFULL 4206#define RX_INDEX_NUM_MASK 0x0000000000000FFFULL
4207#define RX_INDEX_NUM_SHIFT 0 4207#define RX_INDEX_NUM_SHIFT 0
@@ -4214,7 +4214,7 @@ struct cas_rx_comp {
4214 u64 word2; 4214 u64 word2;
4215 u64 word3; 4215 u64 word3;
4216 u64 word4; 4216 u64 word4;
4217}; 4217};
4218 4218
4219enum link_state { 4219enum link_state {
4220 link_down = 0, /* No link, will retry */ 4220 link_down = 0, /* No link, will retry */
@@ -4235,9 +4235,9 @@ typedef struct cas_page {
4235 4235
4236/* some alignment constraints: 4236/* some alignment constraints:
4237 * TX DESC, RX DESC, and RX COMP must each be 8K aligned. 4237 * TX DESC, RX DESC, and RX COMP must each be 8K aligned.
4238 * TX COMPWB must be 8-byte aligned. 4238 * TX COMPWB must be 8-byte aligned.
4239 * to accomplish this, here's what we do: 4239 * to accomplish this, here's what we do:
4240 * 4240 *
4241 * INIT_BLOCK_RX_COMP = 64k (already aligned) 4241 * INIT_BLOCK_RX_COMP = 64k (already aligned)
4242 * INIT_BLOCK_RX_DESC = 8k 4242 * INIT_BLOCK_RX_DESC = 8k
4243 * INIT_BLOCK_TX = 8k 4243 * INIT_BLOCK_TX = 8k
@@ -4250,9 +4250,9 @@ typedef struct cas_page {
4250 4250
4251struct cas_init_block { 4251struct cas_init_block {
4252 struct cas_rx_comp rxcs[N_RX_COMP_RINGS][INIT_BLOCK_RX_COMP]; 4252 struct cas_rx_comp rxcs[N_RX_COMP_RINGS][INIT_BLOCK_RX_COMP];
4253 struct cas_rx_desc rxds[N_RX_DESC_RINGS][INIT_BLOCK_RX_DESC]; 4253 struct cas_rx_desc rxds[N_RX_DESC_RINGS][INIT_BLOCK_RX_DESC];
4254 struct cas_tx_desc txds[N_TX_RINGS][INIT_BLOCK_TX]; 4254 struct cas_tx_desc txds[N_TX_RINGS][INIT_BLOCK_TX];
4255 u64 tx_compwb; 4255 u64 tx_compwb;
4256}; 4256};
4257 4257
4258/* tiny buffers to deal with target abort issue. we allocate a bit 4258/* tiny buffers to deal with target abort issue. we allocate a bit
@@ -4278,7 +4278,7 @@ struct cas {
4278 int tx_new[N_TX_RINGS], tx_old[N_TX_RINGS]; 4278 int tx_new[N_TX_RINGS], tx_old[N_TX_RINGS];
4279 int rx_old[N_RX_DESC_RINGS]; 4279 int rx_old[N_RX_DESC_RINGS];
4280 int rx_cur[N_RX_COMP_RINGS], rx_new[N_RX_COMP_RINGS]; 4280 int rx_cur[N_RX_COMP_RINGS], rx_new[N_RX_COMP_RINGS];
4281 int rx_last[N_RX_DESC_RINGS]; 4281 int rx_last[N_RX_DESC_RINGS];
4282 4282
4283 /* Set when chip is actually in operational state 4283 /* Set when chip is actually in operational state
4284 * (ie. not power managed) */ 4284 * (ie. not power managed) */
@@ -4337,7 +4337,7 @@ struct cas {
4337 int min_frame_size; /* for tx fifo workaround */ 4337 int min_frame_size; /* for tx fifo workaround */
4338 4338
4339 /* page size allocation */ 4339 /* page size allocation */
4340 int page_size; 4340 int page_size;
4341 int page_order; 4341 int page_order;
4342 int mtu_stride; 4342 int mtu_stride;
4343 4343
@@ -4362,7 +4362,7 @@ struct cas {
4362#ifdef CONFIG_CASSINI_QGE_DEBUG 4362#ifdef CONFIG_CASSINI_QGE_DEBUG
4363 atomic_t interrupt_seen; /* 1 if any interrupts are getting through */ 4363 atomic_t interrupt_seen; /* 1 if any interrupts are getting through */
4364#endif 4364#endif
4365 4365
4366 /* Link-down problem workaround */ 4366 /* Link-down problem workaround */
4367#define LINK_TRANSITION_UNKNOWN 0 4367#define LINK_TRANSITION_UNKNOWN 0
4368#define LINK_TRANSITION_ON_FAILURE 1 4368#define LINK_TRANSITION_ON_FAILURE 1
@@ -4383,7 +4383,7 @@ struct cas {
4383 int casreg_len; /* reg-space size for dumping */ 4383 int casreg_len; /* reg-space size for dumping */
4384 u64 pause_entered; 4384 u64 pause_entered;
4385 u16 pause_last_time_recvd; 4385 u16 pause_last_time_recvd;
4386 4386
4387 dma_addr_t block_dvma, tx_tiny_dvma[N_TX_RINGS]; 4387 dma_addr_t block_dvma, tx_tiny_dvma[N_TX_RINGS];
4388 struct pci_dev *pdev; 4388 struct pci_dev *pdev;
4389 struct net_device *dev; 4389 struct net_device *dev;
@@ -4394,7 +4394,7 @@ struct cas {
4394#define RX_COMP_ENTRY(r, x) ((x) & (RX_COMP_RINGN_SIZE(r) - 1)) 4394#define RX_COMP_ENTRY(r, x) ((x) & (RX_COMP_RINGN_SIZE(r) - 1))
4395 4395
4396#define TX_BUFF_COUNT(r, x, y) ((x) <= (y) ? ((y) - (x)) : \ 4396#define TX_BUFF_COUNT(r, x, y) ((x) <= (y) ? ((y) - (x)) : \
4397 (TX_DESC_RINGN_SIZE(r) - (x) + (y))) 4397 (TX_DESC_RINGN_SIZE(r) - (x) + (y)))
4398 4398
4399#define TX_BUFFS_AVAIL(cp, i) ((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \ 4399#define TX_BUFFS_AVAIL(cp, i) ((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \
4400 (cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \ 4400 (cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 00:27:03 -0500