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-rw-r--r--drivers/net/cassini.c5237
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diff --git a/drivers/net/cassini.c b/drivers/net/cassini.c
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1/* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
2 *
3 * Copyright (C) 2004 Sun Microsystems Inc.
4 * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
19 * 02111-1307, USA.
20 *
21 * This driver uses the sungem driver (c) David Miller
22 * (davem@redhat.com) as its basis.
23 *
24 * The cassini chip has a number of features that distinguish it from
25 * the gem chip:
26 * 4 transmit descriptor rings that are used for either QoS (VLAN) or
27 * load balancing (non-VLAN mode)
28 * batching of multiple packets
29 * multiple CPU dispatching
30 * page-based RX descriptor engine with separate completion rings
31 * Gigabit support (GMII and PCS interface)
32 * MIF link up/down detection works
33 *
34 * RX is handled by page sized buffers that are attached as fragments to
35 * the skb. here's what's done:
36 * -- driver allocates pages at a time and keeps reference counts
37 * on them.
38 * -- the upper protocol layers assume that the header is in the skb
39 * itself. as a result, cassini will copy a small amount (64 bytes)
40 * to make them happy.
41 * -- driver appends the rest of the data pages as frags to skbuffs
42 * and increments the reference count
43 * -- on page reclamation, the driver swaps the page with a spare page.
44 * if that page is still in use, it frees its reference to that page,
45 * and allocates a new page for use. otherwise, it just recycles the
46 * the page.
47 *
48 * NOTE: cassini can parse the header. however, it's not worth it
49 * as long as the network stack requires a header copy.
50 *
51 * TX has 4 queues. currently these queues are used in a round-robin
52 * fashion for load balancing. They can also be used for QoS. for that
53 * to work, however, QoS information needs to be exposed down to the driver
54 * level so that subqueues get targetted to particular transmit rings.
55 * alternatively, the queues can be configured via use of the all-purpose
56 * ioctl.
57 *
58 * RX DATA: the rx completion ring has all the info, but the rx desc
59 * ring has all of the data. RX can conceivably come in under multiple
60 * interrupts, but the INT# assignment needs to be set up properly by
61 * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
62 * that. also, the two descriptor rings are designed to distinguish between
63 * encrypted and non-encrypted packets, but we use them for buffering
64 * instead.
65 *
66 * by default, the selective clear mask is set up to process rx packets.
67 */
68
69#include <linux/config.h>
70#include <linux/version.h>
71
72#include <linux/module.h>
73#include <linux/kernel.h>
74#include <linux/types.h>
75#include <linux/compiler.h>
76#include <linux/slab.h>
77#include <linux/delay.h>
78#include <linux/init.h>
79#include <linux/ioport.h>
80#include <linux/pci.h>
81#include <linux/mm.h>
82#include <linux/highmem.h>
83#include <linux/list.h>
84#include <linux/dma-mapping.h>
85
86#include <linux/netdevice.h>
87#include <linux/etherdevice.h>
88#include <linux/skbuff.h>
89#include <linux/ethtool.h>
90#include <linux/crc32.h>
91#include <linux/random.h>
92#include <linux/mii.h>
93#include <linux/ip.h>
94#include <linux/tcp.h>
95
96#include <net/checksum.h>
97
98#include <asm/atomic.h>
99#include <asm/system.h>
100#include <asm/io.h>
101#include <asm/byteorder.h>
102#include <asm/uaccess.h>
103
104#define cas_page_map(x) kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
105#define cas_page_unmap(x) kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
106#define CAS_NCPUS num_online_cpus()
107
108#if defined(CONFIG_CASSINI_NAPI) && defined(HAVE_NETDEV_POLL)
109#define USE_NAPI
110#define cas_skb_release(x) netif_receive_skb(x)
111#else
112#define cas_skb_release(x) netif_rx(x)
113#endif
114
115/* select which firmware to use */
116#define USE_HP_WORKAROUND
117#define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
118#define CAS_HP_ALT_FIRMWARE cas_prog_null /* alternate firmware */
119
120#include "cassini.h"
121
122#define USE_TX_COMPWB /* use completion writeback registers */
123#define USE_CSMA_CD_PROTO /* standard CSMA/CD */
124#define USE_RX_BLANK /* hw interrupt mitigation */
125#undef USE_ENTROPY_DEV /* don't test for entropy device */
126
127/* NOTE: these aren't useable unless PCI interrupts can be assigned.
128 * also, we need to make cp->lock finer-grained.
129 */
130#undef USE_PCI_INTB
131#undef USE_PCI_INTC
132#undef USE_PCI_INTD
133#undef USE_QOS
134
135#undef USE_VPD_DEBUG /* debug vpd information if defined */
136
137/* rx processing options */
138#define USE_PAGE_ORDER /* specify to allocate large rx pages */
139#define RX_DONT_BATCH 0 /* if 1, don't batch flows */
140#define RX_COPY_ALWAYS 0 /* if 0, use frags */
141#define RX_COPY_MIN 64 /* copy a little to make upper layers happy */
142#undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */
143
144#define DRV_MODULE_NAME "cassini"
145#define PFX DRV_MODULE_NAME ": "
146#define DRV_MODULE_VERSION "1.4"
147#define DRV_MODULE_RELDATE "1 July 2004"
148
149#define CAS_DEF_MSG_ENABLE \
150 (NETIF_MSG_DRV | \
151 NETIF_MSG_PROBE | \
152 NETIF_MSG_LINK | \
153 NETIF_MSG_TIMER | \
154 NETIF_MSG_IFDOWN | \
155 NETIF_MSG_IFUP | \
156 NETIF_MSG_RX_ERR | \
157 NETIF_MSG_TX_ERR)
158
159/* length of time before we decide the hardware is borked,
160 * and dev->tx_timeout() should be called to fix the problem
161 */
162#define CAS_TX_TIMEOUT (HZ)
163#define CAS_LINK_TIMEOUT (22*HZ/10)
164#define CAS_LINK_FAST_TIMEOUT (1)
165
166/* timeout values for state changing. these specify the number
167 * of 10us delays to be used before giving up.
168 */
169#define STOP_TRIES_PHY 1000
170#define STOP_TRIES 5000
171
172/* specify a minimum frame size to deal with some fifo issues
173 * max mtu == 2 * page size - ethernet header - 64 - swivel =
174 * 2 * page_size - 0x50
175 */
176#define CAS_MIN_FRAME 97
177#define CAS_1000MB_MIN_FRAME 255
178#define CAS_MIN_MTU 60
179#define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000)
180
181#if 1
182/*
183 * Eliminate these and use separate atomic counters for each, to
184 * avoid a race condition.
185 */
186#else
187#define CAS_RESET_MTU 1
188#define CAS_RESET_ALL 2
189#define CAS_RESET_SPARE 3
190#endif
191
192static char version[] __devinitdata =
193 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
194
195MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
196MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
197MODULE_LICENSE("GPL");
198MODULE_PARM(cassini_debug, "i");
199MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
200MODULE_PARM(link_mode, "i");
201MODULE_PARM_DESC(link_mode, "default link mode");
202
203/*
204 * Work around for a PCS bug in which the link goes down due to the chip
205 * being confused and never showing a link status of "up."
206 */
207#define DEFAULT_LINKDOWN_TIMEOUT 5
208/*
209 * Value in seconds, for user input.
210 */
211static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
212MODULE_PARM(linkdown_timeout, "i");
213MODULE_PARM_DESC(linkdown_timeout,
214"min reset interval in sec. for PCS linkdown issue; disabled if not positive");
215
216/*
217 * value in 'ticks' (units used by jiffies). Set when we init the
218 * module because 'HZ' in actually a function call on some flavors of
219 * Linux. This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
220 */
221static int link_transition_timeout;
222
223
224static int cassini_debug = -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */
225static int link_mode;
226
227static u16 link_modes[] __devinitdata = {
228 BMCR_ANENABLE, /* 0 : autoneg */
229 0, /* 1 : 10bt half duplex */
230 BMCR_SPEED100, /* 2 : 100bt half duplex */
231 BMCR_FULLDPLX, /* 3 : 10bt full duplex */
232 BMCR_SPEED100|BMCR_FULLDPLX, /* 4 : 100bt full duplex */
233 CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
234};
235
236static struct pci_device_id cas_pci_tbl[] __devinitdata = {
237 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
239 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
241 { 0, }
242};
243
244MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
245
246static void cas_set_link_modes(struct cas *cp);
247
248static inline void cas_lock_tx(struct cas *cp)
249{
250 int i;
251
252 for (i = 0; i < N_TX_RINGS; i++)
253 spin_lock(&cp->tx_lock[i]);
254}
255
256static inline void cas_lock_all(struct cas *cp)
257{
258 spin_lock_irq(&cp->lock);
259 cas_lock_tx(cp);
260}
261
262/* WTZ: QA was finding deadlock problems with the previous
263 * versions after long test runs with multiple cards per machine.
264 * See if replacing cas_lock_all with safer versions helps. The
265 * symptoms QA is reporting match those we'd expect if interrupts
266 * aren't being properly restored, and we fixed a previous deadlock
267 * with similar symptoms by using save/restore versions in other
268 * places.
269 */
270#define cas_lock_all_save(cp, flags) \
271do { \
272 struct cas *xxxcp = (cp); \
273 spin_lock_irqsave(&xxxcp->lock, flags); \
274 cas_lock_tx(xxxcp); \
275} while (0)
276
277static inline void cas_unlock_tx(struct cas *cp)
278{
279 int i;
280
281 for (i = N_TX_RINGS; i > 0; i--)
282 spin_unlock(&cp->tx_lock[i - 1]);
283}
284
285static inline void cas_unlock_all(struct cas *cp)
286{
287 cas_unlock_tx(cp);
288 spin_unlock_irq(&cp->lock);
289}
290
291#define cas_unlock_all_restore(cp, flags) \
292do { \
293 struct cas *xxxcp = (cp); \
294 cas_unlock_tx(xxxcp); \
295 spin_unlock_irqrestore(&xxxcp->lock, flags); \
296} while (0)
297
298static void cas_disable_irq(struct cas *cp, const int ring)
299{
300 /* Make sure we won't get any more interrupts */
301 if (ring == 0) {
302 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
303 return;
304 }
305
306 /* disable completion interrupts and selectively mask */
307 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
308 switch (ring) {
309#if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
310#ifdef USE_PCI_INTB
311 case 1:
312#endif
313#ifdef USE_PCI_INTC
314 case 2:
315#endif
316#ifdef USE_PCI_INTD
317 case 3:
318#endif
319 writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
320 cp->regs + REG_PLUS_INTRN_MASK(ring));
321 break;
322#endif
323 default:
324 writel(INTRN_MASK_CLEAR_ALL, cp->regs +
325 REG_PLUS_INTRN_MASK(ring));
326 break;
327 }
328 }
329}
330
331static inline void cas_mask_intr(struct cas *cp)
332{
333 int i;
334
335 for (i = 0; i < N_RX_COMP_RINGS; i++)
336 cas_disable_irq(cp, i);
337}
338
339static void cas_enable_irq(struct cas *cp, const int ring)
340{
341 if (ring == 0) { /* all but TX_DONE */
342 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
343 return;
344 }
345
346 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
347 switch (ring) {
348#if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
349#ifdef USE_PCI_INTB
350 case 1:
351#endif
352#ifdef USE_PCI_INTC
353 case 2:
354#endif
355#ifdef USE_PCI_INTD
356 case 3:
357#endif
358 writel(INTRN_MASK_RX_EN, cp->regs +
359 REG_PLUS_INTRN_MASK(ring));
360 break;
361#endif
362 default:
363 break;
364 }
365 }
366}
367
368static inline void cas_unmask_intr(struct cas *cp)
369{
370 int i;
371
372 for (i = 0; i < N_RX_COMP_RINGS; i++)
373 cas_enable_irq(cp, i);
374}
375
376static inline void cas_entropy_gather(struct cas *cp)
377{
378#ifdef USE_ENTROPY_DEV
379 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
380 return;
381
382 batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
383 readl(cp->regs + REG_ENTROPY_IV),
384 sizeof(uint64_t)*8);
385#endif
386}
387
388static inline void cas_entropy_reset(struct cas *cp)
389{
390#ifdef USE_ENTROPY_DEV
391 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
392 return;
393
394 writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
395 cp->regs + REG_BIM_LOCAL_DEV_EN);
396 writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
397 writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
398
399 /* if we read back 0x0, we don't have an entropy device */
400 if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
401 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
402#endif
403}
404
405/* access to the phy. the following assumes that we've initialized the MIF to
406 * be in frame rather than bit-bang mode
407 */
408static u16 cas_phy_read(struct cas *cp, int reg)
409{
410 u32 cmd;
411 int limit = STOP_TRIES_PHY;
412
413 cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
414 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
415 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
416 cmd |= MIF_FRAME_TURN_AROUND_MSB;
417 writel(cmd, cp->regs + REG_MIF_FRAME);
418
419 /* poll for completion */
420 while (limit-- > 0) {
421 udelay(10);
422 cmd = readl(cp->regs + REG_MIF_FRAME);
423 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
424 return (cmd & MIF_FRAME_DATA_MASK);
425 }
426 return 0xFFFF; /* -1 */
427}
428
429static int cas_phy_write(struct cas *cp, int reg, u16 val)
430{
431 int limit = STOP_TRIES_PHY;
432 u32 cmd;
433
434 cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
435 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
436 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
437 cmd |= MIF_FRAME_TURN_AROUND_MSB;
438 cmd |= val & MIF_FRAME_DATA_MASK;
439 writel(cmd, cp->regs + REG_MIF_FRAME);
440
441 /* poll for completion */
442 while (limit-- > 0) {
443 udelay(10);
444 cmd = readl(cp->regs + REG_MIF_FRAME);
445 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
446 return 0;
447 }
448 return -1;
449}
450
451static void cas_phy_powerup(struct cas *cp)
452{
453 u16 ctl = cas_phy_read(cp, MII_BMCR);
454
455 if ((ctl & BMCR_PDOWN) == 0)
456 return;
457 ctl &= ~BMCR_PDOWN;
458 cas_phy_write(cp, MII_BMCR, ctl);
459}
460
461static void cas_phy_powerdown(struct cas *cp)
462{
463 u16 ctl = cas_phy_read(cp, MII_BMCR);
464
465 if (ctl & BMCR_PDOWN)
466 return;
467 ctl |= BMCR_PDOWN;
468 cas_phy_write(cp, MII_BMCR, ctl);
469}
470
471/* cp->lock held. note: the last put_page will free the buffer */
472static int cas_page_free(struct cas *cp, cas_page_t *page)
473{
474 pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
475 PCI_DMA_FROMDEVICE);
476 __free_pages(page->buffer, cp->page_order);
477 kfree(page);
478 return 0;
479}
480
481#ifdef RX_COUNT_BUFFERS
482#define RX_USED_ADD(x, y) ((x)->used += (y))
483#define RX_USED_SET(x, y) ((x)->used = (y))
484#else
485#define RX_USED_ADD(x, y)
486#define RX_USED_SET(x, y)
487#endif
488
489/* local page allocation routines for the receive buffers. jumbo pages
490 * require at least 8K contiguous and 8K aligned buffers.
491 */
492static cas_page_t *cas_page_alloc(struct cas *cp, const int flags)
493{
494 cas_page_t *page;
495
496 page = kmalloc(sizeof(cas_page_t), flags);
497 if (!page)
498 return NULL;
499
500 INIT_LIST_HEAD(&page->list);
501 RX_USED_SET(page, 0);
502 page->buffer = alloc_pages(flags, cp->page_order);
503 if (!page->buffer)
504 goto page_err;
505 page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
506 cp->page_size, PCI_DMA_FROMDEVICE);
507 return page;
508
509page_err:
510 kfree(page);
511 return NULL;
512}
513
514/* initialize spare pool of rx buffers, but allocate during the open */
515static void cas_spare_init(struct cas *cp)
516{
517 spin_lock(&cp->rx_inuse_lock);
518 INIT_LIST_HEAD(&cp->rx_inuse_list);
519 spin_unlock(&cp->rx_inuse_lock);
520
521 spin_lock(&cp->rx_spare_lock);
522 INIT_LIST_HEAD(&cp->rx_spare_list);
523 cp->rx_spares_needed = RX_SPARE_COUNT;
524 spin_unlock(&cp->rx_spare_lock);
525}
526
527/* used on close. free all the spare buffers. */
528static void cas_spare_free(struct cas *cp)
529{
530 struct list_head list, *elem, *tmp;
531
532 /* free spare buffers */
533 INIT_LIST_HEAD(&list);
534 spin_lock(&cp->rx_spare_lock);
535 list_splice(&cp->rx_spare_list, &list);
536 INIT_LIST_HEAD(&cp->rx_spare_list);
537 spin_unlock(&cp->rx_spare_lock);
538 list_for_each_safe(elem, tmp, &list) {
539 cas_page_free(cp, list_entry(elem, cas_page_t, list));
540 }
541
542 INIT_LIST_HEAD(&list);
543#if 1
544 /*
545 * Looks like Adrian had protected this with a different
546 * lock than used everywhere else to manipulate this list.
547 */
548 spin_lock(&cp->rx_inuse_lock);
549 list_splice(&cp->rx_inuse_list, &list);
550 INIT_LIST_HEAD(&cp->rx_inuse_list);
551 spin_unlock(&cp->rx_inuse_lock);
552#else
553 spin_lock(&cp->rx_spare_lock);
554 list_splice(&cp->rx_inuse_list, &list);
555 INIT_LIST_HEAD(&cp->rx_inuse_list);
556 spin_unlock(&cp->rx_spare_lock);
557#endif
558 list_for_each_safe(elem, tmp, &list) {
559 cas_page_free(cp, list_entry(elem, cas_page_t, list));
560 }
561}
562
563/* replenish spares if needed */
564static void cas_spare_recover(struct cas *cp, const int flags)
565{
566 struct list_head list, *elem, *tmp;
567 int needed, i;
568
569 /* check inuse list. if we don't need any more free buffers,
570 * just free it
571 */
572
573 /* make a local copy of the list */
574 INIT_LIST_HEAD(&list);
575 spin_lock(&cp->rx_inuse_lock);
576 list_splice(&cp->rx_inuse_list, &list);
577 INIT_LIST_HEAD(&cp->rx_inuse_list);
578 spin_unlock(&cp->rx_inuse_lock);
579
580 list_for_each_safe(elem, tmp, &list) {
581 cas_page_t *page = list_entry(elem, cas_page_t, list);
582
583 if (page_count(page->buffer) > 1)
584 continue;
585
586 list_del(elem);
587 spin_lock(&cp->rx_spare_lock);
588 if (cp->rx_spares_needed > 0) {
589 list_add(elem, &cp->rx_spare_list);
590 cp->rx_spares_needed--;
591 spin_unlock(&cp->rx_spare_lock);
592 } else {
593 spin_unlock(&cp->rx_spare_lock);
594 cas_page_free(cp, page);
595 }
596 }
597
598 /* put any inuse buffers back on the list */
599 if (!list_empty(&list)) {
600 spin_lock(&cp->rx_inuse_lock);
601 list_splice(&list, &cp->rx_inuse_list);
602 spin_unlock(&cp->rx_inuse_lock);
603 }
604
605 spin_lock(&cp->rx_spare_lock);
606 needed = cp->rx_spares_needed;
607 spin_unlock(&cp->rx_spare_lock);
608 if (!needed)
609 return;
610
611 /* we still need spares, so try to allocate some */
612 INIT_LIST_HEAD(&list);
613 i = 0;
614 while (i < needed) {
615 cas_page_t *spare = cas_page_alloc(cp, flags);
616 if (!spare)
617 break;
618 list_add(&spare->list, &list);
619 i++;
620 }
621
622 spin_lock(&cp->rx_spare_lock);
623 list_splice(&list, &cp->rx_spare_list);
624 cp->rx_spares_needed -= i;
625 spin_unlock(&cp->rx_spare_lock);
626}
627
628/* pull a page from the list. */
629static cas_page_t *cas_page_dequeue(struct cas *cp)
630{
631 struct list_head *entry;
632 int recover;
633
634 spin_lock(&cp->rx_spare_lock);
635 if (list_empty(&cp->rx_spare_list)) {
636 /* try to do a quick recovery */
637 spin_unlock(&cp->rx_spare_lock);
638 cas_spare_recover(cp, GFP_ATOMIC);
639 spin_lock(&cp->rx_spare_lock);
640 if (list_empty(&cp->rx_spare_list)) {
641 if (netif_msg_rx_err(cp))
642 printk(KERN_ERR "%s: no spare buffers "
643 "available.\n", cp->dev->name);
644 spin_unlock(&cp->rx_spare_lock);
645 return NULL;
646 }
647 }
648
649 entry = cp->rx_spare_list.next;
650 list_del(entry);
651 recover = ++cp->rx_spares_needed;
652 spin_unlock(&cp->rx_spare_lock);
653
654 /* trigger the timer to do the recovery */
655 if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
656#if 1
657 atomic_inc(&cp->reset_task_pending);
658 atomic_inc(&cp->reset_task_pending_spare);
659 schedule_work(&cp->reset_task);
660#else
661 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
662 schedule_work(&cp->reset_task);
663#endif
664 }
665 return list_entry(entry, cas_page_t, list);
666}
667
668
669static void cas_mif_poll(struct cas *cp, const int enable)
670{
671 u32 cfg;
672
673 cfg = readl(cp->regs + REG_MIF_CFG);
674 cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
675
676 if (cp->phy_type & CAS_PHY_MII_MDIO1)
677 cfg |= MIF_CFG_PHY_SELECT;
678
679 /* poll and interrupt on link status change. */
680 if (enable) {
681 cfg |= MIF_CFG_POLL_EN;
682 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
683 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
684 }
685 writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
686 cp->regs + REG_MIF_MASK);
687 writel(cfg, cp->regs + REG_MIF_CFG);
688}
689
690/* Must be invoked under cp->lock */
691static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
692{
693 u16 ctl;
694#if 1
695 int lcntl;
696 int changed = 0;
697 int oldstate = cp->lstate;
698 int link_was_not_down = !(oldstate == link_down);
699#endif
700 /* Setup link parameters */
701 if (!ep)
702 goto start_aneg;
703 lcntl = cp->link_cntl;
704 if (ep->autoneg == AUTONEG_ENABLE)
705 cp->link_cntl = BMCR_ANENABLE;
706 else {
707 cp->link_cntl = 0;
708 if (ep->speed == SPEED_100)
709 cp->link_cntl |= BMCR_SPEED100;
710 else if (ep->speed == SPEED_1000)
711 cp->link_cntl |= CAS_BMCR_SPEED1000;
712 if (ep->duplex == DUPLEX_FULL)
713 cp->link_cntl |= BMCR_FULLDPLX;
714 }
715#if 1
716 changed = (lcntl != cp->link_cntl);
717#endif
718start_aneg:
719 if (cp->lstate == link_up) {
720 printk(KERN_INFO "%s: PCS link down.\n",
721 cp->dev->name);
722 } else {
723 if (changed) {
724 printk(KERN_INFO "%s: link configuration changed\n",
725 cp->dev->name);
726 }
727 }
728 cp->lstate = link_down;
729 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
730 if (!cp->hw_running)
731 return;
732#if 1
733 /*
734 * WTZ: If the old state was link_up, we turn off the carrier
735 * to replicate everything we do elsewhere on a link-down
736 * event when we were already in a link-up state..
737 */
738 if (oldstate == link_up)
739 netif_carrier_off(cp->dev);
740 if (changed && link_was_not_down) {
741 /*
742 * WTZ: This branch will simply schedule a full reset after
743 * we explicitly changed link modes in an ioctl. See if this
744 * fixes the link-problems we were having for forced mode.
745 */
746 atomic_inc(&cp->reset_task_pending);
747 atomic_inc(&cp->reset_task_pending_all);
748 schedule_work(&cp->reset_task);
749 cp->timer_ticks = 0;
750 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
751 return;
752 }
753#endif
754 if (cp->phy_type & CAS_PHY_SERDES) {
755 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
756
757 if (cp->link_cntl & BMCR_ANENABLE) {
758 val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
759 cp->lstate = link_aneg;
760 } else {
761 if (cp->link_cntl & BMCR_FULLDPLX)
762 val |= PCS_MII_CTRL_DUPLEX;
763 val &= ~PCS_MII_AUTONEG_EN;
764 cp->lstate = link_force_ok;
765 }
766 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
767 writel(val, cp->regs + REG_PCS_MII_CTRL);
768
769 } else {
770 cas_mif_poll(cp, 0);
771 ctl = cas_phy_read(cp, MII_BMCR);
772 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
773 CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
774 ctl |= cp->link_cntl;
775 if (ctl & BMCR_ANENABLE) {
776 ctl |= BMCR_ANRESTART;
777 cp->lstate = link_aneg;
778 } else {
779 cp->lstate = link_force_ok;
780 }
781 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
782 cas_phy_write(cp, MII_BMCR, ctl);
783 cas_mif_poll(cp, 1);
784 }
785
786 cp->timer_ticks = 0;
787 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
788}
789
790/* Must be invoked under cp->lock. */
791static int cas_reset_mii_phy(struct cas *cp)
792{
793 int limit = STOP_TRIES_PHY;
794 u16 val;
795
796 cas_phy_write(cp, MII_BMCR, BMCR_RESET);
797 udelay(100);
798 while (limit--) {
799 val = cas_phy_read(cp, MII_BMCR);
800 if ((val & BMCR_RESET) == 0)
801 break;
802 udelay(10);
803 }
804 return (limit <= 0);
805}
806
807static void cas_saturn_firmware_load(struct cas *cp)
808{
809 cas_saturn_patch_t *patch = cas_saturn_patch;
810
811 cas_phy_powerdown(cp);
812
813 /* expanded memory access mode */
814 cas_phy_write(cp, DP83065_MII_MEM, 0x0);
815
816 /* pointer configuration for new firmware */
817 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
818 cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
819 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
820 cas_phy_write(cp, DP83065_MII_REGD, 0x82);
821 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
822 cas_phy_write(cp, DP83065_MII_REGD, 0x0);
823 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
824 cas_phy_write(cp, DP83065_MII_REGD, 0x39);
825
826 /* download new firmware */
827 cas_phy_write(cp, DP83065_MII_MEM, 0x1);
828 cas_phy_write(cp, DP83065_MII_REGE, patch->addr);
829 while (patch->addr) {
830 cas_phy_write(cp, DP83065_MII_REGD, patch->val);
831 patch++;
832 }
833
834 /* enable firmware */
835 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
836 cas_phy_write(cp, DP83065_MII_REGD, 0x1);
837}
838
839
840/* phy initialization */
841static void cas_phy_init(struct cas *cp)
842{
843 u16 val;
844
845 /* if we're in MII/GMII mode, set up phy */
846 if (CAS_PHY_MII(cp->phy_type)) {
847 writel(PCS_DATAPATH_MODE_MII,
848 cp->regs + REG_PCS_DATAPATH_MODE);
849
850 cas_mif_poll(cp, 0);
851 cas_reset_mii_phy(cp); /* take out of isolate mode */
852
853 if (PHY_LUCENT_B0 == cp->phy_id) {
854 /* workaround link up/down issue with lucent */
855 cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
856 cas_phy_write(cp, MII_BMCR, 0x00f1);
857 cas_phy_write(cp, LUCENT_MII_REG, 0x0);
858
859 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
860 /* workarounds for broadcom phy */
861 cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
862 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
863 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
864 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
865 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
866 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
867 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
868 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
869 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
870 cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
871 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
872
873 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
874 val = cas_phy_read(cp, BROADCOM_MII_REG4);
875 val = cas_phy_read(cp, BROADCOM_MII_REG4);
876 if (val & 0x0080) {
877 /* link workaround */
878 cas_phy_write(cp, BROADCOM_MII_REG4,
879 val & ~0x0080);
880 }
881
882 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
883 writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
884 SATURN_PCFG_FSI : 0x0,
885 cp->regs + REG_SATURN_PCFG);
886
887 /* load firmware to address 10Mbps auto-negotiation
888 * issue. NOTE: this will need to be changed if the
889 * default firmware gets fixed.
890 */
891 if (PHY_NS_DP83065 == cp->phy_id) {
892 cas_saturn_firmware_load(cp);
893 }
894 cas_phy_powerup(cp);
895 }
896
897 /* advertise capabilities */
898 val = cas_phy_read(cp, MII_BMCR);
899 val &= ~BMCR_ANENABLE;
900 cas_phy_write(cp, MII_BMCR, val);
901 udelay(10);
902
903 cas_phy_write(cp, MII_ADVERTISE,
904 cas_phy_read(cp, MII_ADVERTISE) |
905 (ADVERTISE_10HALF | ADVERTISE_10FULL |
906 ADVERTISE_100HALF | ADVERTISE_100FULL |
907 CAS_ADVERTISE_PAUSE |
908 CAS_ADVERTISE_ASYM_PAUSE));
909
910 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
911 /* make sure that we don't advertise half
912 * duplex to avoid a chip issue
913 */
914 val = cas_phy_read(cp, CAS_MII_1000_CTRL);
915 val &= ~CAS_ADVERTISE_1000HALF;
916 val |= CAS_ADVERTISE_1000FULL;
917 cas_phy_write(cp, CAS_MII_1000_CTRL, val);
918 }
919
920 } else {
921 /* reset pcs for serdes */
922 u32 val;
923 int limit;
924
925 writel(PCS_DATAPATH_MODE_SERDES,
926 cp->regs + REG_PCS_DATAPATH_MODE);
927
928 /* enable serdes pins on saturn */
929 if (cp->cas_flags & CAS_FLAG_SATURN)
930 writel(0, cp->regs + REG_SATURN_PCFG);
931
932 /* Reset PCS unit. */
933 val = readl(cp->regs + REG_PCS_MII_CTRL);
934 val |= PCS_MII_RESET;
935 writel(val, cp->regs + REG_PCS_MII_CTRL);
936
937 limit = STOP_TRIES;
938 while (limit-- > 0) {
939 udelay(10);
940 if ((readl(cp->regs + REG_PCS_MII_CTRL) &
941 PCS_MII_RESET) == 0)
942 break;
943 }
944 if (limit <= 0)
945 printk(KERN_WARNING "%s: PCS reset bit would not "
946 "clear [%08x].\n", cp->dev->name,
947 readl(cp->regs + REG_PCS_STATE_MACHINE));
948
949 /* Make sure PCS is disabled while changing advertisement
950 * configuration.
951 */
952 writel(0x0, cp->regs + REG_PCS_CFG);
953
954 /* Advertise all capabilities except half-duplex. */
955 val = readl(cp->regs + REG_PCS_MII_ADVERT);
956 val &= ~PCS_MII_ADVERT_HD;
957 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
958 PCS_MII_ADVERT_ASYM_PAUSE);
959 writel(val, cp->regs + REG_PCS_MII_ADVERT);
960
961 /* enable PCS */
962 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
963
964 /* pcs workaround: enable sync detect */
965 writel(PCS_SERDES_CTRL_SYNCD_EN,
966 cp->regs + REG_PCS_SERDES_CTRL);
967 }
968}
969
970
971static int cas_pcs_link_check(struct cas *cp)
972{
973 u32 stat, state_machine;
974 int retval = 0;
975
976 /* The link status bit latches on zero, so you must
977 * read it twice in such a case to see a transition
978 * to the link being up.
979 */
980 stat = readl(cp->regs + REG_PCS_MII_STATUS);
981 if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
982 stat = readl(cp->regs + REG_PCS_MII_STATUS);
983
984 /* The remote-fault indication is only valid
985 * when autoneg has completed.
986 */
987 if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
988 PCS_MII_STATUS_REMOTE_FAULT)) ==
989 (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT)) {
990 if (netif_msg_link(cp))
991 printk(KERN_INFO "%s: PCS RemoteFault\n",
992 cp->dev->name);
993 }
994
995 /* work around link detection issue by querying the PCS state
996 * machine directly.
997 */
998 state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
999 if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
1000 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1001 } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1002 stat |= PCS_MII_STATUS_LINK_STATUS;
1003 }
1004
1005 if (stat & PCS_MII_STATUS_LINK_STATUS) {
1006 if (cp->lstate != link_up) {
1007 if (cp->opened) {
1008 cp->lstate = link_up;
1009 cp->link_transition = LINK_TRANSITION_LINK_UP;
1010
1011 cas_set_link_modes(cp);
1012 netif_carrier_on(cp->dev);
1013 }
1014 }
1015 } else if (cp->lstate == link_up) {
1016 cp->lstate = link_down;
1017 if (link_transition_timeout != 0 &&
1018 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1019 !cp->link_transition_jiffies_valid) {
1020 /*
1021 * force a reset, as a workaround for the
1022 * link-failure problem. May want to move this to a
1023 * point a bit earlier in the sequence. If we had
1024 * generated a reset a short time ago, we'll wait for
1025 * the link timer to check the status until a
1026 * timer expires (link_transistion_jiffies_valid is
1027 * true when the timer is running.) Instead of using
1028 * a system timer, we just do a check whenever the
1029 * link timer is running - this clears the flag after
1030 * a suitable delay.
1031 */
1032 retval = 1;
1033 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1034 cp->link_transition_jiffies = jiffies;
1035 cp->link_transition_jiffies_valid = 1;
1036 } else {
1037 cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1038 }
1039 netif_carrier_off(cp->dev);
1040 if (cp->opened && netif_msg_link(cp)) {
1041 printk(KERN_INFO "%s: PCS link down.\n",
1042 cp->dev->name);
1043 }
1044
1045 /* Cassini only: if you force a mode, there can be
1046 * sync problems on link down. to fix that, the following
1047 * things need to be checked:
1048 * 1) read serialink state register
1049 * 2) read pcs status register to verify link down.
1050 * 3) if link down and serial link == 0x03, then you need
1051 * to global reset the chip.
1052 */
1053 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1054 /* should check to see if we're in a forced mode */
1055 stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1056 if (stat == 0x03)
1057 return 1;
1058 }
1059 } else if (cp->lstate == link_down) {
1060 if (link_transition_timeout != 0 &&
1061 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1062 !cp->link_transition_jiffies_valid) {
1063 /* force a reset, as a workaround for the
1064 * link-failure problem. May want to move
1065 * this to a point a bit earlier in the
1066 * sequence.
1067 */
1068 retval = 1;
1069 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1070 cp->link_transition_jiffies = jiffies;
1071 cp->link_transition_jiffies_valid = 1;
1072 } else {
1073 cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1074 }
1075 }
1076
1077 return retval;
1078}
1079
1080static int cas_pcs_interrupt(struct net_device *dev,
1081 struct cas *cp, u32 status)
1082{
1083 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1084
1085 if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1086 return 0;
1087 return cas_pcs_link_check(cp);
1088}
1089
1090static int cas_txmac_interrupt(struct net_device *dev,
1091 struct cas *cp, u32 status)
1092{
1093 u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1094
1095 if (!txmac_stat)
1096 return 0;
1097
1098 if (netif_msg_intr(cp))
1099 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
1100 cp->dev->name, txmac_stat);
1101
1102 /* Defer timer expiration is quite normal,
1103 * don't even log the event.
1104 */
1105 if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1106 !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1107 return 0;
1108
1109 spin_lock(&cp->stat_lock[0]);
1110 if (txmac_stat & MAC_TX_UNDERRUN) {
1111 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
1112 dev->name);
1113 cp->net_stats[0].tx_fifo_errors++;
1114 }
1115
1116 if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1117 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
1118 dev->name);
1119 cp->net_stats[0].tx_errors++;
1120 }
1121
1122 /* The rest are all cases of one of the 16-bit TX
1123 * counters expiring.
1124 */
1125 if (txmac_stat & MAC_TX_COLL_NORMAL)
1126 cp->net_stats[0].collisions += 0x10000;
1127
1128 if (txmac_stat & MAC_TX_COLL_EXCESS) {
1129 cp->net_stats[0].tx_aborted_errors += 0x10000;
1130 cp->net_stats[0].collisions += 0x10000;
1131 }
1132
1133 if (txmac_stat & MAC_TX_COLL_LATE) {
1134 cp->net_stats[0].tx_aborted_errors += 0x10000;
1135 cp->net_stats[0].collisions += 0x10000;
1136 }
1137 spin_unlock(&cp->stat_lock[0]);
1138
1139 /* We do not keep track of MAC_TX_COLL_FIRST and
1140 * MAC_TX_PEAK_ATTEMPTS events.
1141 */
1142 return 0;
1143}
1144
1145static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1146{
1147 cas_hp_inst_t *inst;
1148 u32 val;
1149 int i;
1150
1151 i = 0;
1152 while ((inst = firmware) && inst->note) {
1153 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1154
1155 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1156 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1157 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1158
1159 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1160 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1161 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1162 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1163 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1164 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1165 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1166 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1167
1168 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1169 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1170 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1171 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1172 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1173 ++firmware;
1174 ++i;
1175 }
1176}
1177
1178static void cas_init_rx_dma(struct cas *cp)
1179{
1180 u64 desc_dma = cp->block_dvma;
1181 u32 val;
1182 int i, size;
1183
1184 /* rx free descriptors */
1185 val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1186 val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1187 val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1188 if ((N_RX_DESC_RINGS > 1) &&
1189 (cp->cas_flags & CAS_FLAG_REG_PLUS)) /* do desc 2 */
1190 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1191 writel(val, cp->regs + REG_RX_CFG);
1192
1193 val = (unsigned long) cp->init_rxds[0] -
1194 (unsigned long) cp->init_block;
1195 writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1196 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1197 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1198
1199 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1200 /* rx desc 2 is for IPSEC packets. however,
1201 * we don't it that for that purpose.
1202 */
1203 val = (unsigned long) cp->init_rxds[1] -
1204 (unsigned long) cp->init_block;
1205 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1206 writel((desc_dma + val) & 0xffffffff, cp->regs +
1207 REG_PLUS_RX_DB1_LOW);
1208 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1209 REG_PLUS_RX_KICK1);
1210 }
1211
1212 /* rx completion registers */
1213 val = (unsigned long) cp->init_rxcs[0] -
1214 (unsigned long) cp->init_block;
1215 writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1216 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1217
1218 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1219 /* rx comp 2-4 */
1220 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1221 val = (unsigned long) cp->init_rxcs[i] -
1222 (unsigned long) cp->init_block;
1223 writel((desc_dma + val) >> 32, cp->regs +
1224 REG_PLUS_RX_CBN_HI(i));
1225 writel((desc_dma + val) & 0xffffffff, cp->regs +
1226 REG_PLUS_RX_CBN_LOW(i));
1227 }
1228 }
1229
1230 /* read selective clear regs to prevent spurious interrupts
1231 * on reset because complete == kick.
1232 * selective clear set up to prevent interrupts on resets
1233 */
1234 readl(cp->regs + REG_INTR_STATUS_ALIAS);
1235 writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1236 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1237 for (i = 1; i < N_RX_COMP_RINGS; i++)
1238 readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1239
1240 /* 2 is different from 3 and 4 */
1241 if (N_RX_COMP_RINGS > 1)
1242 writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
1243 cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1244
1245 for (i = 2; i < N_RX_COMP_RINGS; i++)
1246 writel(INTR_RX_DONE_ALT,
1247 cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1248 }
1249
1250 /* set up pause thresholds */
1251 val = CAS_BASE(RX_PAUSE_THRESH_OFF,
1252 cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1253 val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1254 cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1255 writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1256
1257 /* zero out dma reassembly buffers */
1258 for (i = 0; i < 64; i++) {
1259 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1260 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1261 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1262 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1263 }
1264
1265 /* make sure address register is 0 for normal operation */
1266 writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1267 writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1268
1269 /* interrupt mitigation */
1270#ifdef USE_RX_BLANK
1271 val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1272 val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1273 writel(val, cp->regs + REG_RX_BLANK);
1274#else
1275 writel(0x0, cp->regs + REG_RX_BLANK);
1276#endif
1277
1278 /* interrupt generation as a function of low water marks for
1279 * free desc and completion entries. these are used to trigger
1280 * housekeeping for rx descs. we don't use the free interrupt
1281 * as it's not very useful
1282 */
1283 /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1284 val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1285 writel(val, cp->regs + REG_RX_AE_THRESH);
1286 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1287 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1288 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1289 }
1290
1291 /* Random early detect registers. useful for congestion avoidance.
1292 * this should be tunable.
1293 */
1294 writel(0x0, cp->regs + REG_RX_RED);
1295
1296 /* receive page sizes. default == 2K (0x800) */
1297 val = 0;
1298 if (cp->page_size == 0x1000)
1299 val = 0x1;
1300 else if (cp->page_size == 0x2000)
1301 val = 0x2;
1302 else if (cp->page_size == 0x4000)
1303 val = 0x3;
1304
1305 /* round mtu + offset. constrain to page size. */
1306 size = cp->dev->mtu + 64;
1307 if (size > cp->page_size)
1308 size = cp->page_size;
1309
1310 if (size <= 0x400)
1311 i = 0x0;
1312 else if (size <= 0x800)
1313 i = 0x1;
1314 else if (size <= 0x1000)
1315 i = 0x2;
1316 else
1317 i = 0x3;
1318
1319 cp->mtu_stride = 1 << (i + 10);
1320 val = CAS_BASE(RX_PAGE_SIZE, val);
1321 val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1322 val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1323 val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1324 writel(val, cp->regs + REG_RX_PAGE_SIZE);
1325
1326 /* enable the header parser if desired */
1327 if (CAS_HP_FIRMWARE == cas_prog_null)
1328 return;
1329
1330 val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1331 val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1332 val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1333 writel(val, cp->regs + REG_HP_CFG);
1334}
1335
1336static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1337{
1338 memset(rxc, 0, sizeof(*rxc));
1339 rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1340}
1341
1342/* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1343 * flipping is protected by the fact that the chip will not
1344 * hand back the same page index while it's being processed.
1345 */
1346static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1347{
1348 cas_page_t *page = cp->rx_pages[1][index];
1349 cas_page_t *new;
1350
1351 if (page_count(page->buffer) == 1)
1352 return page;
1353
1354 new = cas_page_dequeue(cp);
1355 if (new) {
1356 spin_lock(&cp->rx_inuse_lock);
1357 list_add(&page->list, &cp->rx_inuse_list);
1358 spin_unlock(&cp->rx_inuse_lock);
1359 }
1360 return new;
1361}
1362
1363/* this needs to be changed if we actually use the ENC RX DESC ring */
1364static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1365 const int index)
1366{
1367 cas_page_t **page0 = cp->rx_pages[0];
1368 cas_page_t **page1 = cp->rx_pages[1];
1369
1370 /* swap if buffer is in use */
1371 if (page_count(page0[index]->buffer) > 1) {
1372 cas_page_t *new = cas_page_spare(cp, index);
1373 if (new) {
1374 page1[index] = page0[index];
1375 page0[index] = new;
1376 }
1377 }
1378 RX_USED_SET(page0[index], 0);
1379 return page0[index];
1380}
1381
1382static void cas_clean_rxds(struct cas *cp)
1383{
1384 /* only clean ring 0 as ring 1 is used for spare buffers */
1385 struct cas_rx_desc *rxd = cp->init_rxds[0];
1386 int i, size;
1387
1388 /* release all rx flows */
1389 for (i = 0; i < N_RX_FLOWS; i++) {
1390 struct sk_buff *skb;
1391 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1392 cas_skb_release(skb);
1393 }
1394 }
1395
1396 /* initialize descriptors */
1397 size = RX_DESC_RINGN_SIZE(0);
1398 for (i = 0; i < size; i++) {
1399 cas_page_t *page = cas_page_swap(cp, 0, i);
1400 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1401 rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1402 CAS_BASE(RX_INDEX_RING, 0));
1403 }
1404
1405 cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4;
1406 cp->rx_last[0] = 0;
1407 cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1408}
1409
1410static void cas_clean_rxcs(struct cas *cp)
1411{
1412 int i, j;
1413
1414 /* take ownership of rx comp descriptors */
1415 memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1416 memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1417 for (i = 0; i < N_RX_COMP_RINGS; i++) {
1418 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1419 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1420 cas_rxc_init(rxc + j);
1421 }
1422 }
1423}
1424
1425#if 0
1426/* When we get a RX fifo overflow, the RX unit is probably hung
1427 * so we do the following.
1428 *
1429 * If any part of the reset goes wrong, we return 1 and that causes the
1430 * whole chip to be reset.
1431 */
1432static int cas_rxmac_reset(struct cas *cp)
1433{
1434 struct net_device *dev = cp->dev;
1435 int limit;
1436 u32 val;
1437
1438 /* First, reset MAC RX. */
1439 writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1440 for (limit = 0; limit < STOP_TRIES; limit++) {
1441 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1442 break;
1443 udelay(10);
1444 }
1445 if (limit == STOP_TRIES) {
1446 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
1447 "chip.\n", dev->name);
1448 return 1;
1449 }
1450
1451 /* Second, disable RX DMA. */
1452 writel(0, cp->regs + REG_RX_CFG);
1453 for (limit = 0; limit < STOP_TRIES; limit++) {
1454 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1455 break;
1456 udelay(10);
1457 }
1458 if (limit == STOP_TRIES) {
1459 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
1460 "chip.\n", dev->name);
1461 return 1;
1462 }
1463
1464 mdelay(5);
1465
1466 /* Execute RX reset command. */
1467 writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1468 for (limit = 0; limit < STOP_TRIES; limit++) {
1469 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1470 break;
1471 udelay(10);
1472 }
1473 if (limit == STOP_TRIES) {
1474 printk(KERN_ERR "%s: RX reset command will not execute, "
1475 "resetting whole chip.\n", dev->name);
1476 return 1;
1477 }
1478
1479 /* reset driver rx state */
1480 cas_clean_rxds(cp);
1481 cas_clean_rxcs(cp);
1482
1483 /* Now, reprogram the rest of RX unit. */
1484 cas_init_rx_dma(cp);
1485
1486 /* re-enable */
1487 val = readl(cp->regs + REG_RX_CFG);
1488 writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1489 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1490 val = readl(cp->regs + REG_MAC_RX_CFG);
1491 writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1492 return 0;
1493}
1494#endif
1495
1496static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1497 u32 status)
1498{
1499 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1500
1501 if (!stat)
1502 return 0;
1503
1504 if (netif_msg_intr(cp))
1505 printk(KERN_DEBUG "%s: rxmac interrupt, stat: 0x%x\n",
1506 cp->dev->name, stat);
1507
1508 /* these are all rollovers */
1509 spin_lock(&cp->stat_lock[0]);
1510 if (stat & MAC_RX_ALIGN_ERR)
1511 cp->net_stats[0].rx_frame_errors += 0x10000;
1512
1513 if (stat & MAC_RX_CRC_ERR)
1514 cp->net_stats[0].rx_crc_errors += 0x10000;
1515
1516 if (stat & MAC_RX_LEN_ERR)
1517 cp->net_stats[0].rx_length_errors += 0x10000;
1518
1519 if (stat & MAC_RX_OVERFLOW) {
1520 cp->net_stats[0].rx_over_errors++;
1521 cp->net_stats[0].rx_fifo_errors++;
1522 }
1523
1524 /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1525 * events.
1526 */
1527 spin_unlock(&cp->stat_lock[0]);
1528 return 0;
1529}
1530
1531static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1532 u32 status)
1533{
1534 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1535
1536 if (!stat)
1537 return 0;
1538
1539 if (netif_msg_intr(cp))
1540 printk(KERN_DEBUG "%s: mac interrupt, stat: 0x%x\n",
1541 cp->dev->name, stat);
1542
1543 /* This interrupt is just for pause frame and pause
1544 * tracking. It is useful for diagnostics and debug
1545 * but probably by default we will mask these events.
1546 */
1547 if (stat & MAC_CTRL_PAUSE_STATE)
1548 cp->pause_entered++;
1549
1550 if (stat & MAC_CTRL_PAUSE_RECEIVED)
1551 cp->pause_last_time_recvd = (stat >> 16);
1552
1553 return 0;
1554}
1555
1556
1557/* Must be invoked under cp->lock. */
1558static inline int cas_mdio_link_not_up(struct cas *cp)
1559{
1560 u16 val;
1561
1562 switch (cp->lstate) {
1563 case link_force_ret:
1564 if (netif_msg_link(cp))
1565 printk(KERN_INFO "%s: Autoneg failed again, keeping"
1566 " forced mode\n", cp->dev->name);
1567 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1568 cp->timer_ticks = 5;
1569 cp->lstate = link_force_ok;
1570 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1571 break;
1572
1573 case link_aneg:
1574 val = cas_phy_read(cp, MII_BMCR);
1575
1576 /* Try forced modes. we try things in the following order:
1577 * 1000 full -> 100 full/half -> 10 half
1578 */
1579 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1580 val |= BMCR_FULLDPLX;
1581 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1582 CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1583 cas_phy_write(cp, MII_BMCR, val);
1584 cp->timer_ticks = 5;
1585 cp->lstate = link_force_try;
1586 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1587 break;
1588
1589 case link_force_try:
1590 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1591 val = cas_phy_read(cp, MII_BMCR);
1592 cp->timer_ticks = 5;
1593 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1594 val &= ~CAS_BMCR_SPEED1000;
1595 val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1596 cas_phy_write(cp, MII_BMCR, val);
1597 break;
1598 }
1599
1600 if (val & BMCR_SPEED100) {
1601 if (val & BMCR_FULLDPLX) /* fd failed */
1602 val &= ~BMCR_FULLDPLX;
1603 else { /* 100Mbps failed */
1604 val &= ~BMCR_SPEED100;
1605 }
1606 cas_phy_write(cp, MII_BMCR, val);
1607 break;
1608 }
1609 default:
1610 break;
1611 }
1612 return 0;
1613}
1614
1615
1616/* must be invoked with cp->lock held */
1617static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1618{
1619 int restart;
1620
1621 if (bmsr & BMSR_LSTATUS) {
1622 /* Ok, here we got a link. If we had it due to a forced
1623 * fallback, and we were configured for autoneg, we
1624 * retry a short autoneg pass. If you know your hub is
1625 * broken, use ethtool ;)
1626 */
1627 if ((cp->lstate == link_force_try) &&
1628 (cp->link_cntl & BMCR_ANENABLE)) {
1629 cp->lstate = link_force_ret;
1630 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1631 cas_mif_poll(cp, 0);
1632 cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1633 cp->timer_ticks = 5;
1634 if (cp->opened && netif_msg_link(cp))
1635 printk(KERN_INFO "%s: Got link after fallback, retrying"
1636 " autoneg once...\n", cp->dev->name);
1637 cas_phy_write(cp, MII_BMCR,
1638 cp->link_fcntl | BMCR_ANENABLE |
1639 BMCR_ANRESTART);
1640 cas_mif_poll(cp, 1);
1641
1642 } else if (cp->lstate != link_up) {
1643 cp->lstate = link_up;
1644 cp->link_transition = LINK_TRANSITION_LINK_UP;
1645
1646 if (cp->opened) {
1647 cas_set_link_modes(cp);
1648 netif_carrier_on(cp->dev);
1649 }
1650 }
1651 return 0;
1652 }
1653
1654 /* link not up. if the link was previously up, we restart the
1655 * whole process
1656 */
1657 restart = 0;
1658 if (cp->lstate == link_up) {
1659 cp->lstate = link_down;
1660 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1661
1662 netif_carrier_off(cp->dev);
1663 if (cp->opened && netif_msg_link(cp))
1664 printk(KERN_INFO "%s: Link down\n",
1665 cp->dev->name);
1666 restart = 1;
1667
1668 } else if (++cp->timer_ticks > 10)
1669 cas_mdio_link_not_up(cp);
1670
1671 return restart;
1672}
1673
1674static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1675 u32 status)
1676{
1677 u32 stat = readl(cp->regs + REG_MIF_STATUS);
1678 u16 bmsr;
1679
1680 /* check for a link change */
1681 if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1682 return 0;
1683
1684 bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1685 return cas_mii_link_check(cp, bmsr);
1686}
1687
1688static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1689 u32 status)
1690{
1691 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1692
1693 if (!stat)
1694 return 0;
1695
1696 printk(KERN_ERR "%s: PCI error [%04x:%04x] ", dev->name, stat,
1697 readl(cp->regs + REG_BIM_DIAG));
1698
1699 /* cassini+ has this reserved */
1700 if ((stat & PCI_ERR_BADACK) &&
1701 ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1702 printk("<No ACK64# during ABS64 cycle> ");
1703
1704 if (stat & PCI_ERR_DTRTO)
1705 printk("<Delayed transaction timeout> ");
1706 if (stat & PCI_ERR_OTHER)
1707 printk("<other> ");
1708 if (stat & PCI_ERR_BIM_DMA_WRITE)
1709 printk("<BIM DMA 0 write req> ");
1710 if (stat & PCI_ERR_BIM_DMA_READ)
1711 printk("<BIM DMA 0 read req> ");
1712 printk("\n");
1713
1714 if (stat & PCI_ERR_OTHER) {
1715 u16 cfg;
1716
1717 /* Interrogate PCI config space for the
1718 * true cause.
1719 */
1720 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
1721 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
1722 dev->name, cfg);
1723 if (cfg & PCI_STATUS_PARITY)
1724 printk(KERN_ERR "%s: PCI parity error detected.\n",
1725 dev->name);
1726 if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
1727 printk(KERN_ERR "%s: PCI target abort.\n",
1728 dev->name);
1729 if (cfg & PCI_STATUS_REC_TARGET_ABORT)
1730 printk(KERN_ERR "%s: PCI master acks target abort.\n",
1731 dev->name);
1732 if (cfg & PCI_STATUS_REC_MASTER_ABORT)
1733 printk(KERN_ERR "%s: PCI master abort.\n", dev->name);
1734 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
1735 printk(KERN_ERR "%s: PCI system error SERR#.\n",
1736 dev->name);
1737 if (cfg & PCI_STATUS_DETECTED_PARITY)
1738 printk(KERN_ERR "%s: PCI parity error.\n",
1739 dev->name);
1740
1741 /* Write the error bits back to clear them. */
1742 cfg &= (PCI_STATUS_PARITY |
1743 PCI_STATUS_SIG_TARGET_ABORT |
1744 PCI_STATUS_REC_TARGET_ABORT |
1745 PCI_STATUS_REC_MASTER_ABORT |
1746 PCI_STATUS_SIG_SYSTEM_ERROR |
1747 PCI_STATUS_DETECTED_PARITY);
1748 pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
1749 }
1750
1751 /* For all PCI errors, we should reset the chip. */
1752 return 1;
1753}
1754
1755/* All non-normal interrupt conditions get serviced here.
1756 * Returns non-zero if we should just exit the interrupt
1757 * handler right now (ie. if we reset the card which invalidates
1758 * all of the other original irq status bits).
1759 */
1760static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1761 u32 status)
1762{
1763 if (status & INTR_RX_TAG_ERROR) {
1764 /* corrupt RX tag framing */
1765 if (netif_msg_rx_err(cp))
1766 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
1767 cp->dev->name);
1768 spin_lock(&cp->stat_lock[0]);
1769 cp->net_stats[0].rx_errors++;
1770 spin_unlock(&cp->stat_lock[0]);
1771 goto do_reset;
1772 }
1773
1774 if (status & INTR_RX_LEN_MISMATCH) {
1775 /* length mismatch. */
1776 if (netif_msg_rx_err(cp))
1777 printk(KERN_DEBUG "%s: length mismatch for rx frame\n",
1778 cp->dev->name);
1779 spin_lock(&cp->stat_lock[0]);
1780 cp->net_stats[0].rx_errors++;
1781 spin_unlock(&cp->stat_lock[0]);
1782 goto do_reset;
1783 }
1784
1785 if (status & INTR_PCS_STATUS) {
1786 if (cas_pcs_interrupt(dev, cp, status))
1787 goto do_reset;
1788 }
1789
1790 if (status & INTR_TX_MAC_STATUS) {
1791 if (cas_txmac_interrupt(dev, cp, status))
1792 goto do_reset;
1793 }
1794
1795 if (status & INTR_RX_MAC_STATUS) {
1796 if (cas_rxmac_interrupt(dev, cp, status))
1797 goto do_reset;
1798 }
1799
1800 if (status & INTR_MAC_CTRL_STATUS) {
1801 if (cas_mac_interrupt(dev, cp, status))
1802 goto do_reset;
1803 }
1804
1805 if (status & INTR_MIF_STATUS) {
1806 if (cas_mif_interrupt(dev, cp, status))
1807 goto do_reset;
1808 }
1809
1810 if (status & INTR_PCI_ERROR_STATUS) {
1811 if (cas_pci_interrupt(dev, cp, status))
1812 goto do_reset;
1813 }
1814 return 0;
1815
1816do_reset:
1817#if 1
1818 atomic_inc(&cp->reset_task_pending);
1819 atomic_inc(&cp->reset_task_pending_all);
1820 printk(KERN_ERR "%s:reset called in cas_abnormal_irq [0x%x]\n",
1821 dev->name, status);
1822 schedule_work(&cp->reset_task);
1823#else
1824 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1825 printk(KERN_ERR "reset called in cas_abnormal_irq\n");
1826 schedule_work(&cp->reset_task);
1827#endif
1828 return 1;
1829}
1830
1831/* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1832 * determining whether to do a netif_stop/wakeup
1833 */
1834#define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1835#define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1836static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1837 const int len)
1838{
1839 unsigned long off = addr + len;
1840
1841 if (CAS_TABORT(cp) == 1)
1842 return 0;
1843 if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1844 return 0;
1845 return TX_TARGET_ABORT_LEN;
1846}
1847
1848static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1849{
1850 struct cas_tx_desc *txds;
1851 struct sk_buff **skbs;
1852 struct net_device *dev = cp->dev;
1853 int entry, count;
1854
1855 spin_lock(&cp->tx_lock[ring]);
1856 txds = cp->init_txds[ring];
1857 skbs = cp->tx_skbs[ring];
1858 entry = cp->tx_old[ring];
1859
1860 count = TX_BUFF_COUNT(ring, entry, limit);
1861 while (entry != limit) {
1862 struct sk_buff *skb = skbs[entry];
1863 dma_addr_t daddr;
1864 u32 dlen;
1865 int frag;
1866
1867 if (!skb) {
1868 /* this should never occur */
1869 entry = TX_DESC_NEXT(ring, entry);
1870 continue;
1871 }
1872
1873 /* however, we might get only a partial skb release. */
1874 count -= skb_shinfo(skb)->nr_frags +
1875 + cp->tx_tiny_use[ring][entry].nbufs + 1;
1876 if (count < 0)
1877 break;
1878
1879 if (netif_msg_tx_done(cp))
1880 printk(KERN_DEBUG "%s: tx[%d] done, slot %d\n",
1881 cp->dev->name, ring, entry);
1882
1883 skbs[entry] = NULL;
1884 cp->tx_tiny_use[ring][entry].nbufs = 0;
1885
1886 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1887 struct cas_tx_desc *txd = txds + entry;
1888
1889 daddr = le64_to_cpu(txd->buffer);
1890 dlen = CAS_VAL(TX_DESC_BUFLEN,
1891 le64_to_cpu(txd->control));
1892 pci_unmap_page(cp->pdev, daddr, dlen,
1893 PCI_DMA_TODEVICE);
1894 entry = TX_DESC_NEXT(ring, entry);
1895
1896 /* tiny buffer may follow */
1897 if (cp->tx_tiny_use[ring][entry].used) {
1898 cp->tx_tiny_use[ring][entry].used = 0;
1899 entry = TX_DESC_NEXT(ring, entry);
1900 }
1901 }
1902
1903 spin_lock(&cp->stat_lock[ring]);
1904 cp->net_stats[ring].tx_packets++;
1905 cp->net_stats[ring].tx_bytes += skb->len;
1906 spin_unlock(&cp->stat_lock[ring]);
1907 dev_kfree_skb_irq(skb);
1908 }
1909 cp->tx_old[ring] = entry;
1910
1911 /* this is wrong for multiple tx rings. the net device needs
1912 * multiple queues for this to do the right thing. we wait
1913 * for 2*packets to be available when using tiny buffers
1914 */
1915 if (netif_queue_stopped(dev) &&
1916 (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1917 netif_wake_queue(dev);
1918 spin_unlock(&cp->tx_lock[ring]);
1919}
1920
1921static void cas_tx(struct net_device *dev, struct cas *cp,
1922 u32 status)
1923{
1924 int limit, ring;
1925#ifdef USE_TX_COMPWB
1926 u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1927#endif
1928 if (netif_msg_intr(cp))
1929 printk(KERN_DEBUG "%s: tx interrupt, status: 0x%x, %lx\n",
1930 cp->dev->name, status, compwb);
1931 /* process all the rings */
1932 for (ring = 0; ring < N_TX_RINGS; ring++) {
1933#ifdef USE_TX_COMPWB
1934 /* use the completion writeback registers */
1935 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1936 CAS_VAL(TX_COMPWB_LSB, compwb);
1937 compwb = TX_COMPWB_NEXT(compwb);
1938#else
1939 limit = readl(cp->regs + REG_TX_COMPN(ring));
1940#endif
1941 if (cp->tx_old[ring] != limit)
1942 cas_tx_ringN(cp, ring, limit);
1943 }
1944}
1945
1946
1947static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1948 int entry, const u64 *words,
1949 struct sk_buff **skbref)
1950{
1951 int dlen, hlen, len, i, alloclen;
1952 int off, swivel = RX_SWIVEL_OFF_VAL;
1953 struct cas_page *page;
1954 struct sk_buff *skb;
1955 void *addr, *crcaddr;
1956 char *p;
1957
1958 hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1959 dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1960 len = hlen + dlen;
1961
1962 if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
1963 alloclen = len;
1964 else
1965 alloclen = max(hlen, RX_COPY_MIN);
1966
1967 skb = dev_alloc_skb(alloclen + swivel + cp->crc_size);
1968 if (skb == NULL)
1969 return -1;
1970
1971 *skbref = skb;
1972 skb->dev = cp->dev;
1973 skb_reserve(skb, swivel);
1974
1975 p = skb->data;
1976 addr = crcaddr = NULL;
1977 if (hlen) { /* always copy header pages */
1978 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
1979 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1980 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
1981 swivel;
1982
1983 i = hlen;
1984 if (!dlen) /* attach FCS */
1985 i += cp->crc_size;
1986 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
1987 PCI_DMA_FROMDEVICE);
1988 addr = cas_page_map(page->buffer);
1989 memcpy(p, addr + off, i);
1990 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
1991 PCI_DMA_FROMDEVICE);
1992 cas_page_unmap(addr);
1993 RX_USED_ADD(page, 0x100);
1994 p += hlen;
1995 swivel = 0;
1996 }
1997
1998
1999 if (alloclen < (hlen + dlen)) {
2000 skb_frag_t *frag = skb_shinfo(skb)->frags;
2001
2002 /* normal or jumbo packets. we use frags */
2003 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2004 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2005 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2006
2007 hlen = min(cp->page_size - off, dlen);
2008 if (hlen < 0) {
2009 if (netif_msg_rx_err(cp)) {
2010 printk(KERN_DEBUG "%s: rx page overflow: "
2011 "%d\n", cp->dev->name, hlen);
2012 }
2013 dev_kfree_skb_irq(skb);
2014 return -1;
2015 }
2016 i = hlen;
2017 if (i == dlen) /* attach FCS */
2018 i += cp->crc_size;
2019 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2020 PCI_DMA_FROMDEVICE);
2021
2022 /* make sure we always copy a header */
2023 swivel = 0;
2024 if (p == (char *) skb->data) { /* not split */
2025 addr = cas_page_map(page->buffer);
2026 memcpy(p, addr + off, RX_COPY_MIN);
2027 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2028 PCI_DMA_FROMDEVICE);
2029 cas_page_unmap(addr);
2030 off += RX_COPY_MIN;
2031 swivel = RX_COPY_MIN;
2032 RX_USED_ADD(page, cp->mtu_stride);
2033 } else {
2034 RX_USED_ADD(page, hlen);
2035 }
2036 skb_put(skb, alloclen);
2037
2038 skb_shinfo(skb)->nr_frags++;
2039 skb->data_len += hlen - swivel;
2040 skb->len += hlen - swivel;
2041
2042 get_page(page->buffer);
2043 frag->page = page->buffer;
2044 frag->page_offset = off;
2045 frag->size = hlen - swivel;
2046
2047 /* any more data? */
2048 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2049 hlen = dlen;
2050 off = 0;
2051
2052 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2053 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2054 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2055 hlen + cp->crc_size,
2056 PCI_DMA_FROMDEVICE);
2057 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2058 hlen + cp->crc_size,
2059 PCI_DMA_FROMDEVICE);
2060
2061 skb_shinfo(skb)->nr_frags++;
2062 skb->data_len += hlen;
2063 skb->len += hlen;
2064 frag++;
2065
2066 get_page(page->buffer);
2067 frag->page = page->buffer;
2068 frag->page_offset = 0;
2069 frag->size = hlen;
2070 RX_USED_ADD(page, hlen + cp->crc_size);
2071 }
2072
2073 if (cp->crc_size) {
2074 addr = cas_page_map(page->buffer);
2075 crcaddr = addr + off + hlen;
2076 }
2077
2078 } else {
2079 /* copying packet */
2080 if (!dlen)
2081 goto end_copy_pkt;
2082
2083 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2084 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2085 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2086 hlen = min(cp->page_size - off, dlen);
2087 if (hlen < 0) {
2088 if (netif_msg_rx_err(cp)) {
2089 printk(KERN_DEBUG "%s: rx page overflow: "
2090 "%d\n", cp->dev->name, hlen);
2091 }
2092 dev_kfree_skb_irq(skb);
2093 return -1;
2094 }
2095 i = hlen;
2096 if (i == dlen) /* attach FCS */
2097 i += cp->crc_size;
2098 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2099 PCI_DMA_FROMDEVICE);
2100 addr = cas_page_map(page->buffer);
2101 memcpy(p, addr + off, i);
2102 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2103 PCI_DMA_FROMDEVICE);
2104 cas_page_unmap(addr);
2105 if (p == (char *) skb->data) /* not split */
2106 RX_USED_ADD(page, cp->mtu_stride);
2107 else
2108 RX_USED_ADD(page, i);
2109
2110 /* any more data? */
2111 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2112 p += hlen;
2113 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2114 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2115 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2116 dlen + cp->crc_size,
2117 PCI_DMA_FROMDEVICE);
2118 addr = cas_page_map(page->buffer);
2119 memcpy(p, addr, dlen + cp->crc_size);
2120 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2121 dlen + cp->crc_size,
2122 PCI_DMA_FROMDEVICE);
2123 cas_page_unmap(addr);
2124 RX_USED_ADD(page, dlen + cp->crc_size);
2125 }
2126end_copy_pkt:
2127 if (cp->crc_size) {
2128 addr = NULL;
2129 crcaddr = skb->data + alloclen;
2130 }
2131 skb_put(skb, alloclen);
2132 }
2133
2134 i = CAS_VAL(RX_COMP4_TCP_CSUM, words[3]);
2135 if (cp->crc_size) {
2136 /* checksum includes FCS. strip it out. */
2137 i = csum_fold(csum_partial(crcaddr, cp->crc_size, i));
2138 if (addr)
2139 cas_page_unmap(addr);
2140 }
2141 skb->csum = ntohs(i ^ 0xffff);
2142 skb->ip_summed = CHECKSUM_HW;
2143 skb->protocol = eth_type_trans(skb, cp->dev);
2144 return len;
2145}
2146
2147
2148/* we can handle up to 64 rx flows at a time. we do the same thing
2149 * as nonreassm except that we batch up the buffers.
2150 * NOTE: we currently just treat each flow as a bunch of packets that
2151 * we pass up. a better way would be to coalesce the packets
2152 * into a jumbo packet. to do that, we need to do the following:
2153 * 1) the first packet will have a clean split between header and
2154 * data. save both.
2155 * 2) each time the next flow packet comes in, extend the
2156 * data length and merge the checksums.
2157 * 3) on flow release, fix up the header.
2158 * 4) make sure the higher layer doesn't care.
2159 * because packets get coalesced, we shouldn't run into fragment count
2160 * issues.
2161 */
2162static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2163 struct sk_buff *skb)
2164{
2165 int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2166 struct sk_buff_head *flow = &cp->rx_flows[flowid];
2167
2168 /* this is protected at a higher layer, so no need to
2169 * do any additional locking here. stick the buffer
2170 * at the end.
2171 */
2172 __skb_insert(skb, flow->prev, (struct sk_buff *) flow, flow);
2173 if (words[0] & RX_COMP1_RELEASE_FLOW) {
2174 while ((skb = __skb_dequeue(flow))) {
2175 cas_skb_release(skb);
2176 }
2177 }
2178}
2179
2180/* put rx descriptor back on ring. if a buffer is in use by a higher
2181 * layer, this will need to put in a replacement.
2182 */
2183static void cas_post_page(struct cas *cp, const int ring, const int index)
2184{
2185 cas_page_t *new;
2186 int entry;
2187
2188 entry = cp->rx_old[ring];
2189
2190 new = cas_page_swap(cp, ring, index);
2191 cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2192 cp->init_rxds[ring][entry].index =
2193 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2194 CAS_BASE(RX_INDEX_RING, ring));
2195
2196 entry = RX_DESC_ENTRY(ring, entry + 1);
2197 cp->rx_old[ring] = entry;
2198
2199 if (entry % 4)
2200 return;
2201
2202 if (ring == 0)
2203 writel(entry, cp->regs + REG_RX_KICK);
2204 else if ((N_RX_DESC_RINGS > 1) &&
2205 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2206 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2207}
2208
2209
2210/* only when things are bad */
2211static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2212{
2213 unsigned int entry, last, count, released;
2214 int cluster;
2215 cas_page_t **page = cp->rx_pages[ring];
2216
2217 entry = cp->rx_old[ring];
2218
2219 if (netif_msg_intr(cp))
2220 printk(KERN_DEBUG "%s: rxd[%d] interrupt, done: %d\n",
2221 cp->dev->name, ring, entry);
2222
2223 cluster = -1;
2224 count = entry & 0x3;
2225 last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2226 released = 0;
2227 while (entry != last) {
2228 /* make a new buffer if it's still in use */
2229 if (page_count(page[entry]->buffer) > 1) {
2230 cas_page_t *new = cas_page_dequeue(cp);
2231 if (!new) {
2232 /* let the timer know that we need to
2233 * do this again
2234 */
2235 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2236 if (!timer_pending(&cp->link_timer))
2237 mod_timer(&cp->link_timer, jiffies +
2238 CAS_LINK_FAST_TIMEOUT);
2239 cp->rx_old[ring] = entry;
2240 cp->rx_last[ring] = num ? num - released : 0;
2241 return -ENOMEM;
2242 }
2243 spin_lock(&cp->rx_inuse_lock);
2244 list_add(&page[entry]->list, &cp->rx_inuse_list);
2245 spin_unlock(&cp->rx_inuse_lock);
2246 cp->init_rxds[ring][entry].buffer =
2247 cpu_to_le64(new->dma_addr);
2248 page[entry] = new;
2249
2250 }
2251
2252 if (++count == 4) {
2253 cluster = entry;
2254 count = 0;
2255 }
2256 released++;
2257 entry = RX_DESC_ENTRY(ring, entry + 1);
2258 }
2259 cp->rx_old[ring] = entry;
2260
2261 if (cluster < 0)
2262 return 0;
2263
2264 if (ring == 0)
2265 writel(cluster, cp->regs + REG_RX_KICK);
2266 else if ((N_RX_DESC_RINGS > 1) &&
2267 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2268 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2269 return 0;
2270}
2271
2272
2273/* process a completion ring. packets are set up in three basic ways:
2274 * small packets: should be copied header + data in single buffer.
2275 * large packets: header and data in a single buffer.
2276 * split packets: header in a separate buffer from data.
2277 * data may be in multiple pages. data may be > 256
2278 * bytes but in a single page.
2279 *
2280 * NOTE: RX page posting is done in this routine as well. while there's
2281 * the capability of using multiple RX completion rings, it isn't
2282 * really worthwhile due to the fact that the page posting will
2283 * force serialization on the single descriptor ring.
2284 */
2285static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2286{
2287 struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2288 int entry, drops;
2289 int npackets = 0;
2290
2291 if (netif_msg_intr(cp))
2292 printk(KERN_DEBUG "%s: rx[%d] interrupt, done: %d/%d\n",
2293 cp->dev->name, ring,
2294 readl(cp->regs + REG_RX_COMP_HEAD),
2295 cp->rx_new[ring]);
2296
2297 entry = cp->rx_new[ring];
2298 drops = 0;
2299 while (1) {
2300 struct cas_rx_comp *rxc = rxcs + entry;
2301 struct sk_buff *skb;
2302 int type, len;
2303 u64 words[4];
2304 int i, dring;
2305
2306 words[0] = le64_to_cpu(rxc->word1);
2307 words[1] = le64_to_cpu(rxc->word2);
2308 words[2] = le64_to_cpu(rxc->word3);
2309 words[3] = le64_to_cpu(rxc->word4);
2310
2311 /* don't touch if still owned by hw */
2312 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2313 if (type == 0)
2314 break;
2315
2316 /* hw hasn't cleared the zero bit yet */
2317 if (words[3] & RX_COMP4_ZERO) {
2318 break;
2319 }
2320
2321 /* get info on the packet */
2322 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2323 spin_lock(&cp->stat_lock[ring]);
2324 cp->net_stats[ring].rx_errors++;
2325 if (words[3] & RX_COMP4_LEN_MISMATCH)
2326 cp->net_stats[ring].rx_length_errors++;
2327 if (words[3] & RX_COMP4_BAD)
2328 cp->net_stats[ring].rx_crc_errors++;
2329 spin_unlock(&cp->stat_lock[ring]);
2330
2331 /* We'll just return it to Cassini. */
2332 drop_it:
2333 spin_lock(&cp->stat_lock[ring]);
2334 ++cp->net_stats[ring].rx_dropped;
2335 spin_unlock(&cp->stat_lock[ring]);
2336 goto next;
2337 }
2338
2339 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2340 if (len < 0) {
2341 ++drops;
2342 goto drop_it;
2343 }
2344
2345 /* see if it's a flow re-assembly or not. the driver
2346 * itself handles release back up.
2347 */
2348 if (RX_DONT_BATCH || (type == 0x2)) {
2349 /* non-reassm: these always get released */
2350 cas_skb_release(skb);
2351 } else {
2352 cas_rx_flow_pkt(cp, words, skb);
2353 }
2354
2355 spin_lock(&cp->stat_lock[ring]);
2356 cp->net_stats[ring].rx_packets++;
2357 cp->net_stats[ring].rx_bytes += len;
2358 spin_unlock(&cp->stat_lock[ring]);
2359 cp->dev->last_rx = jiffies;
2360
2361 next:
2362 npackets++;
2363
2364 /* should it be released? */
2365 if (words[0] & RX_COMP1_RELEASE_HDR) {
2366 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2367 dring = CAS_VAL(RX_INDEX_RING, i);
2368 i = CAS_VAL(RX_INDEX_NUM, i);
2369 cas_post_page(cp, dring, i);
2370 }
2371
2372 if (words[0] & RX_COMP1_RELEASE_DATA) {
2373 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2374 dring = CAS_VAL(RX_INDEX_RING, i);
2375 i = CAS_VAL(RX_INDEX_NUM, i);
2376 cas_post_page(cp, dring, i);
2377 }
2378
2379 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2380 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2381 dring = CAS_VAL(RX_INDEX_RING, i);
2382 i = CAS_VAL(RX_INDEX_NUM, i);
2383 cas_post_page(cp, dring, i);
2384 }
2385
2386 /* skip to the next entry */
2387 entry = RX_COMP_ENTRY(ring, entry + 1 +
2388 CAS_VAL(RX_COMP1_SKIP, words[0]));
2389#ifdef USE_NAPI
2390 if (budget && (npackets >= budget))
2391 break;
2392#endif
2393 }
2394 cp->rx_new[ring] = entry;
2395
2396 if (drops)
2397 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
2398 cp->dev->name);
2399 return npackets;
2400}
2401
2402
2403/* put completion entries back on the ring */
2404static void cas_post_rxcs_ringN(struct net_device *dev,
2405 struct cas *cp, int ring)
2406{
2407 struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2408 int last, entry;
2409
2410 last = cp->rx_cur[ring];
2411 entry = cp->rx_new[ring];
2412 if (netif_msg_intr(cp))
2413 printk(KERN_DEBUG "%s: rxc[%d] interrupt, done: %d/%d\n",
2414 dev->name, ring, readl(cp->regs + REG_RX_COMP_HEAD),
2415 entry);
2416
2417 /* zero and re-mark descriptors */
2418 while (last != entry) {
2419 cas_rxc_init(rxc + last);
2420 last = RX_COMP_ENTRY(ring, last + 1);
2421 }
2422 cp->rx_cur[ring] = last;
2423
2424 if (ring == 0)
2425 writel(last, cp->regs + REG_RX_COMP_TAIL);
2426 else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2427 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2428}
2429
2430
2431
2432/* cassini can use all four PCI interrupts for the completion ring.
2433 * rings 3 and 4 are identical
2434 */
2435#if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2436static inline void cas_handle_irqN(struct net_device *dev,
2437 struct cas *cp, const u32 status,
2438 const int ring)
2439{
2440 if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2441 cas_post_rxcs_ringN(dev, cp, ring);
2442}
2443
2444static irqreturn_t cas_interruptN(int irq, void *dev_id, struct pt_regs *regs)
2445{
2446 struct net_device *dev = dev_id;
2447 struct cas *cp = netdev_priv(dev);
2448 unsigned long flags;
2449 int ring;
2450 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2451
2452 /* check for shared irq */
2453 if (status == 0)
2454 return IRQ_NONE;
2455
2456 ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2457 spin_lock_irqsave(&cp->lock, flags);
2458 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2459#ifdef USE_NAPI
2460 cas_mask_intr(cp);
2461 netif_rx_schedule(dev);
2462#else
2463 cas_rx_ringN(cp, ring, 0);
2464#endif
2465 status &= ~INTR_RX_DONE_ALT;
2466 }
2467
2468 if (status)
2469 cas_handle_irqN(dev, cp, status, ring);
2470 spin_unlock_irqrestore(&cp->lock, flags);
2471 return IRQ_HANDLED;
2472}
2473#endif
2474
2475#ifdef USE_PCI_INTB
2476/* everything but rx packets */
2477static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2478{
2479 if (status & INTR_RX_BUF_UNAVAIL_1) {
2480 /* Frame arrived, no free RX buffers available.
2481 * NOTE: we can get this on a link transition. */
2482 cas_post_rxds_ringN(cp, 1, 0);
2483 spin_lock(&cp->stat_lock[1]);
2484 cp->net_stats[1].rx_dropped++;
2485 spin_unlock(&cp->stat_lock[1]);
2486 }
2487
2488 if (status & INTR_RX_BUF_AE_1)
2489 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2490 RX_AE_FREEN_VAL(1));
2491
2492 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2493 cas_post_rxcs_ringN(cp, 1);
2494}
2495
2496/* ring 2 handles a few more events than 3 and 4 */
2497static irqreturn_t cas_interrupt1(int irq, void *dev_id, struct pt_regs *regs)
2498{
2499 struct net_device *dev = dev_id;
2500 struct cas *cp = netdev_priv(dev);
2501 unsigned long flags;
2502 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2503
2504 /* check for shared interrupt */
2505 if (status == 0)
2506 return IRQ_NONE;
2507
2508 spin_lock_irqsave(&cp->lock, flags);
2509 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2510#ifdef USE_NAPI
2511 cas_mask_intr(cp);
2512 netif_rx_schedule(dev);
2513#else
2514 cas_rx_ringN(cp, 1, 0);
2515#endif
2516 status &= ~INTR_RX_DONE_ALT;
2517 }
2518 if (status)
2519 cas_handle_irq1(cp, status);
2520 spin_unlock_irqrestore(&cp->lock, flags);
2521 return IRQ_HANDLED;
2522}
2523#endif
2524
2525static inline void cas_handle_irq(struct net_device *dev,
2526 struct cas *cp, const u32 status)
2527{
2528 /* housekeeping interrupts */
2529 if (status & INTR_ERROR_MASK)
2530 cas_abnormal_irq(dev, cp, status);
2531
2532 if (status & INTR_RX_BUF_UNAVAIL) {
2533 /* Frame arrived, no free RX buffers available.
2534 * NOTE: we can get this on a link transition.
2535 */
2536 cas_post_rxds_ringN(cp, 0, 0);
2537 spin_lock(&cp->stat_lock[0]);
2538 cp->net_stats[0].rx_dropped++;
2539 spin_unlock(&cp->stat_lock[0]);
2540 } else if (status & INTR_RX_BUF_AE) {
2541 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2542 RX_AE_FREEN_VAL(0));
2543 }
2544
2545 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2546 cas_post_rxcs_ringN(dev, cp, 0);
2547}
2548
2549static irqreturn_t cas_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2550{
2551 struct net_device *dev = dev_id;
2552 struct cas *cp = netdev_priv(dev);
2553 unsigned long flags;
2554 u32 status = readl(cp->regs + REG_INTR_STATUS);
2555
2556 if (status == 0)
2557 return IRQ_NONE;
2558
2559 spin_lock_irqsave(&cp->lock, flags);
2560 if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2561 cas_tx(dev, cp, status);
2562 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2563 }
2564
2565 if (status & INTR_RX_DONE) {
2566#ifdef USE_NAPI
2567 cas_mask_intr(cp);
2568 netif_rx_schedule(dev);
2569#else
2570 cas_rx_ringN(cp, 0, 0);
2571#endif
2572 status &= ~INTR_RX_DONE;
2573 }
2574
2575 if (status)
2576 cas_handle_irq(dev, cp, status);
2577 spin_unlock_irqrestore(&cp->lock, flags);
2578 return IRQ_HANDLED;
2579}
2580
2581
2582#ifdef USE_NAPI
2583static int cas_poll(struct net_device *dev, int *budget)
2584{
2585 struct cas *cp = netdev_priv(dev);
2586 int i, enable_intr, todo, credits;
2587 u32 status = readl(cp->regs + REG_INTR_STATUS);
2588 unsigned long flags;
2589
2590 spin_lock_irqsave(&cp->lock, flags);
2591 cas_tx(dev, cp, status);
2592 spin_unlock_irqrestore(&cp->lock, flags);
2593
2594 /* NAPI rx packets. we spread the credits across all of the
2595 * rxc rings
2596 */
2597 todo = min(*budget, dev->quota);
2598
2599 /* to make sure we're fair with the work we loop through each
2600 * ring N_RX_COMP_RING times with a request of
2601 * todo / N_RX_COMP_RINGS
2602 */
2603 enable_intr = 1;
2604 credits = 0;
2605 for (i = 0; i < N_RX_COMP_RINGS; i++) {
2606 int j;
2607 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2608 credits += cas_rx_ringN(cp, j, todo / N_RX_COMP_RINGS);
2609 if (credits >= todo) {
2610 enable_intr = 0;
2611 goto rx_comp;
2612 }
2613 }
2614 }
2615
2616rx_comp:
2617 *budget -= credits;
2618 dev->quota -= credits;
2619
2620 /* final rx completion */
2621 spin_lock_irqsave(&cp->lock, flags);
2622 if (status)
2623 cas_handle_irq(dev, cp, status);
2624
2625#ifdef USE_PCI_INTB
2626 if (N_RX_COMP_RINGS > 1) {
2627 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2628 if (status)
2629 cas_handle_irq1(dev, cp, status);
2630 }
2631#endif
2632
2633#ifdef USE_PCI_INTC
2634 if (N_RX_COMP_RINGS > 2) {
2635 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2636 if (status)
2637 cas_handle_irqN(dev, cp, status, 2);
2638 }
2639#endif
2640
2641#ifdef USE_PCI_INTD
2642 if (N_RX_COMP_RINGS > 3) {
2643 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2644 if (status)
2645 cas_handle_irqN(dev, cp, status, 3);
2646 }
2647#endif
2648 spin_unlock_irqrestore(&cp->lock, flags);
2649 if (enable_intr) {
2650 netif_rx_complete(dev);
2651 cas_unmask_intr(cp);
2652 return 0;
2653 }
2654 return 1;
2655}
2656#endif
2657
2658#ifdef CONFIG_NET_POLL_CONTROLLER
2659static void cas_netpoll(struct net_device *dev)
2660{
2661 struct cas *cp = netdev_priv(dev);
2662
2663 cas_disable_irq(cp, 0);
2664 cas_interrupt(cp->pdev->irq, dev, NULL);
2665 cas_enable_irq(cp, 0);
2666
2667#ifdef USE_PCI_INTB
2668 if (N_RX_COMP_RINGS > 1) {
2669 /* cas_interrupt1(); */
2670 }
2671#endif
2672#ifdef USE_PCI_INTC
2673 if (N_RX_COMP_RINGS > 2) {
2674 /* cas_interruptN(); */
2675 }
2676#endif
2677#ifdef USE_PCI_INTD
2678 if (N_RX_COMP_RINGS > 3) {
2679 /* cas_interruptN(); */
2680 }
2681#endif
2682}
2683#endif
2684
2685static void cas_tx_timeout(struct net_device *dev)
2686{
2687 struct cas *cp = netdev_priv(dev);
2688
2689 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2690 if (!cp->hw_running) {
2691 printk("%s: hrm.. hw not running!\n", dev->name);
2692 return;
2693 }
2694
2695 printk(KERN_ERR "%s: MIF_STATE[%08x]\n",
2696 dev->name, readl(cp->regs + REG_MIF_STATE_MACHINE));
2697
2698 printk(KERN_ERR "%s: MAC_STATE[%08x]\n",
2699 dev->name, readl(cp->regs + REG_MAC_STATE_MACHINE));
2700
2701 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x] "
2702 "FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2703 dev->name,
2704 readl(cp->regs + REG_TX_CFG),
2705 readl(cp->regs + REG_MAC_TX_STATUS),
2706 readl(cp->regs + REG_MAC_TX_CFG),
2707 readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2708 readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2709 readl(cp->regs + REG_TX_FIFO_READ_PTR),
2710 readl(cp->regs + REG_TX_SM_1),
2711 readl(cp->regs + REG_TX_SM_2));
2712
2713 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
2714 dev->name,
2715 readl(cp->regs + REG_RX_CFG),
2716 readl(cp->regs + REG_MAC_RX_STATUS),
2717 readl(cp->regs + REG_MAC_RX_CFG));
2718
2719 printk(KERN_ERR "%s: HP_STATE[%08x:%08x:%08x:%08x]\n",
2720 dev->name,
2721 readl(cp->regs + REG_HP_STATE_MACHINE),
2722 readl(cp->regs + REG_HP_STATUS0),
2723 readl(cp->regs + REG_HP_STATUS1),
2724 readl(cp->regs + REG_HP_STATUS2));
2725
2726#if 1
2727 atomic_inc(&cp->reset_task_pending);
2728 atomic_inc(&cp->reset_task_pending_all);
2729 schedule_work(&cp->reset_task);
2730#else
2731 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2732 schedule_work(&cp->reset_task);
2733#endif
2734}
2735
2736static inline int cas_intme(int ring, int entry)
2737{
2738 /* Algorithm: IRQ every 1/2 of descriptors. */
2739 if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2740 return 1;
2741 return 0;
2742}
2743
2744
2745static void cas_write_txd(struct cas *cp, int ring, int entry,
2746 dma_addr_t mapping, int len, u64 ctrl, int last)
2747{
2748 struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2749
2750 ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2751 if (cas_intme(ring, entry))
2752 ctrl |= TX_DESC_INTME;
2753 if (last)
2754 ctrl |= TX_DESC_EOF;
2755 txd->control = cpu_to_le64(ctrl);
2756 txd->buffer = cpu_to_le64(mapping);
2757}
2758
2759static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2760 const int entry)
2761{
2762 return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2763}
2764
2765static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2766 const int entry, const int tentry)
2767{
2768 cp->tx_tiny_use[ring][tentry].nbufs++;
2769 cp->tx_tiny_use[ring][entry].used = 1;
2770 return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2771}
2772
2773static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2774 struct sk_buff *skb)
2775{
2776 struct net_device *dev = cp->dev;
2777 int entry, nr_frags, frag, tabort, tentry;
2778 dma_addr_t mapping;
2779 unsigned long flags;
2780 u64 ctrl;
2781 u32 len;
2782
2783 spin_lock_irqsave(&cp->tx_lock[ring], flags);
2784
2785 /* This is a hard error, log it. */
2786 if (TX_BUFFS_AVAIL(cp, ring) <=
2787 CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2788 netif_stop_queue(dev);
2789 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2790 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
2791 "queue awake!\n", dev->name);
2792 return 1;
2793 }
2794
2795 ctrl = 0;
2796 if (skb->ip_summed == CHECKSUM_HW) {
2797 u64 csum_start_off, csum_stuff_off;
2798
2799 csum_start_off = (u64) (skb->h.raw - skb->data);
2800 csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data);
2801
2802 ctrl = TX_DESC_CSUM_EN |
2803 CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2804 CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2805 }
2806
2807 entry = cp->tx_new[ring];
2808 cp->tx_skbs[ring][entry] = skb;
2809
2810 nr_frags = skb_shinfo(skb)->nr_frags;
2811 len = skb_headlen(skb);
2812 mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2813 offset_in_page(skb->data), len,
2814 PCI_DMA_TODEVICE);
2815
2816 tentry = entry;
2817 tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2818 if (unlikely(tabort)) {
2819 /* NOTE: len is always > tabort */
2820 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2821 ctrl | TX_DESC_SOF, 0);
2822 entry = TX_DESC_NEXT(ring, entry);
2823
2824 memcpy(tx_tiny_buf(cp, ring, entry), skb->data +
2825 len - tabort, tabort);
2826 mapping = tx_tiny_map(cp, ring, entry, tentry);
2827 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2828 (nr_frags == 0));
2829 } else {
2830 cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2831 TX_DESC_SOF, (nr_frags == 0));
2832 }
2833 entry = TX_DESC_NEXT(ring, entry);
2834
2835 for (frag = 0; frag < nr_frags; frag++) {
2836 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2837
2838 len = fragp->size;
2839 mapping = pci_map_page(cp->pdev, fragp->page,
2840 fragp->page_offset, len,
2841 PCI_DMA_TODEVICE);
2842
2843 tabort = cas_calc_tabort(cp, fragp->page_offset, len);
2844 if (unlikely(tabort)) {
2845 void *addr;
2846
2847 /* NOTE: len is always > tabort */
2848 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2849 ctrl, 0);
2850 entry = TX_DESC_NEXT(ring, entry);
2851
2852 addr = cas_page_map(fragp->page);
2853 memcpy(tx_tiny_buf(cp, ring, entry),
2854 addr + fragp->page_offset + len - tabort,
2855 tabort);
2856 cas_page_unmap(addr);
2857 mapping = tx_tiny_map(cp, ring, entry, tentry);
2858 len = tabort;
2859 }
2860
2861 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2862 (frag + 1 == nr_frags));
2863 entry = TX_DESC_NEXT(ring, entry);
2864 }
2865
2866 cp->tx_new[ring] = entry;
2867 if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2868 netif_stop_queue(dev);
2869
2870 if (netif_msg_tx_queued(cp))
2871 printk(KERN_DEBUG "%s: tx[%d] queued, slot %d, skblen %d, "
2872 "avail %d\n",
2873 dev->name, ring, entry, skb->len,
2874 TX_BUFFS_AVAIL(cp, ring));
2875 writel(entry, cp->regs + REG_TX_KICKN(ring));
2876 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2877 return 0;
2878}
2879
2880static int cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2881{
2882 struct cas *cp = netdev_priv(dev);
2883
2884 /* this is only used as a load-balancing hint, so it doesn't
2885 * need to be SMP safe
2886 */
2887 static int ring;
2888
2889 skb = skb_padto(skb, cp->min_frame_size);
2890 if (!skb)
2891 return 0;
2892
2893 /* XXX: we need some higher-level QoS hooks to steer packets to
2894 * individual queues.
2895 */
2896 if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2897 return 1;
2898 dev->trans_start = jiffies;
2899 return 0;
2900}
2901
2902static void cas_init_tx_dma(struct cas *cp)
2903{
2904 u64 desc_dma = cp->block_dvma;
2905 unsigned long off;
2906 u32 val;
2907 int i;
2908
2909 /* set up tx completion writeback registers. must be 8-byte aligned */
2910#ifdef USE_TX_COMPWB
2911 off = offsetof(struct cas_init_block, tx_compwb);
2912 writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2913 writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2914#endif
2915
2916 /* enable completion writebacks, enable paced mode,
2917 * disable read pipe, and disable pre-interrupt compwbs
2918 */
2919 val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2920 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2921 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2922 TX_CFG_INTR_COMPWB_DIS;
2923
2924 /* write out tx ring info and tx desc bases */
2925 for (i = 0; i < MAX_TX_RINGS; i++) {
2926 off = (unsigned long) cp->init_txds[i] -
2927 (unsigned long) cp->init_block;
2928
2929 val |= CAS_TX_RINGN_BASE(i);
2930 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2931 writel((desc_dma + off) & 0xffffffff, cp->regs +
2932 REG_TX_DBN_LOW(i));
2933 /* don't zero out the kick register here as the system
2934 * will wedge
2935 */
2936 }
2937 writel(val, cp->regs + REG_TX_CFG);
2938
2939 /* program max burst sizes. these numbers should be different
2940 * if doing QoS.
2941 */
2942#ifdef USE_QOS
2943 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2944 writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2945 writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2946 writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2947#else
2948 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2949 writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2950 writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2951 writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2952#endif
2953}
2954
2955/* Must be invoked under cp->lock. */
2956static inline void cas_init_dma(struct cas *cp)
2957{
2958 cas_init_tx_dma(cp);
2959 cas_init_rx_dma(cp);
2960}
2961
2962/* Must be invoked under cp->lock. */
2963static u32 cas_setup_multicast(struct cas *cp)
2964{
2965 u32 rxcfg = 0;
2966 int i;
2967
2968 if (cp->dev->flags & IFF_PROMISC) {
2969 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2970
2971 } else if (cp->dev->flags & IFF_ALLMULTI) {
2972 for (i=0; i < 16; i++)
2973 writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
2974 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2975
2976 } else {
2977 u16 hash_table[16];
2978 u32 crc;
2979 struct dev_mc_list *dmi = cp->dev->mc_list;
2980 int i;
2981
2982 /* use the alternate mac address registers for the
2983 * first 15 multicast addresses
2984 */
2985 for (i = 1; i <= CAS_MC_EXACT_MATCH_SIZE; i++) {
2986 if (!dmi) {
2987 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 0));
2988 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 1));
2989 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 2));
2990 continue;
2991 }
2992 writel((dmi->dmi_addr[4] << 8) | dmi->dmi_addr[5],
2993 cp->regs + REG_MAC_ADDRN(i*3 + 0));
2994 writel((dmi->dmi_addr[2] << 8) | dmi->dmi_addr[3],
2995 cp->regs + REG_MAC_ADDRN(i*3 + 1));
2996 writel((dmi->dmi_addr[0] << 8) | dmi->dmi_addr[1],
2997 cp->regs + REG_MAC_ADDRN(i*3 + 2));
2998 dmi = dmi->next;
2999 }
3000
3001 /* use hw hash table for the next series of
3002 * multicast addresses
3003 */
3004 memset(hash_table, 0, sizeof(hash_table));
3005 while (dmi) {
3006 crc = ether_crc_le(ETH_ALEN, dmi->dmi_addr);
3007 crc >>= 24;
3008 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
3009 dmi = dmi->next;
3010 }
3011 for (i=0; i < 16; i++)
3012 writel(hash_table[i], cp->regs +
3013 REG_MAC_HASH_TABLEN(i));
3014 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3015 }
3016
3017 return rxcfg;
3018}
3019
3020/* must be invoked under cp->stat_lock[N_TX_RINGS] */
3021static void cas_clear_mac_err(struct cas *cp)
3022{
3023 writel(0, cp->regs + REG_MAC_COLL_NORMAL);
3024 writel(0, cp->regs + REG_MAC_COLL_FIRST);
3025 writel(0, cp->regs + REG_MAC_COLL_EXCESS);
3026 writel(0, cp->regs + REG_MAC_COLL_LATE);
3027 writel(0, cp->regs + REG_MAC_TIMER_DEFER);
3028 writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
3029 writel(0, cp->regs + REG_MAC_RECV_FRAME);
3030 writel(0, cp->regs + REG_MAC_LEN_ERR);
3031 writel(0, cp->regs + REG_MAC_ALIGN_ERR);
3032 writel(0, cp->regs + REG_MAC_FCS_ERR);
3033 writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
3034}
3035
3036
3037static void cas_mac_reset(struct cas *cp)
3038{
3039 int i;
3040
3041 /* do both TX and RX reset */
3042 writel(0x1, cp->regs + REG_MAC_TX_RESET);
3043 writel(0x1, cp->regs + REG_MAC_RX_RESET);
3044
3045 /* wait for TX */
3046 i = STOP_TRIES;
3047 while (i-- > 0) {
3048 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3049 break;
3050 udelay(10);
3051 }
3052
3053 /* wait for RX */
3054 i = STOP_TRIES;
3055 while (i-- > 0) {
3056 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3057 break;
3058 udelay(10);
3059 }
3060
3061 if (readl(cp->regs + REG_MAC_TX_RESET) |
3062 readl(cp->regs + REG_MAC_RX_RESET))
3063 printk(KERN_ERR "%s: mac tx[%d]/rx[%d] reset failed [%08x]\n",
3064 cp->dev->name, readl(cp->regs + REG_MAC_TX_RESET),
3065 readl(cp->regs + REG_MAC_RX_RESET),
3066 readl(cp->regs + REG_MAC_STATE_MACHINE));
3067}
3068
3069
3070/* Must be invoked under cp->lock. */
3071static void cas_init_mac(struct cas *cp)
3072{
3073 unsigned char *e = &cp->dev->dev_addr[0];
3074 int i;
3075#ifdef CONFIG_CASSINI_MULTICAST_REG_WRITE
3076 u32 rxcfg;
3077#endif
3078 cas_mac_reset(cp);
3079
3080 /* setup core arbitration weight register */
3081 writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3082
3083 /* XXX Use pci_dma_burst_advice() */
3084#if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3085 /* set the infinite burst register for chips that don't have
3086 * pci issues.
3087 */
3088 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3089 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3090#endif
3091
3092 writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3093
3094 writel(0x00, cp->regs + REG_MAC_IPG0);
3095 writel(0x08, cp->regs + REG_MAC_IPG1);
3096 writel(0x04, cp->regs + REG_MAC_IPG2);
3097
3098 /* change later for 802.3z */
3099 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3100
3101 /* min frame + FCS */
3102 writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3103
3104 /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3105 * specify the maximum frame size to prevent RX tag errors on
3106 * oversized frames.
3107 */
3108 writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3109 CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3110 (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3111 cp->regs + REG_MAC_FRAMESIZE_MAX);
3112
3113 /* NOTE: crc_size is used as a surrogate for half-duplex.
3114 * workaround saturn half-duplex issue by increasing preamble
3115 * size to 65 bytes.
3116 */
3117 if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3118 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3119 else
3120 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3121 writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3122 writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3123 writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3124
3125 writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3126
3127 writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3128 writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3129 writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3130 writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3131 writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3132
3133 /* setup mac address in perfect filter array */
3134 for (i = 0; i < 45; i++)
3135 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3136
3137 writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3138 writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3139 writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3140
3141 writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3142 writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3143 writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3144
3145#ifndef CONFIG_CASSINI_MULTICAST_REG_WRITE
3146 cp->mac_rx_cfg = cas_setup_multicast(cp);
3147#else
3148 /* WTZ: Do what Adrian did in cas_set_multicast. Doing
3149 * a writel does not seem to be necessary because Cassini
3150 * seems to preserve the configuration when we do the reset.
3151 * If the chip is in trouble, though, it is not clear if we
3152 * can really count on this behavior. cas_set_multicast uses
3153 * spin_lock_irqsave, but we are called only in cas_init_hw and
3154 * cas_init_hw is protected by cas_lock_all, which calls
3155 * spin_lock_irq (so it doesn't need to save the flags, and
3156 * we should be OK for the writel, as that is the only
3157 * difference).
3158 */
3159 cp->mac_rx_cfg = rxcfg = cas_setup_multicast(cp);
3160 writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
3161#endif
3162 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3163 cas_clear_mac_err(cp);
3164 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3165
3166 /* Setup MAC interrupts. We want to get all of the interesting
3167 * counter expiration events, but we do not want to hear about
3168 * normal rx/tx as the DMA engine tells us that.
3169 */
3170 writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3171 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3172
3173 /* Don't enable even the PAUSE interrupts for now, we
3174 * make no use of those events other than to record them.
3175 */
3176 writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3177}
3178
3179/* Must be invoked under cp->lock. */
3180static void cas_init_pause_thresholds(struct cas *cp)
3181{
3182 /* Calculate pause thresholds. Setting the OFF threshold to the
3183 * full RX fifo size effectively disables PAUSE generation
3184 */
3185 if (cp->rx_fifo_size <= (2 * 1024)) {
3186 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3187 } else {
3188 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3189 if (max_frame * 3 > cp->rx_fifo_size) {
3190 cp->rx_pause_off = 7104;
3191 cp->rx_pause_on = 960;
3192 } else {
3193 int off = (cp->rx_fifo_size - (max_frame * 2));
3194 int on = off - max_frame;
3195 cp->rx_pause_off = off;
3196 cp->rx_pause_on = on;
3197 }
3198 }
3199}
3200
3201static int cas_vpd_match(const void __iomem *p, const char *str)
3202{
3203 int len = strlen(str) + 1;
3204 int i;
3205
3206 for (i = 0; i < len; i++) {
3207 if (readb(p + i) != str[i])
3208 return 0;
3209 }
3210 return 1;
3211}
3212
3213
3214/* get the mac address by reading the vpd information in the rom.
3215 * also get the phy type and determine if there's an entropy generator.
3216 * NOTE: this is a bit convoluted for the following reasons:
3217 * 1) vpd info has order-dependent mac addresses for multinic cards
3218 * 2) the only way to determine the nic order is to use the slot
3219 * number.
3220 * 3) fiber cards don't have bridges, so their slot numbers don't
3221 * mean anything.
3222 * 4) we don't actually know we have a fiber card until after
3223 * the mac addresses are parsed.
3224 */
3225static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3226 const int offset)
3227{
3228 void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3229 void __iomem *base, *kstart;
3230 int i, len;
3231 int found = 0;
3232#define VPD_FOUND_MAC 0x01
3233#define VPD_FOUND_PHY 0x02
3234
3235 int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3236 int mac_off = 0;
3237
3238 /* give us access to the PROM */
3239 writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3240 cp->regs + REG_BIM_LOCAL_DEV_EN);
3241
3242 /* check for an expansion rom */
3243 if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3244 goto use_random_mac_addr;
3245
3246 /* search for beginning of vpd */
3247 base = NULL;
3248 for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3249 /* check for PCIR */
3250 if ((readb(p + i + 0) == 0x50) &&
3251 (readb(p + i + 1) == 0x43) &&
3252 (readb(p + i + 2) == 0x49) &&
3253 (readb(p + i + 3) == 0x52)) {
3254 base = p + (readb(p + i + 8) |
3255 (readb(p + i + 9) << 8));
3256 break;
3257 }
3258 }
3259
3260 if (!base || (readb(base) != 0x82))
3261 goto use_random_mac_addr;
3262
3263 i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3264 while (i < EXPANSION_ROM_SIZE) {
3265 if (readb(base + i) != 0x90) /* no vpd found */
3266 goto use_random_mac_addr;
3267
3268 /* found a vpd field */
3269 len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3270
3271 /* extract keywords */
3272 kstart = base + i + 3;
3273 p = kstart;
3274 while ((p - kstart) < len) {
3275 int klen = readb(p + 2);
3276 int j;
3277 char type;
3278
3279 p += 3;
3280
3281 /* look for the following things:
3282 * -- correct length == 29
3283 * 3 (type) + 2 (size) +
3284 * 18 (strlen("local-mac-address") + 1) +
3285 * 6 (mac addr)
3286 * -- VPD Instance 'I'
3287 * -- VPD Type Bytes 'B'
3288 * -- VPD data length == 6
3289 * -- property string == local-mac-address
3290 *
3291 * -- correct length == 24
3292 * 3 (type) + 2 (size) +
3293 * 12 (strlen("entropy-dev") + 1) +
3294 * 7 (strlen("vms110") + 1)
3295 * -- VPD Instance 'I'
3296 * -- VPD Type String 'B'
3297 * -- VPD data length == 7
3298 * -- property string == entropy-dev
3299 *
3300 * -- correct length == 18
3301 * 3 (type) + 2 (size) +
3302 * 9 (strlen("phy-type") + 1) +
3303 * 4 (strlen("pcs") + 1)
3304 * -- VPD Instance 'I'
3305 * -- VPD Type String 'S'
3306 * -- VPD data length == 4
3307 * -- property string == phy-type
3308 *
3309 * -- correct length == 23
3310 * 3 (type) + 2 (size) +
3311 * 14 (strlen("phy-interface") + 1) +
3312 * 4 (strlen("pcs") + 1)
3313 * -- VPD Instance 'I'
3314 * -- VPD Type String 'S'
3315 * -- VPD data length == 4
3316 * -- property string == phy-interface
3317 */
3318 if (readb(p) != 'I')
3319 goto next;
3320
3321 /* finally, check string and length */
3322 type = readb(p + 3);
3323 if (type == 'B') {
3324 if ((klen == 29) && readb(p + 4) == 6 &&
3325 cas_vpd_match(p + 5,
3326 "local-mac-address")) {
3327 if (mac_off++ > offset)
3328 goto next;
3329
3330 /* set mac address */
3331 for (j = 0; j < 6; j++)
3332 dev_addr[j] =
3333 readb(p + 23 + j);
3334 goto found_mac;
3335 }
3336 }
3337
3338 if (type != 'S')
3339 goto next;
3340
3341#ifdef USE_ENTROPY_DEV
3342 if ((klen == 24) &&
3343 cas_vpd_match(p + 5, "entropy-dev") &&
3344 cas_vpd_match(p + 17, "vms110")) {
3345 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3346 goto next;
3347 }
3348#endif
3349
3350 if (found & VPD_FOUND_PHY)
3351 goto next;
3352
3353 if ((klen == 18) && readb(p + 4) == 4 &&
3354 cas_vpd_match(p + 5, "phy-type")) {
3355 if (cas_vpd_match(p + 14, "pcs")) {
3356 phy_type = CAS_PHY_SERDES;
3357 goto found_phy;
3358 }
3359 }
3360
3361 if ((klen == 23) && readb(p + 4) == 4 &&
3362 cas_vpd_match(p + 5, "phy-interface")) {
3363 if (cas_vpd_match(p + 19, "pcs")) {
3364 phy_type = CAS_PHY_SERDES;
3365 goto found_phy;
3366 }
3367 }
3368found_mac:
3369 found |= VPD_FOUND_MAC;
3370 goto next;
3371
3372found_phy:
3373 found |= VPD_FOUND_PHY;
3374
3375next:
3376 p += klen;
3377 }
3378 i += len + 3;
3379 }
3380
3381use_random_mac_addr:
3382 if (found & VPD_FOUND_MAC)
3383 goto done;
3384
3385 /* Sun MAC prefix then 3 random bytes. */
3386 printk(PFX "MAC address not found in ROM VPD\n");
3387 dev_addr[0] = 0x08;
3388 dev_addr[1] = 0x00;
3389 dev_addr[2] = 0x20;
3390 get_random_bytes(dev_addr + 3, 3);
3391
3392done:
3393 writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3394 return phy_type;
3395}
3396
3397/* check pci invariants */
3398static void cas_check_pci_invariants(struct cas *cp)
3399{
3400 struct pci_dev *pdev = cp->pdev;
3401 u8 rev;
3402
3403 cp->cas_flags = 0;
3404 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
3405 if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3406 (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3407 if (rev >= CAS_ID_REVPLUS)
3408 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3409 if (rev < CAS_ID_REVPLUS02u)
3410 cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3411
3412 /* Original Cassini supports HW CSUM, but it's not
3413 * enabled by default as it can trigger TX hangs.
3414 */
3415 if (rev < CAS_ID_REV2)
3416 cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3417 } else {
3418 /* Only sun has original cassini chips. */
3419 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3420
3421 /* We use a flag because the same phy might be externally
3422 * connected.
3423 */
3424 if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3425 (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3426 cp->cas_flags |= CAS_FLAG_SATURN;
3427 }
3428}
3429
3430
3431static int cas_check_invariants(struct cas *cp)
3432{
3433 struct pci_dev *pdev = cp->pdev;
3434 u32 cfg;
3435 int i;
3436
3437 /* get page size for rx buffers. */
3438 cp->page_order = 0;
3439#ifdef USE_PAGE_ORDER
3440 if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3441 /* see if we can allocate larger pages */
3442 struct page *page = alloc_pages(GFP_ATOMIC,
3443 CAS_JUMBO_PAGE_SHIFT -
3444 PAGE_SHIFT);
3445 if (page) {
3446 __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3447 cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3448 } else {
3449 printk(PFX "MTU limited to %d bytes\n", CAS_MAX_MTU);
3450 }
3451 }
3452#endif
3453 cp->page_size = (PAGE_SIZE << cp->page_order);
3454
3455 /* Fetch the FIFO configurations. */
3456 cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3457 cp->rx_fifo_size = RX_FIFO_SIZE;
3458
3459 /* finish phy determination. MDIO1 takes precedence over MDIO0 if
3460 * they're both connected.
3461 */
3462 cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
3463 PCI_SLOT(pdev->devfn));
3464 if (cp->phy_type & CAS_PHY_SERDES) {
3465 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3466 return 0; /* no more checking needed */
3467 }
3468
3469 /* MII */
3470 cfg = readl(cp->regs + REG_MIF_CFG);
3471 if (cfg & MIF_CFG_MDIO_1) {
3472 cp->phy_type = CAS_PHY_MII_MDIO1;
3473 } else if (cfg & MIF_CFG_MDIO_0) {
3474 cp->phy_type = CAS_PHY_MII_MDIO0;
3475 }
3476
3477 cas_mif_poll(cp, 0);
3478 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3479
3480 for (i = 0; i < 32; i++) {
3481 u32 phy_id;
3482 int j;
3483
3484 for (j = 0; j < 3; j++) {
3485 cp->phy_addr = i;
3486 phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3487 phy_id |= cas_phy_read(cp, MII_PHYSID2);
3488 if (phy_id && (phy_id != 0xFFFFFFFF)) {
3489 cp->phy_id = phy_id;
3490 goto done;
3491 }
3492 }
3493 }
3494 printk(KERN_ERR PFX "MII phy did not respond [%08x]\n",
3495 readl(cp->regs + REG_MIF_STATE_MACHINE));
3496 return -1;
3497
3498done:
3499 /* see if we can do gigabit */
3500 cfg = cas_phy_read(cp, MII_BMSR);
3501 if ((cfg & CAS_BMSR_1000_EXTEND) &&
3502 cas_phy_read(cp, CAS_MII_1000_EXTEND))
3503 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3504 return 0;
3505}
3506
3507/* Must be invoked under cp->lock. */
3508static inline void cas_start_dma(struct cas *cp)
3509{
3510 int i;
3511 u32 val;
3512 int txfailed = 0;
3513
3514 /* enable dma */
3515 val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3516 writel(val, cp->regs + REG_TX_CFG);
3517 val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3518 writel(val, cp->regs + REG_RX_CFG);
3519
3520 /* enable the mac */
3521 val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3522 writel(val, cp->regs + REG_MAC_TX_CFG);
3523 val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3524 writel(val, cp->regs + REG_MAC_RX_CFG);
3525
3526 i = STOP_TRIES;
3527 while (i-- > 0) {
3528 val = readl(cp->regs + REG_MAC_TX_CFG);
3529 if ((val & MAC_TX_CFG_EN))
3530 break;
3531 udelay(10);
3532 }
3533 if (i < 0) txfailed = 1;
3534 i = STOP_TRIES;
3535 while (i-- > 0) {
3536 val = readl(cp->regs + REG_MAC_RX_CFG);
3537 if ((val & MAC_RX_CFG_EN)) {
3538 if (txfailed) {
3539 printk(KERN_ERR
3540 "%s: enabling mac failed [tx:%08x:%08x].\n",
3541 cp->dev->name,
3542 readl(cp->regs + REG_MIF_STATE_MACHINE),
3543 readl(cp->regs + REG_MAC_STATE_MACHINE));
3544 }
3545 goto enable_rx_done;
3546 }
3547 udelay(10);
3548 }
3549 printk(KERN_ERR "%s: enabling mac failed [%s:%08x:%08x].\n",
3550 cp->dev->name,
3551 (txfailed? "tx,rx":"rx"),
3552 readl(cp->regs + REG_MIF_STATE_MACHINE),
3553 readl(cp->regs + REG_MAC_STATE_MACHINE));
3554
3555enable_rx_done:
3556 cas_unmask_intr(cp); /* enable interrupts */
3557 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3558 writel(0, cp->regs + REG_RX_COMP_TAIL);
3559
3560 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3561 if (N_RX_DESC_RINGS > 1)
3562 writel(RX_DESC_RINGN_SIZE(1) - 4,
3563 cp->regs + REG_PLUS_RX_KICK1);
3564
3565 for (i = 1; i < N_RX_COMP_RINGS; i++)
3566 writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
3567 }
3568}
3569
3570/* Must be invoked under cp->lock. */
3571static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3572 int *pause)
3573{
3574 u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3575 *fd = (val & PCS_MII_LPA_FD) ? 1 : 0;
3576 *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3577 if (val & PCS_MII_LPA_ASYM_PAUSE)
3578 *pause |= 0x10;
3579 *spd = 1000;
3580}
3581
3582/* Must be invoked under cp->lock. */
3583static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3584 int *pause)
3585{
3586 u32 val;
3587
3588 *fd = 0;
3589 *spd = 10;
3590 *pause = 0;
3591
3592 /* use GMII registers */
3593 val = cas_phy_read(cp, MII_LPA);
3594 if (val & CAS_LPA_PAUSE)
3595 *pause = 0x01;
3596
3597 if (val & CAS_LPA_ASYM_PAUSE)
3598 *pause |= 0x10;
3599
3600 if (val & LPA_DUPLEX)
3601 *fd = 1;
3602 if (val & LPA_100)
3603 *spd = 100;
3604
3605 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3606 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3607 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3608 *spd = 1000;
3609 if (val & CAS_LPA_1000FULL)
3610 *fd = 1;
3611 }
3612}
3613
3614/* A link-up condition has occurred, initialize and enable the
3615 * rest of the chip.
3616 *
3617 * Must be invoked under cp->lock.
3618 */
3619static void cas_set_link_modes(struct cas *cp)
3620{
3621 u32 val;
3622 int full_duplex, speed, pause;
3623
3624 full_duplex = 0;
3625 speed = 10;
3626 pause = 0;
3627
3628 if (CAS_PHY_MII(cp->phy_type)) {
3629 cas_mif_poll(cp, 0);
3630 val = cas_phy_read(cp, MII_BMCR);
3631 if (val & BMCR_ANENABLE) {
3632 cas_read_mii_link_mode(cp, &full_duplex, &speed,
3633 &pause);
3634 } else {
3635 if (val & BMCR_FULLDPLX)
3636 full_duplex = 1;
3637
3638 if (val & BMCR_SPEED100)
3639 speed = 100;
3640 else if (val & CAS_BMCR_SPEED1000)
3641 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3642 1000 : 100;
3643 }
3644 cas_mif_poll(cp, 1);
3645
3646 } else {
3647 val = readl(cp->regs + REG_PCS_MII_CTRL);
3648 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3649 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3650 if (val & PCS_MII_CTRL_DUPLEX)
3651 full_duplex = 1;
3652 }
3653 }
3654
3655 if (netif_msg_link(cp))
3656 printk(KERN_INFO "%s: Link up at %d Mbps, %s-duplex.\n",
3657 cp->dev->name, speed, (full_duplex ? "full" : "half"));
3658
3659 val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3660 if (CAS_PHY_MII(cp->phy_type)) {
3661 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3662 if (!full_duplex)
3663 val |= MAC_XIF_DISABLE_ECHO;
3664 }
3665 if (full_duplex)
3666 val |= MAC_XIF_FDPLX_LED;
3667 if (speed == 1000)
3668 val |= MAC_XIF_GMII_MODE;
3669 writel(val, cp->regs + REG_MAC_XIF_CFG);
3670
3671 /* deal with carrier and collision detect. */
3672 val = MAC_TX_CFG_IPG_EN;
3673 if (full_duplex) {
3674 val |= MAC_TX_CFG_IGNORE_CARRIER;
3675 val |= MAC_TX_CFG_IGNORE_COLL;
3676 } else {
3677#ifndef USE_CSMA_CD_PROTO
3678 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3679 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3680#endif
3681 }
3682 /* val now set up for REG_MAC_TX_CFG */
3683
3684 /* If gigabit and half-duplex, enable carrier extension
3685 * mode. increase slot time to 512 bytes as well.
3686 * else, disable it and make sure slot time is 64 bytes.
3687 * also activate checksum bug workaround
3688 */
3689 if ((speed == 1000) && !full_duplex) {
3690 writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3691 cp->regs + REG_MAC_TX_CFG);
3692
3693 val = readl(cp->regs + REG_MAC_RX_CFG);
3694 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
3695 writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3696 cp->regs + REG_MAC_RX_CFG);
3697
3698 writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3699
3700 cp->crc_size = 4;
3701 /* minimum size gigabit frame at half duplex */
3702 cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3703
3704 } else {
3705 writel(val, cp->regs + REG_MAC_TX_CFG);
3706
3707 /* checksum bug workaround. don't strip FCS when in
3708 * half-duplex mode
3709 */
3710 val = readl(cp->regs + REG_MAC_RX_CFG);
3711 if (full_duplex) {
3712 val |= MAC_RX_CFG_STRIP_FCS;
3713 cp->crc_size = 0;
3714 cp->min_frame_size = CAS_MIN_MTU;
3715 } else {
3716 val &= ~MAC_RX_CFG_STRIP_FCS;
3717 cp->crc_size = 4;
3718 cp->min_frame_size = CAS_MIN_FRAME;
3719 }
3720 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3721 cp->regs + REG_MAC_RX_CFG);
3722 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3723 }
3724
3725 if (netif_msg_link(cp)) {
3726 if (pause & 0x01) {
3727 printk(KERN_INFO "%s: Pause is enabled "
3728 "(rxfifo: %d off: %d on: %d)\n",
3729 cp->dev->name,
3730 cp->rx_fifo_size,
3731 cp->rx_pause_off,
3732 cp->rx_pause_on);
3733 } else if (pause & 0x10) {
3734 printk(KERN_INFO "%s: TX pause enabled\n",
3735 cp->dev->name);
3736 } else {
3737 printk(KERN_INFO "%s: Pause is disabled\n",
3738 cp->dev->name);
3739 }
3740 }
3741
3742 val = readl(cp->regs + REG_MAC_CTRL_CFG);
3743 val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3744 if (pause) { /* symmetric or asymmetric pause */
3745 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3746 if (pause & 0x01) { /* symmetric pause */
3747 val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3748 }
3749 }
3750 writel(val, cp->regs + REG_MAC_CTRL_CFG);
3751 cas_start_dma(cp);
3752}
3753
3754/* Must be invoked under cp->lock. */
3755static void cas_init_hw(struct cas *cp, int restart_link)
3756{
3757 if (restart_link)
3758 cas_phy_init(cp);
3759
3760 cas_init_pause_thresholds(cp);
3761 cas_init_mac(cp);
3762 cas_init_dma(cp);
3763
3764 if (restart_link) {
3765 /* Default aneg parameters */
3766 cp->timer_ticks = 0;
3767 cas_begin_auto_negotiation(cp, NULL);
3768 } else if (cp->lstate == link_up) {
3769 cas_set_link_modes(cp);
3770 netif_carrier_on(cp->dev);
3771 }
3772}
3773
3774/* Must be invoked under cp->lock. on earlier cassini boards,
3775 * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
3776 * let it settle out, and then restore pci state.
3777 */
3778static void cas_hard_reset(struct cas *cp)
3779{
3780 writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3781 udelay(20);
3782 pci_restore_state(cp->pdev);
3783}
3784
3785
3786static void cas_global_reset(struct cas *cp, int blkflag)
3787{
3788 int limit;
3789
3790 /* issue a global reset. don't use RSTOUT. */
3791 if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3792 /* For PCS, when the blkflag is set, we should set the
3793 * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
3794 * the last autonegotiation from being cleared. We'll
3795 * need some special handling if the chip is set into a
3796 * loopback mode.
3797 */
3798 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
3799 cp->regs + REG_SW_RESET);
3800 } else {
3801 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3802 }
3803
3804 /* need to wait at least 3ms before polling register */
3805 mdelay(3);
3806
3807 limit = STOP_TRIES;
3808 while (limit-- > 0) {
3809 u32 val = readl(cp->regs + REG_SW_RESET);
3810 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3811 goto done;
3812 udelay(10);
3813 }
3814 printk(KERN_ERR "%s: sw reset failed.\n", cp->dev->name);
3815
3816done:
3817 /* enable various BIM interrupts */
3818 writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
3819 BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3820
3821 /* clear out pci error status mask for handled errors.
3822 * we don't deal with DMA counter overflows as they happen
3823 * all the time.
3824 */
3825 writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
3826 PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
3827 PCI_ERR_BIM_DMA_READ), cp->regs +
3828 REG_PCI_ERR_STATUS_MASK);
3829
3830 /* set up for MII by default to address mac rx reset timeout
3831 * issue
3832 */
3833 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3834}
3835
3836static void cas_reset(struct cas *cp, int blkflag)
3837{
3838 u32 val;
3839
3840 cas_mask_intr(cp);
3841 cas_global_reset(cp, blkflag);
3842 cas_mac_reset(cp);
3843 cas_entropy_reset(cp);
3844
3845 /* disable dma engines. */
3846 val = readl(cp->regs + REG_TX_CFG);
3847 val &= ~TX_CFG_DMA_EN;
3848 writel(val, cp->regs + REG_TX_CFG);
3849
3850 val = readl(cp->regs + REG_RX_CFG);
3851 val &= ~RX_CFG_DMA_EN;
3852 writel(val, cp->regs + REG_RX_CFG);
3853
3854 /* program header parser */
3855 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3856 (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
3857 cas_load_firmware(cp, CAS_HP_FIRMWARE);
3858 } else {
3859 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3860 }
3861
3862 /* clear out error registers */
3863 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3864 cas_clear_mac_err(cp);
3865 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3866}
3867
3868/* Shut down the chip, must be called with pm_sem held. */
3869static void cas_shutdown(struct cas *cp)
3870{
3871 unsigned long flags;
3872
3873 /* Make us not-running to avoid timers respawning */
3874 cp->hw_running = 0;
3875
3876 del_timer_sync(&cp->link_timer);
3877
3878 /* Stop the reset task */
3879#if 0
3880 while (atomic_read(&cp->reset_task_pending_mtu) ||
3881 atomic_read(&cp->reset_task_pending_spare) ||
3882 atomic_read(&cp->reset_task_pending_all))
3883 schedule();
3884
3885#else
3886 while (atomic_read(&cp->reset_task_pending))
3887 schedule();
3888#endif
3889 /* Actually stop the chip */
3890 cas_lock_all_save(cp, flags);
3891 cas_reset(cp, 0);
3892 if (cp->cas_flags & CAS_FLAG_SATURN)
3893 cas_phy_powerdown(cp);
3894 cas_unlock_all_restore(cp, flags);
3895}
3896
3897static int cas_change_mtu(struct net_device *dev, int new_mtu)
3898{
3899 struct cas *cp = netdev_priv(dev);
3900
3901 if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU)
3902 return -EINVAL;
3903
3904 dev->mtu = new_mtu;
3905 if (!netif_running(dev) || !netif_device_present(dev))
3906 return 0;
3907
3908 /* let the reset task handle it */
3909#if 1
3910 atomic_inc(&cp->reset_task_pending);
3911 if ((cp->phy_type & CAS_PHY_SERDES)) {
3912 atomic_inc(&cp->reset_task_pending_all);
3913 } else {
3914 atomic_inc(&cp->reset_task_pending_mtu);
3915 }
3916 schedule_work(&cp->reset_task);
3917#else
3918 atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
3919 CAS_RESET_ALL : CAS_RESET_MTU);
3920 printk(KERN_ERR "reset called in cas_change_mtu\n");
3921 schedule_work(&cp->reset_task);
3922#endif
3923
3924 flush_scheduled_work();
3925 return 0;
3926}
3927
3928static void cas_clean_txd(struct cas *cp, int ring)
3929{
3930 struct cas_tx_desc *txd = cp->init_txds[ring];
3931 struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3932 u64 daddr, dlen;
3933 int i, size;
3934
3935 size = TX_DESC_RINGN_SIZE(ring);
3936 for (i = 0; i < size; i++) {
3937 int frag;
3938
3939 if (skbs[i] == NULL)
3940 continue;
3941
3942 skb = skbs[i];
3943 skbs[i] = NULL;
3944
3945 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
3946 int ent = i & (size - 1);
3947
3948 /* first buffer is never a tiny buffer and so
3949 * needs to be unmapped.
3950 */
3951 daddr = le64_to_cpu(txd[ent].buffer);
3952 dlen = CAS_VAL(TX_DESC_BUFLEN,
3953 le64_to_cpu(txd[ent].control));
3954 pci_unmap_page(cp->pdev, daddr, dlen,
3955 PCI_DMA_TODEVICE);
3956
3957 if (frag != skb_shinfo(skb)->nr_frags) {
3958 i++;
3959
3960 /* next buffer might by a tiny buffer.
3961 * skip past it.
3962 */
3963 ent = i & (size - 1);
3964 if (cp->tx_tiny_use[ring][ent].used)
3965 i++;
3966 }
3967 }
3968 dev_kfree_skb_any(skb);
3969 }
3970
3971 /* zero out tiny buf usage */
3972 memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
3973}
3974
3975/* freed on close */
3976static inline void cas_free_rx_desc(struct cas *cp, int ring)
3977{
3978 cas_page_t **page = cp->rx_pages[ring];
3979 int i, size;
3980
3981 size = RX_DESC_RINGN_SIZE(ring);
3982 for (i = 0; i < size; i++) {
3983 if (page[i]) {
3984 cas_page_free(cp, page[i]);
3985 page[i] = NULL;
3986 }
3987 }
3988}
3989
3990static void cas_free_rxds(struct cas *cp)
3991{
3992 int i;
3993
3994 for (i = 0; i < N_RX_DESC_RINGS; i++)
3995 cas_free_rx_desc(cp, i);
3996}
3997
3998/* Must be invoked under cp->lock. */
3999static void cas_clean_rings(struct cas *cp)
4000{
4001 int i;
4002
4003 /* need to clean all tx rings */
4004 memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
4005 memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
4006 for (i = 0; i < N_TX_RINGS; i++)
4007 cas_clean_txd(cp, i);
4008
4009 /* zero out init block */
4010 memset(cp->init_block, 0, sizeof(struct cas_init_block));
4011 cas_clean_rxds(cp);
4012 cas_clean_rxcs(cp);
4013}
4014
4015/* allocated on open */
4016static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
4017{
4018 cas_page_t **page = cp->rx_pages[ring];
4019 int size, i = 0;
4020
4021 size = RX_DESC_RINGN_SIZE(ring);
4022 for (i = 0; i < size; i++) {
4023 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
4024 return -1;
4025 }
4026 return 0;
4027}
4028
4029static int cas_alloc_rxds(struct cas *cp)
4030{
4031 int i;
4032
4033 for (i = 0; i < N_RX_DESC_RINGS; i++) {
4034 if (cas_alloc_rx_desc(cp, i) < 0) {
4035 cas_free_rxds(cp);
4036 return -1;
4037 }
4038 }
4039 return 0;
4040}
4041
4042static void cas_reset_task(void *data)
4043{
4044 struct cas *cp = (struct cas *) data;
4045#if 0
4046 int pending = atomic_read(&cp->reset_task_pending);
4047#else
4048 int pending_all = atomic_read(&cp->reset_task_pending_all);
4049 int pending_spare = atomic_read(&cp->reset_task_pending_spare);
4050 int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
4051
4052 if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
4053 /* We can have more tasks scheduled than actually
4054 * needed.
4055 */
4056 atomic_dec(&cp->reset_task_pending);
4057 return;
4058 }
4059#endif
4060 /* The link went down, we reset the ring, but keep
4061 * DMA stopped. Use this function for reset
4062 * on error as well.
4063 */
4064 if (cp->hw_running) {
4065 unsigned long flags;
4066
4067 /* Make sure we don't get interrupts or tx packets */
4068 netif_device_detach(cp->dev);
4069 cas_lock_all_save(cp, flags);
4070
4071 if (cp->opened) {
4072 /* We call cas_spare_recover when we call cas_open.
4073 * but we do not initialize the lists cas_spare_recover
4074 * uses until cas_open is called.
4075 */
4076 cas_spare_recover(cp, GFP_ATOMIC);
4077 }
4078#if 1
4079 /* test => only pending_spare set */
4080 if (!pending_all && !pending_mtu)
4081 goto done;
4082#else
4083 if (pending == CAS_RESET_SPARE)
4084 goto done;
4085#endif
4086 /* when pending == CAS_RESET_ALL, the following
4087 * call to cas_init_hw will restart auto negotiation.
4088 * Setting the second argument of cas_reset to
4089 * !(pending == CAS_RESET_ALL) will set this argument
4090 * to 1 (avoiding reinitializing the PHY for the normal
4091 * PCS case) when auto negotiation is not restarted.
4092 */
4093#if 1
4094 cas_reset(cp, !(pending_all > 0));
4095 if (cp->opened)
4096 cas_clean_rings(cp);
4097 cas_init_hw(cp, (pending_all > 0));
4098#else
4099 cas_reset(cp, !(pending == CAS_RESET_ALL));
4100 if (cp->opened)
4101 cas_clean_rings(cp);
4102 cas_init_hw(cp, pending == CAS_RESET_ALL);
4103#endif
4104
4105done:
4106 cas_unlock_all_restore(cp, flags);
4107 netif_device_attach(cp->dev);
4108 }
4109#if 1
4110 atomic_sub(pending_all, &cp->reset_task_pending_all);
4111 atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4112 atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4113 atomic_dec(&cp->reset_task_pending);
4114#else
4115 atomic_set(&cp->reset_task_pending, 0);
4116#endif
4117}
4118
4119static void cas_link_timer(unsigned long data)
4120{
4121 struct cas *cp = (struct cas *) data;
4122 int mask, pending = 0, reset = 0;
4123 unsigned long flags;
4124
4125 if (link_transition_timeout != 0 &&
4126 cp->link_transition_jiffies_valid &&
4127 ((jiffies - cp->link_transition_jiffies) >
4128 (link_transition_timeout))) {
4129 /* One-second counter so link-down workaround doesn't
4130 * cause resets to occur so fast as to fool the switch
4131 * into thinking the link is down.
4132 */
4133 cp->link_transition_jiffies_valid = 0;
4134 }
4135
4136 if (!cp->hw_running)
4137 return;
4138
4139 spin_lock_irqsave(&cp->lock, flags);
4140 cas_lock_tx(cp);
4141 cas_entropy_gather(cp);
4142
4143 /* If the link task is still pending, we just
4144 * reschedule the link timer
4145 */
4146#if 1
4147 if (atomic_read(&cp->reset_task_pending_all) ||
4148 atomic_read(&cp->reset_task_pending_spare) ||
4149 atomic_read(&cp->reset_task_pending_mtu))
4150 goto done;
4151#else
4152 if (atomic_read(&cp->reset_task_pending))
4153 goto done;
4154#endif
4155
4156 /* check for rx cleaning */
4157 if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4158 int i, rmask;
4159
4160 for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4161 rmask = CAS_FLAG_RXD_POST(i);
4162 if ((mask & rmask) == 0)
4163 continue;
4164
4165 /* post_rxds will do a mod_timer */
4166 if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4167 pending = 1;
4168 continue;
4169 }
4170 cp->cas_flags &= ~rmask;
4171 }
4172 }
4173
4174 if (CAS_PHY_MII(cp->phy_type)) {
4175 u16 bmsr;
4176 cas_mif_poll(cp, 0);
4177 bmsr = cas_phy_read(cp, MII_BMSR);
4178 /* WTZ: Solaris driver reads this twice, but that
4179 * may be due to the PCS case and the use of a
4180 * common implementation. Read it twice here to be
4181 * safe.
4182 */
4183 bmsr = cas_phy_read(cp, MII_BMSR);
4184 cas_mif_poll(cp, 1);
4185 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
4186 reset = cas_mii_link_check(cp, bmsr);
4187 } else {
4188 reset = cas_pcs_link_check(cp);
4189 }
4190
4191 if (reset)
4192 goto done;
4193
4194 /* check for tx state machine confusion */
4195 if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4196 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4197 u32 wptr, rptr;
4198 int tlm = CAS_VAL(MAC_SM_TLM, val);
4199
4200 if (((tlm == 0x5) || (tlm == 0x3)) &&
4201 (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4202 if (netif_msg_tx_err(cp))
4203 printk(KERN_DEBUG "%s: tx err: "
4204 "MAC_STATE[%08x]\n",
4205 cp->dev->name, val);
4206 reset = 1;
4207 goto done;
4208 }
4209
4210 val = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4211 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4212 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4213 if ((val == 0) && (wptr != rptr)) {
4214 if (netif_msg_tx_err(cp))
4215 printk(KERN_DEBUG "%s: tx err: "
4216 "TX_FIFO[%08x:%08x:%08x]\n",
4217 cp->dev->name, val, wptr, rptr);
4218 reset = 1;
4219 }
4220
4221 if (reset)
4222 cas_hard_reset(cp);
4223 }
4224
4225done:
4226 if (reset) {
4227#if 1
4228 atomic_inc(&cp->reset_task_pending);
4229 atomic_inc(&cp->reset_task_pending_all);
4230 schedule_work(&cp->reset_task);
4231#else
4232 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4233 printk(KERN_ERR "reset called in cas_link_timer\n");
4234 schedule_work(&cp->reset_task);
4235#endif
4236 }
4237
4238 if (!pending)
4239 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4240 cas_unlock_tx(cp);
4241 spin_unlock_irqrestore(&cp->lock, flags);
4242}
4243
4244/* tiny buffers are used to avoid target abort issues with
4245 * older cassini's
4246 */
4247static void cas_tx_tiny_free(struct cas *cp)
4248{
4249 struct pci_dev *pdev = cp->pdev;
4250 int i;
4251
4252 for (i = 0; i < N_TX_RINGS; i++) {
4253 if (!cp->tx_tiny_bufs[i])
4254 continue;
4255
4256 pci_free_consistent(pdev, TX_TINY_BUF_BLOCK,
4257 cp->tx_tiny_bufs[i],
4258 cp->tx_tiny_dvma[i]);
4259 cp->tx_tiny_bufs[i] = NULL;
4260 }
4261}
4262
4263static int cas_tx_tiny_alloc(struct cas *cp)
4264{
4265 struct pci_dev *pdev = cp->pdev;
4266 int i;
4267
4268 for (i = 0; i < N_TX_RINGS; i++) {
4269 cp->tx_tiny_bufs[i] =
4270 pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
4271 &cp->tx_tiny_dvma[i]);
4272 if (!cp->tx_tiny_bufs[i]) {
4273 cas_tx_tiny_free(cp);
4274 return -1;
4275 }
4276 }
4277 return 0;
4278}
4279
4280
4281static int cas_open(struct net_device *dev)
4282{
4283 struct cas *cp = netdev_priv(dev);
4284 int hw_was_up, err;
4285 unsigned long flags;
4286
4287 down(&cp->pm_sem);
4288
4289 hw_was_up = cp->hw_running;
4290
4291 /* The power-management semaphore protects the hw_running
4292 * etc. state so it is safe to do this bit without cp->lock
4293 */
4294 if (!cp->hw_running) {
4295 /* Reset the chip */
4296 cas_lock_all_save(cp, flags);
4297 /* We set the second arg to cas_reset to zero
4298 * because cas_init_hw below will have its second
4299 * argument set to non-zero, which will force
4300 * autonegotiation to start.
4301 */
4302 cas_reset(cp, 0);
4303 cp->hw_running = 1;
4304 cas_unlock_all_restore(cp, flags);
4305 }
4306
4307 if (cas_tx_tiny_alloc(cp) < 0)
4308 return -ENOMEM;
4309
4310 /* alloc rx descriptors */
4311 err = -ENOMEM;
4312 if (cas_alloc_rxds(cp) < 0)
4313 goto err_tx_tiny;
4314
4315 /* allocate spares */
4316 cas_spare_init(cp);
4317 cas_spare_recover(cp, GFP_KERNEL);
4318
4319 /* We can now request the interrupt as we know it's masked
4320 * on the controller. cassini+ has up to 4 interrupts
4321 * that can be used, but you need to do explicit pci interrupt
4322 * mapping to expose them
4323 */
4324 if (request_irq(cp->pdev->irq, cas_interrupt,
4325 SA_SHIRQ, dev->name, (void *) dev)) {
4326 printk(KERN_ERR "%s: failed to request irq !\n",
4327 cp->dev->name);
4328 err = -EAGAIN;
4329 goto err_spare;
4330 }
4331
4332 /* init hw */
4333 cas_lock_all_save(cp, flags);
4334 cas_clean_rings(cp);
4335 cas_init_hw(cp, !hw_was_up);
4336 cp->opened = 1;
4337 cas_unlock_all_restore(cp, flags);
4338
4339 netif_start_queue(dev);
4340 up(&cp->pm_sem);
4341 return 0;
4342
4343err_spare:
4344 cas_spare_free(cp);
4345 cas_free_rxds(cp);
4346err_tx_tiny:
4347 cas_tx_tiny_free(cp);
4348 up(&cp->pm_sem);
4349 return err;
4350}
4351
4352static int cas_close(struct net_device *dev)
4353{
4354 unsigned long flags;
4355 struct cas *cp = netdev_priv(dev);
4356
4357 /* Make sure we don't get distracted by suspend/resume */
4358 down(&cp->pm_sem);
4359
4360 netif_stop_queue(dev);
4361
4362 /* Stop traffic, mark us closed */
4363 cas_lock_all_save(cp, flags);
4364 cp->opened = 0;
4365 cas_reset(cp, 0);
4366 cas_phy_init(cp);
4367 cas_begin_auto_negotiation(cp, NULL);
4368 cas_clean_rings(cp);
4369 cas_unlock_all_restore(cp, flags);
4370
4371 free_irq(cp->pdev->irq, (void *) dev);
4372 cas_spare_free(cp);
4373 cas_free_rxds(cp);
4374 cas_tx_tiny_free(cp);
4375 up(&cp->pm_sem);
4376 return 0;
4377}
4378
4379static struct {
4380 const char name[ETH_GSTRING_LEN];
4381} ethtool_cassini_statnames[] = {
4382 {"collisions"},
4383 {"rx_bytes"},
4384 {"rx_crc_errors"},
4385 {"rx_dropped"},
4386 {"rx_errors"},
4387 {"rx_fifo_errors"},
4388 {"rx_frame_errors"},
4389 {"rx_length_errors"},
4390 {"rx_over_errors"},
4391 {"rx_packets"},
4392 {"tx_aborted_errors"},
4393 {"tx_bytes"},
4394 {"tx_dropped"},
4395 {"tx_errors"},
4396 {"tx_fifo_errors"},
4397 {"tx_packets"}
4398};
4399#define CAS_NUM_STAT_KEYS (sizeof(ethtool_cassini_statnames)/ETH_GSTRING_LEN)
4400
4401static struct {
4402 const int offsets; /* neg. values for 2nd arg to cas_read_phy */
4403} ethtool_register_table[] = {
4404 {-MII_BMSR},
4405 {-MII_BMCR},
4406 {REG_CAWR},
4407 {REG_INF_BURST},
4408 {REG_BIM_CFG},
4409 {REG_RX_CFG},
4410 {REG_HP_CFG},
4411 {REG_MAC_TX_CFG},
4412 {REG_MAC_RX_CFG},
4413 {REG_MAC_CTRL_CFG},
4414 {REG_MAC_XIF_CFG},
4415 {REG_MIF_CFG},
4416 {REG_PCS_CFG},
4417 {REG_SATURN_PCFG},
4418 {REG_PCS_MII_STATUS},
4419 {REG_PCS_STATE_MACHINE},
4420 {REG_MAC_COLL_EXCESS},
4421 {REG_MAC_COLL_LATE}
4422};
4423#define CAS_REG_LEN (sizeof(ethtool_register_table)/sizeof(int))
4424#define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN)
4425
4426static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4427{
4428 u8 *p;
4429 int i;
4430 unsigned long flags;
4431
4432 spin_lock_irqsave(&cp->lock, flags);
4433 for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4434 u16 hval;
4435 u32 val;
4436 if (ethtool_register_table[i].offsets < 0) {
4437 hval = cas_phy_read(cp,
4438 -ethtool_register_table[i].offsets);
4439 val = hval;
4440 } else {
4441 val= readl(cp->regs+ethtool_register_table[i].offsets);
4442 }
4443 memcpy(p, (u8 *)&val, sizeof(u32));
4444 }
4445 spin_unlock_irqrestore(&cp->lock, flags);
4446}
4447
4448static struct net_device_stats *cas_get_stats(struct net_device *dev)
4449{
4450 struct cas *cp = netdev_priv(dev);
4451 struct net_device_stats *stats = cp->net_stats;
4452 unsigned long flags;
4453 int i;
4454 unsigned long tmp;
4455
4456 /* we collate all of the stats into net_stats[N_TX_RING] */
4457 if (!cp->hw_running)
4458 return stats + N_TX_RINGS;
4459
4460 /* collect outstanding stats */
4461 /* WTZ: the Cassini spec gives these as 16 bit counters but
4462 * stored in 32-bit words. Added a mask of 0xffff to be safe,
4463 * in case the chip somehow puts any garbage in the other bits.
4464 * Also, counter usage didn't seem to mach what Adrian did
4465 * in the parts of the code that set these quantities. Made
4466 * that consistent.
4467 */
4468 spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4469 stats[N_TX_RINGS].rx_crc_errors +=
4470 readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4471 stats[N_TX_RINGS].rx_frame_errors +=
4472 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4473 stats[N_TX_RINGS].rx_length_errors +=
4474 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4475#if 1
4476 tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4477 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4478 stats[N_TX_RINGS].tx_aborted_errors += tmp;
4479 stats[N_TX_RINGS].collisions +=
4480 tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4481#else
4482 stats[N_TX_RINGS].tx_aborted_errors +=
4483 readl(cp->regs + REG_MAC_COLL_EXCESS);
4484 stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4485 readl(cp->regs + REG_MAC_COLL_LATE);
4486#endif
4487 cas_clear_mac_err(cp);
4488
4489 /* saved bits that are unique to ring 0 */
4490 spin_lock(&cp->stat_lock[0]);
4491 stats[N_TX_RINGS].collisions += stats[0].collisions;
4492 stats[N_TX_RINGS].rx_over_errors += stats[0].rx_over_errors;
4493 stats[N_TX_RINGS].rx_frame_errors += stats[0].rx_frame_errors;
4494 stats[N_TX_RINGS].rx_fifo_errors += stats[0].rx_fifo_errors;
4495 stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4496 stats[N_TX_RINGS].tx_fifo_errors += stats[0].tx_fifo_errors;
4497 spin_unlock(&cp->stat_lock[0]);
4498
4499 for (i = 0; i < N_TX_RINGS; i++) {
4500 spin_lock(&cp->stat_lock[i]);
4501 stats[N_TX_RINGS].rx_length_errors +=
4502 stats[i].rx_length_errors;
4503 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4504 stats[N_TX_RINGS].rx_packets += stats[i].rx_packets;
4505 stats[N_TX_RINGS].tx_packets += stats[i].tx_packets;
4506 stats[N_TX_RINGS].rx_bytes += stats[i].rx_bytes;
4507 stats[N_TX_RINGS].tx_bytes += stats[i].tx_bytes;
4508 stats[N_TX_RINGS].rx_errors += stats[i].rx_errors;
4509 stats[N_TX_RINGS].tx_errors += stats[i].tx_errors;
4510 stats[N_TX_RINGS].rx_dropped += stats[i].rx_dropped;
4511 stats[N_TX_RINGS].tx_dropped += stats[i].tx_dropped;
4512 memset(stats + i, 0, sizeof(struct net_device_stats));
4513 spin_unlock(&cp->stat_lock[i]);
4514 }
4515 spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4516 return stats + N_TX_RINGS;
4517}
4518
4519
4520static void cas_set_multicast(struct net_device *dev)
4521{
4522 struct cas *cp = netdev_priv(dev);
4523 u32 rxcfg, rxcfg_new;
4524 unsigned long flags;
4525 int limit = STOP_TRIES;
4526
4527 if (!cp->hw_running)
4528 return;
4529
4530 spin_lock_irqsave(&cp->lock, flags);
4531 rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4532
4533 /* disable RX MAC and wait for completion */
4534 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4535 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4536 if (!limit--)
4537 break;
4538 udelay(10);
4539 }
4540
4541 /* disable hash filter and wait for completion */
4542 limit = STOP_TRIES;
4543 rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4544 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4545 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4546 if (!limit--)
4547 break;
4548 udelay(10);
4549 }
4550
4551 /* program hash filters */
4552 cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4553 rxcfg |= rxcfg_new;
4554 writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4555 spin_unlock_irqrestore(&cp->lock, flags);
4556}
4557
4558static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4559{
4560 struct cas *cp = netdev_priv(dev);
4561 strncpy(info->driver, DRV_MODULE_NAME, ETHTOOL_BUSINFO_LEN);
4562 strncpy(info->version, DRV_MODULE_VERSION, ETHTOOL_BUSINFO_LEN);
4563 info->fw_version[0] = '\0';
4564 strncpy(info->bus_info, pci_name(cp->pdev), ETHTOOL_BUSINFO_LEN);
4565 info->regdump_len = cp->casreg_len < CAS_MAX_REGS ?
4566 cp->casreg_len : CAS_MAX_REGS;
4567 info->n_stats = CAS_NUM_STAT_KEYS;
4568}
4569
4570static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4571{
4572 struct cas *cp = netdev_priv(dev);
4573 u16 bmcr;
4574 int full_duplex, speed, pause;
4575 unsigned long flags;
4576 enum link_state linkstate = link_up;
4577
4578 cmd->advertising = 0;
4579 cmd->supported = SUPPORTED_Autoneg;
4580 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4581 cmd->supported |= SUPPORTED_1000baseT_Full;
4582 cmd->advertising |= ADVERTISED_1000baseT_Full;
4583 }
4584
4585 /* Record PHY settings if HW is on. */
4586 spin_lock_irqsave(&cp->lock, flags);
4587 bmcr = 0;
4588 linkstate = cp->lstate;
4589 if (CAS_PHY_MII(cp->phy_type)) {
4590 cmd->port = PORT_MII;
4591 cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ?
4592 XCVR_INTERNAL : XCVR_EXTERNAL;
4593 cmd->phy_address = cp->phy_addr;
4594 cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII |
4595 ADVERTISED_10baseT_Half |
4596 ADVERTISED_10baseT_Full |
4597 ADVERTISED_100baseT_Half |
4598 ADVERTISED_100baseT_Full;
4599
4600 cmd->supported |=
4601 (SUPPORTED_10baseT_Half |
4602 SUPPORTED_10baseT_Full |
4603 SUPPORTED_100baseT_Half |
4604 SUPPORTED_100baseT_Full |
4605 SUPPORTED_TP | SUPPORTED_MII);
4606
4607 if (cp->hw_running) {
4608 cas_mif_poll(cp, 0);
4609 bmcr = cas_phy_read(cp, MII_BMCR);
4610 cas_read_mii_link_mode(cp, &full_duplex,
4611 &speed, &pause);
4612 cas_mif_poll(cp, 1);
4613 }
4614
4615 } else {
4616 cmd->port = PORT_FIBRE;
4617 cmd->transceiver = XCVR_INTERNAL;
4618 cmd->phy_address = 0;
4619 cmd->supported |= SUPPORTED_FIBRE;
4620 cmd->advertising |= ADVERTISED_FIBRE;
4621
4622 if (cp->hw_running) {
4623 /* pcs uses the same bits as mii */
4624 bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4625 cas_read_pcs_link_mode(cp, &full_duplex,
4626 &speed, &pause);
4627 }
4628 }
4629 spin_unlock_irqrestore(&cp->lock, flags);
4630
4631 if (bmcr & BMCR_ANENABLE) {
4632 cmd->advertising |= ADVERTISED_Autoneg;
4633 cmd->autoneg = AUTONEG_ENABLE;
4634 cmd->speed = ((speed == 10) ?
4635 SPEED_10 :
4636 ((speed == 1000) ?
4637 SPEED_1000 : SPEED_100));
4638 cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4639 } else {
4640 cmd->autoneg = AUTONEG_DISABLE;
4641 cmd->speed =
4642 (bmcr & CAS_BMCR_SPEED1000) ?
4643 SPEED_1000 :
4644 ((bmcr & BMCR_SPEED100) ? SPEED_100:
4645 SPEED_10);
4646 cmd->duplex =
4647 (bmcr & BMCR_FULLDPLX) ?
4648 DUPLEX_FULL : DUPLEX_HALF;
4649 }
4650 if (linkstate != link_up) {
4651 /* Force these to "unknown" if the link is not up and
4652 * autonogotiation in enabled. We can set the link
4653 * speed to 0, but not cmd->duplex,
4654 * because its legal values are 0 and 1. Ethtool will
4655 * print the value reported in parentheses after the
4656 * word "Unknown" for unrecognized values.
4657 *
4658 * If in forced mode, we report the speed and duplex
4659 * settings that we configured.
4660 */
4661 if (cp->link_cntl & BMCR_ANENABLE) {
4662 cmd->speed = 0;
4663 cmd->duplex = 0xff;
4664 } else {
4665 cmd->speed = SPEED_10;
4666 if (cp->link_cntl & BMCR_SPEED100) {
4667 cmd->speed = SPEED_100;
4668 } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4669 cmd->speed = SPEED_1000;
4670 }
4671 cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)?
4672 DUPLEX_FULL : DUPLEX_HALF;
4673 }
4674 }
4675 return 0;
4676}
4677
4678static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4679{
4680 struct cas *cp = netdev_priv(dev);
4681 unsigned long flags;
4682
4683 /* Verify the settings we care about. */
4684 if (cmd->autoneg != AUTONEG_ENABLE &&
4685 cmd->autoneg != AUTONEG_DISABLE)
4686 return -EINVAL;
4687
4688 if (cmd->autoneg == AUTONEG_DISABLE &&
4689 ((cmd->speed != SPEED_1000 &&
4690 cmd->speed != SPEED_100 &&
4691 cmd->speed != SPEED_10) ||
4692 (cmd->duplex != DUPLEX_HALF &&
4693 cmd->duplex != DUPLEX_FULL)))
4694 return -EINVAL;
4695
4696 /* Apply settings and restart link process. */
4697 spin_lock_irqsave(&cp->lock, flags);
4698 cas_begin_auto_negotiation(cp, cmd);
4699 spin_unlock_irqrestore(&cp->lock, flags);
4700 return 0;
4701}
4702
4703static int cas_nway_reset(struct net_device *dev)
4704{
4705 struct cas *cp = netdev_priv(dev);
4706 unsigned long flags;
4707
4708 if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4709 return -EINVAL;
4710
4711 /* Restart link process. */
4712 spin_lock_irqsave(&cp->lock, flags);
4713 cas_begin_auto_negotiation(cp, NULL);
4714 spin_unlock_irqrestore(&cp->lock, flags);
4715
4716 return 0;
4717}
4718
4719static u32 cas_get_link(struct net_device *dev)
4720{
4721 struct cas *cp = netdev_priv(dev);
4722 return cp->lstate == link_up;
4723}
4724
4725static u32 cas_get_msglevel(struct net_device *dev)
4726{
4727 struct cas *cp = netdev_priv(dev);
4728 return cp->msg_enable;
4729}
4730
4731static void cas_set_msglevel(struct net_device *dev, u32 value)
4732{
4733 struct cas *cp = netdev_priv(dev);
4734 cp->msg_enable = value;
4735}
4736
4737static int cas_get_regs_len(struct net_device *dev)
4738{
4739 struct cas *cp = netdev_priv(dev);
4740 return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
4741}
4742
4743static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4744 void *p)
4745{
4746 struct cas *cp = netdev_priv(dev);
4747 regs->version = 0;
4748 /* cas_read_regs handles locks (cp->lock). */
4749 cas_read_regs(cp, p, regs->len / sizeof(u32));
4750}
4751
4752static int cas_get_stats_count(struct net_device *dev)
4753{
4754 return CAS_NUM_STAT_KEYS;
4755}
4756
4757static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4758{
4759 memcpy(data, &ethtool_cassini_statnames,
4760 CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4761}
4762
4763static void cas_get_ethtool_stats(struct net_device *dev,
4764 struct ethtool_stats *estats, u64 *data)
4765{
4766 struct cas *cp = netdev_priv(dev);
4767 struct net_device_stats *stats = cas_get_stats(cp->dev);
4768 int i = 0;
4769 data[i++] = stats->collisions;
4770 data[i++] = stats->rx_bytes;
4771 data[i++] = stats->rx_crc_errors;
4772 data[i++] = stats->rx_dropped;
4773 data[i++] = stats->rx_errors;
4774 data[i++] = stats->rx_fifo_errors;
4775 data[i++] = stats->rx_frame_errors;
4776 data[i++] = stats->rx_length_errors;
4777 data[i++] = stats->rx_over_errors;
4778 data[i++] = stats->rx_packets;
4779 data[i++] = stats->tx_aborted_errors;
4780 data[i++] = stats->tx_bytes;
4781 data[i++] = stats->tx_dropped;
4782 data[i++] = stats->tx_errors;
4783 data[i++] = stats->tx_fifo_errors;
4784 data[i++] = stats->tx_packets;
4785 BUG_ON(i != CAS_NUM_STAT_KEYS);
4786}
4787
4788static struct ethtool_ops cas_ethtool_ops = {
4789 .get_drvinfo = cas_get_drvinfo,
4790 .get_settings = cas_get_settings,
4791 .set_settings = cas_set_settings,
4792 .nway_reset = cas_nway_reset,
4793 .get_link = cas_get_link,
4794 .get_msglevel = cas_get_msglevel,
4795 .set_msglevel = cas_set_msglevel,
4796 .get_regs_len = cas_get_regs_len,
4797 .get_regs = cas_get_regs,
4798 .get_stats_count = cas_get_stats_count,
4799 .get_strings = cas_get_strings,
4800 .get_ethtool_stats = cas_get_ethtool_stats,
4801};
4802
4803static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4804{
4805 struct cas *cp = netdev_priv(dev);
4806 struct mii_ioctl_data *data = if_mii(ifr);
4807 unsigned long flags;
4808 int rc = -EOPNOTSUPP;
4809
4810 /* Hold the PM semaphore while doing ioctl's or we may collide
4811 * with open/close and power management and oops.
4812 */
4813 down(&cp->pm_sem);
4814 switch (cmd) {
4815 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
4816 data->phy_id = cp->phy_addr;
4817 /* Fallthrough... */
4818
4819 case SIOCGMIIREG: /* Read MII PHY register. */
4820 spin_lock_irqsave(&cp->lock, flags);
4821 cas_mif_poll(cp, 0);
4822 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4823 cas_mif_poll(cp, 1);
4824 spin_unlock_irqrestore(&cp->lock, flags);
4825 rc = 0;
4826 break;
4827
4828 case SIOCSMIIREG: /* Write MII PHY register. */
4829 if (!capable(CAP_NET_ADMIN)) {
4830 rc = -EPERM;
4831 break;
4832 }
4833 spin_lock_irqsave(&cp->lock, flags);
4834 cas_mif_poll(cp, 0);
4835 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4836 cas_mif_poll(cp, 1);
4837 spin_unlock_irqrestore(&cp->lock, flags);
4838 break;
4839 default:
4840 break;
4841 };
4842
4843 up(&cp->pm_sem);
4844 return rc;
4845}
4846
4847static int __devinit cas_init_one(struct pci_dev *pdev,
4848 const struct pci_device_id *ent)
4849{
4850 static int cas_version_printed = 0;
4851 unsigned long casreg_base, casreg_len;
4852 struct net_device *dev;
4853 struct cas *cp;
4854 int i, err, pci_using_dac;
4855 u16 pci_cmd;
4856 u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
4857
4858 if (cas_version_printed++ == 0)
4859 printk(KERN_INFO "%s", version);
4860
4861 err = pci_enable_device(pdev);
4862 if (err) {
4863 printk(KERN_ERR PFX "Cannot enable PCI device, "
4864 "aborting.\n");
4865 return err;
4866 }
4867
4868 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4869 printk(KERN_ERR PFX "Cannot find proper PCI device "
4870 "base address, aborting.\n");
4871 err = -ENODEV;
4872 goto err_out_disable_pdev;
4873 }
4874
4875 dev = alloc_etherdev(sizeof(*cp));
4876 if (!dev) {
4877 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
4878 err = -ENOMEM;
4879 goto err_out_disable_pdev;
4880 }
4881 SET_MODULE_OWNER(dev);
4882 SET_NETDEV_DEV(dev, &pdev->dev);
4883
4884 err = pci_request_regions(pdev, dev->name);
4885 if (err) {
4886 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
4887 "aborting.\n");
4888 goto err_out_free_netdev;
4889 }
4890 pci_set_master(pdev);
4891
4892 /* we must always turn on parity response or else parity
4893 * doesn't get generated properly. disable SERR/PERR as well.
4894 * in addition, we want to turn MWI on.
4895 */
4896 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4897 pci_cmd &= ~PCI_COMMAND_SERR;
4898 pci_cmd |= PCI_COMMAND_PARITY;
4899 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4900 pci_set_mwi(pdev);
4901 /*
4902 * On some architectures, the default cache line size set
4903 * by pci_set_mwi reduces perforamnce. We have to increase
4904 * it for this case. To start, we'll print some configuration
4905 * data.
4906 */
4907#if 1
4908 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
4909 &orig_cacheline_size);
4910 if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
4911 cas_cacheline_size =
4912 (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
4913 CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
4914 if (pci_write_config_byte(pdev,
4915 PCI_CACHE_LINE_SIZE,
4916 cas_cacheline_size)) {
4917 printk(KERN_ERR PFX "Could not set PCI cache "
4918 "line size\n");
4919 goto err_write_cacheline;
4920 }
4921 }
4922#endif
4923
4924
4925 /* Configure DMA attributes. */
4926 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
4927 pci_using_dac = 1;
4928 err = pci_set_consistent_dma_mask(pdev,
4929 DMA_64BIT_MASK);
4930 if (err < 0) {
4931 printk(KERN_ERR PFX "Unable to obtain 64-bit DMA "
4932 "for consistent allocations\n");
4933 goto err_out_free_res;
4934 }
4935
4936 } else {
4937 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4938 if (err) {
4939 printk(KERN_ERR PFX "No usable DMA configuration, "
4940 "aborting.\n");
4941 goto err_out_free_res;
4942 }
4943 pci_using_dac = 0;
4944 }
4945
4946 casreg_base = pci_resource_start(pdev, 0);
4947 casreg_len = pci_resource_len(pdev, 0);
4948
4949 cp = netdev_priv(dev);
4950 cp->pdev = pdev;
4951#if 1
4952 /* A value of 0 indicates we never explicitly set it */
4953 cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
4954#endif
4955 cp->dev = dev;
4956 cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
4957 cassini_debug;
4958
4959 cp->link_transition = LINK_TRANSITION_UNKNOWN;
4960 cp->link_transition_jiffies_valid = 0;
4961
4962 spin_lock_init(&cp->lock);
4963 spin_lock_init(&cp->rx_inuse_lock);
4964 spin_lock_init(&cp->rx_spare_lock);
4965 for (i = 0; i < N_TX_RINGS; i++) {
4966 spin_lock_init(&cp->stat_lock[i]);
4967 spin_lock_init(&cp->tx_lock[i]);
4968 }
4969 spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
4970 init_MUTEX(&cp->pm_sem);
4971
4972 init_timer(&cp->link_timer);
4973 cp->link_timer.function = cas_link_timer;
4974 cp->link_timer.data = (unsigned long) cp;
4975
4976#if 1
4977 /* Just in case the implementation of atomic operations
4978 * change so that an explicit initialization is necessary.
4979 */
4980 atomic_set(&cp->reset_task_pending, 0);
4981 atomic_set(&cp->reset_task_pending_all, 0);
4982 atomic_set(&cp->reset_task_pending_spare, 0);
4983 atomic_set(&cp->reset_task_pending_mtu, 0);
4984#endif
4985 INIT_WORK(&cp->reset_task, cas_reset_task, cp);
4986
4987 /* Default link parameters */
4988 if (link_mode >= 0 && link_mode <= 6)
4989 cp->link_cntl = link_modes[link_mode];
4990 else
4991 cp->link_cntl = BMCR_ANENABLE;
4992 cp->lstate = link_down;
4993 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
4994 netif_carrier_off(cp->dev);
4995 cp->timer_ticks = 0;
4996
4997 /* give us access to cassini registers */
4998 cp->regs = ioremap(casreg_base, casreg_len);
4999 if (cp->regs == 0UL) {
5000 printk(KERN_ERR PFX "Cannot map device registers, "
5001 "aborting.\n");
5002 goto err_out_free_res;
5003 }
5004 cp->casreg_len = casreg_len;
5005
5006 pci_save_state(pdev);
5007 cas_check_pci_invariants(cp);
5008 cas_hard_reset(cp);
5009 cas_reset(cp, 0);
5010 if (cas_check_invariants(cp))
5011 goto err_out_iounmap;
5012
5013 cp->init_block = (struct cas_init_block *)
5014 pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
5015 &cp->block_dvma);
5016 if (!cp->init_block) {
5017 printk(KERN_ERR PFX "Cannot allocate init block, "
5018 "aborting.\n");
5019 goto err_out_iounmap;
5020 }
5021
5022 for (i = 0; i < N_TX_RINGS; i++)
5023 cp->init_txds[i] = cp->init_block->txds[i];
5024
5025 for (i = 0; i < N_RX_DESC_RINGS; i++)
5026 cp->init_rxds[i] = cp->init_block->rxds[i];
5027
5028 for (i = 0; i < N_RX_COMP_RINGS; i++)
5029 cp->init_rxcs[i] = cp->init_block->rxcs[i];
5030
5031 for (i = 0; i < N_RX_FLOWS; i++)
5032 skb_queue_head_init(&cp->rx_flows[i]);
5033
5034 dev->open = cas_open;
5035 dev->stop = cas_close;
5036 dev->hard_start_xmit = cas_start_xmit;
5037 dev->get_stats = cas_get_stats;
5038 dev->set_multicast_list = cas_set_multicast;
5039 dev->do_ioctl = cas_ioctl;
5040 dev->ethtool_ops = &cas_ethtool_ops;
5041 dev->tx_timeout = cas_tx_timeout;
5042 dev->watchdog_timeo = CAS_TX_TIMEOUT;
5043 dev->change_mtu = cas_change_mtu;
5044#ifdef USE_NAPI
5045 dev->poll = cas_poll;
5046 dev->weight = 64;
5047#endif
5048#ifdef CONFIG_NET_POLL_CONTROLLER
5049 dev->poll_controller = cas_netpoll;
5050#endif
5051 dev->irq = pdev->irq;
5052 dev->dma = 0;
5053
5054 /* Cassini features. */
5055 if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5056 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5057
5058 if (pci_using_dac)
5059 dev->features |= NETIF_F_HIGHDMA;
5060
5061 if (register_netdev(dev)) {
5062 printk(KERN_ERR PFX "Cannot register net device, "
5063 "aborting.\n");
5064 goto err_out_free_consistent;
5065 }
5066
5067 i = readl(cp->regs + REG_BIM_CFG);
5068 printk(KERN_INFO "%s: Sun Cassini%s (%sbit/%sMHz PCI/%s) "
5069 "Ethernet[%d] ", dev->name,
5070 (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
5071 (i & BIM_CFG_32BIT) ? "32" : "64",
5072 (i & BIM_CFG_66MHZ) ? "66" : "33",
5073 (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq);
5074
5075 for (i = 0; i < 6; i++)
5076 printk("%2.2x%c", dev->dev_addr[i],
5077 i == 5 ? ' ' : ':');
5078 printk("\n");
5079
5080 pci_set_drvdata(pdev, dev);
5081 cp->hw_running = 1;
5082 cas_entropy_reset(cp);
5083 cas_phy_init(cp);
5084 cas_begin_auto_negotiation(cp, NULL);
5085 return 0;
5086
5087err_out_free_consistent:
5088 pci_free_consistent(pdev, sizeof(struct cas_init_block),
5089 cp->init_block, cp->block_dvma);
5090
5091err_out_iounmap:
5092 down(&cp->pm_sem);
5093 if (cp->hw_running)
5094 cas_shutdown(cp);
5095 up(&cp->pm_sem);
5096
5097 iounmap(cp->regs);
5098
5099
5100err_out_free_res:
5101 pci_release_regions(pdev);
5102
5103err_write_cacheline:
5104 /* Try to restore it in case the error occured after we
5105 * set it.
5106 */
5107 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5108
5109err_out_free_netdev:
5110 free_netdev(dev);
5111
5112err_out_disable_pdev:
5113 pci_disable_device(pdev);
5114 pci_set_drvdata(pdev, NULL);
5115 return -ENODEV;
5116}
5117
5118static void __devexit cas_remove_one(struct pci_dev *pdev)
5119{
5120 struct net_device *dev = pci_get_drvdata(pdev);
5121 struct cas *cp;
5122 if (!dev)
5123 return;
5124
5125 cp = netdev_priv(dev);
5126 unregister_netdev(dev);
5127
5128 down(&cp->pm_sem);
5129 flush_scheduled_work();
5130 if (cp->hw_running)
5131 cas_shutdown(cp);
5132 up(&cp->pm_sem);
5133
5134#if 1
5135 if (cp->orig_cacheline_size) {
5136 /* Restore the cache line size if we had modified
5137 * it.
5138 */
5139 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5140 cp->orig_cacheline_size);
5141 }
5142#endif
5143 pci_free_consistent(pdev, sizeof(struct cas_init_block),
5144 cp->init_block, cp->block_dvma);
5145 iounmap(cp->regs);
5146 free_netdev(dev);
5147 pci_release_regions(pdev);
5148 pci_disable_device(pdev);
5149 pci_set_drvdata(pdev, NULL);
5150}
5151
5152#ifdef CONFIG_PM
5153static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
5154{
5155 struct net_device *dev = pci_get_drvdata(pdev);
5156 struct cas *cp = netdev_priv(dev);
5157 unsigned long flags;
5158
5159 /* We hold the PM semaphore during entire driver
5160 * sleep time
5161 */
5162 down(&cp->pm_sem);
5163
5164 /* If the driver is opened, we stop the DMA */
5165 if (cp->opened) {
5166 netif_device_detach(dev);
5167
5168 cas_lock_all_save(cp, flags);
5169
5170 /* We can set the second arg of cas_reset to 0
5171 * because on resume, we'll call cas_init_hw with
5172 * its second arg set so that autonegotiation is
5173 * restarted.
5174 */
5175 cas_reset(cp, 0);
5176 cas_clean_rings(cp);
5177 cas_unlock_all_restore(cp, flags);
5178 }
5179
5180 if (cp->hw_running)
5181 cas_shutdown(cp);
5182
5183 return 0;
5184}
5185
5186static int cas_resume(struct pci_dev *pdev)
5187{
5188 struct net_device *dev = pci_get_drvdata(pdev);
5189 struct cas *cp = netdev_priv(dev);
5190
5191 printk(KERN_INFO "%s: resuming\n", dev->name);
5192
5193 cas_hard_reset(cp);
5194 if (cp->opened) {
5195 unsigned long flags;
5196 cas_lock_all_save(cp, flags);
5197 cas_reset(cp, 0);
5198 cp->hw_running = 1;
5199 cas_clean_rings(cp);
5200 cas_init_hw(cp, 1);
5201 cas_unlock_all_restore(cp, flags);
5202
5203 netif_device_attach(dev);
5204 }
5205 up(&cp->pm_sem);
5206 return 0;
5207}
5208#endif /* CONFIG_PM */
5209
5210static struct pci_driver cas_driver = {
5211 .name = DRV_MODULE_NAME,
5212 .id_table = cas_pci_tbl,
5213 .probe = cas_init_one,
5214 .remove = __devexit_p(cas_remove_one),
5215#ifdef CONFIG_PM
5216 .suspend = cas_suspend,
5217 .resume = cas_resume
5218#endif
5219};
5220
5221static int __init cas_init(void)
5222{
5223 if (linkdown_timeout > 0)
5224 link_transition_timeout = linkdown_timeout * HZ;
5225 else
5226 link_transition_timeout = 0;
5227
5228 return pci_module_init(&cas_driver);
5229}
5230
5231static void __exit cas_cleanup(void)
5232{
5233 pci_unregister_driver(&cas_driver);
5234}
5235
5236module_init(cas_init);
5237module_exit(cas_cleanup);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 21:59:05 -0500