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-rw-r--r--drivers/net/can/c_can/c_can.c648
-rw-r--r--drivers/net/can/c_can/c_can.h23
-rw-r--r--drivers/net/can/c_can/c_can_pci.c9
-rw-r--r--drivers/net/can/c_can/c_can_platform.c2
-rw-r--r--drivers/net/can/dev.c2
-rw-r--r--drivers/net/can/sja1000/peak_pci.c14
-rw-r--r--drivers/net/can/sja1000/sja1000_isa.c16
-rw-r--r--drivers/net/can/slcan.c6
8 files changed, 321 insertions, 399 deletions
diff --git a/drivers/net/can/c_can/c_can.c b/drivers/net/can/c_can/c_can.c
index a5c8dcfa8357..95e04e2002da 100644
--- a/drivers/net/can/c_can/c_can.c
+++ b/drivers/net/can/c_can/c_can.c
@@ -60,6 +60,8 @@
60#define CONTROL_IE BIT(1) 60#define CONTROL_IE BIT(1)
61#define CONTROL_INIT BIT(0) 61#define CONTROL_INIT BIT(0)
62 62
63#define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE)
64
63/* test register */ 65/* test register */
64#define TEST_RX BIT(7) 66#define TEST_RX BIT(7)
65#define TEST_TX1 BIT(6) 67#define TEST_TX1 BIT(6)
@@ -108,11 +110,14 @@
108#define IF_COMM_CONTROL BIT(4) 110#define IF_COMM_CONTROL BIT(4)
109#define IF_COMM_CLR_INT_PND BIT(3) 111#define IF_COMM_CLR_INT_PND BIT(3)
110#define IF_COMM_TXRQST BIT(2) 112#define IF_COMM_TXRQST BIT(2)
113#define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST
111#define IF_COMM_DATAA BIT(1) 114#define IF_COMM_DATAA BIT(1)
112#define IF_COMM_DATAB BIT(0) 115#define IF_COMM_DATAB BIT(0)
113#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ 116
114 IF_COMM_CONTROL | IF_COMM_TXRQST | \ 117/* TX buffer setup */
115 IF_COMM_DATAA | IF_COMM_DATAB) 118#define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \
119 IF_COMM_TXRQST | \
120 IF_COMM_DATAA | IF_COMM_DATAB)
116 121
117/* For the low buffers we clear the interrupt bit, but keep newdat */ 122/* For the low buffers we clear the interrupt bit, but keep newdat */
118#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ 123#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \
@@ -120,12 +125,19 @@
120 IF_COMM_DATAA | IF_COMM_DATAB) 125 IF_COMM_DATAA | IF_COMM_DATAB)
121 126
122/* For the high buffers we clear the interrupt bit and newdat */ 127/* For the high buffers we clear the interrupt bit and newdat */
123#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_TXRQST) 128#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT)
129
130
131/* Receive setup of message objects */
132#define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL)
133
134/* Invalidation of message objects */
135#define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL)
124 136
125/* IFx arbitration */ 137/* IFx arbitration */
126#define IF_ARB_MSGVAL BIT(15) 138#define IF_ARB_MSGVAL BIT(31)
127#define IF_ARB_MSGXTD BIT(14) 139#define IF_ARB_MSGXTD BIT(30)
128#define IF_ARB_TRANSMIT BIT(13) 140#define IF_ARB_TRANSMIT BIT(29)
129 141
130/* IFx message control */ 142/* IFx message control */
131#define IF_MCONT_NEWDAT BIT(15) 143#define IF_MCONT_NEWDAT BIT(15)
@@ -139,19 +151,17 @@
139#define IF_MCONT_EOB BIT(7) 151#define IF_MCONT_EOB BIT(7)
140#define IF_MCONT_DLC_MASK 0xf 152#define IF_MCONT_DLC_MASK 0xf
141 153
154#define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK)
155#define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB)
156
157#define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB)
158
142/* 159/*
143 * Use IF1 for RX and IF2 for TX 160 * Use IF1 for RX and IF2 for TX
144 */ 161 */
145#define IF_RX 0 162#define IF_RX 0
146#define IF_TX 1 163#define IF_TX 1
147 164
148/* status interrupt */
149#define STATUS_INTERRUPT 0x8000
150
151/* global interrupt masks */
152#define ENABLE_ALL_INTERRUPTS 1
153#define DISABLE_ALL_INTERRUPTS 0
154
155/* minimum timeout for checking BUSY status */ 165/* minimum timeout for checking BUSY status */
156#define MIN_TIMEOUT_VALUE 6 166#define MIN_TIMEOUT_VALUE 6
157 167
@@ -171,6 +181,7 @@ enum c_can_lec_type {
171 LEC_BIT0_ERROR, 181 LEC_BIT0_ERROR,
172 LEC_CRC_ERROR, 182 LEC_CRC_ERROR,
173 LEC_UNUSED, 183 LEC_UNUSED,
184 LEC_MASK = LEC_UNUSED,
174}; 185};
175 186
176/* 187/*
@@ -226,143 +237,115 @@ static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable)
226 priv->raminit(priv, enable); 237 priv->raminit(priv, enable);
227} 238}
228 239
229static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) 240static void c_can_irq_control(struct c_can_priv *priv, bool enable)
230{
231 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) +
232 C_CAN_MSG_OBJ_TX_FIRST;
233}
234
235static inline int get_tx_echo_msg_obj(int txecho)
236{
237 return (txecho & C_CAN_NEXT_MSG_OBJ_MASK) + C_CAN_MSG_OBJ_TX_FIRST;
238}
239
240static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index)
241{
242 u32 val = priv->read_reg(priv, index);
243 val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
244 return val;
245}
246
247static void c_can_enable_all_interrupts(struct c_can_priv *priv,
248 int enable)
249{ 241{
250 unsigned int cntrl_save = priv->read_reg(priv, 242 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK;
251 C_CAN_CTRL_REG);
252 243
253 if (enable) 244 if (enable)
254 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); 245 ctrl |= CONTROL_IRQMSK;
255 else
256 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE);
257 246
258 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save); 247 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl);
259} 248}
260 249
261static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) 250static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj)
262{ 251{
263 int count = MIN_TIMEOUT_VALUE; 252 struct c_can_priv *priv = netdev_priv(dev);
253 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface);
264 254
265 while (count && priv->read_reg(priv, 255 priv->write_reg(priv, reg + 1, cmd);
266 C_CAN_IFACE(COMREQ_REG, iface)) & 256 priv->write_reg(priv, reg, obj);
267 IF_COMR_BUSY) { 257
268 count--; 258 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) {
259 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY))
260 return;
269 udelay(1); 261 udelay(1);
270 } 262 }
263 netdev_err(dev, "Updating object timed out\n");
271 264
272 if (!count) 265}
273 return 1;
274 266
275 return 0; 267static inline void c_can_object_get(struct net_device *dev, int iface,
268 u32 obj, u32 cmd)
269{
270 c_can_obj_update(dev, iface, cmd, obj);
276} 271}
277 272
278static inline void c_can_object_get(struct net_device *dev, 273static inline void c_can_object_put(struct net_device *dev, int iface,
279 int iface, int objno, int mask) 274 u32 obj, u32 cmd)
280{ 275{
281 struct c_can_priv *priv = netdev_priv(dev); 276 c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj);
277}
282 278
283 /* 279/*
284 * As per specs, after writting the message object number in the 280 * Note: According to documentation clearing TXIE while MSGVAL is set
285 * IF command request register the transfer b/w interface 281 * is not allowed, but works nicely on C/DCAN. And that lowers the I/O
286 * register and message RAM must be complete in 6 CAN-CLK 282 * load significantly.
287 * period. 283 */
288 */ 284static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj)
289 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 285{
290 IFX_WRITE_LOW_16BIT(mask)); 286 struct c_can_priv *priv = netdev_priv(dev);
291 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface),
292 IFX_WRITE_LOW_16BIT(objno));
293 287
294 if (c_can_msg_obj_is_busy(priv, iface)) 288 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
295 netdev_err(dev, "timed out in object get\n"); 289 c_can_object_put(dev, iface, obj, IF_COMM_INVAL);
296} 290}
297 291
298static inline void c_can_object_put(struct net_device *dev, 292static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj)
299 int iface, int objno, int mask)
300{ 293{
301 struct c_can_priv *priv = netdev_priv(dev); 294 struct c_can_priv *priv = netdev_priv(dev);
302 295
303 /* 296 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
304 * As per specs, after writting the message object number in the 297 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0);
305 * IF command request register the transfer b/w interface 298 c_can_inval_tx_object(dev, iface, obj);
306 * register and message RAM must be complete in 6 CAN-CLK
307 * period.
308 */
309 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface),
310 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask)));
311 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface),
312 IFX_WRITE_LOW_16BIT(objno));
313
314 if (c_can_msg_obj_is_busy(priv, iface))
315 netdev_err(dev, "timed out in object put\n");
316} 299}
317 300
318static void c_can_write_msg_object(struct net_device *dev, 301static void c_can_setup_tx_object(struct net_device *dev, int iface,
319 int iface, struct can_frame *frame, int objno) 302 struct can_frame *frame, int idx)
320{ 303{
321 int i;
322 u16 flags = 0;
323 unsigned int id;
324 struct c_can_priv *priv = netdev_priv(dev); 304 struct c_can_priv *priv = netdev_priv(dev);
325 305 u16 ctrl = IF_MCONT_TX | frame->can_dlc;
326 if (!(frame->can_id & CAN_RTR_FLAG)) 306 bool rtr = frame->can_id & CAN_RTR_FLAG;
327 flags |= IF_ARB_TRANSMIT; 307 u32 arb = IF_ARB_MSGVAL;
308 int i;
328 309
329 if (frame->can_id & CAN_EFF_FLAG) { 310 if (frame->can_id & CAN_EFF_FLAG) {
330 id = frame->can_id & CAN_EFF_MASK; 311 arb |= frame->can_id & CAN_EFF_MASK;
331 flags |= IF_ARB_MSGXTD; 312 arb |= IF_ARB_MSGXTD;
332 } else 313 } else {
333 id = ((frame->can_id & CAN_SFF_MASK) << 18); 314 arb |= (frame->can_id & CAN_SFF_MASK) << 18;
315 }
316
317 if (!rtr)
318 arb |= IF_ARB_TRANSMIT;
319
320 /*
321 * If we change the DIR bit, we need to invalidate the buffer
322 * first, i.e. clear the MSGVAL flag in the arbiter.
323 */
324 if (rtr != (bool)test_bit(idx, &priv->tx_dir)) {
325 u32 obj = idx + C_CAN_MSG_OBJ_TX_FIRST;
326
327 c_can_inval_msg_object(dev, iface, obj);
328 change_bit(idx, &priv->tx_dir);
329 }
334 330
335 flags |= IF_ARB_MSGVAL; 331 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), arb);
332 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), arb >> 16);
336 333
337 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 334 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
338 IFX_WRITE_LOW_16BIT(id));
339 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags |
340 IFX_WRITE_HIGH_16BIT(id));
341 335
342 for (i = 0; i < frame->can_dlc; i += 2) { 336 for (i = 0; i < frame->can_dlc; i += 2) {
343 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 337 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2,
344 frame->data[i] | (frame->data[i + 1] << 8)); 338 frame->data[i] | (frame->data[i + 1] << 8));
345 } 339 }
346
347 /* enable interrupt for this message object */
348 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
349 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB |
350 frame->can_dlc);
351 c_can_object_put(dev, iface, objno, IF_COMM_ALL);
352} 340}
353 341
354static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 342static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev,
355 int iface, 343 int iface)
356 int ctrl_mask)
357{ 344{
358 int i; 345 int i;
359 struct c_can_priv *priv = netdev_priv(dev);
360 346
361 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { 347 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++)
362 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 348 c_can_object_get(dev, iface, i, IF_COMM_CLR_NEWDAT);
363 ctrl_mask & ~IF_MCONT_NEWDAT);
364 c_can_object_put(dev, iface, i, IF_COMM_CONTROL);
365 }
366} 349}
367 350
368static int c_can_handle_lost_msg_obj(struct net_device *dev, 351static int c_can_handle_lost_msg_obj(struct net_device *dev,
@@ -377,6 +360,9 @@ static int c_can_handle_lost_msg_obj(struct net_device *dev,
377 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 360 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
378 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 361 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL);
379 362
363 stats->rx_errors++;
364 stats->rx_over_errors++;
365
380 /* create an error msg */ 366 /* create an error msg */
381 skb = alloc_can_err_skb(dev, &frame); 367 skb = alloc_can_err_skb(dev, &frame);
382 if (unlikely(!skb)) 368 if (unlikely(!skb))
@@ -384,22 +370,18 @@ static int c_can_handle_lost_msg_obj(struct net_device *dev,
384 370
385 frame->can_id |= CAN_ERR_CRTL; 371 frame->can_id |= CAN_ERR_CRTL;
386 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 372 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
387 stats->rx_errors++;
388 stats->rx_over_errors++;
389 373
390 netif_receive_skb(skb); 374 netif_receive_skb(skb);
391 return 1; 375 return 1;
392} 376}
393 377
394static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) 378static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl)
395{ 379{
396 u16 flags, data;
397 int i;
398 unsigned int val;
399 struct c_can_priv *priv = netdev_priv(dev);
400 struct net_device_stats *stats = &dev->stats; 380 struct net_device_stats *stats = &dev->stats;
401 struct sk_buff *skb; 381 struct c_can_priv *priv = netdev_priv(dev);
402 struct can_frame *frame; 382 struct can_frame *frame;
383 struct sk_buff *skb;
384 u32 arb, data;
403 385
404 skb = alloc_can_skb(dev, &frame); 386 skb = alloc_can_skb(dev, &frame);
405 if (!skb) { 387 if (!skb) {
@@ -409,115 +391,82 @@ static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl)
409 391
410 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 392 frame->can_dlc = get_can_dlc(ctrl & 0x0F);
411 393
412 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)); 394 arb = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface));
413 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) | 395 arb |= priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)) << 16;
414 (flags << 16);
415 396
416 if (flags & IF_ARB_MSGXTD) 397 if (arb & IF_ARB_MSGXTD)
417 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; 398 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG;
418 else 399 else
419 frame->can_id = (val >> 18) & CAN_SFF_MASK; 400 frame->can_id = (arb >> 18) & CAN_SFF_MASK;
420 401
421 if (flags & IF_ARB_TRANSMIT) 402 if (arb & IF_ARB_TRANSMIT) {
422 frame->can_id |= CAN_RTR_FLAG; 403 frame->can_id |= CAN_RTR_FLAG;
423 else { 404 } else {
424 for (i = 0; i < frame->can_dlc; i += 2) { 405 int i, dreg = C_CAN_IFACE(DATA1_REG, iface);
425 data = priv->read_reg(priv, 406
426 C_CAN_IFACE(DATA1_REG, iface) + i / 2); 407 for (i = 0; i < frame->can_dlc; i += 2, dreg ++) {
408 data = priv->read_reg(priv, dreg);
427 frame->data[i] = data; 409 frame->data[i] = data;
428 frame->data[i + 1] = data >> 8; 410 frame->data[i + 1] = data >> 8;
429 } 411 }
430 } 412 }
431 413
432 netif_receive_skb(skb);
433
434 stats->rx_packets++; 414 stats->rx_packets++;
435 stats->rx_bytes += frame->can_dlc; 415 stats->rx_bytes += frame->can_dlc;
416
417 netif_receive_skb(skb);
436 return 0; 418 return 0;
437} 419}
438 420
439static void c_can_setup_receive_object(struct net_device *dev, int iface, 421static void c_can_setup_receive_object(struct net_device *dev, int iface,
440 int objno, unsigned int mask, 422 u32 obj, u32 mask, u32 id, u32 mcont)
441 unsigned int id, unsigned int mcont)
442{ 423{
443 struct c_can_priv *priv = netdev_priv(dev); 424 struct c_can_priv *priv = netdev_priv(dev);
444 425
445 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), 426 mask |= BIT(29);
446 IFX_WRITE_LOW_16BIT(mask)); 427 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), mask);
447 428 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), mask >> 16);
448 /* According to C_CAN documentation, the reserved bit
449 * in IFx_MASK2 register is fixed 1
450 */
451 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface),
452 IFX_WRITE_HIGH_16BIT(mask) | BIT(13));
453 429
454 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 430 id |= IF_ARB_MSGVAL;
455 IFX_WRITE_LOW_16BIT(id)); 431 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), id);
456 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 432 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), id >> 16);
457 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id)));
458 433
459 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 434 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
460 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 435 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP);
461
462 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
463 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG));
464}
465
466static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno)
467{
468 struct c_can_priv *priv = netdev_priv(dev);
469
470 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
471 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0);
472 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
473
474 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL);
475
476 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
477 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG));
478}
479
480static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno)
481{
482 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG);
483
484 /*
485 * as transmission request register's bit n-1 corresponds to
486 * message object n, we need to handle the same properly.
487 */
488 if (val & (1 << (objno - 1)))
489 return 1;
490
491 return 0;
492} 436}
493 437
494static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 438static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
495 struct net_device *dev) 439 struct net_device *dev)
496{ 440{
497 u32 msg_obj_no;
498 struct c_can_priv *priv = netdev_priv(dev);
499 struct can_frame *frame = (struct can_frame *)skb->data; 441 struct can_frame *frame = (struct can_frame *)skb->data;
442 struct c_can_priv *priv = netdev_priv(dev);
443 u32 idx, obj;
500 444
501 if (can_dropped_invalid_skb(dev, skb)) 445 if (can_dropped_invalid_skb(dev, skb))
502 return NETDEV_TX_OK; 446 return NETDEV_TX_OK;
503
504 spin_lock_bh(&priv->xmit_lock);
505 msg_obj_no = get_tx_next_msg_obj(priv);
506
507 /* prepare message object for transmission */
508 c_can_write_msg_object(dev, IF_TX, frame, msg_obj_no);
509 priv->dlc[msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST] = frame->can_dlc;
510 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
511
512 /* 447 /*
513 * we have to stop the queue in case of a wrap around or 448 * This is not a FIFO. C/D_CAN sends out the buffers
514 * if the next TX message object is still in use 449 * prioritized. The lowest buffer number wins.
515 */ 450 */
516 priv->tx_next++; 451 idx = fls(atomic_read(&priv->tx_active));
517 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || 452 obj = idx + C_CAN_MSG_OBJ_TX_FIRST;
518 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) 453
454 /* If this is the last buffer, stop the xmit queue */
455 if (idx == C_CAN_MSG_OBJ_TX_NUM - 1)
519 netif_stop_queue(dev); 456 netif_stop_queue(dev);
520 spin_unlock_bh(&priv->xmit_lock); 457 /*
458 * Store the message in the interface so we can call
459 * can_put_echo_skb(). We must do this before we enable
460 * transmit as we might race against do_tx().
461 */
462 c_can_setup_tx_object(dev, IF_TX, frame, idx);
463 priv->dlc[idx] = frame->can_dlc;
464 can_put_echo_skb(skb, dev, idx);
465
466 /* Update the active bits */
467 atomic_add((1 << idx), &priv->tx_active);
468 /* Start transmission */
469 c_can_object_put(dev, IF_TX, obj, IF_COMM_TX);
521 470
522 return NETDEV_TX_OK; 471 return NETDEV_TX_OK;
523} 472}
@@ -594,11 +543,10 @@ static void c_can_configure_msg_objects(struct net_device *dev)
594 543
595 /* setup receive message objects */ 544 /* setup receive message objects */
596 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 545 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++)
597 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, 546 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, IF_MCONT_RCV);
598 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB);
599 547
600 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 548 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0,
601 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); 549 IF_MCONT_RCV_EOB);
602} 550}
603 551
604/* 552/*
@@ -612,30 +560,22 @@ static int c_can_chip_config(struct net_device *dev)
612 struct c_can_priv *priv = netdev_priv(dev); 560 struct c_can_priv *priv = netdev_priv(dev);
613 561
614 /* enable automatic retransmission */ 562 /* enable automatic retransmission */
615 priv->write_reg(priv, C_CAN_CTRL_REG, 563 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR);
616 CONTROL_ENABLE_AR);
617 564
618 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 565 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) &&
619 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 566 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) {
620 /* loopback + silent mode : useful for hot self-test */ 567 /* loopback + silent mode : useful for hot self-test */
621 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 568 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
622 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 569 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT);
623 priv->write_reg(priv, C_CAN_TEST_REG,
624 TEST_LBACK | TEST_SILENT);
625 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 570 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
626 /* loopback mode : useful for self-test function */ 571 /* loopback mode : useful for self-test function */
627 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 572 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
628 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
629 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 573 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK);
630 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 574 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
631 /* silent mode : bus-monitoring mode */ 575 /* silent mode : bus-monitoring mode */
632 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 576 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
633 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
634 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 577 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT);
635 } else 578 }
636 /* normal mode*/
637 priv->write_reg(priv, C_CAN_CTRL_REG,
638 CONTROL_EIE | CONTROL_SIE | CONTROL_IE);
639 579
640 /* configure message objects */ 580 /* configure message objects */
641 c_can_configure_msg_objects(dev); 581 c_can_configure_msg_objects(dev);
@@ -643,6 +583,11 @@ static int c_can_chip_config(struct net_device *dev)
643 /* set a `lec` value so that we can check for updates later */ 583 /* set a `lec` value so that we can check for updates later */
644 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 584 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
645 585
586 /* Clear all internal status */
587 atomic_set(&priv->tx_active, 0);
588 priv->rxmasked = 0;
589 priv->tx_dir = 0;
590
646 /* set bittiming params */ 591 /* set bittiming params */
647 return c_can_set_bittiming(dev); 592 return c_can_set_bittiming(dev);
648} 593}
@@ -657,13 +602,11 @@ static int c_can_start(struct net_device *dev)
657 if (err) 602 if (err)
658 return err; 603 return err;
659 604
660 priv->can.state = CAN_STATE_ERROR_ACTIVE; 605 /* Setup the command for new messages */
661 606 priv->comm_rcv_high = priv->type != BOSCH_D_CAN ?
662 /* reset tx helper pointers */ 607 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH;
663 priv->tx_next = priv->tx_echo = 0;
664 608
665 /* enable status change, error and module interrupts */ 609 priv->can.state = CAN_STATE_ERROR_ACTIVE;
666 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
667 610
668 return 0; 611 return 0;
669} 612}
@@ -672,15 +615,13 @@ static void c_can_stop(struct net_device *dev)
672{ 615{
673 struct c_can_priv *priv = netdev_priv(dev); 616 struct c_can_priv *priv = netdev_priv(dev);
674 617
675 /* disable all interrupts */ 618 c_can_irq_control(priv, false);
676 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
677
678 /* set the state as STOPPED */
679 priv->can.state = CAN_STATE_STOPPED; 619 priv->can.state = CAN_STATE_STOPPED;
680} 620}
681 621
682static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 622static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
683{ 623{
624 struct c_can_priv *priv = netdev_priv(dev);
684 int err; 625 int err;
685 626
686 switch (mode) { 627 switch (mode) {
@@ -689,6 +630,7 @@ static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
689 if (err) 630 if (err)
690 return err; 631 return err;
691 netif_wake_queue(dev); 632 netif_wake_queue(dev);
633 c_can_irq_control(priv, true);
692 break; 634 break;
693 default: 635 default:
694 return -EOPNOTSUPP; 636 return -EOPNOTSUPP;
@@ -724,42 +666,29 @@ static int c_can_get_berr_counter(const struct net_device *dev,
724 return err; 666 return err;
725} 667}
726 668
727/*
728 * priv->tx_echo holds the number of the oldest can_frame put for
729 * transmission into the hardware, but not yet ACKed by the CAN tx
730 * complete IRQ.
731 *
732 * We iterate from priv->tx_echo to priv->tx_next and check if the
733 * packet has been transmitted, echo it back to the CAN framework.
734 * If we discover a not yet transmitted packet, stop looking for more.
735 */
736static void c_can_do_tx(struct net_device *dev) 669static void c_can_do_tx(struct net_device *dev)
737{ 670{
738 struct c_can_priv *priv = netdev_priv(dev); 671 struct c_can_priv *priv = netdev_priv(dev);
739 struct net_device_stats *stats = &dev->stats; 672 struct net_device_stats *stats = &dev->stats;
740 u32 val, obj, pkts = 0, bytes = 0; 673 u32 idx, obj, pkts = 0, bytes = 0, pend, clr;
741
742 spin_lock_bh(&priv->xmit_lock);
743
744 for (; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
745 obj = get_tx_echo_msg_obj(priv->tx_echo);
746 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG);
747 674
748 if (val & (1 << (obj - 1))) 675 clr = pend = priv->read_reg(priv, C_CAN_INTPND2_REG);
749 break;
750 676
751 can_get_echo_skb(dev, obj - C_CAN_MSG_OBJ_TX_FIRST); 677 while ((idx = ffs(pend))) {
752 bytes += priv->dlc[obj - C_CAN_MSG_OBJ_TX_FIRST]; 678 idx--;
679 pend &= ~(1 << idx);
680 obj = idx + C_CAN_MSG_OBJ_TX_FIRST;
681 c_can_inval_tx_object(dev, IF_RX, obj);
682 can_get_echo_skb(dev, idx);
683 bytes += priv->dlc[idx];
753 pkts++; 684 pkts++;
754 c_can_inval_msg_object(dev, IF_TX, obj);
755 } 685 }
756 686
757 /* restart queue if wrap-up or if queue stalled on last pkt */ 687 /* Clear the bits in the tx_active mask */
758 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || 688 atomic_sub(clr, &priv->tx_active);
759 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0))
760 netif_wake_queue(dev);
761 689
762 spin_unlock_bh(&priv->xmit_lock); 690 if (clr & (1 << (C_CAN_MSG_OBJ_TX_NUM - 1)))
691 netif_wake_queue(dev);
763 692
764 if (pkts) { 693 if (pkts) {
765 stats->tx_bytes += bytes; 694 stats->tx_bytes += bytes;
@@ -800,18 +729,28 @@ static u32 c_can_adjust_pending(u32 pend)
800 return pend & ~((1 << lasts) - 1); 729 return pend & ~((1 << lasts) - 1);
801} 730}
802 731
732static inline void c_can_rx_object_get(struct net_device *dev,
733 struct c_can_priv *priv, u32 obj)
734{
735 c_can_object_get(dev, IF_RX, obj, priv->comm_rcv_high);
736}
737
738static inline void c_can_rx_finalize(struct net_device *dev,
739 struct c_can_priv *priv, u32 obj)
740{
741 if (priv->type != BOSCH_D_CAN)
742 c_can_object_get(dev, IF_RX, obj, IF_COMM_CLR_NEWDAT);
743}
744
803static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, 745static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv,
804 u32 pend, int quota) 746 u32 pend, int quota)
805{ 747{
806 u32 pkts = 0, ctrl, obj, mcmd; 748 u32 pkts = 0, ctrl, obj;
807 749
808 while ((obj = ffs(pend)) && quota > 0) { 750 while ((obj = ffs(pend)) && quota > 0) {
809 pend &= ~BIT(obj - 1); 751 pend &= ~BIT(obj - 1);
810 752
811 mcmd = obj < C_CAN_MSG_RX_LOW_LAST ? 753 c_can_rx_object_get(dev, priv, obj);
812 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH;
813
814 c_can_object_get(dev, IF_RX, obj, mcmd);
815 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); 754 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX));
816 755
817 if (ctrl & IF_MCONT_MSGLST) { 756 if (ctrl & IF_MCONT_MSGLST) {
@@ -833,9 +772,7 @@ static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv,
833 /* read the data from the message object */ 772 /* read the data from the message object */
834 c_can_read_msg_object(dev, IF_RX, ctrl); 773 c_can_read_msg_object(dev, IF_RX, ctrl);
835 774
836 if (obj == C_CAN_MSG_RX_LOW_LAST) 775 c_can_rx_finalize(dev, priv, obj);
837 /* activate all lower message objects */
838 c_can_activate_all_lower_rx_msg_obj(dev, IF_RX, ctrl);
839 776
840 pkts++; 777 pkts++;
841 quota--; 778 quota--;
@@ -844,6 +781,13 @@ static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv,
844 return pkts; 781 return pkts;
845} 782}
846 783
784static inline u32 c_can_get_pending(struct c_can_priv *priv)
785{
786 u32 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG);
787
788 return pend;
789}
790
847/* 791/*
848 * theory of operation: 792 * theory of operation:
849 * 793 *
@@ -853,18 +797,9 @@ static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv,
853 * has arrived. To work-around this issue, we keep two groups of message 797 * has arrived. To work-around this issue, we keep two groups of message
854 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 798 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT.
855 * 799 *
856 * To ensure in-order frame reception we use the following 800 * We clear the newdat bit right away.
857 * approach while re-activating a message object to receive further 801 *
858 * frames: 802 * This can result in packet reordering when the readout is slow.
859 * - if the current message object number is lower than
860 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing
861 * the INTPND bit.
862 * - if the current message object number is equal to
863 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower
864 * receive message objects.
865 * - if the current message object number is greater than
866 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of
867 * only this message object.
868 */ 803 */
869static int c_can_do_rx_poll(struct net_device *dev, int quota) 804static int c_can_do_rx_poll(struct net_device *dev, int quota)
870{ 805{
@@ -880,7 +815,7 @@ static int c_can_do_rx_poll(struct net_device *dev, int quota)
880 815
881 while (quota > 0) { 816 while (quota > 0) {
882 if (!pend) { 817 if (!pend) {
883 pend = priv->read_reg(priv, C_CAN_INTPND1_REG); 818 pend = c_can_get_pending(priv);
884 if (!pend) 819 if (!pend)
885 break; 820 break;
886 /* 821 /*
@@ -905,12 +840,6 @@ static int c_can_do_rx_poll(struct net_device *dev, int quota)
905 return pkts; 840 return pkts;
906} 841}
907 842
908static inline int c_can_has_and_handle_berr(struct c_can_priv *priv)
909{
910 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
911 (priv->current_status & LEC_UNUSED);
912}
913
914static int c_can_handle_state_change(struct net_device *dev, 843static int c_can_handle_state_change(struct net_device *dev,
915 enum c_can_bus_error_types error_type) 844 enum c_can_bus_error_types error_type)
916{ 845{
@@ -922,6 +851,26 @@ static int c_can_handle_state_change(struct net_device *dev,
922 struct sk_buff *skb; 851 struct sk_buff *skb;
923 struct can_berr_counter bec; 852 struct can_berr_counter bec;
924 853
854 switch (error_type) {
855 case C_CAN_ERROR_WARNING:
856 /* error warning state */
857 priv->can.can_stats.error_warning++;
858 priv->can.state = CAN_STATE_ERROR_WARNING;
859 break;
860 case C_CAN_ERROR_PASSIVE:
861 /* error passive state */
862 priv->can.can_stats.error_passive++;
863 priv->can.state = CAN_STATE_ERROR_PASSIVE;
864 break;
865 case C_CAN_BUS_OFF:
866 /* bus-off state */
867 priv->can.state = CAN_STATE_BUS_OFF;
868 can_bus_off(dev);
869 break;
870 default:
871 break;
872 }
873
925 /* propagate the error condition to the CAN stack */ 874 /* propagate the error condition to the CAN stack */
926 skb = alloc_can_err_skb(dev, &cf); 875 skb = alloc_can_err_skb(dev, &cf);
927 if (unlikely(!skb)) 876 if (unlikely(!skb))
@@ -935,8 +884,6 @@ static int c_can_handle_state_change(struct net_device *dev,
935 switch (error_type) { 884 switch (error_type) {
936 case C_CAN_ERROR_WARNING: 885 case C_CAN_ERROR_WARNING:
937 /* error warning state */ 886 /* error warning state */
938 priv->can.can_stats.error_warning++;
939 priv->can.state = CAN_STATE_ERROR_WARNING;
940 cf->can_id |= CAN_ERR_CRTL; 887 cf->can_id |= CAN_ERR_CRTL;
941 cf->data[1] = (bec.txerr > bec.rxerr) ? 888 cf->data[1] = (bec.txerr > bec.rxerr) ?
942 CAN_ERR_CRTL_TX_WARNING : 889 CAN_ERR_CRTL_TX_WARNING :
@@ -947,8 +894,6 @@ static int c_can_handle_state_change(struct net_device *dev,
947 break; 894 break;
948 case C_CAN_ERROR_PASSIVE: 895 case C_CAN_ERROR_PASSIVE:
949 /* error passive state */ 896 /* error passive state */
950 priv->can.can_stats.error_passive++;
951 priv->can.state = CAN_STATE_ERROR_PASSIVE;
952 cf->can_id |= CAN_ERR_CRTL; 897 cf->can_id |= CAN_ERR_CRTL;
953 if (rx_err_passive) 898 if (rx_err_passive)
954 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 899 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
@@ -960,22 +905,16 @@ static int c_can_handle_state_change(struct net_device *dev,
960 break; 905 break;
961 case C_CAN_BUS_OFF: 906 case C_CAN_BUS_OFF:
962 /* bus-off state */ 907 /* bus-off state */
963 priv->can.state = CAN_STATE_BUS_OFF;
964 cf->can_id |= CAN_ERR_BUSOFF; 908 cf->can_id |= CAN_ERR_BUSOFF;
965 /*
966 * disable all interrupts in bus-off mode to ensure that
967 * the CPU is not hogged down
968 */
969 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
970 can_bus_off(dev); 909 can_bus_off(dev);
971 break; 910 break;
972 default: 911 default:
973 break; 912 break;
974 } 913 }
975 914
976 netif_receive_skb(skb);
977 stats->rx_packets++; 915 stats->rx_packets++;
978 stats->rx_bytes += cf->can_dlc; 916 stats->rx_bytes += cf->can_dlc;
917 netif_receive_skb(skb);
979 918
980 return 1; 919 return 1;
981} 920}
@@ -996,6 +935,13 @@ static int c_can_handle_bus_err(struct net_device *dev,
996 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 935 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
997 return 0; 936 return 0;
998 937
938 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
939 return 0;
940
941 /* common for all type of bus errors */
942 priv->can.can_stats.bus_error++;
943 stats->rx_errors++;
944
999 /* propagate the error condition to the CAN stack */ 945 /* propagate the error condition to the CAN stack */
1000 skb = alloc_can_err_skb(dev, &cf); 946 skb = alloc_can_err_skb(dev, &cf);
1001 if (unlikely(!skb)) 947 if (unlikely(!skb))
@@ -1005,10 +951,6 @@ static int c_can_handle_bus_err(struct net_device *dev,
1005 * check for 'last error code' which tells us the 951 * check for 'last error code' which tells us the
1006 * type of the last error to occur on the CAN bus 952 * type of the last error to occur on the CAN bus
1007 */ 953 */
1008
1009 /* common for all type of bus errors */
1010 priv->can.can_stats.bus_error++;
1011 stats->rx_errors++;
1012 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 954 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
1013 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 955 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
1014 956
@@ -1043,95 +985,64 @@ static int c_can_handle_bus_err(struct net_device *dev,
1043 break; 985 break;
1044 } 986 }
1045 987
1046 /* set a `lec` value so that we can check for updates later */
1047 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
1048
1049 netif_receive_skb(skb);
1050 stats->rx_packets++; 988 stats->rx_packets++;
1051 stats->rx_bytes += cf->can_dlc; 989 stats->rx_bytes += cf->can_dlc;
1052 990 netif_receive_skb(skb);
1053 return 1; 991 return 1;
1054} 992}
1055 993
1056static int c_can_poll(struct napi_struct *napi, int quota) 994static int c_can_poll(struct napi_struct *napi, int quota)
1057{ 995{
1058 u16 irqstatus;
1059 int lec_type = 0;
1060 int work_done = 0;
1061 struct net_device *dev = napi->dev; 996 struct net_device *dev = napi->dev;
1062 struct c_can_priv *priv = netdev_priv(dev); 997 struct c_can_priv *priv = netdev_priv(dev);
998 u16 curr, last = priv->last_status;
999 int work_done = 0;
1063 1000
1064 irqstatus = priv->irqstatus; 1001 priv->last_status = curr = priv->read_reg(priv, C_CAN_STS_REG);
1065 if (!irqstatus) 1002 /* Ack status on C_CAN. D_CAN is self clearing */
1066 goto end; 1003 if (priv->type != BOSCH_D_CAN)
1004 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
1067 1005
1068 /* status events have the highest priority */ 1006 /* handle state changes */
1069 if (irqstatus == STATUS_INTERRUPT) { 1007 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) {
1070 priv->current_status = priv->read_reg(priv, 1008 netdev_dbg(dev, "entered error warning state\n");
1071 C_CAN_STS_REG); 1009 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING);
1072 1010 }
1073 /* handle Tx/Rx events */
1074 if (priv->current_status & STATUS_TXOK)
1075 priv->write_reg(priv, C_CAN_STS_REG,
1076 priv->current_status & ~STATUS_TXOK);
1077
1078 if (priv->current_status & STATUS_RXOK)
1079 priv->write_reg(priv, C_CAN_STS_REG,
1080 priv->current_status & ~STATUS_RXOK);
1081
1082 /* handle state changes */
1083 if ((priv->current_status & STATUS_EWARN) &&
1084 (!(priv->last_status & STATUS_EWARN))) {
1085 netdev_dbg(dev, "entered error warning state\n");
1086 work_done += c_can_handle_state_change(dev,
1087 C_CAN_ERROR_WARNING);
1088 }
1089 if ((priv->current_status & STATUS_EPASS) &&
1090 (!(priv->last_status & STATUS_EPASS))) {
1091 netdev_dbg(dev, "entered error passive state\n");
1092 work_done += c_can_handle_state_change(dev,
1093 C_CAN_ERROR_PASSIVE);
1094 }
1095 if ((priv->current_status & STATUS_BOFF) &&
1096 (!(priv->last_status & STATUS_BOFF))) {
1097 netdev_dbg(dev, "entered bus off state\n");
1098 work_done += c_can_handle_state_change(dev,
1099 C_CAN_BUS_OFF);
1100 }
1101 1011
1102 /* handle bus recovery events */ 1012 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) {
1103 if ((!(priv->current_status & STATUS_BOFF)) && 1013 netdev_dbg(dev, "entered error passive state\n");
1104 (priv->last_status & STATUS_BOFF)) { 1014 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE);
1105 netdev_dbg(dev, "left bus off state\n"); 1015 }
1106 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1107 }
1108 if ((!(priv->current_status & STATUS_EPASS)) &&
1109 (priv->last_status & STATUS_EPASS)) {
1110 netdev_dbg(dev, "left error passive state\n");
1111 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1112 }
1113 1016
1114 priv->last_status = priv->current_status; 1017 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) {
1115 1018 netdev_dbg(dev, "entered bus off state\n");
1116 /* handle lec errors on the bus */ 1019 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF);
1117 lec_type = c_can_has_and_handle_berr(priv); 1020 goto end;
1118 if (lec_type)
1119 work_done += c_can_handle_bus_err(dev, lec_type);
1120 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) &&
1121 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) {
1122 /* handle events corresponding to receive message objects */
1123 work_done += c_can_do_rx_poll(dev, (quota - work_done));
1124 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) &&
1125 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) {
1126 /* handle events corresponding to transmit message objects */
1127 c_can_do_tx(dev);
1128 } 1021 }
1129 1022
1023 /* handle bus recovery events */
1024 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) {
1025 netdev_dbg(dev, "left bus off state\n");
1026 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1027 }
1028 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) {
1029 netdev_dbg(dev, "left error passive state\n");
1030 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1031 }
1032
1033 /* handle lec errors on the bus */
1034 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK);
1035
1036 /* Handle Tx/Rx events. We do this unconditionally */
1037 work_done += c_can_do_rx_poll(dev, (quota - work_done));
1038 c_can_do_tx(dev);
1039
1130end: 1040end:
1131 if (work_done < quota) { 1041 if (work_done < quota) {
1132 napi_complete(napi); 1042 napi_complete(napi);
1133 /* enable all IRQs */ 1043 /* enable all IRQs if we are not in bus off state */
1134 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1044 if (priv->can.state != CAN_STATE_BUS_OFF)
1045 c_can_irq_control(priv, true);
1135 } 1046 }
1136 1047
1137 return work_done; 1048 return work_done;
@@ -1142,12 +1053,11 @@ static irqreturn_t c_can_isr(int irq, void *dev_id)
1142 struct net_device *dev = (struct net_device *)dev_id; 1053 struct net_device *dev = (struct net_device *)dev_id;
1143 struct c_can_priv *priv = netdev_priv(dev); 1054 struct c_can_priv *priv = netdev_priv(dev);
1144 1055
1145 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG); 1056 if (!priv->read_reg(priv, C_CAN_INT_REG))
1146 if (!priv->irqstatus)
1147 return IRQ_NONE; 1057 return IRQ_NONE;
1148 1058
1149 /* disable all interrupts and schedule the NAPI */ 1059 /* disable all interrupts and schedule the NAPI */
1150 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1060 c_can_irq_control(priv, false);
1151 napi_schedule(&priv->napi); 1061 napi_schedule(&priv->napi);
1152 1062
1153 return IRQ_HANDLED; 1063 return IRQ_HANDLED;
@@ -1184,6 +1094,8 @@ static int c_can_open(struct net_device *dev)
1184 can_led_event(dev, CAN_LED_EVENT_OPEN); 1094 can_led_event(dev, CAN_LED_EVENT_OPEN);
1185 1095
1186 napi_enable(&priv->napi); 1096 napi_enable(&priv->napi);
1097 /* enable status change, error and module interrupts */
1098 c_can_irq_control(priv, true);
1187 netif_start_queue(dev); 1099 netif_start_queue(dev);
1188 1100
1189 return 0; 1101 return 0;
@@ -1226,7 +1138,6 @@ struct net_device *alloc_c_can_dev(void)
1226 return NULL; 1138 return NULL;
1227 1139
1228 priv = netdev_priv(dev); 1140 priv = netdev_priv(dev);
1229 spin_lock_init(&priv->xmit_lock);
1230 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1141 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT);
1231 1142
1232 priv->dev = dev; 1143 priv->dev = dev;
@@ -1281,6 +1192,7 @@ int c_can_power_up(struct net_device *dev)
1281 u32 val; 1192 u32 val;
1282 unsigned long time_out; 1193 unsigned long time_out;
1283 struct c_can_priv *priv = netdev_priv(dev); 1194 struct c_can_priv *priv = netdev_priv(dev);
1195 int ret;
1284 1196
1285 if (!(dev->flags & IFF_UP)) 1197 if (!(dev->flags & IFF_UP))
1286 return 0; 1198 return 0;
@@ -1307,7 +1219,11 @@ int c_can_power_up(struct net_device *dev)
1307 if (time_after(jiffies, time_out)) 1219 if (time_after(jiffies, time_out))
1308 return -ETIMEDOUT; 1220 return -ETIMEDOUT;
1309 1221
1310 return c_can_start(dev); 1222 ret = c_can_start(dev);
1223 if (!ret)
1224 c_can_irq_control(priv, true);
1225
1226 return ret;
1311} 1227}
1312EXPORT_SYMBOL_GPL(c_can_power_up); 1228EXPORT_SYMBOL_GPL(c_can_power_up);
1313#endif 1229#endif
diff --git a/drivers/net/can/c_can/c_can.h b/drivers/net/can/c_can/c_can.h
index faa8404162b3..c56f1b1c11ca 100644
--- a/drivers/net/can/c_can/c_can.h
+++ b/drivers/net/can/c_can/c_can.h
@@ -22,14 +22,6 @@
22#ifndef C_CAN_H 22#ifndef C_CAN_H
23#define C_CAN_H 23#define C_CAN_H
24 24
25/*
26 * IFx register masks:
27 * allow easy operation on 16-bit registers when the
28 * argument is 32-bit instead
29 */
30#define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF)
31#define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16)
32
33/* message object split */ 25/* message object split */
34#define C_CAN_NO_OF_OBJECTS 32 26#define C_CAN_NO_OF_OBJECTS 32
35#define C_CAN_MSG_OBJ_RX_NUM 16 27#define C_CAN_MSG_OBJ_RX_NUM 16
@@ -45,8 +37,6 @@
45 37
46#define C_CAN_MSG_OBJ_RX_SPLIT 9 38#define C_CAN_MSG_OBJ_RX_SPLIT 9
47#define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1) 39#define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1)
48
49#define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1)
50#define RECEIVE_OBJECT_BITS 0x0000ffff 40#define RECEIVE_OBJECT_BITS 0x0000ffff
51 41
52enum reg { 42enum reg {
@@ -183,23 +173,20 @@ struct c_can_priv {
183 struct napi_struct napi; 173 struct napi_struct napi;
184 struct net_device *dev; 174 struct net_device *dev;
185 struct device *device; 175 struct device *device;
186 spinlock_t xmit_lock; 176 atomic_t tx_active;
187 int tx_object; 177 unsigned long tx_dir;
188 int current_status;
189 int last_status; 178 int last_status;
190 u16 (*read_reg) (struct c_can_priv *priv, enum reg index); 179 u16 (*read_reg) (struct c_can_priv *priv, enum reg index);
191 void (*write_reg) (struct c_can_priv *priv, enum reg index, u16 val); 180 void (*write_reg) (struct c_can_priv *priv, enum reg index, u16 val);
192 void __iomem *base; 181 void __iomem *base;
193 const u16 *regs; 182 const u16 *regs;
194 unsigned long irq_flags; /* for request_irq() */
195 unsigned int tx_next;
196 unsigned int tx_echo;
197 void *priv; /* for board-specific data */ 183 void *priv; /* for board-specific data */
198 u16 irqstatus;
199 enum c_can_dev_id type; 184 enum c_can_dev_id type;
200 u32 __iomem *raminit_ctrlreg; 185 u32 __iomem *raminit_ctrlreg;
201 unsigned int instance; 186 int instance;
202 void (*raminit) (const struct c_can_priv *priv, bool enable); 187 void (*raminit) (const struct c_can_priv *priv, bool enable);
188 u32 comm_rcv_high;
189 u32 rxmasked;
203 u32 dlc[C_CAN_MSG_OBJ_TX_NUM]; 190 u32 dlc[C_CAN_MSG_OBJ_TX_NUM];
204}; 191};
205 192
diff --git a/drivers/net/can/c_can/c_can_pci.c b/drivers/net/can/c_can/c_can_pci.c
index bce0be54c2f5..fe5f6303b584 100644
--- a/drivers/net/can/c_can/c_can_pci.c
+++ b/drivers/net/can/c_can/c_can_pci.c
@@ -84,8 +84,11 @@ static int c_can_pci_probe(struct pci_dev *pdev,
84 goto out_disable_device; 84 goto out_disable_device;
85 } 85 }
86 86
87 pci_set_master(pdev); 87 ret = pci_enable_msi(pdev);
88 pci_enable_msi(pdev); 88 if (!ret) {
89 dev_info(&pdev->dev, "MSI enabled\n");
90 pci_set_master(pdev);
91 }
89 92
90 addr = pci_iomap(pdev, 0, pci_resource_len(pdev, 0)); 93 addr = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
91 if (!addr) { 94 if (!addr) {
@@ -132,6 +135,8 @@ static int c_can_pci_probe(struct pci_dev *pdev,
132 goto out_free_c_can; 135 goto out_free_c_can;
133 } 136 }
134 137
138 priv->type = c_can_pci_data->type;
139
135 /* Configure access to registers */ 140 /* Configure access to registers */
136 switch (c_can_pci_data->reg_align) { 141 switch (c_can_pci_data->reg_align) {
137 case C_CAN_REG_ALIGN_32: 142 case C_CAN_REG_ALIGN_32:
diff --git a/drivers/net/can/c_can/c_can_platform.c b/drivers/net/can/c_can/c_can_platform.c
index 806d92753427..1df0b322d1e4 100644
--- a/drivers/net/can/c_can/c_can_platform.c
+++ b/drivers/net/can/c_can/c_can_platform.c
@@ -222,7 +222,7 @@ static int c_can_plat_probe(struct platform_device *pdev)
222 222
223 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 223 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
224 priv->raminit_ctrlreg = devm_ioremap_resource(&pdev->dev, res); 224 priv->raminit_ctrlreg = devm_ioremap_resource(&pdev->dev, res);
225 if (IS_ERR(priv->raminit_ctrlreg) || (int)priv->instance < 0) 225 if (IS_ERR(priv->raminit_ctrlreg) || priv->instance < 0)
226 dev_info(&pdev->dev, "control memory is not used for raminit\n"); 226 dev_info(&pdev->dev, "control memory is not used for raminit\n");
227 else 227 else
228 priv->raminit = c_can_hw_raminit; 228 priv->raminit = c_can_hw_raminit;
diff --git a/drivers/net/can/dev.c b/drivers/net/can/dev.c
index c7a260478749..e318e87e2bfc 100644
--- a/drivers/net/can/dev.c
+++ b/drivers/net/can/dev.c
@@ -256,7 +256,7 @@ static int can_get_bittiming(struct net_device *dev, struct can_bittiming *bt,
256 256
257 /* Check if the CAN device has bit-timing parameters */ 257 /* Check if the CAN device has bit-timing parameters */
258 if (!btc) 258 if (!btc)
259 return -ENOTSUPP; 259 return -EOPNOTSUPP;
260 260
261 /* 261 /*
262 * Depending on the given can_bittiming parameter structure the CAN 262 * Depending on the given can_bittiming parameter structure the CAN
diff --git a/drivers/net/can/sja1000/peak_pci.c b/drivers/net/can/sja1000/peak_pci.c
index c540e3d12e3d..564933ae218c 100644
--- a/drivers/net/can/sja1000/peak_pci.c
+++ b/drivers/net/can/sja1000/peak_pci.c
@@ -551,7 +551,7 @@ static int peak_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
551{ 551{
552 struct sja1000_priv *priv; 552 struct sja1000_priv *priv;
553 struct peak_pci_chan *chan; 553 struct peak_pci_chan *chan;
554 struct net_device *dev; 554 struct net_device *dev, *prev_dev;
555 void __iomem *cfg_base, *reg_base; 555 void __iomem *cfg_base, *reg_base;
556 u16 sub_sys_id, icr; 556 u16 sub_sys_id, icr;
557 int i, err, channels; 557 int i, err, channels;
@@ -688,11 +688,13 @@ failure_remove_channels:
688 writew(0x0, cfg_base + PITA_ICR + 2); 688 writew(0x0, cfg_base + PITA_ICR + 2);
689 689
690 chan = NULL; 690 chan = NULL;
691 for (dev = pci_get_drvdata(pdev); dev; dev = chan->prev_dev) { 691 for (dev = pci_get_drvdata(pdev); dev; dev = prev_dev) {
692 unregister_sja1000dev(dev);
693 free_sja1000dev(dev);
694 priv = netdev_priv(dev); 692 priv = netdev_priv(dev);
695 chan = priv->priv; 693 chan = priv->priv;
694 prev_dev = chan->prev_dev;
695
696 unregister_sja1000dev(dev);
697 free_sja1000dev(dev);
696 } 698 }
697 699
698 /* free any PCIeC resources too */ 700 /* free any PCIeC resources too */
@@ -726,10 +728,12 @@ static void peak_pci_remove(struct pci_dev *pdev)
726 728
727 /* Loop over all registered devices */ 729 /* Loop over all registered devices */
728 while (1) { 730 while (1) {
731 struct net_device *prev_dev = chan->prev_dev;
732
729 dev_info(&pdev->dev, "removing device %s\n", dev->name); 733 dev_info(&pdev->dev, "removing device %s\n", dev->name);
730 unregister_sja1000dev(dev); 734 unregister_sja1000dev(dev);
731 free_sja1000dev(dev); 735 free_sja1000dev(dev);
732 dev = chan->prev_dev; 736 dev = prev_dev;
733 737
734 if (!dev) { 738 if (!dev) {
735 /* do that only for first channel */ 739 /* do that only for first channel */
diff --git a/drivers/net/can/sja1000/sja1000_isa.c b/drivers/net/can/sja1000/sja1000_isa.c
index df136a2516c4..014695d7e6a3 100644
--- a/drivers/net/can/sja1000/sja1000_isa.c
+++ b/drivers/net/can/sja1000/sja1000_isa.c
@@ -46,6 +46,7 @@ static int clk[MAXDEV];
46static unsigned char cdr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff}; 46static unsigned char cdr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff};
47static unsigned char ocr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff}; 47static unsigned char ocr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff};
48static int indirect[MAXDEV] = {[0 ... (MAXDEV - 1)] = -1}; 48static int indirect[MAXDEV] = {[0 ... (MAXDEV - 1)] = -1};
49static spinlock_t indirect_lock[MAXDEV]; /* lock for indirect access mode */
49 50
50module_param_array(port, ulong, NULL, S_IRUGO); 51module_param_array(port, ulong, NULL, S_IRUGO);
51MODULE_PARM_DESC(port, "I/O port number"); 52MODULE_PARM_DESC(port, "I/O port number");
@@ -101,19 +102,26 @@ static void sja1000_isa_port_write_reg(const struct sja1000_priv *priv,
101static u8 sja1000_isa_port_read_reg_indirect(const struct sja1000_priv *priv, 102static u8 sja1000_isa_port_read_reg_indirect(const struct sja1000_priv *priv,
102 int reg) 103 int reg)
103{ 104{
104 unsigned long base = (unsigned long)priv->reg_base; 105 unsigned long flags, base = (unsigned long)priv->reg_base;
106 u8 readval;
105 107
108 spin_lock_irqsave(&indirect_lock[priv->dev->dev_id], flags);
106 outb(reg, base); 109 outb(reg, base);
107 return inb(base + 1); 110 readval = inb(base + 1);
111 spin_unlock_irqrestore(&indirect_lock[priv->dev->dev_id], flags);
112
113 return readval;
108} 114}
109 115
110static void sja1000_isa_port_write_reg_indirect(const struct sja1000_priv *priv, 116static void sja1000_isa_port_write_reg_indirect(const struct sja1000_priv *priv,
111 int reg, u8 val) 117 int reg, u8 val)
112{ 118{
113 unsigned long base = (unsigned long)priv->reg_base; 119 unsigned long flags, base = (unsigned long)priv->reg_base;
114 120
121 spin_lock_irqsave(&indirect_lock[priv->dev->dev_id], flags);
115 outb(reg, base); 122 outb(reg, base);
116 outb(val, base + 1); 123 outb(val, base + 1);
124 spin_unlock_irqrestore(&indirect_lock[priv->dev->dev_id], flags);
117} 125}
118 126
119static int sja1000_isa_probe(struct platform_device *pdev) 127static int sja1000_isa_probe(struct platform_device *pdev)
@@ -169,6 +177,7 @@ static int sja1000_isa_probe(struct platform_device *pdev)
169 if (iosize == SJA1000_IOSIZE_INDIRECT) { 177 if (iosize == SJA1000_IOSIZE_INDIRECT) {
170 priv->read_reg = sja1000_isa_port_read_reg_indirect; 178 priv->read_reg = sja1000_isa_port_read_reg_indirect;
171 priv->write_reg = sja1000_isa_port_write_reg_indirect; 179 priv->write_reg = sja1000_isa_port_write_reg_indirect;
180 spin_lock_init(&indirect_lock[idx]);
172 } else { 181 } else {
173 priv->read_reg = sja1000_isa_port_read_reg; 182 priv->read_reg = sja1000_isa_port_read_reg;
174 priv->write_reg = sja1000_isa_port_write_reg; 183 priv->write_reg = sja1000_isa_port_write_reg;
@@ -198,6 +207,7 @@ static int sja1000_isa_probe(struct platform_device *pdev)
198 207
199 platform_set_drvdata(pdev, dev); 208 platform_set_drvdata(pdev, dev);
200 SET_NETDEV_DEV(dev, &pdev->dev); 209 SET_NETDEV_DEV(dev, &pdev->dev);
210 dev->dev_id = idx;
201 211
202 err = register_sja1000dev(dev); 212 err = register_sja1000dev(dev);
203 if (err) { 213 if (err) {
diff --git a/drivers/net/can/slcan.c b/drivers/net/can/slcan.c
index f5b16e0e3a12..dcf9196f6316 100644
--- a/drivers/net/can/slcan.c
+++ b/drivers/net/can/slcan.c
@@ -322,13 +322,13 @@ static void slcan_write_wakeup(struct tty_struct *tty)
322 if (!sl || sl->magic != SLCAN_MAGIC || !netif_running(sl->dev)) 322 if (!sl || sl->magic != SLCAN_MAGIC || !netif_running(sl->dev))
323 return; 323 return;
324 324
325 spin_lock(&sl->lock); 325 spin_lock_bh(&sl->lock);
326 if (sl->xleft <= 0) { 326 if (sl->xleft <= 0) {
327 /* Now serial buffer is almost free & we can start 327 /* Now serial buffer is almost free & we can start
328 * transmission of another packet */ 328 * transmission of another packet */
329 sl->dev->stats.tx_packets++; 329 sl->dev->stats.tx_packets++;
330 clear_bit(TTY_DO_WRITE_WAKEUP, &tty->flags); 330 clear_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);
331 spin_unlock(&sl->lock); 331 spin_unlock_bh(&sl->lock);
332 netif_wake_queue(sl->dev); 332 netif_wake_queue(sl->dev);
333 return; 333 return;
334 } 334 }
@@ -336,7 +336,7 @@ static void slcan_write_wakeup(struct tty_struct *tty)
336 actual = tty->ops->write(tty, sl->xhead, sl->xleft); 336 actual = tty->ops->write(tty, sl->xhead, sl->xleft);
337 sl->xleft -= actual; 337 sl->xleft -= actual;
338 sl->xhead += actual; 338 sl->xhead += actual;
339 spin_unlock(&sl->lock); 339 spin_unlock_bh(&sl->lock);
340} 340}
341 341
342/* Send a can_frame to a TTY queue. */ 342/* Send a can_frame to a TTY queue. */