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path: root/drivers/net/can/janz-ican3.c
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-rw-r--r--drivers/net/can/janz-ican3.c1830
1 files changed, 1830 insertions, 0 deletions
diff --git a/drivers/net/can/janz-ican3.c b/drivers/net/can/janz-ican3.c
new file mode 100644
index 000000000000..6e533dcc36c0
--- /dev/null
+++ b/drivers/net/can/janz-ican3.c
@@ -0,0 +1,1830 @@
1/*
2 * Janz MODULbus VMOD-ICAN3 CAN Interface Driver
3 *
4 * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/delay.h>
17#include <linux/platform_device.h>
18
19#include <linux/netdevice.h>
20#include <linux/can.h>
21#include <linux/can/dev.h>
22#include <linux/can/error.h>
23
24#include <linux/mfd/janz.h>
25
26/* the DPM has 64k of memory, organized into 256x 256 byte pages */
27#define DPM_NUM_PAGES 256
28#define DPM_PAGE_SIZE 256
29#define DPM_PAGE_ADDR(p) ((p) * DPM_PAGE_SIZE)
30
31/* JANZ ICAN3 "old-style" host interface queue page numbers */
32#define QUEUE_OLD_CONTROL 0
33#define QUEUE_OLD_RB0 1
34#define QUEUE_OLD_RB1 2
35#define QUEUE_OLD_WB0 3
36#define QUEUE_OLD_WB1 4
37
38/* Janz ICAN3 "old-style" host interface control registers */
39#define MSYNC_PEER 0x00 /* ICAN only */
40#define MSYNC_LOCL 0x01 /* host only */
41#define TARGET_RUNNING 0x02
42
43#define MSYNC_RB0 0x01
44#define MSYNC_RB1 0x02
45#define MSYNC_RBLW 0x04
46#define MSYNC_RB_MASK (MSYNC_RB0 | MSYNC_RB1)
47
48#define MSYNC_WB0 0x10
49#define MSYNC_WB1 0x20
50#define MSYNC_WBLW 0x40
51#define MSYNC_WB_MASK (MSYNC_WB0 | MSYNC_WB1)
52
53/* Janz ICAN3 "new-style" host interface queue page numbers */
54#define QUEUE_TOHOST 5
55#define QUEUE_FROMHOST_MID 6
56#define QUEUE_FROMHOST_HIGH 7
57#define QUEUE_FROMHOST_LOW 8
58
59/* The first free page in the DPM is #9 */
60#define DPM_FREE_START 9
61
62/* Janz ICAN3 "new-style" and "fast" host interface descriptor flags */
63#define DESC_VALID 0x80
64#define DESC_WRAP 0x40
65#define DESC_INTERRUPT 0x20
66#define DESC_IVALID 0x10
67#define DESC_LEN(len) (len)
68
69/* Janz ICAN3 Firmware Messages */
70#define MSG_CONNECTI 0x02
71#define MSG_DISCONNECT 0x03
72#define MSG_IDVERS 0x04
73#define MSG_MSGLOST 0x05
74#define MSG_NEWHOSTIF 0x08
75#define MSG_INQUIRY 0x0a
76#define MSG_SETAFILMASK 0x10
77#define MSG_INITFDPMQUEUE 0x11
78#define MSG_HWCONF 0x12
79#define MSG_FMSGLOST 0x15
80#define MSG_CEVTIND 0x37
81#define MSG_CBTRREQ 0x41
82#define MSG_COFFREQ 0x42
83#define MSG_CONREQ 0x43
84#define MSG_CCONFREQ 0x47
85
86/*
87 * Janz ICAN3 CAN Inquiry Message Types
88 *
89 * NOTE: there appears to be a firmware bug here. You must send
90 * NOTE: INQUIRY_STATUS and expect to receive an INQUIRY_EXTENDED
91 * NOTE: response. The controller never responds to a message with
92 * NOTE: the INQUIRY_EXTENDED subspec :(
93 */
94#define INQUIRY_STATUS 0x00
95#define INQUIRY_TERMINATION 0x01
96#define INQUIRY_EXTENDED 0x04
97
98/* Janz ICAN3 CAN Set Acceptance Filter Mask Message Types */
99#define SETAFILMASK_REJECT 0x00
100#define SETAFILMASK_FASTIF 0x02
101
102/* Janz ICAN3 CAN Hardware Configuration Message Types */
103#define HWCONF_TERMINATE_ON 0x01
104#define HWCONF_TERMINATE_OFF 0x00
105
106/* Janz ICAN3 CAN Event Indication Message Types */
107#define CEVTIND_EI 0x01
108#define CEVTIND_DOI 0x02
109#define CEVTIND_LOST 0x04
110#define CEVTIND_FULL 0x08
111#define CEVTIND_BEI 0x10
112
113#define CEVTIND_CHIP_SJA1000 0x02
114
115#define ICAN3_BUSERR_QUOTA_MAX 255
116
117/* Janz ICAN3 CAN Frame Conversion */
118#define ICAN3_ECHO 0x10
119#define ICAN3_EFF_RTR 0x40
120#define ICAN3_SFF_RTR 0x10
121#define ICAN3_EFF 0x80
122
123#define ICAN3_CAN_TYPE_MASK 0x0f
124#define ICAN3_CAN_TYPE_SFF 0x00
125#define ICAN3_CAN_TYPE_EFF 0x01
126
127#define ICAN3_CAN_DLC_MASK 0x0f
128
129/*
130 * SJA1000 Status and Error Register Definitions
131 *
132 * Copied from drivers/net/can/sja1000/sja1000.h
133 */
134
135/* status register content */
136#define SR_BS 0x80
137#define SR_ES 0x40
138#define SR_TS 0x20
139#define SR_RS 0x10
140#define SR_TCS 0x08
141#define SR_TBS 0x04
142#define SR_DOS 0x02
143#define SR_RBS 0x01
144
145#define SR_CRIT (SR_BS|SR_ES)
146
147/* ECC register */
148#define ECC_SEG 0x1F
149#define ECC_DIR 0x20
150#define ECC_ERR 6
151#define ECC_BIT 0x00
152#define ECC_FORM 0x40
153#define ECC_STUFF 0x80
154#define ECC_MASK 0xc0
155
156/* Number of buffers for use in the "new-style" host interface */
157#define ICAN3_NEW_BUFFERS 16
158
159/* Number of buffers for use in the "fast" host interface */
160#define ICAN3_TX_BUFFERS 512
161#define ICAN3_RX_BUFFERS 1024
162
163/* SJA1000 Clock Input */
164#define ICAN3_CAN_CLOCK 8000000
165
166/* Driver Name */
167#define DRV_NAME "janz-ican3"
168
169/* DPM Control Registers -- starts at offset 0x100 in the MODULbus registers */
170struct ican3_dpm_control {
171 /* window address register */
172 u8 window_address;
173 u8 unused1;
174
175 /*
176 * Read access: clear interrupt from microcontroller
177 * Write access: send interrupt to microcontroller
178 */
179 u8 interrupt;
180 u8 unused2;
181
182 /* write-only: reset all hardware on the module */
183 u8 hwreset;
184 u8 unused3;
185
186 /* write-only: generate an interrupt to the TPU */
187 u8 tpuinterrupt;
188};
189
190struct ican3_dev {
191
192 /* must be the first member */
193 struct can_priv can;
194
195 /* CAN network device */
196 struct net_device *ndev;
197 struct napi_struct napi;
198
199 /* Device for printing */
200 struct device *dev;
201
202 /* module number */
203 unsigned int num;
204
205 /* base address of registers and IRQ */
206 struct janz_cmodio_onboard_regs __iomem *ctrl;
207 struct ican3_dpm_control __iomem *dpmctrl;
208 void __iomem *dpm;
209 int irq;
210
211 /* CAN bus termination status */
212 struct completion termination_comp;
213 bool termination_enabled;
214
215 /* CAN bus error status registers */
216 struct completion buserror_comp;
217 struct can_berr_counter bec;
218
219 /* old and new style host interface */
220 unsigned int iftype;
221
222 /*
223 * Any function which changes the current DPM page must hold this
224 * lock while it is performing data accesses. This ensures that the
225 * function will not be preempted and end up reading data from a
226 * different DPM page than it expects.
227 */
228 spinlock_t lock;
229
230 /* new host interface */
231 unsigned int rx_int;
232 unsigned int rx_num;
233 unsigned int tx_num;
234
235 /* fast host interface */
236 unsigned int fastrx_start;
237 unsigned int fastrx_int;
238 unsigned int fastrx_num;
239 unsigned int fasttx_start;
240 unsigned int fasttx_num;
241
242 /* first free DPM page */
243 unsigned int free_page;
244};
245
246struct ican3_msg {
247 u8 control;
248 u8 spec;
249 __le16 len;
250 u8 data[252];
251};
252
253struct ican3_new_desc {
254 u8 control;
255 u8 pointer;
256};
257
258struct ican3_fast_desc {
259 u8 control;
260 u8 command;
261 u8 data[14];
262};
263
264/* write to the window basic address register */
265static inline void ican3_set_page(struct ican3_dev *mod, unsigned int page)
266{
267 BUG_ON(page >= DPM_NUM_PAGES);
268 iowrite8(page, &mod->dpmctrl->window_address);
269}
270
271/*
272 * ICAN3 "old-style" host interface
273 */
274
275/*
276 * Recieve a message from the ICAN3 "old-style" firmware interface
277 *
278 * LOCKING: must hold mod->lock
279 *
280 * returns 0 on success, -ENOMEM when no message exists
281 */
282static int ican3_old_recv_msg(struct ican3_dev *mod, struct ican3_msg *msg)
283{
284 unsigned int mbox, mbox_page;
285 u8 locl, peer, xord;
286
287 /* get the MSYNC registers */
288 ican3_set_page(mod, QUEUE_OLD_CONTROL);
289 peer = ioread8(mod->dpm + MSYNC_PEER);
290 locl = ioread8(mod->dpm + MSYNC_LOCL);
291 xord = locl ^ peer;
292
293 if ((xord & MSYNC_RB_MASK) == 0x00) {
294 dev_dbg(mod->dev, "no mbox for reading\n");
295 return -ENOMEM;
296 }
297
298 /* find the first free mbox to read */
299 if ((xord & MSYNC_RB_MASK) == MSYNC_RB_MASK)
300 mbox = (xord & MSYNC_RBLW) ? MSYNC_RB0 : MSYNC_RB1;
301 else
302 mbox = (xord & MSYNC_RB0) ? MSYNC_RB0 : MSYNC_RB1;
303
304 /* copy the message */
305 mbox_page = (mbox == MSYNC_RB0) ? QUEUE_OLD_RB0 : QUEUE_OLD_RB1;
306 ican3_set_page(mod, mbox_page);
307 memcpy_fromio(msg, mod->dpm, sizeof(*msg));
308
309 /*
310 * notify the firmware that the read buffer is available
311 * for it to fill again
312 */
313 locl ^= mbox;
314
315 ican3_set_page(mod, QUEUE_OLD_CONTROL);
316 iowrite8(locl, mod->dpm + MSYNC_LOCL);
317 return 0;
318}
319
320/*
321 * Send a message through the "old-style" firmware interface
322 *
323 * LOCKING: must hold mod->lock
324 *
325 * returns 0 on success, -ENOMEM when no free space exists
326 */
327static int ican3_old_send_msg(struct ican3_dev *mod, struct ican3_msg *msg)
328{
329 unsigned int mbox, mbox_page;
330 u8 locl, peer, xord;
331
332 /* get the MSYNC registers */
333 ican3_set_page(mod, QUEUE_OLD_CONTROL);
334 peer = ioread8(mod->dpm + MSYNC_PEER);
335 locl = ioread8(mod->dpm + MSYNC_LOCL);
336 xord = locl ^ peer;
337
338 if ((xord & MSYNC_WB_MASK) == MSYNC_WB_MASK) {
339 dev_err(mod->dev, "no mbox for writing\n");
340 return -ENOMEM;
341 }
342
343 /* calculate a free mbox to use */
344 mbox = (xord & MSYNC_WB0) ? MSYNC_WB1 : MSYNC_WB0;
345
346 /* copy the message to the DPM */
347 mbox_page = (mbox == MSYNC_WB0) ? QUEUE_OLD_WB0 : QUEUE_OLD_WB1;
348 ican3_set_page(mod, mbox_page);
349 memcpy_toio(mod->dpm, msg, sizeof(*msg));
350
351 locl ^= mbox;
352 if (mbox == MSYNC_WB1)
353 locl |= MSYNC_WBLW;
354
355 ican3_set_page(mod, QUEUE_OLD_CONTROL);
356 iowrite8(locl, mod->dpm + MSYNC_LOCL);
357 return 0;
358}
359
360/*
361 * ICAN3 "new-style" Host Interface Setup
362 */
363
364static void __devinit ican3_init_new_host_interface(struct ican3_dev *mod)
365{
366 struct ican3_new_desc desc;
367 unsigned long flags;
368 void __iomem *dst;
369 int i;
370
371 spin_lock_irqsave(&mod->lock, flags);
372
373 /* setup the internal datastructures for RX */
374 mod->rx_num = 0;
375 mod->rx_int = 0;
376
377 /* tohost queue descriptors are in page 5 */
378 ican3_set_page(mod, QUEUE_TOHOST);
379 dst = mod->dpm;
380
381 /* initialize the tohost (rx) queue descriptors: pages 9-24 */
382 for (i = 0; i < ICAN3_NEW_BUFFERS; i++) {
383 desc.control = DESC_INTERRUPT | DESC_LEN(1); /* I L=1 */
384 desc.pointer = mod->free_page;
385
386 /* set wrap flag on last buffer */
387 if (i == ICAN3_NEW_BUFFERS - 1)
388 desc.control |= DESC_WRAP;
389
390 memcpy_toio(dst, &desc, sizeof(desc));
391 dst += sizeof(desc);
392 mod->free_page++;
393 }
394
395 /* fromhost (tx) mid queue descriptors are in page 6 */
396 ican3_set_page(mod, QUEUE_FROMHOST_MID);
397 dst = mod->dpm;
398
399 /* setup the internal datastructures for TX */
400 mod->tx_num = 0;
401
402 /* initialize the fromhost mid queue descriptors: pages 25-40 */
403 for (i = 0; i < ICAN3_NEW_BUFFERS; i++) {
404 desc.control = DESC_VALID | DESC_LEN(1); /* V L=1 */
405 desc.pointer = mod->free_page;
406
407 /* set wrap flag on last buffer */
408 if (i == ICAN3_NEW_BUFFERS - 1)
409 desc.control |= DESC_WRAP;
410
411 memcpy_toio(dst, &desc, sizeof(desc));
412 dst += sizeof(desc);
413 mod->free_page++;
414 }
415
416 /* fromhost hi queue descriptors are in page 7 */
417 ican3_set_page(mod, QUEUE_FROMHOST_HIGH);
418 dst = mod->dpm;
419
420 /* initialize only a single buffer in the fromhost hi queue (unused) */
421 desc.control = DESC_VALID | DESC_WRAP | DESC_LEN(1); /* VW L=1 */
422 desc.pointer = mod->free_page;
423 memcpy_toio(dst, &desc, sizeof(desc));
424 mod->free_page++;
425
426 /* fromhost low queue descriptors are in page 8 */
427 ican3_set_page(mod, QUEUE_FROMHOST_LOW);
428 dst = mod->dpm;
429
430 /* initialize only a single buffer in the fromhost low queue (unused) */
431 desc.control = DESC_VALID | DESC_WRAP | DESC_LEN(1); /* VW L=1 */
432 desc.pointer = mod->free_page;
433 memcpy_toio(dst, &desc, sizeof(desc));
434 mod->free_page++;
435
436 spin_unlock_irqrestore(&mod->lock, flags);
437}
438
439/*
440 * ICAN3 Fast Host Interface Setup
441 */
442
443static void __devinit ican3_init_fast_host_interface(struct ican3_dev *mod)
444{
445 struct ican3_fast_desc desc;
446 unsigned long flags;
447 unsigned int addr;
448 void __iomem *dst;
449 int i;
450
451 spin_lock_irqsave(&mod->lock, flags);
452
453 /* save the start recv page */
454 mod->fastrx_start = mod->free_page;
455 mod->fastrx_num = 0;
456 mod->fastrx_int = 0;
457
458 /* build a single fast tohost queue descriptor */
459 memset(&desc, 0, sizeof(desc));
460 desc.control = 0x00;
461 desc.command = 1;
462
463 /* build the tohost queue descriptor ring in memory */
464 addr = 0;
465 for (i = 0; i < ICAN3_RX_BUFFERS; i++) {
466
467 /* set the wrap bit on the last buffer */
468 if (i == ICAN3_RX_BUFFERS - 1)
469 desc.control |= DESC_WRAP;
470
471 /* switch to the correct page */
472 ican3_set_page(mod, mod->free_page);
473
474 /* copy the descriptor to the DPM */
475 dst = mod->dpm + addr;
476 memcpy_toio(dst, &desc, sizeof(desc));
477 addr += sizeof(desc);
478
479 /* move to the next page if necessary */
480 if (addr >= DPM_PAGE_SIZE) {
481 addr = 0;
482 mod->free_page++;
483 }
484 }
485
486 /* make sure we page-align the next queue */
487 if (addr != 0)
488 mod->free_page++;
489
490 /* save the start xmit page */
491 mod->fasttx_start = mod->free_page;
492 mod->fasttx_num = 0;
493
494 /* build a single fast fromhost queue descriptor */
495 memset(&desc, 0, sizeof(desc));
496 desc.control = DESC_VALID;
497 desc.command = 1;
498
499 /* build the fromhost queue descriptor ring in memory */
500 addr = 0;
501 for (i = 0; i < ICAN3_TX_BUFFERS; i++) {
502
503 /* set the wrap bit on the last buffer */
504 if (i == ICAN3_TX_BUFFERS - 1)
505 desc.control |= DESC_WRAP;
506
507 /* switch to the correct page */
508 ican3_set_page(mod, mod->free_page);
509
510 /* copy the descriptor to the DPM */
511 dst = mod->dpm + addr;
512 memcpy_toio(dst, &desc, sizeof(desc));
513 addr += sizeof(desc);
514
515 /* move to the next page if necessary */
516 if (addr >= DPM_PAGE_SIZE) {
517 addr = 0;
518 mod->free_page++;
519 }
520 }
521
522 spin_unlock_irqrestore(&mod->lock, flags);
523}
524
525/*
526 * ICAN3 "new-style" Host Interface Message Helpers
527 */
528
529/*
530 * LOCKING: must hold mod->lock
531 */
532static int ican3_new_send_msg(struct ican3_dev *mod, struct ican3_msg *msg)
533{
534 struct ican3_new_desc desc;
535 void __iomem *desc_addr = mod->dpm + (mod->tx_num * sizeof(desc));
536
537 /* switch to the fromhost mid queue, and read the buffer descriptor */
538 ican3_set_page(mod, QUEUE_FROMHOST_MID);
539 memcpy_fromio(&desc, desc_addr, sizeof(desc));
540
541 if (!(desc.control & DESC_VALID)) {
542 dev_dbg(mod->dev, "%s: no free buffers\n", __func__);
543 return -ENOMEM;
544 }
545
546 /* switch to the data page, copy the data */
547 ican3_set_page(mod, desc.pointer);
548 memcpy_toio(mod->dpm, msg, sizeof(*msg));
549
550 /* switch back to the descriptor, set the valid bit, write it back */
551 ican3_set_page(mod, QUEUE_FROMHOST_MID);
552 desc.control ^= DESC_VALID;
553 memcpy_toio(desc_addr, &desc, sizeof(desc));
554
555 /* update the tx number */
556 mod->tx_num = (desc.control & DESC_WRAP) ? 0 : (mod->tx_num + 1);
557 return 0;
558}
559
560/*
561 * LOCKING: must hold mod->lock
562 */
563static int ican3_new_recv_msg(struct ican3_dev *mod, struct ican3_msg *msg)
564{
565 struct ican3_new_desc desc;
566 void __iomem *desc_addr = mod->dpm + (mod->rx_num * sizeof(desc));
567
568 /* switch to the tohost queue, and read the buffer descriptor */
569 ican3_set_page(mod, QUEUE_TOHOST);
570 memcpy_fromio(&desc, desc_addr, sizeof(desc));
571
572 if (!(desc.control & DESC_VALID)) {
573 dev_dbg(mod->dev, "%s: no buffers to recv\n", __func__);
574 return -ENOMEM;
575 }
576
577 /* switch to the data page, copy the data */
578 ican3_set_page(mod, desc.pointer);
579 memcpy_fromio(msg, mod->dpm, sizeof(*msg));
580
581 /* switch back to the descriptor, toggle the valid bit, write it back */
582 ican3_set_page(mod, QUEUE_TOHOST);
583 desc.control ^= DESC_VALID;
584 memcpy_toio(desc_addr, &desc, sizeof(desc));
585
586 /* update the rx number */
587 mod->rx_num = (desc.control & DESC_WRAP) ? 0 : (mod->rx_num + 1);
588 return 0;
589}
590
591/*
592 * Message Send / Recv Helpers
593 */
594
595static int ican3_send_msg(struct ican3_dev *mod, struct ican3_msg *msg)
596{
597 unsigned long flags;
598 int ret;
599
600 spin_lock_irqsave(&mod->lock, flags);
601
602 if (mod->iftype == 0)
603 ret = ican3_old_send_msg(mod, msg);
604 else
605 ret = ican3_new_send_msg(mod, msg);
606
607 spin_unlock_irqrestore(&mod->lock, flags);
608 return ret;
609}
610
611static int ican3_recv_msg(struct ican3_dev *mod, struct ican3_msg *msg)
612{
613 unsigned long flags;
614 int ret;
615
616 spin_lock_irqsave(&mod->lock, flags);
617
618 if (mod->iftype == 0)
619 ret = ican3_old_recv_msg(mod, msg);
620 else
621 ret = ican3_new_recv_msg(mod, msg);
622
623 spin_unlock_irqrestore(&mod->lock, flags);
624 return ret;
625}
626
627/*
628 * Quick Pre-constructed Messages
629 */
630
631static int __devinit ican3_msg_connect(struct ican3_dev *mod)
632{
633 struct ican3_msg msg;
634
635 memset(&msg, 0, sizeof(msg));
636 msg.spec = MSG_CONNECTI;
637 msg.len = cpu_to_le16(0);
638
639 return ican3_send_msg(mod, &msg);
640}
641
642static int __devexit ican3_msg_disconnect(struct ican3_dev *mod)
643{
644 struct ican3_msg msg;
645
646 memset(&msg, 0, sizeof(msg));
647 msg.spec = MSG_DISCONNECT;
648 msg.len = cpu_to_le16(0);
649
650 return ican3_send_msg(mod, &msg);
651}
652
653static int __devinit ican3_msg_newhostif(struct ican3_dev *mod)
654{
655 struct ican3_msg msg;
656 int ret;
657
658 memset(&msg, 0, sizeof(msg));
659 msg.spec = MSG_NEWHOSTIF;
660 msg.len = cpu_to_le16(0);
661
662 /* If we're not using the old interface, switching seems bogus */
663 WARN_ON(mod->iftype != 0);
664
665 ret = ican3_send_msg(mod, &msg);
666 if (ret)
667 return ret;
668
669 /* mark the module as using the new host interface */
670 mod->iftype = 1;
671 return 0;
672}
673
674static int __devinit ican3_msg_fasthostif(struct ican3_dev *mod)
675{
676 struct ican3_msg msg;
677 unsigned int addr;
678
679 memset(&msg, 0, sizeof(msg));
680 msg.spec = MSG_INITFDPMQUEUE;
681 msg.len = cpu_to_le16(8);
682
683 /* write the tohost queue start address */
684 addr = DPM_PAGE_ADDR(mod->fastrx_start);
685 msg.data[0] = addr & 0xff;
686 msg.data[1] = (addr >> 8) & 0xff;
687 msg.data[2] = (addr >> 16) & 0xff;
688 msg.data[3] = (addr >> 24) & 0xff;
689
690 /* write the fromhost queue start address */
691 addr = DPM_PAGE_ADDR(mod->fasttx_start);
692 msg.data[4] = addr & 0xff;
693 msg.data[5] = (addr >> 8) & 0xff;
694 msg.data[6] = (addr >> 16) & 0xff;
695 msg.data[7] = (addr >> 24) & 0xff;
696
697 /* If we're not using the new interface yet, we cannot do this */
698 WARN_ON(mod->iftype != 1);
699
700 return ican3_send_msg(mod, &msg);
701}
702
703/*
704 * Setup the CAN filter to either accept or reject all
705 * messages from the CAN bus.
706 */
707static int __devinit ican3_set_id_filter(struct ican3_dev *mod, bool accept)
708{
709 struct ican3_msg msg;
710 int ret;
711
712 /* Standard Frame Format */
713 memset(&msg, 0, sizeof(msg));
714 msg.spec = MSG_SETAFILMASK;
715 msg.len = cpu_to_le16(5);
716 msg.data[0] = 0x00; /* IDLo LSB */
717 msg.data[1] = 0x00; /* IDLo MSB */
718 msg.data[2] = 0xff; /* IDHi LSB */
719 msg.data[3] = 0x07; /* IDHi MSB */
720
721 /* accept all frames for fast host if, or reject all frames */
722 msg.data[4] = accept ? SETAFILMASK_FASTIF : SETAFILMASK_REJECT;
723
724 ret = ican3_send_msg(mod, &msg);
725 if (ret)
726 return ret;
727
728 /* Extended Frame Format */
729 memset(&msg, 0, sizeof(msg));
730 msg.spec = MSG_SETAFILMASK;
731 msg.len = cpu_to_le16(13);
732 msg.data[0] = 0; /* MUX = 0 */
733 msg.data[1] = 0x00; /* IDLo LSB */
734 msg.data[2] = 0x00;
735 msg.data[3] = 0x00;
736 msg.data[4] = 0x20; /* IDLo MSB */
737 msg.data[5] = 0xff; /* IDHi LSB */
738 msg.data[6] = 0xff;
739 msg.data[7] = 0xff;
740 msg.data[8] = 0x3f; /* IDHi MSB */
741
742 /* accept all frames for fast host if, or reject all frames */
743 msg.data[9] = accept ? SETAFILMASK_FASTIF : SETAFILMASK_REJECT;
744
745 return ican3_send_msg(mod, &msg);
746}
747
748/*
749 * Bring the CAN bus online or offline
750 */
751static int ican3_set_bus_state(struct ican3_dev *mod, bool on)
752{
753 struct ican3_msg msg;
754
755 memset(&msg, 0, sizeof(msg));
756 msg.spec = on ? MSG_CONREQ : MSG_COFFREQ;
757 msg.len = cpu_to_le16(0);
758
759 return ican3_send_msg(mod, &msg);
760}
761
762static int ican3_set_termination(struct ican3_dev *mod, bool on)
763{
764 struct ican3_msg msg;
765
766 memset(&msg, 0, sizeof(msg));
767 msg.spec = MSG_HWCONF;
768 msg.len = cpu_to_le16(2);
769 msg.data[0] = 0x00;
770 msg.data[1] = on ? HWCONF_TERMINATE_ON : HWCONF_TERMINATE_OFF;
771
772 return ican3_send_msg(mod, &msg);
773}
774
775static int ican3_send_inquiry(struct ican3_dev *mod, u8 subspec)
776{
777 struct ican3_msg msg;
778
779 memset(&msg, 0, sizeof(msg));
780 msg.spec = MSG_INQUIRY;
781 msg.len = cpu_to_le16(2);
782 msg.data[0] = subspec;
783 msg.data[1] = 0x00;
784
785 return ican3_send_msg(mod, &msg);
786}
787
788static int ican3_set_buserror(struct ican3_dev *mod, u8 quota)
789{
790 struct ican3_msg msg;
791
792 memset(&msg, 0, sizeof(msg));
793 msg.spec = MSG_CCONFREQ;
794 msg.len = cpu_to_le16(2);
795 msg.data[0] = 0x00;
796 msg.data[1] = quota;
797
798 return ican3_send_msg(mod, &msg);
799}
800
801/*
802 * ICAN3 to Linux CAN Frame Conversion
803 */
804
805static void ican3_to_can_frame(struct ican3_dev *mod,
806 struct ican3_fast_desc *desc,
807 struct can_frame *cf)
808{
809 if ((desc->command & ICAN3_CAN_TYPE_MASK) == ICAN3_CAN_TYPE_SFF) {
810 if (desc->data[1] & ICAN3_SFF_RTR)
811 cf->can_id |= CAN_RTR_FLAG;
812
813 cf->can_id |= desc->data[0] << 3;
814 cf->can_id |= (desc->data[1] & 0xe0) >> 5;
815 cf->can_dlc = desc->data[1] & ICAN3_CAN_DLC_MASK;
816 memcpy(cf->data, &desc->data[2], sizeof(cf->data));
817 } else {
818 cf->can_dlc = desc->data[0] & ICAN3_CAN_DLC_MASK;
819 if (desc->data[0] & ICAN3_EFF_RTR)
820 cf->can_id |= CAN_RTR_FLAG;
821
822 if (desc->data[0] & ICAN3_EFF) {
823 cf->can_id |= CAN_EFF_FLAG;
824 cf->can_id |= desc->data[2] << 21; /* 28-21 */
825 cf->can_id |= desc->data[3] << 13; /* 20-13 */
826 cf->can_id |= desc->data[4] << 5; /* 12-5 */
827 cf->can_id |= (desc->data[5] & 0xf8) >> 3;
828 } else {
829 cf->can_id |= desc->data[2] << 3; /* 10-3 */
830 cf->can_id |= desc->data[3] >> 5; /* 2-0 */
831 }
832
833 memcpy(cf->data, &desc->data[6], sizeof(cf->data));
834 }
835}
836
837static void can_frame_to_ican3(struct ican3_dev *mod,
838 struct can_frame *cf,
839 struct ican3_fast_desc *desc)
840{
841 /* clear out any stale data in the descriptor */
842 memset(desc->data, 0, sizeof(desc->data));
843
844 /* we always use the extended format, with the ECHO flag set */
845 desc->command = ICAN3_CAN_TYPE_EFF;
846 desc->data[0] |= cf->can_dlc;
847 desc->data[1] |= ICAN3_ECHO;
848
849 if (cf->can_id & CAN_RTR_FLAG)
850 desc->data[0] |= ICAN3_EFF_RTR;
851
852 /* pack the id into the correct places */
853 if (cf->can_id & CAN_EFF_FLAG) {
854 desc->data[0] |= ICAN3_EFF;
855 desc->data[2] = (cf->can_id & 0x1fe00000) >> 21; /* 28-21 */
856 desc->data[3] = (cf->can_id & 0x001fe000) >> 13; /* 20-13 */
857 desc->data[4] = (cf->can_id & 0x00001fe0) >> 5; /* 12-5 */
858 desc->data[5] = (cf->can_id & 0x0000001f) << 3; /* 4-0 */
859 } else {
860 desc->data[2] = (cf->can_id & 0x7F8) >> 3; /* bits 10-3 */
861 desc->data[3] = (cf->can_id & 0x007) << 5; /* bits 2-0 */
862 }
863
864 /* copy the data bits into the descriptor */
865 memcpy(&desc->data[6], cf->data, sizeof(cf->data));
866}
867
868/*
869 * Interrupt Handling
870 */
871
872/*
873 * Handle an ID + Version message response from the firmware. We never generate
874 * this message in production code, but it is very useful when debugging to be
875 * able to display this message.
876 */
877static void ican3_handle_idvers(struct ican3_dev *mod, struct ican3_msg *msg)
878{
879 dev_dbg(mod->dev, "IDVERS response: %s\n", msg->data);
880}
881
882static void ican3_handle_msglost(struct ican3_dev *mod, struct ican3_msg *msg)
883{
884 struct net_device *dev = mod->ndev;
885 struct net_device_stats *stats = &dev->stats;
886 struct can_frame *cf;
887 struct sk_buff *skb;
888
889 /*
890 * Report that communication messages with the microcontroller firmware
891 * are being lost. These are never CAN frames, so we do not generate an
892 * error frame for userspace
893 */
894 if (msg->spec == MSG_MSGLOST) {
895 dev_err(mod->dev, "lost %d control messages\n", msg->data[0]);
896 return;
897 }
898
899 /*
900 * Oops, this indicates that we have lost messages in the fast queue,
901 * which are exclusively CAN messages. Our driver isn't reading CAN
902 * frames fast enough.
903 *
904 * We'll pretend that the SJA1000 told us that it ran out of buffer
905 * space, because there is not a better message for this.
906 */
907 skb = alloc_can_err_skb(dev, &cf);
908 if (skb) {
909 cf->can_id |= CAN_ERR_CRTL;
910 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
911 stats->rx_errors++;
912 stats->rx_bytes += cf->can_dlc;
913 netif_rx(skb);
914 }
915}
916
917/*
918 * Handle CAN Event Indication Messages from the firmware
919 *
920 * The ICAN3 firmware provides the values of some SJA1000 registers when it
921 * generates this message. The code below is largely copied from the
922 * drivers/net/can/sja1000/sja1000.c file, and adapted as necessary
923 */
924static int ican3_handle_cevtind(struct ican3_dev *mod, struct ican3_msg *msg)
925{
926 struct net_device *dev = mod->ndev;
927 struct net_device_stats *stats = &dev->stats;
928 enum can_state state = mod->can.state;
929 u8 status, isrc, rxerr, txerr;
930 struct can_frame *cf;
931 struct sk_buff *skb;
932
933 /* we can only handle the SJA1000 part */
934 if (msg->data[1] != CEVTIND_CHIP_SJA1000) {
935 dev_err(mod->dev, "unable to handle errors on non-SJA1000\n");
936 return -ENODEV;
937 }
938
939 /* check the message length for sanity */
940 if (le16_to_cpu(msg->len) < 6) {
941 dev_err(mod->dev, "error message too short\n");
942 return -EINVAL;
943 }
944
945 skb = alloc_can_err_skb(dev, &cf);
946 if (skb == NULL)
947 return -ENOMEM;
948
949 isrc = msg->data[0];
950 status = msg->data[3];
951 rxerr = msg->data[4];
952 txerr = msg->data[5];
953
954 /* data overrun interrupt */
955 if (isrc == CEVTIND_DOI || isrc == CEVTIND_LOST) {
956 dev_dbg(mod->dev, "data overrun interrupt\n");
957 cf->can_id |= CAN_ERR_CRTL;
958 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
959 stats->rx_over_errors++;
960 stats->rx_errors++;
961 }
962
963 /* error warning + passive interrupt */
964 if (isrc == CEVTIND_EI) {
965 dev_dbg(mod->dev, "error warning + passive interrupt\n");
966 if (status & SR_BS) {
967 state = CAN_STATE_BUS_OFF;
968 cf->can_id |= CAN_ERR_BUSOFF;
969 can_bus_off(dev);
970 } else if (status & SR_ES) {
971 if (rxerr >= 128 || txerr >= 128)
972 state = CAN_STATE_ERROR_PASSIVE;
973 else
974 state = CAN_STATE_ERROR_WARNING;
975 } else {
976 state = CAN_STATE_ERROR_ACTIVE;
977 }
978 }
979
980 /* bus error interrupt */
981 if (isrc == CEVTIND_BEI) {
982 u8 ecc = msg->data[2];
983
984 dev_dbg(mod->dev, "bus error interrupt\n");
985 mod->can.can_stats.bus_error++;
986 stats->rx_errors++;
987 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
988
989 switch (ecc & ECC_MASK) {
990 case ECC_BIT:
991 cf->data[2] |= CAN_ERR_PROT_BIT;
992 break;
993 case ECC_FORM:
994 cf->data[2] |= CAN_ERR_PROT_FORM;
995 break;
996 case ECC_STUFF:
997 cf->data[2] |= CAN_ERR_PROT_STUFF;
998 break;
999 default:
1000 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
1001 cf->data[3] = ecc & ECC_SEG;
1002 break;
1003 }
1004
1005 if ((ecc & ECC_DIR) == 0)
1006 cf->data[2] |= CAN_ERR_PROT_TX;
1007
1008 cf->data[6] = txerr;
1009 cf->data[7] = rxerr;
1010 }
1011
1012 if (state != mod->can.state && (state == CAN_STATE_ERROR_WARNING ||
1013 state == CAN_STATE_ERROR_PASSIVE)) {
1014 cf->can_id |= CAN_ERR_CRTL;
1015 if (state == CAN_STATE_ERROR_WARNING) {
1016 mod->can.can_stats.error_warning++;
1017 cf->data[1] = (txerr > rxerr) ?
1018 CAN_ERR_CRTL_TX_WARNING :
1019 CAN_ERR_CRTL_RX_WARNING;
1020 } else {
1021 mod->can.can_stats.error_passive++;
1022 cf->data[1] = (txerr > rxerr) ?
1023 CAN_ERR_CRTL_TX_PASSIVE :
1024 CAN_ERR_CRTL_RX_PASSIVE;
1025 }
1026
1027 cf->data[6] = txerr;
1028 cf->data[7] = rxerr;
1029 }
1030
1031 mod->can.state = state;
1032 stats->rx_errors++;
1033 stats->rx_bytes += cf->can_dlc;
1034 netif_rx(skb);
1035 return 0;
1036}
1037
1038static void ican3_handle_inquiry(struct ican3_dev *mod, struct ican3_msg *msg)
1039{
1040 switch (msg->data[0]) {
1041 case INQUIRY_STATUS:
1042 case INQUIRY_EXTENDED:
1043 mod->bec.rxerr = msg->data[5];
1044 mod->bec.txerr = msg->data[6];
1045 complete(&mod->buserror_comp);
1046 break;
1047 case INQUIRY_TERMINATION:
1048 mod->termination_enabled = msg->data[6] & HWCONF_TERMINATE_ON;
1049 complete(&mod->termination_comp);
1050 break;
1051 default:
1052 dev_err(mod->dev, "recieved an unknown inquiry response\n");
1053 break;
1054 }
1055}
1056
1057static void ican3_handle_unknown_message(struct ican3_dev *mod,
1058 struct ican3_msg *msg)
1059{
1060 dev_warn(mod->dev, "recieved unknown message: spec 0x%.2x length %d\n",
1061 msg->spec, le16_to_cpu(msg->len));
1062}
1063
1064/*
1065 * Handle a control message from the firmware
1066 */
1067static void ican3_handle_message(struct ican3_dev *mod, struct ican3_msg *msg)
1068{
1069 dev_dbg(mod->dev, "%s: modno %d spec 0x%.2x len %d bytes\n", __func__,
1070 mod->num, msg->spec, le16_to_cpu(msg->len));
1071
1072 switch (msg->spec) {
1073 case MSG_IDVERS:
1074 ican3_handle_idvers(mod, msg);
1075 break;
1076 case MSG_MSGLOST:
1077 case MSG_FMSGLOST:
1078 ican3_handle_msglost(mod, msg);
1079 break;
1080 case MSG_CEVTIND:
1081 ican3_handle_cevtind(mod, msg);
1082 break;
1083 case MSG_INQUIRY:
1084 ican3_handle_inquiry(mod, msg);
1085 break;
1086 default:
1087 ican3_handle_unknown_message(mod, msg);
1088 break;
1089 }
1090}
1091
1092/*
1093 * Check that there is room in the TX ring to transmit another skb
1094 *
1095 * LOCKING: must hold mod->lock
1096 */
1097static bool ican3_txok(struct ican3_dev *mod)
1098{
1099 struct ican3_fast_desc __iomem *desc;
1100 u8 control;
1101
1102 /* copy the control bits of the descriptor */
1103 ican3_set_page(mod, mod->fasttx_start + (mod->fasttx_num / 16));
1104 desc = mod->dpm + ((mod->fasttx_num % 16) * sizeof(*desc));
1105 control = ioread8(&desc->control);
1106
1107 /* if the control bits are not valid, then we have no more space */
1108 if (!(control & DESC_VALID))
1109 return false;
1110
1111 return true;
1112}
1113
1114/*
1115 * Recieve one CAN frame from the hardware
1116 *
1117 * This works like the core of a NAPI function, but is intended to be called
1118 * from workqueue context instead. This driver already needs a workqueue to
1119 * process control messages, so we use the workqueue instead of using NAPI.
1120 * This was done to simplify locking.
1121 *
1122 * CONTEXT: must be called from user context
1123 */
1124static int ican3_recv_skb(struct ican3_dev *mod)
1125{
1126 struct net_device *ndev = mod->ndev;
1127 struct net_device_stats *stats = &ndev->stats;
1128 struct ican3_fast_desc desc;
1129 void __iomem *desc_addr;
1130 struct can_frame *cf;
1131 struct sk_buff *skb;
1132 unsigned long flags;
1133
1134 spin_lock_irqsave(&mod->lock, flags);
1135
1136 /* copy the whole descriptor */
1137 ican3_set_page(mod, mod->fastrx_start + (mod->fastrx_num / 16));
1138 desc_addr = mod->dpm + ((mod->fastrx_num % 16) * sizeof(desc));
1139 memcpy_fromio(&desc, desc_addr, sizeof(desc));
1140
1141 spin_unlock_irqrestore(&mod->lock, flags);
1142
1143 /* check that we actually have a CAN frame */
1144 if (!(desc.control & DESC_VALID))
1145 return -ENOBUFS;
1146
1147 /* allocate an skb */
1148 skb = alloc_can_skb(ndev, &cf);
1149 if (unlikely(skb == NULL)) {
1150 stats->rx_dropped++;
1151 goto err_noalloc;
1152 }
1153
1154 /* convert the ICAN3 frame into Linux CAN format */
1155 ican3_to_can_frame(mod, &desc, cf);
1156
1157 /* receive the skb, update statistics */
1158 netif_receive_skb(skb);
1159 stats->rx_packets++;
1160 stats->rx_bytes += cf->can_dlc;
1161
1162err_noalloc:
1163 /* toggle the valid bit and return the descriptor to the ring */
1164 desc.control ^= DESC_VALID;
1165
1166 spin_lock_irqsave(&mod->lock, flags);
1167
1168 ican3_set_page(mod, mod->fastrx_start + (mod->fastrx_num / 16));
1169 memcpy_toio(desc_addr, &desc, 1);
1170
1171 /* update the next buffer pointer */
1172 mod->fastrx_num = (desc.control & DESC_WRAP) ? 0
1173 : (mod->fastrx_num + 1);
1174
1175 /* there are still more buffers to process */
1176 spin_unlock_irqrestore(&mod->lock, flags);
1177 return 0;
1178}
1179
1180static int ican3_napi(struct napi_struct *napi, int budget)
1181{
1182 struct ican3_dev *mod = container_of(napi, struct ican3_dev, napi);
1183 struct ican3_msg msg;
1184 unsigned long flags;
1185 int received = 0;
1186 int ret;
1187
1188 /* process all communication messages */
1189 while (true) {
1190 ret = ican3_recv_msg(mod, &msg);
1191 if (ret)
1192 break;
1193
1194 ican3_handle_message(mod, &msg);
1195 }
1196
1197 /* process all CAN frames from the fast interface */
1198 while (received < budget) {
1199 ret = ican3_recv_skb(mod);
1200 if (ret)
1201 break;
1202
1203 received++;
1204 }
1205
1206 /* We have processed all packets that the adapter had, but it
1207 * was less than our budget, stop polling */
1208 if (received < budget)
1209 napi_complete(napi);
1210
1211 spin_lock_irqsave(&mod->lock, flags);
1212
1213 /* Wake up the transmit queue if necessary */
1214 if (netif_queue_stopped(mod->ndev) && ican3_txok(mod))
1215 netif_wake_queue(mod->ndev);
1216
1217 spin_unlock_irqrestore(&mod->lock, flags);
1218
1219 /* re-enable interrupt generation */
1220 iowrite8(1 << mod->num, &mod->ctrl->int_enable);
1221 return received;
1222}
1223
1224static irqreturn_t ican3_irq(int irq, void *dev_id)
1225{
1226 struct ican3_dev *mod = dev_id;
1227 u8 stat;
1228
1229 /*
1230 * The interrupt status register on this device reports interrupts
1231 * as zeroes instead of using ones like most other devices
1232 */
1233 stat = ioread8(&mod->ctrl->int_disable) & (1 << mod->num);
1234 if (stat == (1 << mod->num))
1235 return IRQ_NONE;
1236
1237 /* clear the MODULbus interrupt from the microcontroller */
1238 ioread8(&mod->dpmctrl->interrupt);
1239
1240 /* disable interrupt generation, schedule the NAPI poller */
1241 iowrite8(1 << mod->num, &mod->ctrl->int_disable);
1242 napi_schedule(&mod->napi);
1243 return IRQ_HANDLED;
1244}
1245
1246/*
1247 * Firmware reset, startup, and shutdown
1248 */
1249
1250/*
1251 * Reset an ICAN module to its power-on state
1252 *
1253 * CONTEXT: no network device registered
1254 * LOCKING: work function disabled
1255 */
1256static int ican3_reset_module(struct ican3_dev *mod)
1257{
1258 u8 val = 1 << mod->num;
1259 unsigned long start;
1260 u8 runold, runnew;
1261
1262 /* disable interrupts so no more work is scheduled */
1263 iowrite8(1 << mod->num, &mod->ctrl->int_disable);
1264
1265 /* flush any pending work */
1266 flush_scheduled_work();
1267
1268 /* the first unallocated page in the DPM is #9 */
1269 mod->free_page = DPM_FREE_START;
1270
1271 ican3_set_page(mod, QUEUE_OLD_CONTROL);
1272 runold = ioread8(mod->dpm + TARGET_RUNNING);
1273
1274 /* reset the module */
1275 iowrite8(val, &mod->ctrl->reset_assert);
1276 iowrite8(val, &mod->ctrl->reset_deassert);
1277
1278 /* wait until the module has finished resetting and is running */
1279 start = jiffies;
1280 do {
1281 ican3_set_page(mod, QUEUE_OLD_CONTROL);
1282 runnew = ioread8(mod->dpm + TARGET_RUNNING);
1283 if (runnew == (runold ^ 0xff))
1284 return 0;
1285
1286 msleep(10);
1287 } while (time_before(jiffies, start + HZ / 4));
1288
1289 dev_err(mod->dev, "failed to reset CAN module\n");
1290 return -ETIMEDOUT;
1291}
1292
1293static void __devexit ican3_shutdown_module(struct ican3_dev *mod)
1294{
1295 ican3_msg_disconnect(mod);
1296 ican3_reset_module(mod);
1297}
1298
1299/*
1300 * Startup an ICAN module, bringing it into fast mode
1301 */
1302static int __devinit ican3_startup_module(struct ican3_dev *mod)
1303{
1304 int ret;
1305
1306 ret = ican3_reset_module(mod);
1307 if (ret) {
1308 dev_err(mod->dev, "unable to reset module\n");
1309 return ret;
1310 }
1311
1312 /* re-enable interrupts so we can send messages */
1313 iowrite8(1 << mod->num, &mod->ctrl->int_enable);
1314
1315 ret = ican3_msg_connect(mod);
1316 if (ret) {
1317 dev_err(mod->dev, "unable to connect to module\n");
1318 return ret;
1319 }
1320
1321 ican3_init_new_host_interface(mod);
1322 ret = ican3_msg_newhostif(mod);
1323 if (ret) {
1324 dev_err(mod->dev, "unable to switch to new-style interface\n");
1325 return ret;
1326 }
1327
1328 /* default to "termination on" */
1329 ret = ican3_set_termination(mod, true);
1330 if (ret) {
1331 dev_err(mod->dev, "unable to enable termination\n");
1332 return ret;
1333 }
1334
1335 /* default to "bus errors enabled" */
1336 ret = ican3_set_buserror(mod, ICAN3_BUSERR_QUOTA_MAX);
1337 if (ret) {
1338 dev_err(mod->dev, "unable to set bus-error\n");
1339 return ret;
1340 }
1341
1342 ican3_init_fast_host_interface(mod);
1343 ret = ican3_msg_fasthostif(mod);
1344 if (ret) {
1345 dev_err(mod->dev, "unable to switch to fast host interface\n");
1346 return ret;
1347 }
1348
1349 ret = ican3_set_id_filter(mod, true);
1350 if (ret) {
1351 dev_err(mod->dev, "unable to set acceptance filter\n");
1352 return ret;
1353 }
1354
1355 return 0;
1356}
1357
1358/*
1359 * CAN Network Device
1360 */
1361
1362static int ican3_open(struct net_device *ndev)
1363{
1364 struct ican3_dev *mod = netdev_priv(ndev);
1365 u8 quota;
1366 int ret;
1367
1368 /* open the CAN layer */
1369 ret = open_candev(ndev);
1370 if (ret) {
1371 dev_err(mod->dev, "unable to start CAN layer\n");
1372 return ret;
1373 }
1374
1375 /* set the bus error generation state appropriately */
1376 if (mod->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1377 quota = ICAN3_BUSERR_QUOTA_MAX;
1378 else
1379 quota = 0;
1380
1381 ret = ican3_set_buserror(mod, quota);
1382 if (ret) {
1383 dev_err(mod->dev, "unable to set bus-error\n");
1384 close_candev(ndev);
1385 return ret;
1386 }
1387
1388 /* bring the bus online */
1389 ret = ican3_set_bus_state(mod, true);
1390 if (ret) {
1391 dev_err(mod->dev, "unable to set bus-on\n");
1392 close_candev(ndev);
1393 return ret;
1394 }
1395
1396 /* start up the network device */
1397 mod->can.state = CAN_STATE_ERROR_ACTIVE;
1398 netif_start_queue(ndev);
1399
1400 return 0;
1401}
1402
1403static int ican3_stop(struct net_device *ndev)
1404{
1405 struct ican3_dev *mod = netdev_priv(ndev);
1406 int ret;
1407
1408 /* stop the network device xmit routine */
1409 netif_stop_queue(ndev);
1410 mod->can.state = CAN_STATE_STOPPED;
1411
1412 /* bring the bus offline, stop receiving packets */
1413 ret = ican3_set_bus_state(mod, false);
1414 if (ret) {
1415 dev_err(mod->dev, "unable to set bus-off\n");
1416 return ret;
1417 }
1418
1419 /* close the CAN layer */
1420 close_candev(ndev);
1421 return 0;
1422}
1423
1424static int ican3_xmit(struct sk_buff *skb, struct net_device *ndev)
1425{
1426 struct ican3_dev *mod = netdev_priv(ndev);
1427 struct net_device_stats *stats = &ndev->stats;
1428 struct can_frame *cf = (struct can_frame *)skb->data;
1429 struct ican3_fast_desc desc;
1430 void __iomem *desc_addr;
1431 unsigned long flags;
1432
1433 spin_lock_irqsave(&mod->lock, flags);
1434
1435 /* check that we can actually transmit */
1436 if (!ican3_txok(mod)) {
1437 dev_err(mod->dev, "no free descriptors, stopping queue\n");
1438 netif_stop_queue(ndev);
1439 spin_unlock_irqrestore(&mod->lock, flags);
1440 return NETDEV_TX_BUSY;
1441 }
1442
1443 /* copy the control bits of the descriptor */
1444 ican3_set_page(mod, mod->fasttx_start + (mod->fasttx_num / 16));
1445 desc_addr = mod->dpm + ((mod->fasttx_num % 16) * sizeof(desc));
1446 memset(&desc, 0, sizeof(desc));
1447 memcpy_fromio(&desc, desc_addr, 1);
1448
1449 /* convert the Linux CAN frame into ICAN3 format */
1450 can_frame_to_ican3(mod, cf, &desc);
1451
1452 /*
1453 * the programming manual says that you must set the IVALID bit, then
1454 * interrupt, then set the valid bit. Quite weird, but it seems to be
1455 * required for this to work
1456 */
1457 desc.control |= DESC_IVALID;
1458 memcpy_toio(desc_addr, &desc, sizeof(desc));
1459
1460 /* generate a MODULbus interrupt to the microcontroller */
1461 iowrite8(0x01, &mod->dpmctrl->interrupt);
1462
1463 desc.control ^= DESC_VALID;
1464 memcpy_toio(desc_addr, &desc, sizeof(desc));
1465
1466 /* update the next buffer pointer */
1467 mod->fasttx_num = (desc.control & DESC_WRAP) ? 0
1468 : (mod->fasttx_num + 1);
1469
1470 /* update statistics */
1471 stats->tx_packets++;
1472 stats->tx_bytes += cf->can_dlc;
1473 kfree_skb(skb);
1474
1475 /*
1476 * This hardware doesn't have TX-done notifications, so we'll try and
1477 * emulate it the best we can using ECHO skbs. Get the next TX
1478 * descriptor, and see if we have room to send. If not, stop the queue.
1479 * It will be woken when the ECHO skb for the current packet is recv'd.
1480 */
1481
1482 /* copy the control bits of the descriptor */
1483 if (!ican3_txok(mod))
1484 netif_stop_queue(ndev);
1485
1486 spin_unlock_irqrestore(&mod->lock, flags);
1487 return NETDEV_TX_OK;
1488}
1489
1490static const struct net_device_ops ican3_netdev_ops = {
1491 .ndo_open = ican3_open,
1492 .ndo_stop = ican3_stop,
1493 .ndo_start_xmit = ican3_xmit,
1494};
1495
1496/*
1497 * Low-level CAN Device
1498 */
1499
1500/* This structure was stolen from drivers/net/can/sja1000/sja1000.c */
1501static struct can_bittiming_const ican3_bittiming_const = {
1502 .name = DRV_NAME,
1503 .tseg1_min = 1,
1504 .tseg1_max = 16,
1505 .tseg2_min = 1,
1506 .tseg2_max = 8,
1507 .sjw_max = 4,
1508 .brp_min = 1,
1509 .brp_max = 64,
1510 .brp_inc = 1,
1511};
1512
1513/*
1514 * This routine was stolen from drivers/net/can/sja1000/sja1000.c
1515 *
1516 * The bittiming register command for the ICAN3 just sets the bit timing
1517 * registers on the SJA1000 chip directly
1518 */
1519static int ican3_set_bittiming(struct net_device *ndev)
1520{
1521 struct ican3_dev *mod = netdev_priv(ndev);
1522 struct can_bittiming *bt = &mod->can.bittiming;
1523 struct ican3_msg msg;
1524 u8 btr0, btr1;
1525
1526 btr0 = ((bt->brp - 1) & 0x3f) | (((bt->sjw - 1) & 0x3) << 6);
1527 btr1 = ((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) |
1528 (((bt->phase_seg2 - 1) & 0x7) << 4);
1529 if (mod->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1530 btr1 |= 0x80;
1531
1532 memset(&msg, 0, sizeof(msg));
1533 msg.spec = MSG_CBTRREQ;
1534 msg.len = cpu_to_le16(4);
1535 msg.data[0] = 0x00;
1536 msg.data[1] = 0x00;
1537 msg.data[2] = btr0;
1538 msg.data[3] = btr1;
1539
1540 return ican3_send_msg(mod, &msg);
1541}
1542
1543static int ican3_set_mode(struct net_device *ndev, enum can_mode mode)
1544{
1545 struct ican3_dev *mod = netdev_priv(ndev);
1546 int ret;
1547
1548 if (mode != CAN_MODE_START)
1549 return -ENOTSUPP;
1550
1551 /* bring the bus online */
1552 ret = ican3_set_bus_state(mod, true);
1553 if (ret) {
1554 dev_err(mod->dev, "unable to set bus-on\n");
1555 return ret;
1556 }
1557
1558 /* start up the network device */
1559 mod->can.state = CAN_STATE_ERROR_ACTIVE;
1560
1561 if (netif_queue_stopped(ndev))
1562 netif_wake_queue(ndev);
1563
1564 return 0;
1565}
1566
1567static int ican3_get_berr_counter(const struct net_device *ndev,
1568 struct can_berr_counter *bec)
1569{
1570 struct ican3_dev *mod = netdev_priv(ndev);
1571 int ret;
1572
1573 ret = ican3_send_inquiry(mod, INQUIRY_STATUS);
1574 if (ret)
1575 return ret;
1576
1577 ret = wait_for_completion_timeout(&mod->buserror_comp, HZ);
1578 if (ret <= 0) {
1579 dev_info(mod->dev, "%s timed out\n", __func__);
1580 return -ETIMEDOUT;
1581 }
1582
1583 bec->rxerr = mod->bec.rxerr;
1584 bec->txerr = mod->bec.txerr;
1585 return 0;
1586}
1587
1588/*
1589 * Sysfs Attributes
1590 */
1591
1592static ssize_t ican3_sysfs_show_term(struct device *dev,
1593 struct device_attribute *attr,
1594 char *buf)
1595{
1596 struct ican3_dev *mod = netdev_priv(to_net_dev(dev));
1597 int ret;
1598
1599 ret = ican3_send_inquiry(mod, INQUIRY_TERMINATION);
1600 if (ret)
1601 return ret;
1602
1603 ret = wait_for_completion_timeout(&mod->termination_comp, HZ);
1604 if (ret <= 0) {
1605 dev_info(mod->dev, "%s timed out\n", __func__);
1606 return -ETIMEDOUT;
1607 }
1608
1609 return snprintf(buf, PAGE_SIZE, "%u\n", mod->termination_enabled);
1610}
1611
1612static ssize_t ican3_sysfs_set_term(struct device *dev,
1613 struct device_attribute *attr,
1614 const char *buf, size_t count)
1615{
1616 struct ican3_dev *mod = netdev_priv(to_net_dev(dev));
1617 unsigned long enable;
1618 int ret;
1619
1620 if (strict_strtoul(buf, 0, &enable))
1621 return -EINVAL;
1622
1623 ret = ican3_set_termination(mod, enable);
1624 if (ret)
1625 return ret;
1626
1627 return count;
1628}
1629
1630static DEVICE_ATTR(termination, S_IWUGO | S_IRUGO, ican3_sysfs_show_term,
1631 ican3_sysfs_set_term);
1632
1633static struct attribute *ican3_sysfs_attrs[] = {
1634 &dev_attr_termination.attr,
1635 NULL,
1636};
1637
1638static struct attribute_group ican3_sysfs_attr_group = {
1639 .attrs = ican3_sysfs_attrs,
1640};
1641
1642/*
1643 * PCI Subsystem
1644 */
1645
1646static int __devinit ican3_probe(struct platform_device *pdev)
1647{
1648 struct janz_platform_data *pdata;
1649 struct net_device *ndev;
1650 struct ican3_dev *mod;
1651 struct resource *res;
1652 struct device *dev;
1653 int ret;
1654
1655 pdata = pdev->dev.platform_data;
1656 if (!pdata)
1657 return -ENXIO;
1658
1659 dev_dbg(&pdev->dev, "probe: module number %d\n", pdata->modno);
1660
1661 /* save the struct device for printing */
1662 dev = &pdev->dev;
1663
1664 /* allocate the CAN device and private data */
1665 ndev = alloc_candev(sizeof(*mod), 0);
1666 if (!ndev) {
1667 dev_err(dev, "unable to allocate CANdev\n");
1668 ret = -ENOMEM;
1669 goto out_return;
1670 }
1671
1672 platform_set_drvdata(pdev, ndev);
1673 mod = netdev_priv(ndev);
1674 mod->ndev = ndev;
1675 mod->dev = &pdev->dev;
1676 mod->num = pdata->modno;
1677 netif_napi_add(ndev, &mod->napi, ican3_napi, ICAN3_RX_BUFFERS);
1678 spin_lock_init(&mod->lock);
1679 init_completion(&mod->termination_comp);
1680 init_completion(&mod->buserror_comp);
1681
1682 /* setup device-specific sysfs attributes */
1683 ndev->sysfs_groups[0] = &ican3_sysfs_attr_group;
1684
1685 /* the first unallocated page in the DPM is 9 */
1686 mod->free_page = DPM_FREE_START;
1687
1688 ndev->netdev_ops = &ican3_netdev_ops;
1689 ndev->flags |= IFF_ECHO;
1690 SET_NETDEV_DEV(ndev, &pdev->dev);
1691
1692 mod->can.clock.freq = ICAN3_CAN_CLOCK;
1693 mod->can.bittiming_const = &ican3_bittiming_const;
1694 mod->can.do_set_bittiming = ican3_set_bittiming;
1695 mod->can.do_set_mode = ican3_set_mode;
1696 mod->can.do_get_berr_counter = ican3_get_berr_counter;
1697 mod->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES
1698 | CAN_CTRLMODE_BERR_REPORTING;
1699
1700 /* find our IRQ number */
1701 mod->irq = platform_get_irq(pdev, 0);
1702 if (mod->irq < 0) {
1703 dev_err(dev, "IRQ line not found\n");
1704 ret = -ENODEV;
1705 goto out_free_ndev;
1706 }
1707
1708 ndev->irq = mod->irq;
1709
1710 /* get access to the MODULbus registers for this module */
1711 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1712 if (!res) {
1713 dev_err(dev, "MODULbus registers not found\n");
1714 ret = -ENODEV;
1715 goto out_free_ndev;
1716 }
1717
1718 mod->dpm = ioremap(res->start, resource_size(res));
1719 if (!mod->dpm) {
1720 dev_err(dev, "MODULbus registers not ioremap\n");
1721 ret = -ENOMEM;
1722 goto out_free_ndev;
1723 }
1724
1725 mod->dpmctrl = mod->dpm + DPM_PAGE_SIZE;
1726
1727 /* get access to the control registers for this module */
1728 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1729 if (!res) {
1730 dev_err(dev, "CONTROL registers not found\n");
1731 ret = -ENODEV;
1732 goto out_iounmap_dpm;
1733 }
1734
1735 mod->ctrl = ioremap(res->start, resource_size(res));
1736 if (!mod->ctrl) {
1737 dev_err(dev, "CONTROL registers not ioremap\n");
1738 ret = -ENOMEM;
1739 goto out_iounmap_dpm;
1740 }
1741
1742 /* disable our IRQ, then hookup the IRQ handler */
1743 iowrite8(1 << mod->num, &mod->ctrl->int_disable);
1744 ret = request_irq(mod->irq, ican3_irq, IRQF_SHARED, DRV_NAME, mod);
1745 if (ret) {
1746 dev_err(dev, "unable to request IRQ\n");
1747 goto out_iounmap_ctrl;
1748 }
1749
1750 /* reset and initialize the CAN controller into fast mode */
1751 napi_enable(&mod->napi);
1752 ret = ican3_startup_module(mod);
1753 if (ret) {
1754 dev_err(dev, "%s: unable to start CANdev\n", __func__);
1755 goto out_free_irq;
1756 }
1757
1758 /* register with the Linux CAN layer */
1759 ret = register_candev(ndev);
1760 if (ret) {
1761 dev_err(dev, "%s: unable to register CANdev\n", __func__);
1762 goto out_free_irq;
1763 }
1764
1765 dev_info(dev, "module %d: registered CAN device\n", pdata->modno);
1766 return 0;
1767
1768out_free_irq:
1769 napi_disable(&mod->napi);
1770 iowrite8(1 << mod->num, &mod->ctrl->int_disable);
1771 free_irq(mod->irq, mod);
1772out_iounmap_ctrl:
1773 iounmap(mod->ctrl);
1774out_iounmap_dpm:
1775 iounmap(mod->dpm);
1776out_free_ndev:
1777 free_candev(ndev);
1778out_return:
1779 return ret;
1780}
1781
1782static int __devexit ican3_remove(struct platform_device *pdev)
1783{
1784 struct net_device *ndev = platform_get_drvdata(pdev);
1785 struct ican3_dev *mod = netdev_priv(ndev);
1786
1787 /* unregister the netdevice, stop interrupts */
1788 unregister_netdev(ndev);
1789 napi_disable(&mod->napi);
1790 iowrite8(1 << mod->num, &mod->ctrl->int_disable);
1791 free_irq(mod->irq, mod);
1792
1793 /* put the module into reset */
1794 ican3_shutdown_module(mod);
1795
1796 /* unmap all registers */
1797 iounmap(mod->ctrl);
1798 iounmap(mod->dpm);
1799
1800 free_candev(ndev);
1801
1802 return 0;
1803}
1804
1805static struct platform_driver ican3_driver = {
1806 .driver = {
1807 .name = DRV_NAME,
1808 .owner = THIS_MODULE,
1809 },
1810 .probe = ican3_probe,
1811 .remove = __devexit_p(ican3_remove),
1812};
1813
1814static int __init ican3_init(void)
1815{
1816 return platform_driver_register(&ican3_driver);
1817}
1818
1819static void __exit ican3_exit(void)
1820{
1821 platform_driver_unregister(&ican3_driver);
1822}
1823
1824MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>");
1825MODULE_DESCRIPTION("Janz MODULbus VMOD-ICAN3 Driver");
1826MODULE_LICENSE("GPL");
1827MODULE_ALIAS("platform:janz-ican3");
1828
1829module_init(ican3_init);
1830module_exit(ican3_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 11:29:32 -0500