1 files changed, 24 insertions, 9 deletions

diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index b8ce6fc927a0..8e9e7a24f2fc 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -1616,6 +1616,11 @@
 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
    loaded; 0-prepare; -unprepare */
 #define MISC_REG_UNPREPARED                                      0xa424
+#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST      (0x1<<0)
+#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST      (0x1<<1)
+#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN    (0x1<<4)
+#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST      (0x1<<2)
+#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN       (0x1<<3)
 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT      (0x1<<0)
 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS    (0x1<<9)
 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G          (0x1<<15)
@@ -1660,6 +1665,8 @@
 #define NIG_REG_EGRESS_PBF0_IN_EN                                0x100cc
 /* [RW 1] Input enable for TX PBF user packet port1 IF */
 #define NIG_REG_EGRESS_PBF1_IN_EN                                0x100d0
+/* [RW 1] Input enable for TX UMP management packet port0 IF */
+#define NIG_REG_EGRESS_UMP0_IN_EN                                0x100d4
 /* [RW 1] Input enable for RX_EMAC0 IF */
 #define NIG_REG_EMAC0_IN_EN                                      0x100a4
 /* [RW 1] output enable for TX EMAC pause port 0 IF */
@@ -5843,25 +5850,33 @@ Theotherbitsarereservedandshouldbezero*/
 #define MDIO_PMA_REG_ROM_VER2           0xca1a
 #define MDIO_PMA_REG_EDC_FFE_MAIN       0xca1b
 #define MDIO_PMA_REG_PLL_BANDWIDTH      0xca1d
-#define MDIO_PMA_REG_GEN_CTRL2          0xca1e
+#define MDIO_PMA_REG_PLL_CTRL           0xca1e
 #define MDIO_PMA_REG_MISC_CTRL0         0xca23
 #define MDIO_PMA_REG_LRM_MODE           0xca3f
 #define MDIO_PMA_REG_CDR_BANDWIDTH      0xca46
 #define MDIO_PMA_REG_MISC_CTRL1         0xca85
 
-#define MDIO_PMA_REG_8726_TWO_WIRE_CTRL         0x8000
-#define MDIO_PMA_REG_8726_TWO_WIRE_CTRL_STATUS_MASK     0x000c
-#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IDLE          0x0000
-#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_COMPLETE      0x0004
-#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IN_PROGRESS   0x0008
-#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_FAILED        0x000c
-#define MDIO_PMA_REG_8726_TWO_WIRE_BYTE_CNT     0x8002
-#define MDIO_PMA_REG_8726_TWO_WIRE_MEM_ADDR     0x8003
+#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL          0x8000
+#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK      0x000c
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE           0x0000
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE       0x0004
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS    0x0008
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED         0x000c
+#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT      0x8002
+#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR      0x8003
 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF     0xc820
 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
 #define MDIO_PMA_REG_8726_TX_CTRL1              0xca01
 #define MDIO_PMA_REG_8726_TX_CTRL2              0xca05
 
+#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR   0x8005
+#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF     0x8007
+#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
+#define MDIO_PMA_REG_8727_MISC_CTRL             0x8309
+#define MDIO_PMA_REG_8727_TX_CTRL1              0xca02
+#define MDIO_PMA_REG_8727_TX_CTRL2              0xca05
+#define MDIO_PMA_REG_8727_PCS_OPT_CTRL          0xc808
+#define MDIO_PMA_REG_8727_GPIO_CTRL             0xc80e
 
 #define MDIO_PMA_REG_8073_CHIP_REV                      0xc801
 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS             0xc820