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-rw-r--r--drivers/net/bnx2x_reg.h66
1 files changed, 27 insertions, 39 deletions
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index 8707c0d05d9a..15c9a9946724 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -38,21 +38,19 @@
38 was asserted. */ 38 was asserted. */
39#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8 39#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
40#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc 40#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
41#define BRB1_REG_NUM_OF_FULL_CYCLES_2 0x600d0
42#define BRB1_REG_NUM_OF_FULL_CYCLES_3 0x600d4
43#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8 41#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
44/* [ST 32] The number of cycles that the pause signal towards MAC #0 was 42/* [ST 32] The number of cycles that the pause signal towards MAC #0 was
45 asserted. */ 43 asserted. */
46#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8 44#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
47#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc 45#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
48#define BRB1_REG_NUM_OF_PAUSE_CYCLES_2 0x600c0
49#define BRB1_REG_NUM_OF_PAUSE_CYCLES_3 0x600c4
50/* [RW 10] Write client 0: De-assert pause threshold. */ 46/* [RW 10] Write client 0: De-assert pause threshold. */
51#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078 47#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
52#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c 48#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
53/* [RW 10] Write client 0: Assert pause threshold. */ 49/* [RW 10] Write client 0: Assert pause threshold. */
54#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068 50#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
55#define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c 51#define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
52/* [R 24] The number of full blocks occpied by port. */
53#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
56/* [RW 1] Reset the design by software. */ 54/* [RW 1] Reset the design by software. */
57#define BRB1_REG_SOFT_RESET 0x600dc 55#define BRB1_REG_SOFT_RESET 0x600dc
58/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */ 56/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
@@ -513,7 +511,6 @@
513/* [RW 15] Interrupt table Read and write access to it is not possible in 511/* [RW 15] Interrupt table Read and write access to it is not possible in
514 the middle of the work */ 512 the middle of the work */
515#define CSEM_REG_INT_TABLE 0x200400 513#define CSEM_REG_INT_TABLE 0x200400
516#define CSEM_REG_INT_TABLE_SIZE 256
517/* [ST 24] Statistics register. The number of messages that entered through 514/* [ST 24] Statistics register. The number of messages that entered through
518 FIC0 */ 515 FIC0 */
519#define CSEM_REG_MSG_NUM_FIC0 0x200000 516#define CSEM_REG_MSG_NUM_FIC0 0x200000
@@ -587,13 +584,10 @@
587#define DBG_REG_DBG_PRTY_MASK 0xc0a8 584#define DBG_REG_DBG_PRTY_MASK 0xc0a8
588/* [R 1] Parity register #0 read */ 585/* [R 1] Parity register #0 read */
589#define DBG_REG_DBG_PRTY_STS 0xc09c 586#define DBG_REG_DBG_PRTY_STS 0xc09c
590/* [RW 2] debug only: These bits indicate the credit for PCI request type 4
591 interface; MUST be configured AFTER pci_ext_buffer_strt_addr_lsb/msb are
592 configured */
593#define DBG_REG_PCI_REQ_CREDIT 0xc120
594/* [RW 32] Commands memory. The address to command X; row Y is to calculated 587/* [RW 32] Commands memory. The address to command X; row Y is to calculated
595 as 14*X+Y. */ 588 as 14*X+Y. */
596#define DMAE_REG_CMD_MEM 0x102400 589#define DMAE_REG_CMD_MEM 0x102400
590#define DMAE_REG_CMD_MEM_SIZE 224
597/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c 591/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
598 initial value is all ones. */ 592 initial value is all ones. */
599#define DMAE_REG_CRC16C_INIT 0x10201c 593#define DMAE_REG_CRC16C_INIT 0x10201c
@@ -1626,7 +1620,7 @@
1626 is reset to 0x080; giving a default blink period of approximately 8Hz. */ 1620 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1627#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310 1621#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1628/* [RW 1] Port0: If set along with the 1622/* [RW 1] Port0: If set along with the
1629 nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0 1623 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1630 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED 1624 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1631 bit; the Traffic LED will blink with the blink rate specified in 1625 bit; the Traffic LED will blink with the blink rate specified in
1632 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and 1626 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
@@ -1733,9 +1727,21 @@
1733/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 1727/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1734 for port0 */ 1728 for port0 */
1735#define NIG_REG_STAT0_BRB_DISCARD 0x105f0 1729#define NIG_REG_STAT0_BRB_DISCARD 0x105f0
1730/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1731 between 1024 and 1522 bytes for port0 */
1732#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
1733/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1734 between 1523 bytes and above for port0 */
1735#define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
1736/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 1736/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1737 for port1 */ 1737 for port1 */
1738#define NIG_REG_STAT1_BRB_DISCARD 0x10628 1738#define NIG_REG_STAT1_BRB_DISCARD 0x10628
1739/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1740 between 1024 and 1522 bytes for port1 */
1741#define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
1742/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1743 between 1523 bytes and above for port1 */
1744#define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
1739/* [WB_R 64] Rx statistics : User octets received for LP */ 1745/* [WB_R 64] Rx statistics : User octets received for LP */
1740#define NIG_REG_STAT2_BRB_OCTET 0x107e0 1746#define NIG_REG_STAT2_BRB_OCTET 0x107e0
1741#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328 1747#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
@@ -1849,7 +1855,6 @@
1849#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c 1855#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
1850/* [RW 24] CID for port 0 if no match */ 1856/* [RW 24] CID for port 0 if no match */
1851#define PRS_REG_CID_PORT_0 0x400fc 1857#define PRS_REG_CID_PORT_0 0x400fc
1852#define PRS_REG_CID_PORT_1 0x40100
1853/* [RW 32] The CM header for flush message where 'load existed' bit in CFC 1858/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1854 load response is reset and packet type is 0. Used in packet start message 1859 load response is reset and packet type is 0. Used in packet start message
1855 to TCM. */ 1860 to TCM. */
@@ -1957,6 +1962,10 @@
1957#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c 1962#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
1958/* [R 7] Debug only: Number of used entries in the header FIFO */ 1963/* [R 7] Debug only: Number of used entries in the header FIFO */
1959#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478 1964#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
1965#define PXP2_REG_PGL_ADDR_88_F0 0x120534
1966#define PXP2_REG_PGL_ADDR_8C_F0 0x120538
1967#define PXP2_REG_PGL_ADDR_90_F0 0x12053c
1968#define PXP2_REG_PGL_ADDR_94_F0 0x120540
1960#define PXP2_REG_PGL_CONTROL0 0x120490 1969#define PXP2_REG_PGL_CONTROL0 0x120490
1961#define PXP2_REG_PGL_CONTROL1 0x120514 1970#define PXP2_REG_PGL_CONTROL1 0x120514
1962/* [RW 32] third dword data of expansion rom request. this register is 1971/* [RW 32] third dword data of expansion rom request. this register is
@@ -2060,12 +2069,13 @@
2060#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054 2069#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
2061#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c 2070#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
2062#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0 2071#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
2063/* [RW 25] Interrupt mask register #0 read/write */ 2072/* [RW 32] Interrupt mask register #0 read/write */
2064#define PXP2_REG_PXP2_INT_MASK 0x120578 2073#define PXP2_REG_PXP2_INT_MASK_0 0x120578
2065/* [R 25] Interrupt register #0 read */ 2074/* [R 32] Interrupt register #0 read */
2066#define PXP2_REG_PXP2_INT_STS 0x12056c 2075#define PXP2_REG_PXP2_INT_STS_0 0x12056c
2067/* [RC 25] Interrupt register #0 read clear */ 2076#define PXP2_REG_PXP2_INT_STS_1 0x120608
2068#define PXP2_REG_PXP2_INT_STS_CLR 0x120570 2077/* [RC 32] Interrupt register #0 read clear */
2078#define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
2069/* [RW 32] Parity mask register #0 read/write */ 2079/* [RW 32] Parity mask register #0 read/write */
2070#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588 2080#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
2071#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598 2081#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
@@ -2811,22 +2821,6 @@
2811#define QM_REG_QVOQIDX_97 0x16e490 2821#define QM_REG_QVOQIDX_97 0x16e490
2812#define QM_REG_QVOQIDX_98 0x16e494 2822#define QM_REG_QVOQIDX_98 0x16e494
2813#define QM_REG_QVOQIDX_99 0x16e498 2823#define QM_REG_QVOQIDX_99 0x16e498
2814/* [R 24] Remaining pause timeout for queues 15-0 */
2815#define QM_REG_REMAINPAUSETM0 0x168418
2816/* [R 24] Remaining pause timeout for queues 31-16 */
2817#define QM_REG_REMAINPAUSETM1 0x16841c
2818/* [R 24] Remaining pause timeout for queues 47-32 */
2819#define QM_REG_REMAINPAUSETM2 0x16e69c
2820/* [R 24] Remaining pause timeout for queues 63-48 */
2821#define QM_REG_REMAINPAUSETM3 0x16e6a0
2822/* [R 24] Remaining pause timeout for queues 79-64 */
2823#define QM_REG_REMAINPAUSETM4 0x16e6a4
2824/* [R 24] Remaining pause timeout for queues 95-80 */
2825#define QM_REG_REMAINPAUSETM5 0x16e6a8
2826/* [R 24] Remaining pause timeout for queues 111-96 */
2827#define QM_REG_REMAINPAUSETM6 0x16e6ac
2828/* [R 24] Remaining pause timeout for queues 127-112 */
2829#define QM_REG_REMAINPAUSETM7 0x16e6b0
2830/* [RW 1] Initialization bit command */ 2824/* [RW 1] Initialization bit command */
2831#define QM_REG_SOFT_RESET 0x168428 2825#define QM_REG_SOFT_RESET 0x168428
2832/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */ 2826/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
@@ -3826,7 +3820,6 @@
3826/* [RW 15] Interrupt table Read and write access to it is not possible in 3820/* [RW 15] Interrupt table Read and write access to it is not possible in
3827 the middle of the work */ 3821 the middle of the work */
3828#define TSEM_REG_INT_TABLE 0x180400 3822#define TSEM_REG_INT_TABLE 0x180400
3829#define TSEM_REG_INT_TABLE_SIZE 256
3830/* [ST 24] Statistics register. The number of messages that entered through 3823/* [ST 24] Statistics register. The number of messages that entered through
3831 FIC0 */ 3824 FIC0 */
3832#define TSEM_REG_MSG_NUM_FIC0 0x180000 3825#define TSEM_REG_MSG_NUM_FIC0 0x180000
@@ -4283,7 +4276,6 @@
4283/* [RW 15] Interrupt table Read and write access to it is not possible in 4276/* [RW 15] Interrupt table Read and write access to it is not possible in
4284 the middle of the work */ 4277 the middle of the work */
4285#define USEM_REG_INT_TABLE 0x300400 4278#define USEM_REG_INT_TABLE 0x300400
4286#define USEM_REG_INT_TABLE_SIZE 256
4287/* [ST 24] Statistics register. The number of messages that entered through 4279/* [ST 24] Statistics register. The number of messages that entered through
4288 FIC0 */ 4280 FIC0 */
4289#define USEM_REG_MSG_NUM_FIC0 0x300000 4281#define USEM_REG_MSG_NUM_FIC0 0x300000
@@ -4802,7 +4794,6 @@
4802/* [RW 15] Interrupt table Read and write access to it is not possible in 4794/* [RW 15] Interrupt table Read and write access to it is not possible in
4803 the middle of the work */ 4795 the middle of the work */
4804#define XSEM_REG_INT_TABLE 0x280400 4796#define XSEM_REG_INT_TABLE 0x280400
4805#define XSEM_REG_INT_TABLE_SIZE 256
4806/* [ST 24] Statistics register. The number of messages that entered through 4797/* [ST 24] Statistics register. The number of messages that entered through
4807 FIC0 */ 4798 FIC0 */
4808#define XSEM_REG_MSG_NUM_FIC0 0x280000 4799#define XSEM_REG_MSG_NUM_FIC0 0x280000
@@ -4930,10 +4921,7 @@
4930#define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16) 4921#define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
4931#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 4922#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
4932#define EMAC_MODE_25G_MODE (1L<<5) 4923#define EMAC_MODE_25G_MODE (1L<<5)
4933#define EMAC_MODE_ACPI_RCVD (1L<<20)
4934#define EMAC_MODE_HALF_DUPLEX (1L<<1) 4924#define EMAC_MODE_HALF_DUPLEX (1L<<1)
4935#define EMAC_MODE_MPKT (1L<<18)
4936#define EMAC_MODE_MPKT_RCVD (1L<<19)
4937#define EMAC_MODE_PORT_GMII (2L<<2) 4925#define EMAC_MODE_PORT_GMII (2L<<2)
4938#define EMAC_MODE_PORT_MII (1L<<2) 4926#define EMAC_MODE_PORT_MII (1L<<2)
4939#define EMAC_MODE_PORT_MII_10M (3L<<2) 4927#define EMAC_MODE_PORT_MII_10M (3L<<2)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 18:13:04 -0500