1 files changed, 145 insertions, 2 deletions
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index d084e5fc4b51..fc957fa5c249 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -125,6 +125,10 @@
   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
   prioritised); 2 stands for weight 2; tc. */
 #define CCM_REG_CQM_P_WEIGHT                                     0xd00b8
+/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
+   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define CCM_REG_CQM_S_WEIGHT                                     0xd00bc
 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
   acknowledge output is deasserted; all other signals are treated as usual;
   if 1 - normal activity. */
@@ -132,6 +136,10 @@
 /* [RC 1] Set when the message length mismatch (relative to last indication)
   at the SDM interface is detected. */
 #define CCM_REG_CSDM_LENGTH_MIS                                  0xd0170
+/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define CCM_REG_CSDM_WEIGHT                                      0xd00b4
 /* [RW 28] The CM header for QM formatting in case of an error in the QM
   inputs. */
 #define CCM_REG_ERR_CCM_HDR                                      0xd0094
@@ -211,6 +219,11 @@
 /* [RC 1] Set when the message length mismatch (relative to last indication)
   at the STORM interface is detected. */
 #define CCM_REG_STORM_LENGTH_MIS                                 0xd016c
+/* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
+   mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
+   weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
+   tc. */
+#define CCM_REG_STORM_WEIGHT                                     0xd009c
 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
   disregarded; acknowledge output is deasserted; all other signals are
   treated as usual; if 1 - normal activity. */
@@ -323,7 +336,11 @@
   set one of these bits. the bit description can be found in CFC
   specifications */
 #define CFC_REG_ERROR_VECTOR                                     0x10403c
+/* [WB 93] LCID info ram access */
+#define CFC_REG_INFO_RAM                                         0x105000
+#define CFC_REG_INFO_RAM_SIZE                                    1024
 #define CFC_REG_INIT_REG                                         0x10404c
+#define CFC_REG_INTERFACES                                       0x104058
 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
   field allows changing the priorities of the weighted-round-robin arbiter
   which selects which CFC load client should be served next */
@@ -337,8 +354,6 @@
 #define CFC_REG_NUM_LCIDS_ALLOC                                  0x104020
 /* [R 9] Number of Arriving LCIDs in Link List Block */
 #define CFC_REG_NUM_LCIDS_ARRIVING                               0x104004
-/* [R 9] Number of Inside LCIDs in Link List Block */
-#define CFC_REG_NUM_LCIDS_INSIDE                                 0x104008
 /* [R 9] Number of Leaving LCIDs in Link List Block */
 #define CFC_REG_NUM_LCIDS_LEAVING                                0x104018
 /* [RW 8] The event id for aggregated interrupt 0 */
@@ -1554,6 +1569,14 @@
   command bit is written. This bit is set when the SPIO input does not
   match the current value in #OLD_VALUE (reset value 0). */
 #define MISC_REG_SPIO_INT                                        0xa500
+/* [RW 32] reload value for counter 4 if reload; the value will be reload if
+   the counter reached zero and the reload bit
+   (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
+#define MISC_REG_SW_TIMER_RELOAD_VAL_4                           0xa2fc
+/* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
+   in this register. addres 0 - timer 1; address - timer 2�address 7 -
+   timer 8 */
+#define MISC_REG_SW_TIMER_VAL                                    0xa5c0
 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
   loaded; 0-prepare; -unprepare */
 #define MISC_REG_UNPREPARED                                      0xa424
@@ -1885,6 +1908,7 @@
 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2                         0x400e4
 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3                         0x400e8
 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4                         0x400ec
+#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5                         0x400f0
 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
   load response is set and packet type is 0. Used in packet start message
   to TCM. */
@@ -1893,6 +1917,7 @@
 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2                      0x400c4
 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3                      0x400c8
 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4                      0x400cc
+#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5                      0x400d0
 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
   Used in packet start message to TCM. */
 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1                           0x4009c
@@ -2498,6 +2523,11 @@
   considered zero so practically there are only 20 bits in this register;
   queues 63-0 */
 #define QM_REG_BASEADDR                                          0x168900
+/* [RW 32] The base logical address (in bytes) of each physical queue. The
+   index I represents the physical queue number. The 12 lsbs are ignore and
+   considered zero so practically there are only 20 bits in this register;
+   queues 127-64 */
+#define QM_REG_BASEADDR_EXT_A                                    0x16e100
 /* [RW 16] The byte credit cost for each task. This value is for both ports */
 #define QM_REG_BYTECRDCOST                                       0x168234
 /* [RW 16] The initial byte credit value for both ports. */
@@ -3438,6 +3468,16 @@
 #define SRC_REG_KEYRSS0_0                                        0x40408
 #define SRC_REG_KEYRSS0_7                                        0x40424
 #define SRC_REG_KEYRSS1_9                                        0x40454
+#define SRC_REG_KEYSEARCH_0                                      0x40458
+#define SRC_REG_KEYSEARCH_1                                      0x4045c
+#define SRC_REG_KEYSEARCH_2                                      0x40460
+#define SRC_REG_KEYSEARCH_3                                      0x40464
+#define SRC_REG_KEYSEARCH_4                                      0x40468
+#define SRC_REG_KEYSEARCH_5                                      0x4046c
+#define SRC_REG_KEYSEARCH_6                                      0x40470
+#define SRC_REG_KEYSEARCH_7                                      0x40474
+#define SRC_REG_KEYSEARCH_8                                      0x40478
+#define SRC_REG_KEYSEARCH_9                                      0x4047c
 #define SRC_REG_LASTFREE0                                        0x40530
 #define SRC_REG_NUMBER_HASH_BITS0                                0x40400
 /* [RW 1] Reset internal state machines. */
@@ -3481,6 +3521,10 @@
 /* [RC 1] Message length mismatch (relative to last indication) at the In#9
   interface. */
 #define TCM_REG_CSEM_LENGTH_MIS                                  0x50174
+/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define TCM_REG_CSEM_WEIGHT                                      0x500bc
 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
 #define TCM_REG_ERR_EVNT_ID                                      0x500a0
 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
@@ -3524,6 +3568,7 @@
 #define TCM_REG_N_SM_CTX_LD_2                                    0x50058
 #define TCM_REG_N_SM_CTX_LD_3                                    0x5005c
 #define TCM_REG_N_SM_CTX_LD_4                                    0x50060
+#define TCM_REG_N_SM_CTX_LD_5                                    0x50064
 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
   acknowledge output is deasserted; all other signals are treated as usual;
   if 1 - normal activity. */
@@ -3563,6 +3608,10 @@
   disregarded; acknowledge output is deasserted; all other signals are
   treated as usual; if 1 - normal activity. */
 #define TCM_REG_STORM_TCM_IFEN                                   0x50010
+/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define TCM_REG_STORM_WEIGHT                                     0x500ac
 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
   acknowledge output is deasserted; all other signals are treated as usual;
   if 1 - normal activity. */
@@ -3598,10 +3647,22 @@
   disregarded; acknowledge output is deasserted; all other signals are
   treated as usual; if 1 - normal activity. */
 #define TCM_REG_TM_TCM_IFEN                                      0x5001c
+/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define TCM_REG_TM_WEIGHT                                        0x500d0
 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
   the initial credit value; read returns the current value of the credit
   counter. Must be initialized to 32 at start-up. */
 #define TCM_REG_TQM_INIT_CRD                                     0x5021c
+/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
+   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define TCM_REG_TQM_P_WEIGHT                                     0x500c8
+/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
+   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define TCM_REG_TQM_S_WEIGHT                                     0x500cc
 /* [RW 28] The CM header value for QM request (primary). */
 #define TCM_REG_TQM_TCM_HDR_P                                    0x50090
 /* [RW 28] The CM header value for QM request (secondary). */
@@ -3628,6 +3689,10 @@
 /* [RC 1] Message length mismatch (relative to last indication) at the In#8
   interface. */
 #define TCM_REG_USEM_LENGTH_MIS                                  0x50170
+/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define TCM_REG_USEM_WEIGHT                                      0x500b8
 /* [RW 21] Indirect access to the descriptor table of the XX protection
   mechanism. The fields are: [5:0] - length of the message; 15:6] - message
   pointer; 20:16] - next pointer. */
@@ -3677,6 +3742,7 @@
 #define TM_REG_EN_CL1_INPUT                                      0x16400c
 /* [RW 1] Enable client2 input. */
 #define TM_REG_EN_CL2_INPUT                                      0x164010
+#define TM_REG_EN_LINEAR0_TIMER                                  0x164014
 /* [RW 1] Enable real time counter. */
 #define TM_REG_EN_REAL_TIME_CNT                                  0x1640d8
 /* [RW 1] Enable for Timers state machines. */
@@ -3684,14 +3750,22 @@
 /* [RW 4] Load value for expiration credit cnt. CFC max number of
   outstanding load requests for timers (expiration) context loading. */
 #define TM_REG_EXP_CRDCNT_VAL                                    0x164238
+/* [RW 32] Linear0 logic address. */
+#define TM_REG_LIN0_LOGIC_ADDR                                   0x164240
 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
 #define TM_REG_LIN0_MAX_ACTIVE_CID                               0x164048
 /* [WB 64] Linear0 phy address. */
 #define TM_REG_LIN0_PHY_ADDR                                     0x164270
+/* [RW 1] Linear0 physical address valid. */
+#define TM_REG_LIN0_PHY_ADDR_VALID                               0x164248
 /* [RW 24] Linear0 array scan timeout. */
 #define TM_REG_LIN0_SCAN_TIME                                    0x16403c
+/* [RW 32] Linear1 logic address. */
+#define TM_REG_LIN1_LOGIC_ADDR                                   0x164250
 /* [WB 64] Linear1 phy address. */
 #define TM_REG_LIN1_PHY_ADDR                                     0x164280
+/* [RW 1] Linear1 physical address valid. */
+#define TM_REG_LIN1_PHY_ADDR_VALID                               0x164258
 /* [RW 6] Linear timer set_clear fifo threshold. */
 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR                        0x164070
 /* [RW 2] Load value for pci arbiter credit cnt. */
@@ -3708,6 +3782,17 @@
 #define TM_REG_TM_INT_STS                                        0x1640f0
 /* [RW 8] The event id for aggregated interrupt 0 */
 #define TSDM_REG_AGG_INT_EVENT_0                                 0x42038
+#define TSDM_REG_AGG_INT_EVENT_1                                 0x4203c
+#define TSDM_REG_AGG_INT_EVENT_10                                0x42060
+#define TSDM_REG_AGG_INT_EVENT_11                                0x42064
+#define TSDM_REG_AGG_INT_EVENT_12                                0x42068
+#define TSDM_REG_AGG_INT_EVENT_13                                0x4206c
+#define TSDM_REG_AGG_INT_EVENT_14                                0x42070
+#define TSDM_REG_AGG_INT_EVENT_15                                0x42074
+#define TSDM_REG_AGG_INT_EVENT_16                                0x42078
+#define TSDM_REG_AGG_INT_EVENT_17                                0x4207c
+#define TSDM_REG_AGG_INT_EVENT_18                                0x42080
+#define TSDM_REG_AGG_INT_EVENT_19                                0x42084
 #define TSDM_REG_AGG_INT_EVENT_2                                 0x42040
 #define TSDM_REG_AGG_INT_EVENT_20                                0x42088
 #define TSDM_REG_AGG_INT_EVENT_21                                0x4208c
@@ -3723,6 +3808,19 @@
 #define TSDM_REG_AGG_INT_EVENT_30                                0x420b0
 #define TSDM_REG_AGG_INT_EVENT_31                                0x420b4
 #define TSDM_REG_AGG_INT_EVENT_4                                 0x42048
+/* [RW 1] The T bit for aggregated interrupt 0 */
+#define TSDM_REG_AGG_INT_T_0                                     0x420b8
+#define TSDM_REG_AGG_INT_T_1                                     0x420bc
+#define TSDM_REG_AGG_INT_T_10                                    0x420e0
+#define TSDM_REG_AGG_INT_T_11                                    0x420e4
+#define TSDM_REG_AGG_INT_T_12                                    0x420e8
+#define TSDM_REG_AGG_INT_T_13                                    0x420ec
+#define TSDM_REG_AGG_INT_T_14                                    0x420f0
+#define TSDM_REG_AGG_INT_T_15                                    0x420f4
+#define TSDM_REG_AGG_INT_T_16                                    0x420f8
+#define TSDM_REG_AGG_INT_T_17                                    0x420fc
+#define TSDM_REG_AGG_INT_T_18                                    0x42100
+#define TSDM_REG_AGG_INT_T_19                                    0x42104
 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
 #define TSDM_REG_CFC_RSP_START_ADDR                              0x42008
 /* [RW 16] The maximum value of the competion counter #0 */
@@ -3967,6 +4065,10 @@
 /* [RC 1] Set when the message length mismatch (relative to last indication)
   at the dorq interface is detected. */
 #define UCM_REG_DORQ_LENGTH_MIS                                  0xe0168
+/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define UCM_REG_DORQ_WEIGHT                                      0xe00c0
 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
 #define UCM_REG_ERR_EVNT_ID                                      0xe00a4
 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
@@ -4030,6 +4132,10 @@
   disregarded; acknowledge output is deasserted; all other signals are
   treated as usual; if 1 - normal activity. */
 #define UCM_REG_STORM_UCM_IFEN                                   0xe0010
+/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define UCM_REG_STORM_WEIGHT                                     0xe00b0
 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
   writes the initial credit value; read returns the current value of the
   credit counter. Must be initialized to 4 at start-up. */
@@ -4040,6 +4146,10 @@
   disregarded; acknowledge output is deasserted; all other signals are
   treated as usual; if 1 - normal activity. */
 #define UCM_REG_TM_UCM_IFEN                                      0xe001c
+/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define UCM_REG_TM_WEIGHT                                        0xe00d4
 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
   disregarded; acknowledge output is deasserted; all other signals are
   treated as usual; if 1 - normal activity. */
@@ -4092,6 +4202,10 @@
   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
   prioritised); 2 stands for weight 2; tc. */
 #define UCM_REG_UQM_P_WEIGHT                                     0xe00cc
+/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
+   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define UCM_REG_UQM_S_WEIGHT                                     0xe00d0
 /* [RW 28] The CM header value for QM request (primary). */
 #define UCM_REG_UQM_UCM_HDR_P                                    0xe0094
 /* [RW 28] The CM header value for QM request (secondary). */
@@ -4107,6 +4221,10 @@
 /* [RC 1] Set when the message length mismatch (relative to last indication)
   at the SDM interface is detected. */
 #define UCM_REG_USDM_LENGTH_MIS                                  0xe0158
+/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define UCM_REG_USDM_WEIGHT                                      0xe00c8
 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
   disregarded; acknowledge output is deasserted; all other signals are
   treated as usual; if 1 - normal activity. */
@@ -4114,6 +4232,10 @@
 /* [RC 1] Set when the message length mismatch (relative to last indication)
   at the xsem interface isdetected. */
 #define UCM_REG_XSEM_LENGTH_MIS                                  0xe0164
+/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define UCM_REG_XSEM_WEIGHT                                      0xe00bc
 /* [RW 20] Indirect access to the descriptor table of the XX protection
   mechanism. The fields are:[5:0] - message length; 14:6] - message
   pointer; 19:15] - next pointer. */
@@ -4163,6 +4285,7 @@
 #define USDM_REG_AGG_INT_EVENT_30                                0xc40b0
 #define USDM_REG_AGG_INT_EVENT_31                                0xc40b4
 #define USDM_REG_AGG_INT_EVENT_4                                 0xc4048
+#define USDM_REG_AGG_INT_EVENT_5                                 0xc404c
 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
   or auto-mask-mode (1) */
 #define USDM_REG_AGG_INT_MODE_0                                  0xc41b8
@@ -4177,6 +4300,8 @@
 #define USDM_REG_AGG_INT_MODE_17                                 0xc41fc
 #define USDM_REG_AGG_INT_MODE_18                                 0xc4200
 #define USDM_REG_AGG_INT_MODE_19                                 0xc4204
+#define USDM_REG_AGG_INT_MODE_4                                  0xc41c8
+#define USDM_REG_AGG_INT_MODE_5                                  0xc41cc
 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
 #define USDM_REG_CFC_RSP_START_ADDR                              0xc4008
 /* [RW 16] The maximum value of the competion counter #0 */
@@ -4427,6 +4552,10 @@
 /* [RC 1] Set at message length mismatch (relative to last indication) at
   the dorq interface. */
 #define XCM_REG_DORQ_LENGTH_MIS                                  0x20230
+/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define XCM_REG_DORQ_WEIGHT                                      0x200cc
 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
 #define XCM_REG_ERR_EVNT_ID                                      0x200b0
 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
@@ -4465,6 +4594,10 @@
 /* [RC 1] Set at message length mismatch (relative to last indication) at
   the nig0 interface. */
 #define XCM_REG_NIG0_LENGTH_MIS                                  0x20238
+/* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define XCM_REG_NIG0_WEIGHT                                      0x200d4
 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
   disregarded; acknowledge output is deasserted; all other signals are
   treated as usual; if 1 - normal activity. */
@@ -4523,6 +4656,10 @@
   writes the initial credit value; read returns the current value of the
   credit counter. Must be initialized to 4 at start-up. */
 #define XCM_REG_TM_INIT_CRD                                      0x2041c
+/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define XCM_REG_TM_WEIGHT                                        0x200ec
 /* [RW 28] The CM header for Timers expiration command. */
 #define XCM_REG_TM_XCM_HDR                                       0x200a8
 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
@@ -4608,6 +4745,10 @@
   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
   prioritised); 2 stands for weight 2; tc. */
 #define XCM_REG_XQM_P_WEIGHT                                     0x200e4
+/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
+   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define XCM_REG_XQM_S_WEIGHT                                     0x200e8
 /* [RW 28] The CM header value for QM request (primary). */
 #define XCM_REG_XQM_XCM_HDR_P                                    0x200a0
 /* [RW 28] The CM header value for QM request (secondary). */
@@ -4665,6 +4806,8 @@
 #define XSDM_REG_AGG_INT_EVENT_10                                0x166060
 #define XSDM_REG_AGG_INT_EVENT_11                                0x166064
 #define XSDM_REG_AGG_INT_EVENT_12                                0x166068
+#define XSDM_REG_AGG_INT_EVENT_13                                0x16606c
+#define XSDM_REG_AGG_INT_EVENT_14                                0x166070
 #define XSDM_REG_AGG_INT_EVENT_2                                 0x166040
 #define XSDM_REG_AGG_INT_EVENT_20                                0x166088
 #define XSDM_REG_AGG_INT_EVENT_21                                0x16608c