diff options
Diffstat (limited to 'drivers/net/bnx2x_main.c')
-rw-r--r-- | drivers/net/bnx2x_main.c | 42 |
1 files changed, 24 insertions, 18 deletions
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c index 3e86ff4f4d45..c8b61788abb8 100644 --- a/drivers/net/bnx2x_main.c +++ b/drivers/net/bnx2x_main.c | |||
@@ -2450,20 +2450,25 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |||
2450 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | 2450 | MISC_REG_AEU_MASK_ATTN_FUNC_0; |
2451 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : | 2451 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
2452 | NIG_REG_MASK_INTERRUPT_PORT0; | 2452 | NIG_REG_MASK_INTERRUPT_PORT0; |
2453 | u32 aeu_mask; | ||
2453 | 2454 | ||
2454 | if (~bp->aeu_mask & (asserted & 0xff)) | ||
2455 | BNX2X_ERR("IGU ERROR\n"); | ||
2456 | if (bp->attn_state & asserted) | 2455 | if (bp->attn_state & asserted) |
2457 | BNX2X_ERR("IGU ERROR\n"); | 2456 | BNX2X_ERR("IGU ERROR\n"); |
2458 | 2457 | ||
2458 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | ||
2459 | aeu_mask = REG_RD(bp, aeu_addr); | ||
2460 | |||
2459 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", | 2461 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
2460 | bp->aeu_mask, asserted); | 2462 | aeu_mask, asserted); |
2461 | bp->aeu_mask &= ~(asserted & 0xff); | 2463 | aeu_mask &= ~(asserted & 0xff); |
2462 | DP(NETIF_MSG_HW, "after masking: aeu_mask %x\n", bp->aeu_mask); | 2464 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
2463 | 2465 | ||
2464 | REG_WR(bp, aeu_addr, bp->aeu_mask); | 2466 | REG_WR(bp, aeu_addr, aeu_mask); |
2467 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | ||
2465 | 2468 | ||
2469 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | ||
2466 | bp->attn_state |= asserted; | 2470 | bp->attn_state |= asserted; |
2471 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); | ||
2467 | 2472 | ||
2468 | if (asserted & ATTN_HARD_WIRED_MASK) { | 2473 | if (asserted & ATTN_HARD_WIRED_MASK) { |
2469 | if (asserted & ATTN_NIG_FOR_FUNC) { | 2474 | if (asserted & ATTN_NIG_FOR_FUNC) { |
@@ -2717,6 +2722,7 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) | |||
2717 | int index; | 2722 | int index; |
2718 | u32 reg_addr; | 2723 | u32 reg_addr; |
2719 | u32 val; | 2724 | u32 val; |
2725 | u32 aeu_mask; | ||
2720 | 2726 | ||
2721 | /* need to take HW lock because MCP or other port might also | 2727 | /* need to take HW lock because MCP or other port might also |
2722 | try to handle this event */ | 2728 | try to handle this event */ |
@@ -2761,23 +2767,26 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) | |||
2761 | reg_addr = (IGU_ADDR_ATTN_BITS_CLR + IGU_FUNC_BASE * BP_FUNC(bp)) * 8; | 2767 | reg_addr = (IGU_ADDR_ATTN_BITS_CLR + IGU_FUNC_BASE * BP_FUNC(bp)) * 8; |
2762 | 2768 | ||
2763 | val = ~deasserted; | 2769 | val = ~deasserted; |
2764 | /* DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", | 2770 | DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n", |
2765 | val, BAR_IGU_INTMEM + reg_addr); */ | 2771 | val, reg_addr); |
2766 | REG_WR(bp, BAR_IGU_INTMEM + reg_addr, val); | 2772 | REG_WR(bp, BAR_IGU_INTMEM + reg_addr, val); |
2767 | 2773 | ||
2768 | if (bp->aeu_mask & (deasserted & 0xff)) | ||
2769 | BNX2X_ERR("IGU BUG!\n"); | ||
2770 | if (~bp->attn_state & deasserted) | 2774 | if (~bp->attn_state & deasserted) |
2771 | BNX2X_ERR("IGU BUG!\n"); | 2775 | BNX2X_ERR("IGU ERROR\n"); |
2772 | 2776 | ||
2773 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | 2777 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
2774 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | 2778 | MISC_REG_AEU_MASK_ATTN_FUNC_0; |
2775 | 2779 | ||
2776 | DP(NETIF_MSG_HW, "aeu_mask %x\n", bp->aeu_mask); | 2780 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
2777 | bp->aeu_mask |= (deasserted & 0xff); | 2781 | aeu_mask = REG_RD(bp, reg_addr); |
2782 | |||
2783 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", | ||
2784 | aeu_mask, deasserted); | ||
2785 | aeu_mask |= (deasserted & 0xff); | ||
2786 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); | ||
2778 | 2787 | ||
2779 | DP(NETIF_MSG_HW, "new mask %x\n", bp->aeu_mask); | 2788 | REG_WR(bp, reg_addr, aeu_mask); |
2780 | REG_WR(bp, reg_addr, bp->aeu_mask); | 2789 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
2781 | 2790 | ||
2782 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | 2791 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
2783 | bp->attn_state &= ~deasserted; | 2792 | bp->attn_state &= ~deasserted; |
@@ -4083,9 +4092,6 @@ static void bnx2x_init_def_sb(struct bnx2x *bp, | |||
4083 | reg_offset + 0xc + 0x10*index); | 4092 | reg_offset + 0xc + 0x10*index); |
4084 | } | 4093 | } |
4085 | 4094 | ||
4086 | bp->aeu_mask = REG_RD(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | ||
4087 | MISC_REG_AEU_MASK_ATTN_FUNC_0)); | ||
4088 | |||
4089 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : | 4095 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : |
4090 | HC_REG_ATTN_MSG0_ADDR_L); | 4096 | HC_REG_ATTN_MSG0_ADDR_L); |
4091 | 4097 | ||