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path: root/drivers/net/bnx2x_main.c
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Diffstat (limited to 'drivers/net/bnx2x_main.c')
-rw-r--r--drivers/net/bnx2x_main.c3097
1 files changed, 325 insertions, 2772 deletions
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index 70cba64732ca..7b547f03b565 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -61,6 +61,7 @@
61#include "bnx2x_reg.h" 61#include "bnx2x_reg.h"
62#include "bnx2x_fw_defs.h" 62#include "bnx2x_fw_defs.h"
63#include "bnx2x_hsi.h" 63#include "bnx2x_hsi.h"
64#include "bnx2x_link.h"
64#include "bnx2x.h" 65#include "bnx2x.h"
65#include "bnx2x_init.h" 66#include "bnx2x_init.h"
66 67
@@ -174,7 +175,7 @@ static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
174 REG_WR(bp, dmae_reg_go_c[idx], 1); 175 REG_WR(bp, dmae_reg_go_c[idx], 1);
175} 176}
176 177
177static void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, 178void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
178 u32 dst_addr, u32 len32) 179 u32 dst_addr, u32 len32)
179{ 180{
180 struct dmae_command *dmae = &bp->dmae; 181 struct dmae_command *dmae = &bp->dmae;
@@ -236,8 +237,7 @@ static void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
236 } 237 }
237} 238}
238 239
239#ifdef BNX2X_DMAE_RD 240void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
240static void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
241{ 241{
242 struct dmae_command *dmae = &bp->dmae; 242 struct dmae_command *dmae = &bp->dmae;
243 int port = bp->port; 243 int port = bp->port;
@@ -294,7 +294,6 @@ static void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
294 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 294 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
295*/ 295*/
296} 296}
297#endif
298 297
299static int bnx2x_mc_assert(struct bnx2x *bp) 298static int bnx2x_mc_assert(struct bnx2x *bp)
300{ 299{
@@ -1135,67 +1134,19 @@ static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1135 1134
1136/* end of fast path */ 1135/* end of fast path */
1137 1136
1138/* PHY/MAC */ 1137
1138/* Link */
1139 1139
1140/* 1140/*
1141 * General service functions 1141 * General service functions
1142 */ 1142 */
1143 1143
1144static void bnx2x_leds_set(struct bnx2x *bp, unsigned int speed)
1145{
1146 int port = bp->port;
1147
1148 NIG_WR(NIG_REG_LED_MODE_P0 + port*4,
1149 ((bp->hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
1150 SHARED_HW_CFG_LED_MODE_SHIFT));
1151 NIG_WR(NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
1152
1153 /* Set blinking rate to ~15.9Hz */
1154 NIG_WR(NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
1155 LED_BLINK_RATE_VAL);
1156 NIG_WR(NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port*4, 1);
1157
1158 /* On Ax chip versions for speeds less than 10G
1159 LED scheme is different */
1160 if ((CHIP_REV(bp) == CHIP_REV_Ax) && (speed < SPEED_10000)) {
1161 NIG_WR(NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 1);
1162 NIG_WR(NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4, 0);
1163 NIG_WR(NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + port*4, 1);
1164 }
1165}
1166
1167static void bnx2x_leds_unset(struct bnx2x *bp)
1168{
1169 int port = bp->port;
1170
1171 NIG_WR(NIG_REG_LED_10G_P0 + port*4, 0);
1172 NIG_WR(NIG_REG_LED_MODE_P0 + port*4, SHARED_HW_CFG_LED_MAC1);
1173}
1174
1175static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
1176{
1177 u32 val = REG_RD(bp, reg);
1178
1179 val |= bits;
1180 REG_WR(bp, reg, val);
1181 return val;
1182}
1183
1184static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
1185{
1186 u32 val = REG_RD(bp, reg);
1187
1188 val &= ~bits;
1189 REG_WR(bp, reg, val);
1190 return val;
1191}
1192
1193static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource) 1144static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1194{ 1145{
1195 u32 cnt;
1196 u32 lock_status; 1146 u32 lock_status;
1197 u32 resource_bit = (1 << resource); 1147 u32 resource_bit = (1 << resource);
1198 u8 func = bp->port; 1148 u8 port = bp->port;
1149 int cnt;
1199 1150
1200 /* Validating that the resource is within range */ 1151 /* Validating that the resource is within range */
1201 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1152 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
@@ -1206,7 +1157,7 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1206 } 1157 }
1207 1158
1208 /* Validating that the resource is not already taken */ 1159 /* Validating that the resource is not already taken */
1209 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8); 1160 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8);
1210 if (lock_status & resource_bit) { 1161 if (lock_status & resource_bit) {
1211 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1162 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1212 lock_status, resource_bit); 1163 lock_status, resource_bit);
@@ -1216,9 +1167,9 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1216 /* Try for 1 second every 5ms */ 1167 /* Try for 1 second every 5ms */
1217 for (cnt = 0; cnt < 200; cnt++) { 1168 for (cnt = 0; cnt < 200; cnt++) {
1218 /* Try to acquire the lock */ 1169 /* Try to acquire the lock */
1219 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + func*8 + 4, 1170 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + port*8 + 4,
1220 resource_bit); 1171 resource_bit);
1221 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8); 1172 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8);
1222 if (lock_status & resource_bit) 1173 if (lock_status & resource_bit)
1223 return 0; 1174 return 0;
1224 1175
@@ -1232,7 +1183,7 @@ static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource)
1232{ 1183{
1233 u32 lock_status; 1184 u32 lock_status;
1234 u32 resource_bit = (1 << resource); 1185 u32 resource_bit = (1 << resource);
1235 u8 func = bp->port; 1186 u8 port = bp->port;
1236 1187
1237 /* Validating that the resource is within range */ 1188 /* Validating that the resource is within range */
1238 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1189 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
@@ -1243,18 +1194,41 @@ static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource)
1243 } 1194 }
1244 1195
1245 /* Validating that the resource is currently taken */ 1196 /* Validating that the resource is currently taken */
1246 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8); 1197 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8);
1247 if (!(lock_status & resource_bit)) { 1198 if (!(lock_status & resource_bit)) {
1248 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1199 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1249 lock_status, resource_bit); 1200 lock_status, resource_bit);
1250 return -EFAULT; 1201 return -EFAULT;
1251 } 1202 }
1252 1203
1253 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + func*8, resource_bit); 1204 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + port*8, resource_bit);
1254 return 0; 1205 return 0;
1255} 1206}
1256 1207
1257static int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode) 1208/* HW Lock for shared dual port PHYs */
1209static void bnx2x_phy_hw_lock(struct bnx2x *bp)
1210{
1211 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1212
1213 mutex_lock(&bp->phy_mutex);
1214
1215 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1216 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1217 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1218}
1219
1220static void bnx2x_phy_hw_unlock(struct bnx2x *bp)
1221{
1222 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1223
1224 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1225 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1226 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1227
1228 mutex_unlock(&bp->phy_mutex);
1229}
1230
1231int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
1258{ 1232{
1259 /* The GPIO should be swapped if swap register is set and active */ 1233 /* The GPIO should be swapped if swap register is set and active */
1260 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1234 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
@@ -1353,1281 +1327,45 @@ static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1353 return 0; 1327 return 0;
1354} 1328}
1355 1329
1356static int bnx2x_mdio22_write(struct bnx2x *bp, u32 reg, u32 val) 1330static void bnx2x_calc_fc_adv(struct bnx2x *bp)
1357{
1358 int port = bp->port;
1359 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1360 u32 tmp;
1361 int i, rc;
1362
1363/* DP(NETIF_MSG_HW, "phy_addr 0x%x reg 0x%x val 0x%08x\n",
1364 bp->phy_addr, reg, val); */
1365
1366 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1367
1368 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1369 tmp &= ~EMAC_MDIO_MODE_AUTO_POLL;
1370 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
1371 REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1372 udelay(40);
1373 }
1374
1375 tmp = ((bp->phy_addr << 21) | (reg << 16) |
1376 (val & EMAC_MDIO_COMM_DATA) |
1377 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
1378 EMAC_MDIO_COMM_START_BUSY);
1379 EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, tmp);
1380
1381 for (i = 0; i < 50; i++) {
1382 udelay(10);
1383
1384 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM);
1385 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1386 udelay(5);
1387 break;
1388 }
1389 }
1390
1391 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1392 BNX2X_ERR("write phy register failed\n");
1393
1394 rc = -EBUSY;
1395 } else {
1396 rc = 0;
1397 }
1398
1399 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1400
1401 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1402 tmp |= EMAC_MDIO_MODE_AUTO_POLL;
1403 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
1404 }
1405
1406 return rc;
1407}
1408
1409static int bnx2x_mdio22_read(struct bnx2x *bp, u32 reg, u32 *ret_val)
1410{
1411 int port = bp->port;
1412 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1413 u32 val;
1414 int i, rc;
1415
1416 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1417
1418 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1419 val &= ~EMAC_MDIO_MODE_AUTO_POLL;
1420 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
1421 REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1422 udelay(40);
1423 }
1424
1425 val = ((bp->phy_addr << 21) | (reg << 16) |
1426 EMAC_MDIO_COMM_COMMAND_READ_22 |
1427 EMAC_MDIO_COMM_START_BUSY);
1428 EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, val);
1429
1430 for (i = 0; i < 50; i++) {
1431 udelay(10);
1432
1433 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM);
1434 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1435 val &= EMAC_MDIO_COMM_DATA;
1436 break;
1437 }
1438 }
1439
1440 if (val & EMAC_MDIO_COMM_START_BUSY) {
1441 BNX2X_ERR("read phy register failed\n");
1442
1443 *ret_val = 0x0;
1444 rc = -EBUSY;
1445 } else {
1446 *ret_val = val;
1447 rc = 0;
1448 }
1449
1450 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1451
1452 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1453 val |= EMAC_MDIO_MODE_AUTO_POLL;
1454 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
1455 }
1456
1457/* DP(NETIF_MSG_HW, "phy_addr 0x%x reg 0x%x ret_val 0x%08x\n",
1458 bp->phy_addr, reg, *ret_val); */
1459
1460 return rc;
1461}
1462
1463static int bnx2x_mdio45_ctrl_write(struct bnx2x *bp, u32 mdio_ctrl,
1464 u32 phy_addr, u32 reg, u32 addr, u32 val)
1465{
1466 u32 tmp;
1467 int i, rc = 0;
1468
1469 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
1470 * (a value of 49==0x31) and make sure that the AUTO poll is off
1471 */
1472 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1473 tmp &= ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1474 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
1475 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1476 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1477 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1478 udelay(40);
1479
1480 /* address */
1481 tmp = ((phy_addr << 21) | (reg << 16) | addr |
1482 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1483 EMAC_MDIO_COMM_START_BUSY);
1484 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1485
1486 for (i = 0; i < 50; i++) {
1487 udelay(10);
1488
1489 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1490 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1491 udelay(5);
1492 break;
1493 }
1494 }
1495 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1496 BNX2X_ERR("write phy register failed\n");
1497
1498 rc = -EBUSY;
1499
1500 } else {
1501 /* data */
1502 tmp = ((phy_addr << 21) | (reg << 16) | val |
1503 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
1504 EMAC_MDIO_COMM_START_BUSY);
1505 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1506
1507 for (i = 0; i < 50; i++) {
1508 udelay(10);
1509
1510 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1511 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1512 udelay(5);
1513 break;
1514 }
1515 }
1516
1517 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1518 BNX2X_ERR("write phy register failed\n");
1519
1520 rc = -EBUSY;
1521 }
1522 }
1523
1524 /* unset clause 45 mode, set the MDIO clock to a faster value
1525 * (0x13 => 6.25Mhz) and restore the AUTO poll if needed
1526 */
1527 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1528 tmp &= ~(EMAC_MDIO_MODE_CLAUSE_45 | EMAC_MDIO_MODE_CLOCK_CNT);
1529 tmp |= (0x13 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1530 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG)
1531 tmp |= EMAC_MDIO_MODE_AUTO_POLL;
1532 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1533
1534 return rc;
1535}
1536
1537static int bnx2x_mdio45_write(struct bnx2x *bp, u32 phy_addr, u32 reg,
1538 u32 addr, u32 val)
1539{
1540 u32 emac_base = bp->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1541
1542 return bnx2x_mdio45_ctrl_write(bp, emac_base, phy_addr,
1543 reg, addr, val);
1544}
1545
1546static int bnx2x_mdio45_ctrl_read(struct bnx2x *bp, u32 mdio_ctrl,
1547 u32 phy_addr, u32 reg, u32 addr,
1548 u32 *ret_val)
1549{
1550 u32 val;
1551 int i, rc = 0;
1552
1553 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
1554 * (a value of 49==0x31) and make sure that the AUTO poll is off
1555 */
1556 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1557 val &= ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1558 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
1559 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1560 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1561 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1562 udelay(40);
1563
1564 /* address */
1565 val = ((phy_addr << 21) | (reg << 16) | addr |
1566 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1567 EMAC_MDIO_COMM_START_BUSY);
1568 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1569
1570 for (i = 0; i < 50; i++) {
1571 udelay(10);
1572
1573 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1574 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1575 udelay(5);
1576 break;
1577 }
1578 }
1579 if (val & EMAC_MDIO_COMM_START_BUSY) {
1580 BNX2X_ERR("read phy register failed\n");
1581
1582 *ret_val = 0;
1583 rc = -EBUSY;
1584
1585 } else {
1586 /* data */
1587 val = ((phy_addr << 21) | (reg << 16) |
1588 EMAC_MDIO_COMM_COMMAND_READ_45 |
1589 EMAC_MDIO_COMM_START_BUSY);
1590 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1591
1592 for (i = 0; i < 50; i++) {
1593 udelay(10);
1594
1595 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1596 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1597 val &= EMAC_MDIO_COMM_DATA;
1598 break;
1599 }
1600 }
1601
1602 if (val & EMAC_MDIO_COMM_START_BUSY) {
1603 BNX2X_ERR("read phy register failed\n");
1604
1605 val = 0;
1606 rc = -EBUSY;
1607 }
1608
1609 *ret_val = val;
1610 }
1611
1612 /* unset clause 45 mode, set the MDIO clock to a faster value
1613 * (0x13 => 6.25Mhz) and restore the AUTO poll if needed
1614 */
1615 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1616 val &= ~(EMAC_MDIO_MODE_CLAUSE_45 | EMAC_MDIO_MODE_CLOCK_CNT);
1617 val |= (0x13 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1618 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG)
1619 val |= EMAC_MDIO_MODE_AUTO_POLL;
1620 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1621
1622 return rc;
1623}
1624
1625static int bnx2x_mdio45_read(struct bnx2x *bp, u32 phy_addr, u32 reg,
1626 u32 addr, u32 *ret_val)
1627{
1628 u32 emac_base = bp->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1629
1630 return bnx2x_mdio45_ctrl_read(bp, emac_base, phy_addr,
1631 reg, addr, ret_val);
1632}
1633
1634static int bnx2x_mdio45_vwrite(struct bnx2x *bp, u32 phy_addr, u32 reg,
1635 u32 addr, u32 val)
1636{
1637 int i;
1638 u32 rd_val;
1639
1640 might_sleep();
1641 for (i = 0; i < 10; i++) {
1642 bnx2x_mdio45_write(bp, phy_addr, reg, addr, val);
1643 msleep(5);
1644 bnx2x_mdio45_read(bp, phy_addr, reg, addr, &rd_val);
1645 /* if the read value is not the same as the value we wrote,
1646 we should write it again */
1647 if (rd_val == val)
1648 return 0;
1649 }
1650 BNX2X_ERR("MDIO write in CL45 failed\n");
1651 return -EBUSY;
1652}
1653
1654/*
1655 * link management
1656 */
1657
1658static void bnx2x_pause_resolve(struct bnx2x *bp, u32 pause_result)
1659{
1660 switch (pause_result) { /* ASYM P ASYM P */
1661 case 0xb: /* 1 0 1 1 */
1662 bp->flow_ctrl = FLOW_CTRL_TX;
1663 break;
1664
1665 case 0xe: /* 1 1 1 0 */
1666 bp->flow_ctrl = FLOW_CTRL_RX;
1667 break;
1668
1669 case 0x5: /* 0 1 0 1 */
1670 case 0x7: /* 0 1 1 1 */
1671 case 0xd: /* 1 1 0 1 */
1672 case 0xf: /* 1 1 1 1 */
1673 bp->flow_ctrl = FLOW_CTRL_BOTH;
1674 break;
1675
1676 default:
1677 break;
1678 }
1679}
1680
1681static u8 bnx2x_ext_phy_resove_fc(struct bnx2x *bp)
1682{
1683 u32 ext_phy_addr;
1684 u32 ld_pause; /* local */
1685 u32 lp_pause; /* link partner */
1686 u32 an_complete; /* AN complete */
1687 u32 pause_result;
1688 u8 ret = 0;
1689
1690 ext_phy_addr = ((bp->ext_phy_config &
1691 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1692 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1693
1694 /* read twice */
1695 bnx2x_mdio45_read(bp, ext_phy_addr,
1696 EXT_PHY_KR_AUTO_NEG_DEVAD,
1697 EXT_PHY_KR_STATUS, &an_complete);
1698 bnx2x_mdio45_read(bp, ext_phy_addr,
1699 EXT_PHY_KR_AUTO_NEG_DEVAD,
1700 EXT_PHY_KR_STATUS, &an_complete);
1701
1702 if (an_complete & EXT_PHY_KR_AUTO_NEG_COMPLETE) {
1703 ret = 1;
1704 bnx2x_mdio45_read(bp, ext_phy_addr,
1705 EXT_PHY_KR_AUTO_NEG_DEVAD,
1706 EXT_PHY_KR_AUTO_NEG_ADVERT, &ld_pause);
1707 bnx2x_mdio45_read(bp, ext_phy_addr,
1708 EXT_PHY_KR_AUTO_NEG_DEVAD,
1709 EXT_PHY_KR_LP_AUTO_NEG, &lp_pause);
1710 pause_result = (ld_pause &
1711 EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK) >> 8;
1712 pause_result |= (lp_pause &
1713 EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK) >> 10;
1714 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n",
1715 pause_result);
1716 bnx2x_pause_resolve(bp, pause_result);
1717 }
1718 return ret;
1719}
1720
1721static void bnx2x_flow_ctrl_resolve(struct bnx2x *bp, u32 gp_status)
1722{
1723 u32 ld_pause; /* local driver */
1724 u32 lp_pause; /* link partner */
1725 u32 pause_result;
1726
1727 bp->flow_ctrl = 0;
1728
1729 /* resolve from gp_status in case of AN complete and not sgmii */
1730 if ((bp->req_autoneg & AUTONEG_FLOW_CTRL) &&
1731 (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1732 (!(bp->phy_flags & PHY_SGMII_FLAG)) &&
1733 (XGXS_EXT_PHY_TYPE(bp) == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
1734
1735 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
1736 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1737 &ld_pause);
1738 bnx2x_mdio22_read(bp,
1739 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1740 &lp_pause);
1741 pause_result = (ld_pause &
1742 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
1743 pause_result |= (lp_pause &
1744 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
1745 DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result);
1746 bnx2x_pause_resolve(bp, pause_result);
1747 } else if (!(bp->req_autoneg & AUTONEG_FLOW_CTRL) ||
1748 !(bnx2x_ext_phy_resove_fc(bp))) {
1749 /* forced speed */
1750 if (bp->req_autoneg & AUTONEG_FLOW_CTRL) {
1751 switch (bp->req_flow_ctrl) {
1752 case FLOW_CTRL_AUTO:
1753 if (bp->dev->mtu <= 4500)
1754 bp->flow_ctrl = FLOW_CTRL_BOTH;
1755 else
1756 bp->flow_ctrl = FLOW_CTRL_TX;
1757 break;
1758
1759 case FLOW_CTRL_TX:
1760 bp->flow_ctrl = FLOW_CTRL_TX;
1761 break;
1762
1763 case FLOW_CTRL_RX:
1764 if (bp->dev->mtu <= 4500)
1765 bp->flow_ctrl = FLOW_CTRL_RX;
1766 break;
1767
1768 case FLOW_CTRL_BOTH:
1769 if (bp->dev->mtu <= 4500)
1770 bp->flow_ctrl = FLOW_CTRL_BOTH;
1771 else
1772 bp->flow_ctrl = FLOW_CTRL_TX;
1773 break;
1774
1775 case FLOW_CTRL_NONE:
1776 default:
1777 break;
1778 }
1779 } else { /* forced mode */
1780 switch (bp->req_flow_ctrl) {
1781 case FLOW_CTRL_AUTO:
1782 DP(NETIF_MSG_LINK, "req_flow_ctrl 0x%x while"
1783 " req_autoneg 0x%x\n",
1784 bp->req_flow_ctrl, bp->req_autoneg);
1785 break;
1786
1787 case FLOW_CTRL_TX:
1788 case FLOW_CTRL_RX:
1789 case FLOW_CTRL_BOTH:
1790 bp->flow_ctrl = bp->req_flow_ctrl;
1791 break;
1792
1793 case FLOW_CTRL_NONE:
1794 default:
1795 break;
1796 }
1797 }
1798 }
1799 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", bp->flow_ctrl);
1800}
1801
1802static void bnx2x_link_settings_status(struct bnx2x *bp, u32 gp_status)
1803{
1804 bp->link_status = 0;
1805
1806 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1807 DP(NETIF_MSG_LINK, "phy link up\n");
1808
1809 bp->phy_link_up = 1;
1810 bp->link_status |= LINK_STATUS_LINK_UP;
1811
1812 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
1813 bp->duplex = DUPLEX_FULL;
1814 else
1815 bp->duplex = DUPLEX_HALF;
1816
1817 bnx2x_flow_ctrl_resolve(bp, gp_status);
1818
1819 switch (gp_status & GP_STATUS_SPEED_MASK) {
1820 case GP_STATUS_10M:
1821 bp->line_speed = SPEED_10;
1822 if (bp->duplex == DUPLEX_FULL)
1823 bp->link_status |= LINK_10TFD;
1824 else
1825 bp->link_status |= LINK_10THD;
1826 break;
1827
1828 case GP_STATUS_100M:
1829 bp->line_speed = SPEED_100;
1830 if (bp->duplex == DUPLEX_FULL)
1831 bp->link_status |= LINK_100TXFD;
1832 else
1833 bp->link_status |= LINK_100TXHD;
1834 break;
1835
1836 case GP_STATUS_1G:
1837 case GP_STATUS_1G_KX:
1838 bp->line_speed = SPEED_1000;
1839 if (bp->duplex == DUPLEX_FULL)
1840 bp->link_status |= LINK_1000TFD;
1841 else
1842 bp->link_status |= LINK_1000THD;
1843 break;
1844
1845 case GP_STATUS_2_5G:
1846 bp->line_speed = SPEED_2500;
1847 if (bp->duplex == DUPLEX_FULL)
1848 bp->link_status |= LINK_2500TFD;
1849 else
1850 bp->link_status |= LINK_2500THD;
1851 break;
1852
1853 case GP_STATUS_5G:
1854 case GP_STATUS_6G:
1855 BNX2X_ERR("link speed unsupported gp_status 0x%x\n",
1856 gp_status);
1857 break;
1858
1859 case GP_STATUS_10G_KX4:
1860 case GP_STATUS_10G_HIG:
1861 case GP_STATUS_10G_CX4:
1862 bp->line_speed = SPEED_10000;
1863 bp->link_status |= LINK_10GTFD;
1864 break;
1865
1866 case GP_STATUS_12G_HIG:
1867 bp->line_speed = SPEED_12000;
1868 bp->link_status |= LINK_12GTFD;
1869 break;
1870
1871 case GP_STATUS_12_5G:
1872 bp->line_speed = SPEED_12500;
1873 bp->link_status |= LINK_12_5GTFD;
1874 break;
1875
1876 case GP_STATUS_13G:
1877 bp->line_speed = SPEED_13000;
1878 bp->link_status |= LINK_13GTFD;
1879 break;
1880
1881 case GP_STATUS_15G:
1882 bp->line_speed = SPEED_15000;
1883 bp->link_status |= LINK_15GTFD;
1884 break;
1885
1886 case GP_STATUS_16G:
1887 bp->line_speed = SPEED_16000;
1888 bp->link_status |= LINK_16GTFD;
1889 break;
1890
1891 default:
1892 BNX2X_ERR("link speed unsupported gp_status 0x%x\n",
1893 gp_status);
1894 break;
1895 }
1896
1897 bp->link_status |= LINK_STATUS_SERDES_LINK;
1898
1899 if (bp->req_autoneg & AUTONEG_SPEED) {
1900 bp->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
1901
1902 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
1903 bp->link_status |=
1904 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
1905
1906 if (bp->autoneg & AUTONEG_PARALLEL)
1907 bp->link_status |=
1908 LINK_STATUS_PARALLEL_DETECTION_USED;
1909 }
1910
1911 if (bp->flow_ctrl & FLOW_CTRL_TX)
1912 bp->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
1913
1914 if (bp->flow_ctrl & FLOW_CTRL_RX)
1915 bp->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
1916
1917 } else { /* link_down */
1918 DP(NETIF_MSG_LINK, "phy link down\n");
1919
1920 bp->phy_link_up = 0;
1921
1922 bp->line_speed = 0;
1923 bp->duplex = DUPLEX_FULL;
1924 bp->flow_ctrl = 0;
1925 }
1926
1927 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %d\n"
1928 DP_LEVEL " line_speed %d duplex %d flow_ctrl 0x%x"
1929 " link_status 0x%x\n",
1930 gp_status, bp->phy_link_up, bp->line_speed, bp->duplex,
1931 bp->flow_ctrl, bp->link_status);
1932}
1933
1934static void bnx2x_link_int_ack(struct bnx2x *bp, int is_10g)
1935{
1936 int port = bp->port;
1937
1938 /* first reset all status
1939 * we assume only one line will be change at a time */
1940 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1941 (NIG_STATUS_XGXS0_LINK10G |
1942 NIG_STATUS_XGXS0_LINK_STATUS |
1943 NIG_STATUS_SERDES0_LINK_STATUS));
1944 if (bp->phy_link_up) {
1945 if (is_10g) {
1946 /* Disable the 10G link interrupt
1947 * by writing 1 to the status register
1948 */
1949 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
1950 bnx2x_bits_en(bp,
1951 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1952 NIG_STATUS_XGXS0_LINK10G);
1953
1954 } else if (bp->phy_flags & PHY_XGXS_FLAG) {
1955 /* Disable the link interrupt
1956 * by writing 1 to the relevant lane
1957 * in the status register
1958 */
1959 DP(NETIF_MSG_LINK, "1G XGXS phy link up\n");
1960 bnx2x_bits_en(bp,
1961 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1962 ((1 << bp->ser_lane) <<
1963 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
1964
1965 } else { /* SerDes */
1966 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
1967 /* Disable the link interrupt
1968 * by writing 1 to the status register
1969 */
1970 bnx2x_bits_en(bp,
1971 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1972 NIG_STATUS_SERDES0_LINK_STATUS);
1973 }
1974
1975 } else { /* link_down */
1976 }
1977}
1978
1979static int bnx2x_ext_phy_is_link_up(struct bnx2x *bp)
1980{ 1331{
1981 u32 ext_phy_type; 1332 switch (bp->link_vars.ieee_fc) {
1982 u32 ext_phy_addr; 1333 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1983 u32 val1 = 0, val2; 1334 bp->advertising &= ~(ADVERTISED_Asym_Pause |
1984 u32 rx_sd, pcs_status; 1335 ADVERTISED_Pause);
1985
1986 if (bp->phy_flags & PHY_XGXS_FLAG) {
1987 ext_phy_addr = ((bp->ext_phy_config &
1988 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1989 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1990
1991 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
1992 switch (ext_phy_type) {
1993 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
1994 DP(NETIF_MSG_LINK, "XGXS Direct\n");
1995 val1 = 1;
1996 break;
1997
1998 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
1999 DP(NETIF_MSG_LINK, "XGXS 8705\n");
2000 bnx2x_mdio45_read(bp, ext_phy_addr,
2001 EXT_PHY_OPT_WIS_DEVAD,
2002 EXT_PHY_OPT_LASI_STATUS, &val1);
2003 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
2004
2005 bnx2x_mdio45_read(bp, ext_phy_addr,
2006 EXT_PHY_OPT_WIS_DEVAD,
2007 EXT_PHY_OPT_LASI_STATUS, &val1);
2008 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
2009
2010 bnx2x_mdio45_read(bp, ext_phy_addr,
2011 EXT_PHY_OPT_PMA_PMD_DEVAD,
2012 EXT_PHY_OPT_PMD_RX_SD, &rx_sd);
2013 DP(NETIF_MSG_LINK, "8705 rx_sd 0x%x\n", rx_sd);
2014 val1 = (rx_sd & 0x1);
2015 break;
2016
2017 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
2018 DP(NETIF_MSG_LINK, "XGXS 8706\n");
2019 bnx2x_mdio45_read(bp, ext_phy_addr,
2020 EXT_PHY_OPT_PMA_PMD_DEVAD,
2021 EXT_PHY_OPT_LASI_STATUS, &val1);
2022 DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1);
2023
2024 bnx2x_mdio45_read(bp, ext_phy_addr,
2025 EXT_PHY_OPT_PMA_PMD_DEVAD,
2026 EXT_PHY_OPT_LASI_STATUS, &val1);
2027 DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1);
2028
2029 bnx2x_mdio45_read(bp, ext_phy_addr,
2030 EXT_PHY_OPT_PMA_PMD_DEVAD,
2031 EXT_PHY_OPT_PMD_RX_SD, &rx_sd);
2032 bnx2x_mdio45_read(bp, ext_phy_addr,
2033 EXT_PHY_OPT_PCS_DEVAD,
2034 EXT_PHY_OPT_PCS_STATUS, &pcs_status);
2035 bnx2x_mdio45_read(bp, ext_phy_addr,
2036 EXT_PHY_AUTO_NEG_DEVAD,
2037 EXT_PHY_OPT_AN_LINK_STATUS, &val2);
2038
2039 DP(NETIF_MSG_LINK, "8706 rx_sd 0x%x"
2040 " pcs_status 0x%x 1Gbps link_status 0x%x 0x%x\n",
2041 rx_sd, pcs_status, val2, (val2 & (1<<1)));
2042 /* link is up if both bit 0 of pmd_rx_sd and
2043 * bit 0 of pcs_status are set, or if the autoneg bit
2044 1 is set
2045 */
2046 val1 = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
2047 break;
2048
2049 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
2050 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
2051
2052 /* clear the interrupt LASI status register */
2053 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2054 ext_phy_addr,
2055 EXT_PHY_KR_PCS_DEVAD,
2056 EXT_PHY_KR_LASI_STATUS, &val2);
2057 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2058 ext_phy_addr,
2059 EXT_PHY_KR_PCS_DEVAD,
2060 EXT_PHY_KR_LASI_STATUS, &val1);
2061 DP(NETIF_MSG_LINK, "KR LASI status 0x%x->0x%x\n",
2062 val2, val1);
2063 /* Check the LASI */
2064 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2065 ext_phy_addr,
2066 EXT_PHY_KR_PMA_PMD_DEVAD,
2067 0x9003, &val2);
2068 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2069 ext_phy_addr,
2070 EXT_PHY_KR_PMA_PMD_DEVAD,
2071 0x9003, &val1);
2072 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x->0x%x\n",
2073 val2, val1);
2074 /* Check the link status */
2075 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2076 ext_phy_addr,
2077 EXT_PHY_KR_PCS_DEVAD,
2078 EXT_PHY_KR_PCS_STATUS, &val2);
2079 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
2080 /* Check the link status on 1.1.2 */
2081 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2082 ext_phy_addr,
2083 EXT_PHY_OPT_PMA_PMD_DEVAD,
2084 EXT_PHY_KR_STATUS, &val2);
2085 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2086 ext_phy_addr,
2087 EXT_PHY_OPT_PMA_PMD_DEVAD,
2088 EXT_PHY_KR_STATUS, &val1);
2089 DP(NETIF_MSG_LINK,
2090 "KR PMA status 0x%x->0x%x\n", val2, val1);
2091 val1 = ((val1 & 4) == 4);
2092 /* If 1G was requested assume the link is up */
2093 if (!(bp->req_autoneg & AUTONEG_SPEED) &&
2094 (bp->req_line_speed == SPEED_1000))
2095 val1 = 1;
2096 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
2097 break;
2098
2099 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
2100 bnx2x_mdio45_read(bp, ext_phy_addr,
2101 EXT_PHY_OPT_PMA_PMD_DEVAD,
2102 EXT_PHY_OPT_LASI_STATUS, &val2);
2103 bnx2x_mdio45_read(bp, ext_phy_addr,
2104 EXT_PHY_OPT_PMA_PMD_DEVAD,
2105 EXT_PHY_OPT_LASI_STATUS, &val1);
2106 DP(NETIF_MSG_LINK,
2107 "10G-base-T LASI status 0x%x->0x%x\n", val2, val1);
2108 bnx2x_mdio45_read(bp, ext_phy_addr,
2109 EXT_PHY_OPT_PMA_PMD_DEVAD,
2110 EXT_PHY_KR_STATUS, &val2);
2111 bnx2x_mdio45_read(bp, ext_phy_addr,
2112 EXT_PHY_OPT_PMA_PMD_DEVAD,
2113 EXT_PHY_KR_STATUS, &val1);
2114 DP(NETIF_MSG_LINK,
2115 "10G-base-T PMA status 0x%x->0x%x\n", val2, val1);
2116 val1 = ((val1 & 4) == 4);
2117 /* if link is up
2118 * print the AN outcome of the SFX7101 PHY
2119 */
2120 if (val1) {
2121 bnx2x_mdio45_read(bp, ext_phy_addr,
2122 EXT_PHY_KR_AUTO_NEG_DEVAD,
2123 0x21, &val2);
2124 DP(NETIF_MSG_LINK,
2125 "SFX7101 AN status 0x%x->%s\n", val2,
2126 (val2 & (1<<14)) ? "Master" : "Slave");
2127 }
2128 break;
2129
2130 default:
2131 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
2132 bp->ext_phy_config);
2133 val1 = 0;
2134 break;
2135 }
2136
2137 } else { /* SerDes */
2138 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
2139 switch (ext_phy_type) {
2140 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
2141 DP(NETIF_MSG_LINK, "SerDes Direct\n");
2142 val1 = 1;
2143 break;
2144
2145 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
2146 DP(NETIF_MSG_LINK, "SerDes 5482\n");
2147 val1 = 1;
2148 break;
2149
2150 default:
2151 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
2152 bp->ext_phy_config);
2153 val1 = 0;
2154 break;
2155 }
2156 }
2157
2158 return val1;
2159}
2160
2161static void bnx2x_bmac_enable(struct bnx2x *bp, int is_lb)
2162{
2163 int port = bp->port;
2164 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2165 NIG_REG_INGRESS_BMAC0_MEM;
2166 u32 wb_write[2];
2167 u32 val;
2168
2169 DP(NETIF_MSG_LINK, "enabling BigMAC\n");
2170 /* reset and unreset the BigMac */
2171 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2172 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2173 msleep(5);
2174 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2175 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2176
2177 /* enable access for bmac registers */
2178 NIG_WR(NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2179
2180 /* XGXS control */
2181 wb_write[0] = 0x3c;
2182 wb_write[1] = 0;
2183 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2184 wb_write, 2);
2185
2186 /* tx MAC SA */
2187 wb_write[0] = ((bp->dev->dev_addr[2] << 24) |
2188 (bp->dev->dev_addr[3] << 16) |
2189 (bp->dev->dev_addr[4] << 8) |
2190 bp->dev->dev_addr[5]);
2191 wb_write[1] = ((bp->dev->dev_addr[0] << 8) |
2192 bp->dev->dev_addr[1]);
2193 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
2194 wb_write, 2);
2195
2196 /* tx control */
2197 val = 0xc0;
2198 if (bp->flow_ctrl & FLOW_CTRL_TX)
2199 val |= 0x800000;
2200 wb_write[0] = val;
2201 wb_write[1] = 0;
2202 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_write, 2);
2203
2204 /* set tx mtu */
2205 wb_write[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; /* -CRC */
2206 wb_write[1] = 0;
2207 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_write, 2);
2208
2209 /* mac control */
2210 val = 0x3;
2211 if (is_lb) {
2212 val |= 0x4;
2213 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2214 }
2215 wb_write[0] = val;
2216 wb_write[1] = 0;
2217 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
2218 wb_write, 2);
2219
2220 /* rx control set to don't strip crc */
2221 val = 0x14;
2222 if (bp->flow_ctrl & FLOW_CTRL_RX)
2223 val |= 0x20;
2224 wb_write[0] = val;
2225 wb_write[1] = 0;
2226 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_write, 2);
2227
2228 /* set rx mtu */
2229 wb_write[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2230 wb_write[1] = 0;
2231 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_write, 2);
2232
2233 /* set cnt max size */
2234 wb_write[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; /* -VLAN */
2235 wb_write[1] = 0;
2236 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
2237 wb_write, 2);
2238
2239 /* configure safc */
2240 wb_write[0] = 0x1000200;
2241 wb_write[1] = 0;
2242 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2243 wb_write, 2);
2244
2245 /* fix for emulation */
2246 if (CHIP_REV(bp) == CHIP_REV_EMUL) {
2247 wb_write[0] = 0xf000;
2248 wb_write[1] = 0;
2249 REG_WR_DMAE(bp,
2250 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
2251 wb_write, 2);
2252 }
2253
2254 /* reset old bmac stats */
2255 memset(&bp->old_bmac, 0, sizeof(struct bmac_stats));
2256
2257 NIG_WR(NIG_REG_XCM0_OUT_EN + port*4, 0x0);
2258
2259 /* select XGXS */
2260 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2261 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2262
2263 /* disable the NIG in/out to the emac */
2264 NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2265 NIG_WR(NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2266 NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2267
2268 /* enable the NIG in/out to the bmac */
2269 NIG_WR(NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2270
2271 NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2272 val = 0;
2273 if (bp->flow_ctrl & FLOW_CTRL_TX)
2274 val = 1;
2275 NIG_WR(NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2276 NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2277
2278 bp->phy_flags |= PHY_BMAC_FLAG;
2279
2280 bp->stats_state = STATS_STATE_ENABLE;
2281}
2282
2283static void bnx2x_bmac_rx_disable(struct bnx2x *bp)
2284{
2285 int port = bp->port;
2286 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2287 NIG_REG_INGRESS_BMAC0_MEM;
2288 u32 wb_write[2];
2289
2290 /* Only if the bmac is out of reset */
2291 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2292 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)) {
2293 /* Clear Rx Enable bit in BMAC_CONTROL register */
2294#ifdef BNX2X_DMAE_RD
2295 bnx2x_read_dmae(bp, bmac_addr +
2296 BIGMAC_REGISTER_BMAC_CONTROL, 2);
2297 wb_write[0] = *bnx2x_sp(bp, wb_data[0]);
2298 wb_write[1] = *bnx2x_sp(bp, wb_data[1]);
2299#else
2300 wb_write[0] = REG_RD(bp,
2301 bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL);
2302 wb_write[1] = REG_RD(bp,
2303 bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL + 4);
2304#endif
2305 wb_write[0] &= ~BMAC_CONTROL_RX_ENABLE;
2306 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
2307 wb_write, 2);
2308 msleep(1);
2309 }
2310}
2311
2312static void bnx2x_emac_enable(struct bnx2x *bp)
2313{
2314 int port = bp->port;
2315 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2316 u32 val;
2317 int timeout;
2318
2319 DP(NETIF_MSG_LINK, "enabling EMAC\n");
2320 /* reset and unreset the emac core */
2321 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2322 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2323 msleep(5);
2324 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2325 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2326
2327 /* enable emac and not bmac */
2328 NIG_WR(NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
2329
2330 /* for paladium */
2331 if (CHIP_REV(bp) == CHIP_REV_EMUL) {
2332 /* Use lane 1 (of lanes 0-3) */
2333 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2334 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2335 }
2336 /* for fpga */
2337 else if (CHIP_REV(bp) == CHIP_REV_FPGA) {
2338 /* Use lane 1 (of lanes 0-3) */
2339 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2340 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2341 }
2342 /* ASIC */
2343 else {
2344 if (bp->phy_flags & PHY_XGXS_FLAG) {
2345 DP(NETIF_MSG_LINK, "XGXS\n");
2346 /* select the master lanes (out of 0-3) */
2347 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4,
2348 bp->ser_lane);
2349 /* select XGXS */
2350 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2351
2352 } else { /* SerDes */
2353 DP(NETIF_MSG_LINK, "SerDes\n");
2354 /* select SerDes */
2355 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2356 }
2357 }
2358
2359 /* enable emac */
2360 NIG_WR(NIG_REG_NIG_EMAC0_EN + port*4, 1);
2361
2362 /* init emac - use read-modify-write */
2363 /* self clear reset */
2364 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2365 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
2366
2367 timeout = 200;
2368 while (val & EMAC_MODE_RESET) {
2369 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2370 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
2371 if (!timeout) {
2372 BNX2X_ERR("EMAC timeout!\n");
2373 break;
2374 }
2375 timeout--;
2376 }
2377
2378 /* reset tx part */
2379 EMAC_WR(EMAC_REG_EMAC_TX_MODE, EMAC_TX_MODE_RESET);
2380
2381 timeout = 200;
2382 while (val & EMAC_TX_MODE_RESET) {
2383 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_TX_MODE);
2384 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
2385 if (!timeout) {
2386 BNX2X_ERR("EMAC timeout!\n");
2387 break;
2388 }
2389 timeout--;
2390 }
2391
2392 if (CHIP_REV_IS_SLOW(bp)) {
2393 /* config GMII mode */
2394 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2395 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
2396
2397 } else { /* ASIC */
2398 /* pause enable/disable */
2399 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
2400 EMAC_RX_MODE_FLOW_EN);
2401 if (bp->flow_ctrl & FLOW_CTRL_RX)
2402 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
2403 EMAC_RX_MODE_FLOW_EN);
2404
2405 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
2406 EMAC_TX_MODE_EXT_PAUSE_EN);
2407 if (bp->flow_ctrl & FLOW_CTRL_TX)
2408 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
2409 EMAC_TX_MODE_EXT_PAUSE_EN);
2410 }
2411
2412 /* KEEP_VLAN_TAG, promiscuous */
2413 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
2414 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
2415 EMAC_WR(EMAC_REG_EMAC_RX_MODE, val);
2416
2417 /* identify magic packets */
2418 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2419 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_MPKT));
2420
2421 /* enable emac for jumbo packets */
2422 EMAC_WR(EMAC_REG_EMAC_RX_MTU_SIZE,
2423 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
2424 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); /* -VLAN */
2425
2426 /* strip CRC */
2427 NIG_WR(NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
2428
2429 val = ((bp->dev->dev_addr[0] << 8) |
2430 bp->dev->dev_addr[1]);
2431 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH, val);
2432
2433 val = ((bp->dev->dev_addr[2] << 24) |
2434 (bp->dev->dev_addr[3] << 16) |
2435 (bp->dev->dev_addr[4] << 8) |
2436 bp->dev->dev_addr[5]);
2437 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val);
2438
2439 /* disable the NIG in/out to the bmac */
2440 NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0x0);
2441 NIG_WR(NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
2442 NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
2443
2444 /* enable the NIG in/out to the emac */
2445 NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0x1);
2446 val = 0;
2447 if (bp->flow_ctrl & FLOW_CTRL_TX)
2448 val = 1;
2449 NIG_WR(NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
2450 NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
2451
2452 if (CHIP_REV(bp) == CHIP_REV_FPGA) {
2453 /* take the BigMac out of reset */
2454 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2455 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2456
2457 /* enable access for bmac registers */
2458 NIG_WR(NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2459 }
2460
2461 bp->phy_flags |= PHY_EMAC_FLAG;
2462
2463 bp->stats_state = STATS_STATE_ENABLE;
2464}
2465
2466static void bnx2x_emac_program(struct bnx2x *bp)
2467{
2468 u16 mode = 0;
2469 int port = bp->port;
2470
2471 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2472 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2473 (EMAC_MODE_25G_MODE |
2474 EMAC_MODE_PORT_MII_10M |
2475 EMAC_MODE_HALF_DUPLEX));
2476 switch (bp->line_speed) {
2477 case SPEED_10:
2478 mode |= EMAC_MODE_PORT_MII_10M;
2479 break; 1336 break;
2480 1337 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2481 case SPEED_100: 1338 bp->advertising |= (ADVERTISED_Asym_Pause |
2482 mode |= EMAC_MODE_PORT_MII; 1339 ADVERTISED_Pause);
2483 break; 1340 break;
2484 1341 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2485 case SPEED_1000: 1342 bp->advertising |= ADVERTISED_Asym_Pause;
2486 mode |= EMAC_MODE_PORT_GMII;
2487 break;
2488
2489 case SPEED_2500:
2490 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2491 break; 1343 break;
2492
2493 default: 1344 default:
2494 /* 10G not valid for EMAC */ 1345 bp->advertising &= ~(ADVERTISED_Asym_Pause |
2495 BNX2X_ERR("Invalid line_speed 0x%x\n", bp->line_speed); 1346 ADVERTISED_Pause);
2496 break; 1347 break;
2497 } 1348 }
2498
2499 if (bp->duplex == DUPLEX_HALF)
2500 mode |= EMAC_MODE_HALF_DUPLEX;
2501 bnx2x_bits_en(bp, GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2502 mode);
2503
2504 bnx2x_leds_set(bp, bp->line_speed);
2505}
2506
2507static void bnx2x_set_sgmii_tx_driver(struct bnx2x *bp)
2508{
2509 u32 lp_up2;
2510 u32 tx_driver;
2511
2512 /* read precomp */
2513 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_OVER_1G);
2514 bnx2x_mdio22_read(bp, MDIO_OVER_1G_LP_UP2, &lp_up2);
2515
2516 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_TX0);
2517 bnx2x_mdio22_read(bp, MDIO_TX0_TX_DRIVER, &tx_driver);
2518
2519 /* bits [10:7] at lp_up2, positioned at [15:12] */
2520 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2521 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2522 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2523
2524 if ((lp_up2 != 0) &&
2525 (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK))) {
2526 /* replace tx_driver bits [15:12] */
2527 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2528 tx_driver |= lp_up2;
2529 bnx2x_mdio22_write(bp, MDIO_TX0_TX_DRIVER, tx_driver);
2530 }
2531}
2532
2533static void bnx2x_pbf_update(struct bnx2x *bp)
2534{
2535 int port = bp->port;
2536 u32 init_crd, crd;
2537 u32 count = 1000;
2538 u32 pause = 0;
2539
2540 /* disable port */
2541 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2542
2543 /* wait for init credit */
2544 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2545 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2546 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2547
2548 while ((init_crd != crd) && count) {
2549 msleep(5);
2550
2551 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2552 count--;
2553 }
2554 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2555 if (init_crd != crd)
2556 BNX2X_ERR("BUG! init_crd 0x%x != crd 0x%x\n", init_crd, crd);
2557
2558 if (bp->flow_ctrl & FLOW_CTRL_RX)
2559 pause = 1;
2560 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, pause);
2561 if (pause) {
2562 /* update threshold */
2563 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2564 /* update init credit */
2565 init_crd = 778; /* (800-18-4) */
2566
2567 } else {
2568 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)/16;
2569
2570 /* update threshold */
2571 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2572 /* update init credit */
2573 switch (bp->line_speed) {
2574 case SPEED_10:
2575 case SPEED_100:
2576 case SPEED_1000:
2577 init_crd = thresh + 55 - 22;
2578 break;
2579
2580 case SPEED_2500:
2581 init_crd = thresh + 138 - 22;
2582 break;
2583
2584 case SPEED_10000:
2585 init_crd = thresh + 553 - 22;
2586 break;
2587
2588 default:
2589 BNX2X_ERR("Invalid line_speed 0x%x\n",
2590 bp->line_speed);
2591 break;
2592 }
2593 }
2594 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2595 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2596 bp->line_speed, init_crd);
2597
2598 /* probe the credit changes */
2599 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2600 msleep(5);
2601 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2602
2603 /* enable port */
2604 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2605}
2606
2607static void bnx2x_update_mng(struct bnx2x *bp)
2608{
2609 if (!nomcp)
2610 SHMEM_WR(bp, port_mb[bp->port].link_status,
2611 bp->link_status);
2612} 1349}
2613 1350
2614static void bnx2x_link_report(struct bnx2x *bp) 1351static void bnx2x_link_report(struct bnx2x *bp)
2615{ 1352{
2616 if (bp->link_up) { 1353 if (bp->link_vars.link_up) {
2617 netif_carrier_on(bp->dev); 1354 if (bp->state == BNX2X_STATE_OPEN)
1355 netif_carrier_on(bp->dev);
2618 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name); 1356 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
2619 1357
2620 printk("%d Mbps ", bp->line_speed); 1358 printk("%d Mbps ", bp->link_vars.line_speed);
2621 1359
2622 if (bp->duplex == DUPLEX_FULL) 1360 if (bp->link_vars.duplex == DUPLEX_FULL)
2623 printk("full duplex"); 1361 printk("full duplex");
2624 else 1362 else
2625 printk("half duplex"); 1363 printk("half duplex");
2626 1364
2627 if (bp->flow_ctrl) { 1365 if (bp->link_vars.flow_ctrl != FLOW_CTRL_NONE) {
2628 if (bp->flow_ctrl & FLOW_CTRL_RX) { 1366 if (bp->link_vars.flow_ctrl & FLOW_CTRL_RX) {
2629 printk(", receive "); 1367 printk(", receive ");
2630 if (bp->flow_ctrl & FLOW_CTRL_TX) 1368 if (bp->link_vars.flow_ctrl & FLOW_CTRL_TX)
2631 printk("& transmit "); 1369 printk("& transmit ");
2632 } else { 1370 } else {
2633 printk(", transmit "); 1371 printk(", transmit ");
@@ -2638,1318 +1376,78 @@ static void bnx2x_link_report(struct bnx2x *bp)
2638 1376
2639 } else { /* link_down */ 1377 } else { /* link_down */
2640 netif_carrier_off(bp->dev); 1378 netif_carrier_off(bp->dev);
2641 printk(KERN_INFO PFX "%s NIC Link is Down\n", bp->dev->name); 1379 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
2642 }
2643}
2644
2645static void bnx2x_link_up(struct bnx2x *bp)
2646{
2647 int port = bp->port;
2648
2649 /* PBF - link up */
2650 bnx2x_pbf_update(bp);
2651
2652 /* disable drain */
2653 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
2654
2655 /* update shared memory */
2656 bnx2x_update_mng(bp);
2657
2658 /* indicate link up */
2659 bnx2x_link_report(bp);
2660}
2661
2662static void bnx2x_link_down(struct bnx2x *bp)
2663{
2664 int port = bp->port;
2665
2666 /* notify stats */
2667 if (bp->stats_state != STATS_STATE_DISABLE) {
2668 bp->stats_state = STATS_STATE_STOP;
2669 DP(BNX2X_MSG_STATS, "stats_state - STOP\n");
2670 }
2671
2672 /* indicate no mac active */
2673 bp->phy_flags &= ~(PHY_BMAC_FLAG | PHY_EMAC_FLAG);
2674
2675 /* update shared memory */
2676 bnx2x_update_mng(bp);
2677
2678 /* activate nig drain */
2679 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
2680
2681 /* reset BigMac */
2682 bnx2x_bmac_rx_disable(bp);
2683 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2684 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2685
2686 /* indicate link down */
2687 bnx2x_link_report(bp);
2688}
2689
2690static void bnx2x_init_mac_stats(struct bnx2x *bp);
2691
2692/* This function is called upon link interrupt */
2693static void bnx2x_link_update(struct bnx2x *bp)
2694{
2695 int port = bp->port;
2696 int i;
2697 u32 gp_status;
2698 int link_10g;
2699
2700 DP(NETIF_MSG_LINK, "port %x, %s, int_status 0x%x,"
2701 " int_mask 0x%x, saved_mask 0x%x, MI_INT %x, SERDES_LINK %x,"
2702 " 10G %x, XGXS_LINK %x\n", port,
2703 (bp->phy_flags & PHY_XGXS_FLAG)? "XGXS":"SerDes",
2704 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4),
2705 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), bp->nig_mask,
2706 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2707 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c),
2708 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2709 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)
2710 );
2711
2712 might_sleep();
2713 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_GP_STATUS);
2714 /* avoid fast toggling */
2715 for (i = 0; i < 10; i++) {
2716 msleep(10);
2717 bnx2x_mdio22_read(bp, MDIO_GP_STATUS_TOP_AN_STATUS1,
2718 &gp_status);
2719 } 1380 }
2720
2721 bnx2x_link_settings_status(bp, gp_status);
2722
2723 /* anything 10 and over uses the bmac */
2724 link_10g = ((bp->line_speed >= SPEED_10000) &&
2725 (bp->line_speed <= SPEED_16000));
2726
2727 bnx2x_link_int_ack(bp, link_10g);
2728
2729 /* link is up only if both local phy and external phy are up */
2730 bp->link_up = (bp->phy_link_up && bnx2x_ext_phy_is_link_up(bp));
2731 if (bp->link_up) {
2732 if (link_10g) {
2733 bnx2x_bmac_enable(bp, 0);
2734 bnx2x_leds_set(bp, SPEED_10000);
2735
2736 } else {
2737 bnx2x_emac_enable(bp);
2738 bnx2x_emac_program(bp);
2739
2740 /* AN complete? */
2741 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
2742 if (!(bp->phy_flags & PHY_SGMII_FLAG))
2743 bnx2x_set_sgmii_tx_driver(bp);
2744 }
2745 }
2746 bnx2x_link_up(bp);
2747
2748 } else { /* link down */
2749 bnx2x_leds_unset(bp);
2750 bnx2x_link_down(bp);
2751 }
2752
2753 bnx2x_init_mac_stats(bp);
2754} 1381}
2755 1382
2756/* 1383static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
2757 * Init service functions
2758 */
2759
2760static void bnx2x_set_aer_mmd(struct bnx2x *bp)
2761{ 1384{
2762 u16 offset = (bp->phy_flags & PHY_XGXS_FLAG) ? 1385 u8 rc;
2763 (bp->phy_addr + bp->ser_lane) : 0;
2764 1386
2765 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_AER_BLOCK); 1387 /* Initialize link parameters structure variables */
2766 bnx2x_mdio22_write(bp, MDIO_AER_BLOCK_AER_REG, 0x3800 + offset); 1388 bp->link_params.mtu = bp->dev->mtu;
2767}
2768 1389
2769static void bnx2x_set_master_ln(struct bnx2x *bp) 1390 bnx2x_phy_hw_lock(bp);
2770{ 1391 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2771 u32 new_master_ln; 1392 bnx2x_phy_hw_unlock(bp);
2772
2773 /* set the master_ln for AN */
2774 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2);
2775 bnx2x_mdio22_read(bp, MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
2776 &new_master_ln);
2777 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
2778 (new_master_ln | bp->ser_lane));
2779}
2780
2781static void bnx2x_reset_unicore(struct bnx2x *bp)
2782{
2783 u32 mii_control;
2784 int i;
2785
2786 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2787 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
2788 /* reset the unicore */
2789 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
2790 (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET));
2791
2792 /* wait for the reset to self clear */
2793 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
2794 udelay(5);
2795
2796 /* the reset erased the previous bank value */
2797 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2798 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
2799 &mii_control);
2800
2801 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
2802 udelay(5);
2803 return;
2804 }
2805 }
2806
2807 BNX2X_ERR("BUG! %s (0x%x) is still in reset!\n",
2808 (bp->phy_flags & PHY_XGXS_FLAG)? "XGXS":"SerDes",
2809 bp->phy_addr);
2810}
2811
2812static void bnx2x_set_swap_lanes(struct bnx2x *bp)
2813{
2814 /* Each two bits represents a lane number:
2815 No swap is 0123 => 0x1b no need to enable the swap */
2816
2817 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2);
2818 if (bp->rx_lane_swap != 0x1b) {
2819 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_RX_LN_SWAP,
2820 (bp->rx_lane_swap |
2821 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
2822 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
2823 } else {
2824 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
2825 }
2826
2827 if (bp->tx_lane_swap != 0x1b) {
2828 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TX_LN_SWAP,
2829 (bp->tx_lane_swap |
2830 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
2831 } else {
2832 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
2833 }
2834}
2835
2836static void bnx2x_set_parallel_detection(struct bnx2x *bp)
2837{
2838 u32 control2;
2839
2840 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
2841 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
2842 &control2);
2843
2844 if (bp->autoneg & AUTONEG_PARALLEL) {
2845 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
2846 } else {
2847 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
2848 }
2849 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
2850 control2);
2851
2852 if (bp->phy_flags & PHY_XGXS_FLAG) {
2853 DP(NETIF_MSG_LINK, "XGXS\n");
2854 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_10G_PARALLEL_DETECT);
2855
2856 bnx2x_mdio22_write(bp,
2857 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
2858 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
2859
2860 bnx2x_mdio22_read(bp,
2861 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
2862 &control2);
2863
2864 if (bp->autoneg & AUTONEG_PARALLEL) {
2865 control2 |=
2866 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
2867 } else {
2868 control2 &=
2869 ~MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
2870 }
2871 bnx2x_mdio22_write(bp,
2872 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
2873 control2);
2874
2875 /* Disable parallel detection of HiG */
2876 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2);
2877 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
2878 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
2879 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
2880 }
2881}
2882
2883static void bnx2x_set_autoneg(struct bnx2x *bp)
2884{
2885 u32 reg_val;
2886
2887 /* CL37 Autoneg */
2888 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2889 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2890 if ((bp->req_autoneg & AUTONEG_SPEED) &&
2891 (bp->autoneg & AUTONEG_CL37)) {
2892 /* CL37 Autoneg Enabled */
2893 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
2894 } else {
2895 /* CL37 Autoneg Disabled */
2896 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2897 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
2898 }
2899 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2900
2901 /* Enable/Disable Autodetection */
2902 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
2903 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
2904 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN;
2905
2906 if ((bp->req_autoneg & AUTONEG_SPEED) &&
2907 (bp->autoneg & AUTONEG_SGMII_FIBER_AUTODET)) {
2908 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
2909 } else {
2910 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
2911 }
2912 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
2913
2914 /* Enable TetonII and BAM autoneg */
2915 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_BAM_NEXT_PAGE);
2916 bnx2x_mdio22_read(bp, MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
2917 &reg_val);
2918 if ((bp->req_autoneg & AUTONEG_SPEED) &&
2919 (bp->autoneg & AUTONEG_CL37) && (bp->autoneg & AUTONEG_BAM)) {
2920 /* Enable BAM aneg Mode and TetonII aneg Mode */
2921 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
2922 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
2923 } else {
2924 /* TetonII and BAM Autoneg Disabled */
2925 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
2926 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
2927 }
2928 bnx2x_mdio22_write(bp, MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
2929 reg_val);
2930
2931 /* Enable Clause 73 Aneg */
2932 if ((bp->req_autoneg & AUTONEG_SPEED) &&
2933 (bp->autoneg & AUTONEG_CL73)) {
2934 /* Enable BAM Station Manager */
2935 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_USERB0);
2936 bnx2x_mdio22_write(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL1,
2937 (MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
2938 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
2939 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN));
2940
2941 /* Merge CL73 and CL37 aneg resolution */
2942 bnx2x_mdio22_read(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL3,
2943 &reg_val);
2944 bnx2x_mdio22_write(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL3,
2945 (reg_val |
2946 MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR));
2947
2948 /* Set the CL73 AN speed */
2949 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB1);
2950 bnx2x_mdio22_read(bp, MDIO_CL73_IEEEB1_AN_ADV2, &reg_val);
2951 /* In the SerDes we support only the 1G.
2952 In the XGXS we support the 10G KX4
2953 but we currently do not support the KR */
2954 if (bp->phy_flags & PHY_XGXS_FLAG) {
2955 DP(NETIF_MSG_LINK, "XGXS\n");
2956 /* 10G KX4 */
2957 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
2958 } else {
2959 DP(NETIF_MSG_LINK, "SerDes\n");
2960 /* 1000M KX */
2961 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
2962 }
2963 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
2964
2965 /* CL73 Autoneg Enabled */
2966 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
2967 } else {
2968 /* CL73 Autoneg Disabled */
2969 reg_val = 0;
2970 }
2971 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
2972 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
2973}
2974
2975/* program SerDes, forced speed */
2976static void bnx2x_program_serdes(struct bnx2x *bp)
2977{
2978 u32 reg_val;
2979
2980 /* program duplex, disable autoneg */
2981 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2982 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2983 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
2984 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN);
2985 if (bp->req_duplex == DUPLEX_FULL)
2986 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2987 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2988
2989 /* program speed
2990 - needed only if the speed is greater than 1G (2.5G or 10G) */
2991 if (bp->req_line_speed > SPEED_1000) {
2992 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
2993 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_MISC1, &reg_val);
2994 /* clearing the speed value before setting the right speed */
2995 reg_val &= ~MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK;
2996 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2997 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2998 if (bp->req_line_speed == SPEED_10000)
2999 reg_val |=
3000 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
3001 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_MISC1, reg_val);
3002 }
3003}
3004
3005static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x *bp)
3006{
3007 u32 val = 0;
3008
3009 /* configure the 48 bits for BAM AN */
3010 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_OVER_1G);
3011
3012 /* set extended capabilities */
3013 if (bp->advertising & ADVERTISED_2500baseX_Full)
3014 val |= MDIO_OVER_1G_UP1_2_5G;
3015 if (bp->advertising & ADVERTISED_10000baseT_Full)
3016 val |= MDIO_OVER_1G_UP1_10G;
3017 bnx2x_mdio22_write(bp, MDIO_OVER_1G_UP1, val);
3018
3019 bnx2x_mdio22_write(bp, MDIO_OVER_1G_UP3, 0);
3020}
3021
3022static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x *bp)
3023{
3024 u32 an_adv;
3025
3026 /* for AN, we are always publishing full duplex */
3027 an_adv = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3028
3029 /* resolve pause mode and advertisement
3030 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
3031 if (bp->req_autoneg & AUTONEG_FLOW_CTRL) {
3032 switch (bp->req_flow_ctrl) {
3033 case FLOW_CTRL_AUTO:
3034 if (bp->dev->mtu <= 4500) {
3035 an_adv |=
3036 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3037 bp->advertising |= (ADVERTISED_Pause |
3038 ADVERTISED_Asym_Pause);
3039 } else {
3040 an_adv |=
3041 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3042 bp->advertising |= ADVERTISED_Asym_Pause;
3043 }
3044 break;
3045
3046 case FLOW_CTRL_TX:
3047 an_adv |=
3048 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3049 bp->advertising |= ADVERTISED_Asym_Pause;
3050 break;
3051
3052 case FLOW_CTRL_RX:
3053 if (bp->dev->mtu <= 4500) {
3054 an_adv |=
3055 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3056 bp->advertising |= (ADVERTISED_Pause |
3057 ADVERTISED_Asym_Pause);
3058 } else {
3059 an_adv |=
3060 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3061 bp->advertising &= ~(ADVERTISED_Pause |
3062 ADVERTISED_Asym_Pause);
3063 }
3064 break;
3065
3066 case FLOW_CTRL_BOTH:
3067 if (bp->dev->mtu <= 4500) {
3068 an_adv |=
3069 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3070 bp->advertising |= (ADVERTISED_Pause |
3071 ADVERTISED_Asym_Pause);
3072 } else {
3073 an_adv |=
3074 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3075 bp->advertising |= ADVERTISED_Asym_Pause;
3076 }
3077 break;
3078
3079 case FLOW_CTRL_NONE:
3080 default:
3081 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3082 bp->advertising &= ~(ADVERTISED_Pause |
3083 ADVERTISED_Asym_Pause);
3084 break;
3085 }
3086 } else { /* forced mode */
3087 switch (bp->req_flow_ctrl) {
3088 case FLOW_CTRL_AUTO:
3089 DP(NETIF_MSG_LINK, "req_flow_ctrl 0x%x while"
3090 " req_autoneg 0x%x\n",
3091 bp->req_flow_ctrl, bp->req_autoneg);
3092 break;
3093
3094 case FLOW_CTRL_TX:
3095 an_adv |=
3096 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3097 bp->advertising |= ADVERTISED_Asym_Pause;
3098 break;
3099
3100 case FLOW_CTRL_RX:
3101 case FLOW_CTRL_BOTH:
3102 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3103 bp->advertising |= (ADVERTISED_Pause |
3104 ADVERTISED_Asym_Pause);
3105 break;
3106
3107 case FLOW_CTRL_NONE:
3108 default:
3109 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3110 bp->advertising &= ~(ADVERTISED_Pause |
3111 ADVERTISED_Asym_Pause);
3112 break;
3113 }
3114 }
3115
3116 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
3117 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_AUTO_NEG_ADV, an_adv);
3118}
3119
3120static void bnx2x_restart_autoneg(struct bnx2x *bp)
3121{
3122 if (bp->autoneg & AUTONEG_CL73) {
3123 /* enable and restart clause 73 aneg */
3124 u32 an_ctrl;
3125
3126 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
3127 bnx2x_mdio22_read(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
3128 &an_ctrl);
3129 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
3130 (an_ctrl |
3131 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
3132 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
3133
3134 } else {
3135 /* Enable and restart BAM/CL37 aneg */
3136 u32 mii_control;
3137
3138 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
3139 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3140 &mii_control);
3141 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3142 (mii_control |
3143 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
3144 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
3145 }
3146}
3147
3148static void bnx2x_initialize_sgmii_process(struct bnx2x *bp)
3149{
3150 u32 control1;
3151
3152 /* in SGMII mode, the unicore is always slave */
3153 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
3154 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
3155 &control1);
3156 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
3157 /* set sgmii mode (and not fiber) */
3158 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
3159 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
3160 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
3161 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
3162 control1);
3163
3164 /* if forced speed */
3165 if (!(bp->req_autoneg & AUTONEG_SPEED)) {
3166 /* set speed, disable autoneg */
3167 u32 mii_control;
3168
3169 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
3170 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3171 &mii_control);
3172 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
3173 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK |
3174 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
3175
3176 switch (bp->req_line_speed) {
3177 case SPEED_100:
3178 mii_control |=
3179 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
3180 break;
3181 case SPEED_1000:
3182 mii_control |=
3183 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
3184 break;
3185 case SPEED_10:
3186 /* there is nothing to set for 10M */
3187 break;
3188 default:
3189 /* invalid speed for SGMII */
3190 DP(NETIF_MSG_LINK, "Invalid req_line_speed 0x%x\n",
3191 bp->req_line_speed);
3192 break;
3193 }
3194
3195 /* setting the full duplex */
3196 if (bp->req_duplex == DUPLEX_FULL)
3197 mii_control |=
3198 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
3199 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3200 mii_control);
3201
3202 } else { /* AN mode */
3203 /* enable and restart AN */
3204 bnx2x_restart_autoneg(bp);
3205 }
3206}
3207
3208static void bnx2x_link_int_enable(struct bnx2x *bp)
3209{
3210 int port = bp->port;
3211 u32 ext_phy_type;
3212 u32 mask;
3213
3214 /* setting the status to report on link up
3215 for either XGXS or SerDes */
3216 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3217 (NIG_STATUS_XGXS0_LINK10G |
3218 NIG_STATUS_XGXS0_LINK_STATUS |
3219 NIG_STATUS_SERDES0_LINK_STATUS));
3220
3221 if (bp->phy_flags & PHY_XGXS_FLAG) {
3222 mask = (NIG_MASK_XGXS0_LINK10G |
3223 NIG_MASK_XGXS0_LINK_STATUS);
3224 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
3225 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
3226 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3227 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3228 (ext_phy_type !=
3229 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) {
3230 mask |= NIG_MASK_MI_INT;
3231 DP(NETIF_MSG_LINK, "enabled external phy int\n");
3232 }
3233
3234 } else { /* SerDes */
3235 mask = NIG_MASK_SERDES0_LINK_STATUS;
3236 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
3237 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
3238 if ((ext_phy_type !=
3239 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
3240 (ext_phy_type !=
3241 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN)) {
3242 mask |= NIG_MASK_MI_INT;
3243 DP(NETIF_MSG_LINK, "enabled external phy int\n");
3244 }
3245 }
3246 bnx2x_bits_en(bp,
3247 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3248 mask);
3249 DP(NETIF_MSG_LINK, "port %x, %s, int_status 0x%x,"
3250 " int_mask 0x%x, MI_INT %x, SERDES_LINK %x,"
3251 " 10G %x, XGXS_LINK %x\n", port,
3252 (bp->phy_flags & PHY_XGXS_FLAG)? "XGXS":"SerDes",
3253 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4),
3254 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3255 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
3256 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c),
3257 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3258 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)
3259 );
3260}
3261
3262static void bnx2x_bcm8072_external_rom_boot(struct bnx2x *bp)
3263{
3264 u32 ext_phy_addr = ((bp->ext_phy_config &
3265 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3266 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3267 u32 fw_ver1, fw_ver2;
3268
3269 /* Need to wait 200ms after reset */
3270 msleep(200);
3271 /* Boot port from external ROM
3272 * Set ser_boot_ctl bit in the MISC_CTRL1 register
3273 */
3274 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3275 EXT_PHY_KR_PMA_PMD_DEVAD,
3276 EXT_PHY_KR_MISC_CTRL1, 0x0001);
3277
3278 /* Reset internal microprocessor */
3279 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3280 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_GEN_CTRL,
3281 EXT_PHY_KR_ROM_RESET_INTERNAL_MP);
3282 /* set micro reset = 0 */
3283 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3284 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_GEN_CTRL,
3285 EXT_PHY_KR_ROM_MICRO_RESET);
3286 /* Reset internal microprocessor */
3287 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3288 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_GEN_CTRL,
3289 EXT_PHY_KR_ROM_RESET_INTERNAL_MP);
3290 /* wait for 100ms for code download via SPI port */
3291 msleep(100);
3292
3293 /* Clear ser_boot_ctl bit */
3294 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3295 EXT_PHY_KR_PMA_PMD_DEVAD,
3296 EXT_PHY_KR_MISC_CTRL1, 0x0000);
3297 /* Wait 100ms */
3298 msleep(100);
3299
3300 /* Print the PHY FW version */
3301 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, ext_phy_addr,
3302 EXT_PHY_KR_PMA_PMD_DEVAD,
3303 0xca19, &fw_ver1);
3304 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, ext_phy_addr,
3305 EXT_PHY_KR_PMA_PMD_DEVAD,
3306 0xca1a, &fw_ver2);
3307 DP(NETIF_MSG_LINK,
3308 "8072 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2);
3309}
3310
3311static void bnx2x_bcm8072_force_10G(struct bnx2x *bp)
3312{
3313 u32 ext_phy_addr = ((bp->ext_phy_config &
3314 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3315 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3316
3317 /* Force KR or KX */
3318 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3319 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_CTRL,
3320 0x2040);
3321 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3322 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_CTRL2,
3323 0x000b);
3324 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3325 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_PMD_CTRL,
3326 0x0000);
3327 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3328 EXT_PHY_KR_AUTO_NEG_DEVAD, EXT_PHY_KR_CTRL,
3329 0x0000);
3330}
3331
3332static void bnx2x_ext_phy_init(struct bnx2x *bp)
3333{
3334 u32 ext_phy_type;
3335 u32 ext_phy_addr;
3336 u32 cnt;
3337 u32 ctrl;
3338 u32 val = 0;
3339
3340 if (bp->phy_flags & PHY_XGXS_FLAG) {
3341 ext_phy_addr = ((bp->ext_phy_config &
3342 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3343 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3344
3345 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
3346 /* Make sure that the soft reset is off (expect for the 8072:
3347 * due to the lock, it will be done inside the specific
3348 * handling)
3349 */
3350 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3351 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3352 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) &&
3353 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072)) {
3354 /* Wait for soft reset to get cleared upto 1 sec */
3355 for (cnt = 0; cnt < 1000; cnt++) {
3356 bnx2x_mdio45_read(bp, ext_phy_addr,
3357 EXT_PHY_OPT_PMA_PMD_DEVAD,
3358 EXT_PHY_OPT_CNTL, &ctrl);
3359 if (!(ctrl & (1<<15)))
3360 break;
3361 msleep(1);
3362 }
3363 DP(NETIF_MSG_LINK,
3364 "control reg 0x%x (after %d ms)\n", ctrl, cnt);
3365 }
3366
3367 switch (ext_phy_type) {
3368 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
3369 DP(NETIF_MSG_LINK, "XGXS Direct\n");
3370 break;
3371
3372 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3373 DP(NETIF_MSG_LINK, "XGXS 8705\n");
3374
3375 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3376 EXT_PHY_OPT_PMA_PMD_DEVAD,
3377 EXT_PHY_OPT_PMD_MISC_CNTL,
3378 0x8288);
3379 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3380 EXT_PHY_OPT_PMA_PMD_DEVAD,
3381 EXT_PHY_OPT_PHY_IDENTIFIER,
3382 0x7fbf);
3383 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3384 EXT_PHY_OPT_PMA_PMD_DEVAD,
3385 EXT_PHY_OPT_CMU_PLL_BYPASS,
3386 0x0100);
3387 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3388 EXT_PHY_OPT_WIS_DEVAD,
3389 EXT_PHY_OPT_LASI_CNTL, 0x1);
3390 break;
3391
3392 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
3393 DP(NETIF_MSG_LINK, "XGXS 8706\n");
3394
3395 if (!(bp->req_autoneg & AUTONEG_SPEED)) {
3396 /* Force speed */
3397 if (bp->req_line_speed == SPEED_10000) {
3398 DP(NETIF_MSG_LINK,
3399 "XGXS 8706 force 10Gbps\n");
3400 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3401 EXT_PHY_OPT_PMA_PMD_DEVAD,
3402 EXT_PHY_OPT_PMD_DIGITAL_CNT,
3403 0x400);
3404 } else {
3405 /* Force 1Gbps */
3406 DP(NETIF_MSG_LINK,
3407 "XGXS 8706 force 1Gbps\n");
3408
3409 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3410 EXT_PHY_OPT_PMA_PMD_DEVAD,
3411 EXT_PHY_OPT_CNTL,
3412 0x0040);
3413
3414 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3415 EXT_PHY_OPT_PMA_PMD_DEVAD,
3416 EXT_PHY_OPT_CNTL2,
3417 0x000D);
3418 }
3419 1393
3420 /* Enable LASI */ 1394 if (bp->link_vars.link_up)
3421 bnx2x_mdio45_vwrite(bp, ext_phy_addr, 1395 bnx2x_link_report(bp);
3422 EXT_PHY_OPT_PMA_PMD_DEVAD,
3423 EXT_PHY_OPT_LASI_CNTL,
3424 0x1);
3425 } else {
3426 /* AUTONEG */
3427 /* Allow CL37 through CL73 */
3428 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
3429 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3430 EXT_PHY_AUTO_NEG_DEVAD,
3431 EXT_PHY_OPT_AN_CL37_CL73,
3432 0x040c);
3433
3434 /* Enable Full-Duplex advertisment on CL37 */
3435 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3436 EXT_PHY_AUTO_NEG_DEVAD,
3437 EXT_PHY_OPT_AN_CL37_FD,
3438 0x0020);
3439 /* Enable CL37 AN */
3440 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3441 EXT_PHY_AUTO_NEG_DEVAD,
3442 EXT_PHY_OPT_AN_CL37_AN,
3443 0x1000);
3444 /* Advertise 10G/1G support */
3445 if (bp->advertising &
3446 ADVERTISED_1000baseT_Full)
3447 val = (1<<5);
3448 if (bp->advertising &
3449 ADVERTISED_10000baseT_Full)
3450 val |= (1<<7);
3451
3452 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3453 EXT_PHY_AUTO_NEG_DEVAD,
3454 EXT_PHY_OPT_AN_ADV, val);
3455 /* Enable LASI */
3456 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3457 EXT_PHY_OPT_PMA_PMD_DEVAD,
3458 EXT_PHY_OPT_LASI_CNTL,
3459 0x1);
3460
3461 /* Enable clause 73 AN */
3462 bnx2x_mdio45_write(bp, ext_phy_addr,
3463 EXT_PHY_AUTO_NEG_DEVAD,
3464 EXT_PHY_OPT_CNTL,
3465 0x1200);
3466 }
3467 break;
3468
3469 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3470 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
3471 /* Wait for soft reset to get cleared upto 1 sec */
3472 for (cnt = 0; cnt < 1000; cnt++) {
3473 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
3474 ext_phy_addr,
3475 EXT_PHY_OPT_PMA_PMD_DEVAD,
3476 EXT_PHY_OPT_CNTL, &ctrl);
3477 if (!(ctrl & (1<<15)))
3478 break;
3479 msleep(1);
3480 }
3481 DP(NETIF_MSG_LINK,
3482 "8072 control reg 0x%x (after %d ms)\n",
3483 ctrl, cnt);
3484
3485 bnx2x_bcm8072_external_rom_boot(bp);
3486 DP(NETIF_MSG_LINK, "Finshed loading 8072 KR ROM\n");
3487
3488 /* enable LASI */
3489 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3490 ext_phy_addr,
3491 EXT_PHY_KR_PMA_PMD_DEVAD,
3492 0x9000, 0x0400);
3493 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3494 ext_phy_addr,
3495 EXT_PHY_KR_PMA_PMD_DEVAD,
3496 EXT_PHY_KR_LASI_CNTL, 0x0004);
3497
3498 /* If this is forced speed, set to KR or KX
3499 * (all other are not supported)
3500 */
3501 if (!(bp->req_autoneg & AUTONEG_SPEED)) {
3502 if (bp->req_line_speed == SPEED_10000) {
3503 bnx2x_bcm8072_force_10G(bp);
3504 DP(NETIF_MSG_LINK,
3505 "Forced speed 10G on 8072\n");
3506 /* unlock */
3507 bnx2x_hw_unlock(bp,
3508 HW_LOCK_RESOURCE_8072_MDIO);
3509 break;
3510 } else
3511 val = (1<<5);
3512 } else {
3513
3514 /* Advertise 10G/1G support */
3515 if (bp->advertising &
3516 ADVERTISED_1000baseT_Full)
3517 val = (1<<5);
3518 if (bp->advertising &
3519 ADVERTISED_10000baseT_Full)
3520 val |= (1<<7);
3521 }
3522 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3523 ext_phy_addr,
3524 EXT_PHY_KR_AUTO_NEG_DEVAD,
3525 0x11, val);
3526 /* Add support for CL37 ( passive mode ) I */
3527 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3528 ext_phy_addr,
3529 EXT_PHY_KR_AUTO_NEG_DEVAD,
3530 0x8370, 0x040c);
3531 /* Add support for CL37 ( passive mode ) II */
3532 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3533 ext_phy_addr,
3534 EXT_PHY_KR_AUTO_NEG_DEVAD,
3535 0xffe4, 0x20);
3536 /* Add support for CL37 ( passive mode ) III */
3537 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3538 ext_phy_addr,
3539 EXT_PHY_KR_AUTO_NEG_DEVAD,
3540 0xffe0, 0x1000);
3541 /* Restart autoneg */
3542 msleep(500);
3543 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3544 ext_phy_addr,
3545 EXT_PHY_KR_AUTO_NEG_DEVAD,
3546 EXT_PHY_KR_CTRL, 0x1200);
3547 DP(NETIF_MSG_LINK, "8072 Autoneg Restart: "
3548 "1G %ssupported 10G %ssupported\n",
3549 (val & (1<<5)) ? "" : "not ",
3550 (val & (1<<7)) ? "" : "not ");
3551
3552 /* unlock */
3553 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
3554 break;
3555
3556 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
3557 DP(NETIF_MSG_LINK,
3558 "Setting the SFX7101 LASI indication\n");
3559 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3560 EXT_PHY_OPT_PMA_PMD_DEVAD,
3561 EXT_PHY_OPT_LASI_CNTL, 0x1);
3562 DP(NETIF_MSG_LINK,
3563 "Setting the SFX7101 LED to blink on traffic\n");
3564 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3565 EXT_PHY_OPT_PMA_PMD_DEVAD,
3566 0xC007, (1<<3));
3567
3568 /* read modify write pause advertizing */
3569 bnx2x_mdio45_read(bp, ext_phy_addr,
3570 EXT_PHY_KR_AUTO_NEG_DEVAD,
3571 EXT_PHY_KR_AUTO_NEG_ADVERT, &val);
3572 val &= ~EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_BOTH;
3573 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3574 if (bp->advertising & ADVERTISED_Pause)
3575 val |= EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE;
3576
3577 if (bp->advertising & ADVERTISED_Asym_Pause) {
3578 val |=
3579 EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_ASYMMETRIC;
3580 }
3581 DP(NETIF_MSG_LINK, "SFX7101 AN advertize 0x%x\n", val);
3582 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3583 EXT_PHY_KR_AUTO_NEG_DEVAD,
3584 EXT_PHY_KR_AUTO_NEG_ADVERT, val);
3585 /* Restart autoneg */
3586 bnx2x_mdio45_read(bp, ext_phy_addr,
3587 EXT_PHY_KR_AUTO_NEG_DEVAD,
3588 EXT_PHY_KR_CTRL, &val);
3589 val |= 0x200;
3590 bnx2x_mdio45_write(bp, ext_phy_addr,
3591 EXT_PHY_KR_AUTO_NEG_DEVAD,
3592 EXT_PHY_KR_CTRL, val);
3593 break;
3594
3595 default:
3596 BNX2X_ERR("BAD XGXS ext_phy_config 0x%x\n",
3597 bp->ext_phy_config);
3598 break;
3599 }
3600
3601 } else { /* SerDes */
3602/* ext_phy_addr = ((bp->ext_phy_config &
3603 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK) >>
3604 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT);
3605*/
3606 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
3607 switch (ext_phy_type) {
3608 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
3609 DP(NETIF_MSG_LINK, "SerDes Direct\n");
3610 break;
3611
3612 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
3613 DP(NETIF_MSG_LINK, "SerDes 5482\n");
3614 break;
3615
3616 default:
3617 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
3618 bp->ext_phy_config);
3619 break;
3620 }
3621 }
3622}
3623
3624static void bnx2x_ext_phy_reset(struct bnx2x *bp)
3625{
3626 u32 ext_phy_type;
3627 u32 ext_phy_addr = ((bp->ext_phy_config &
3628 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3629 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3630 u32 board = (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK);
3631
3632 /* The PHY reset is controled by GPIO 1
3633 * Give it 1ms of reset pulse
3634 */
3635 if ((board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G) &&
3636 (board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G)) {
3637 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3638 MISC_REGISTERS_GPIO_OUTPUT_LOW);
3639 msleep(1);
3640 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3641 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
3642 }
3643
3644 if (bp->phy_flags & PHY_XGXS_FLAG) {
3645 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
3646 switch (ext_phy_type) {
3647 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
3648 DP(NETIF_MSG_LINK, "XGXS Direct\n");
3649 break;
3650
3651 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3652 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
3653 DP(NETIF_MSG_LINK, "XGXS 8705/8706\n");
3654 bnx2x_mdio45_write(bp, ext_phy_addr,
3655 EXT_PHY_OPT_PMA_PMD_DEVAD,
3656 EXT_PHY_OPT_CNTL, 0xa040);
3657 break;
3658
3659 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3660 DP(NETIF_MSG_LINK, "XGXS 8072\n");
3661 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
3662 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3663 ext_phy_addr,
3664 EXT_PHY_KR_PMA_PMD_DEVAD,
3665 0, 1<<15);
3666 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
3667 break;
3668
3669 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
3670 DP(NETIF_MSG_LINK, "XGXS SFX7101\n");
3671 break;
3672
3673 default:
3674 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
3675 bp->ext_phy_config);
3676 break;
3677 }
3678
3679 } else { /* SerDes */
3680 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
3681 switch (ext_phy_type) {
3682 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
3683 DP(NETIF_MSG_LINK, "SerDes Direct\n");
3684 break;
3685
3686 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
3687 DP(NETIF_MSG_LINK, "SerDes 5482\n");
3688 break;
3689 1396
3690 default: 1397 bnx2x_calc_fc_adv(bp);
3691 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n", 1398 return rc;
3692 bp->ext_phy_config);
3693 break;
3694 }
3695 }
3696} 1399}
3697 1400
3698static void bnx2x_link_initialize(struct bnx2x *bp) 1401static void bnx2x_link_set(struct bnx2x *bp)
3699{ 1402{
3700 int port = bp->port; 1403 bnx2x_phy_hw_lock(bp);
3701 1404 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
3702 /* disable attentions */ 1405 bnx2x_phy_hw_unlock(bp);
3703 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3704 (NIG_MASK_XGXS0_LINK_STATUS |
3705 NIG_MASK_XGXS0_LINK10G |
3706 NIG_MASK_SERDES0_LINK_STATUS |
3707 NIG_MASK_MI_INT));
3708
3709 /* Activate the external PHY */
3710 bnx2x_ext_phy_reset(bp);
3711
3712 bnx2x_set_aer_mmd(bp);
3713
3714 if (bp->phy_flags & PHY_XGXS_FLAG)
3715 bnx2x_set_master_ln(bp);
3716
3717 /* reset the SerDes and wait for reset bit return low */
3718 bnx2x_reset_unicore(bp);
3719
3720 bnx2x_set_aer_mmd(bp);
3721
3722 /* setting the masterLn_def again after the reset */
3723 if (bp->phy_flags & PHY_XGXS_FLAG) {
3724 bnx2x_set_master_ln(bp);
3725 bnx2x_set_swap_lanes(bp);
3726 }
3727
3728 /* Set Parallel Detect */
3729 if (bp->req_autoneg & AUTONEG_SPEED)
3730 bnx2x_set_parallel_detection(bp);
3731
3732 if (bp->phy_flags & PHY_XGXS_FLAG) {
3733 if (bp->req_line_speed &&
3734 bp->req_line_speed < SPEED_1000) {
3735 bp->phy_flags |= PHY_SGMII_FLAG;
3736 } else {
3737 bp->phy_flags &= ~PHY_SGMII_FLAG;
3738 }
3739 }
3740
3741 if (!(bp->phy_flags & PHY_SGMII_FLAG)) {
3742 u16 bank, rx_eq;
3743
3744 rx_eq = ((bp->serdes_config &
3745 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >>
3746 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT);
3747
3748 DP(NETIF_MSG_LINK, "setting rx eq to %d\n", rx_eq);
3749 for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL;
3750 bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0)) {
3751 MDIO_SET_REG_BANK(bp, bank);
3752 bnx2x_mdio22_write(bp, MDIO_RX0_RX_EQ_BOOST,
3753 ((rx_eq &
3754 MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) |
3755 MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL));
3756 }
3757
3758 /* forced speed requested? */
3759 if (!(bp->req_autoneg & AUTONEG_SPEED)) {
3760 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3761
3762 /* disable autoneg */
3763 bnx2x_set_autoneg(bp);
3764
3765 /* program speed and duplex */
3766 bnx2x_program_serdes(bp);
3767
3768 } else { /* AN_mode */
3769 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
3770
3771 /* AN enabled */
3772 bnx2x_set_brcm_cl37_advertisment(bp);
3773
3774 /* program duplex & pause advertisement (for aneg) */
3775 bnx2x_set_ieee_aneg_advertisment(bp);
3776
3777 /* enable autoneg */
3778 bnx2x_set_autoneg(bp);
3779
3780 /* enable and restart AN */
3781 bnx2x_restart_autoneg(bp);
3782 }
3783
3784 } else { /* SGMII mode */
3785 DP(NETIF_MSG_LINK, "SGMII\n");
3786
3787 bnx2x_initialize_sgmii_process(bp);
3788 }
3789
3790 /* init ext phy and enable link state int */
3791 bnx2x_ext_phy_init(bp);
3792 1406
3793 /* enable the interrupt */ 1407 bnx2x_calc_fc_adv(bp);
3794 bnx2x_link_int_enable(bp);
3795} 1408}
3796 1409
3797static void bnx2x_phy_deassert(struct bnx2x *bp) 1410static void bnx2x__link_reset(struct bnx2x *bp)
3798{ 1411{
3799 int port = bp->port; 1412 bnx2x_phy_hw_lock(bp);
3800 u32 val; 1413 bnx2x_link_reset(&bp->link_params, &bp->link_vars);
3801 1414 bnx2x_phy_hw_unlock(bp);
3802 if (bp->phy_flags & PHY_XGXS_FLAG) {
3803 DP(NETIF_MSG_LINK, "XGXS\n");
3804 val = XGXS_RESET_BITS;
3805
3806 } else { /* SerDes */
3807 DP(NETIF_MSG_LINK, "SerDes\n");
3808 val = SERDES_RESET_BITS;
3809 }
3810
3811 val = val << (port*16);
3812
3813 /* reset and unreset the SerDes/XGXS */
3814 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3815 msleep(5);
3816 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3817} 1415}
3818 1416
3819static int bnx2x_phy_init(struct bnx2x *bp) 1417static u8 bnx2x_link_test(struct bnx2x *bp)
3820{ 1418{
3821 DP(NETIF_MSG_LINK, "started\n"); 1419 u8 rc;
3822 if (CHIP_REV(bp) == CHIP_REV_FPGA) {
3823 bp->phy_flags |= PHY_EMAC_FLAG;
3824 bp->link_up = 1;
3825 bp->line_speed = SPEED_10000;
3826 bp->duplex = DUPLEX_FULL;
3827 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + bp->port*4, 0);
3828 bnx2x_emac_enable(bp);
3829 bnx2x_link_report(bp);
3830 return 0;
3831 1420
3832 } else if (CHIP_REV(bp) == CHIP_REV_EMUL) { 1421 bnx2x_phy_hw_lock(bp);
3833 bp->phy_flags |= PHY_BMAC_FLAG; 1422 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
3834 bp->link_up = 1; 1423 bnx2x_phy_hw_unlock(bp);
3835 bp->line_speed = SPEED_10000;
3836 bp->duplex = DUPLEX_FULL;
3837 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + bp->port*4, 0);
3838 bnx2x_bmac_enable(bp, 0);
3839 bnx2x_link_report(bp);
3840 return 0;
3841 1424
3842 } else { 1425 return rc;
3843 bnx2x_phy_deassert(bp);
3844 bnx2x_link_initialize(bp);
3845 }
3846
3847 return 0;
3848} 1426}
3849 1427
3850static void bnx2x_link_reset(struct bnx2x *bp) 1428/* This function is called upon link interrupt */
1429static void bnx2x_link_attn(struct bnx2x *bp)
3851{ 1430{
3852 int port = bp->port; 1431 bnx2x_phy_hw_lock(bp);
3853 u32 board = (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK); 1432 bnx2x_link_update(&bp->link_params, &bp->link_vars);
3854 1433 bnx2x_phy_hw_unlock(bp);
3855 /* update shared memory */
3856 bp->link_status = 0;
3857 bnx2x_update_mng(bp);
3858
3859 /* disable attentions */
3860 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3861 (NIG_MASK_XGXS0_LINK_STATUS |
3862 NIG_MASK_XGXS0_LINK10G |
3863 NIG_MASK_SERDES0_LINK_STATUS |
3864 NIG_MASK_MI_INT));
3865
3866 /* activate nig drain */
3867 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
3868
3869 /* disable nig egress interface */
3870 NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0);
3871 NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
3872
3873 /* Stop BigMac rx */
3874 bnx2x_bmac_rx_disable(bp);
3875
3876 /* disable emac */
3877 NIG_WR(NIG_REG_NIG_EMAC0_EN + port*4, 0);
3878
3879 msleep(10);
3880 1434
3881 /* The PHY reset is controled by GPIO 1 1435 /* indicate link status */
3882 * Hold it as output low 1436 bnx2x_link_report(bp);
3883 */
3884 if ((board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G) &&
3885 (board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G)) {
3886 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3887 MISC_REGISTERS_GPIO_OUTPUT_LOW);
3888 DP(NETIF_MSG_LINK, "reset external PHY\n");
3889 }
3890
3891 /* reset the SerDes/XGXS */
3892 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
3893 (0x1ff << (port*16)));
3894
3895 /* reset BigMac */
3896 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3897 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3898
3899 /* disable nig ingress interface */
3900 NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0);
3901 NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0);
3902
3903 /* set link down */
3904 bp->link_up = 0;
3905} 1437}
3906 1438
3907#ifdef BNX2X_XGXS_LB 1439static void bnx2x__link_status_update(struct bnx2x *bp)
3908static void bnx2x_set_xgxs_loopback(struct bnx2x *bp, int is_10g)
3909{ 1440{
3910 int port = bp->port; 1441 if (bp->state != BNX2X_STATE_OPEN)
3911 1442 return;
3912 if (is_10g) {
3913 u32 md_devad;
3914
3915 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3916
3917 /* change the uni_phy_addr in the nig */
3918 REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18),
3919 &md_devad);
3920 NIG_WR(NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3921
3922 /* change the aer mmd */
3923 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_AER_BLOCK);
3924 bnx2x_mdio22_write(bp, MDIO_AER_BLOCK_AER_REG, 0x2800);
3925
3926 /* config combo IEEE0 control reg for loopback */
3927 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
3928 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
3929 0x6041);
3930
3931 /* set aer mmd back */
3932 bnx2x_set_aer_mmd(bp);
3933
3934 /* and md_devad */
3935 NIG_WR(NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad);
3936
3937 } else {
3938 u32 mii_control;
3939 1443
3940 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); 1444 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
3941 1445
3942 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0); 1446 /* indicate link status */
3943 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, 1447 bnx2x_link_report(bp);
3944 &mii_control);
3945 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3946 (mii_control |
3947 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
3948 }
3949} 1448}
3950#endif
3951 1449
3952/* end of PHY/MAC */ 1450/* end of Link */
3953 1451
3954/* slow path */ 1452/* slow path */
3955 1453
@@ -4113,7 +1611,7 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
4113 bp->nig_mask = REG_RD(bp, nig_int_mask_addr); 1611 bp->nig_mask = REG_RD(bp, nig_int_mask_addr);
4114 REG_WR(bp, nig_int_mask_addr, 0); 1612 REG_WR(bp, nig_int_mask_addr, 0);
4115 1613
4116 bnx2x_link_update(bp); 1614 bnx2x_link_attn(bp);
4117 1615
4118 /* handle unicore attn? */ 1616 /* handle unicore attn? */
4119 } 1617 }
@@ -4196,14 +1694,14 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4196 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 1694 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4197 MISC_REGISTERS_GPIO_OUTPUT_LOW); 1695 MISC_REGISTERS_GPIO_OUTPUT_LOW);
4198 /* mark the failure */ 1696 /* mark the failure */
4199 bp->ext_phy_config &= 1697 bp->link_params.ext_phy_config &=
4200 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 1698 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4201 bp->ext_phy_config |= 1699 bp->link_params.ext_phy_config |=
4202 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 1700 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4203 SHMEM_WR(bp, 1701 SHMEM_WR(bp,
4204 dev_info.port_hw_config[port]. 1702 dev_info.port_hw_config[port].
4205 external_phy_config, 1703 external_phy_config,
4206 bp->ext_phy_config); 1704 bp->link_params.ext_phy_config);
4207 /* log the failure */ 1705 /* log the failure */
4208 printk(KERN_ERR PFX "Fan Failure on Network" 1706 printk(KERN_ERR PFX "Fan Failure on Network"
4209 " Controller %s has caused the driver to" 1707 " Controller %s has caused the driver to"
@@ -4580,7 +2078,7 @@ static void bnx2x_init_mac_stats(struct bnx2x *bp)
4580#endif 2078#endif
4581 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0)); 2079 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
4582 2080
4583 if (bp->link_up) 2081 if (bp->link_vars.link_up)
4584 opcode |= (DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE); 2082 opcode |= (DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE);
4585 2083
4586 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); 2084 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
@@ -4593,7 +2091,7 @@ static void bnx2x_init_mac_stats(struct bnx2x *bp)
4593 dmae->dst_addr_hi = 0; 2091 dmae->dst_addr_hi = 0;
4594 dmae->len = (offsetof(struct bnx2x_eth_stats, mac_stx_end) - 2092 dmae->len = (offsetof(struct bnx2x_eth_stats, mac_stx_end) -
4595 sizeof(u32)) >> 2; 2093 sizeof(u32)) >> 2;
4596 if (bp->link_up) { 2094 if (bp->link_vars.link_up) {
4597 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2; 2095 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4598 dmae->comp_addr_hi = 0; 2096 dmae->comp_addr_hi = 0;
4599 dmae->comp_val = 1; 2097 dmae->comp_val = 1;
@@ -4604,7 +2102,7 @@ static void bnx2x_init_mac_stats(struct bnx2x *bp)
4604 } 2102 }
4605 } 2103 }
4606 2104
4607 if (!bp->link_up) { 2105 if (!bp->link_vars.link_up) {
4608 /* no need to collect statistics in link down */ 2106 /* no need to collect statistics in link down */
4609 return; 2107 return;
4610 } 2108 }
@@ -4619,7 +2117,7 @@ static void bnx2x_init_mac_stats(struct bnx2x *bp)
4619#endif 2117#endif
4620 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0)); 2118 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
4621 2119
4622 if (bp->phy_flags & PHY_BMAC_FLAG) { 2120 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
4623 2121
4624 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM : 2122 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
4625 NIG_REG_INGRESS_BMAC0_MEM); 2123 NIG_REG_INGRESS_BMAC0_MEM);
@@ -4656,7 +2154,7 @@ static void bnx2x_init_mac_stats(struct bnx2x *bp)
4656 dmae->comp_addr_hi = 0; 2154 dmae->comp_addr_hi = 0;
4657 dmae->comp_val = 1; 2155 dmae->comp_val = 1;
4658 2156
4659 } else if (bp->phy_flags & PHY_EMAC_FLAG) { 2157 } else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
4660 2158
4661 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0); 2159 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
4662 2160
@@ -5099,10 +2597,10 @@ static void bnx2x_update_stats(struct bnx2x *bp)
5099 2597
5100 if (!bnx2x_update_storm_stats(bp)) { 2598 if (!bnx2x_update_storm_stats(bp)) {
5101 2599
5102 if (bp->phy_flags & PHY_BMAC_FLAG) { 2600 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
5103 bnx2x_update_bmac_stats(bp); 2601 bnx2x_update_bmac_stats(bp);
5104 2602
5105 } else if (bp->phy_flags & PHY_EMAC_FLAG) { 2603 } else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
5106 bnx2x_update_emac_stats(bp); 2604 bnx2x_update_emac_stats(bp);
5107 2605
5108 } else { /* unreached */ 2606 } else { /* unreached */
@@ -6568,7 +4066,7 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode)
6568 break; 4066 break;
6569 } 4067 }
6570 4068
6571 bnx2x_link_reset(bp); 4069 bnx2x__link_reset(bp);
6572 4070
6573 /* Reset PCIE errors for debug */ 4071 /* Reset PCIE errors for debug */
6574 REG_WR(bp, 0x2114, 0xffffffff); 4072 REG_WR(bp, 0x2114, 0xffffffff);
@@ -7210,7 +4708,7 @@ static int bnx2x_nic_load(struct bnx2x *bp, int req_irq)
7210 4708
7211 bnx2x_set_mac_addr(bp); 4709 bnx2x_set_mac_addr(bp);
7212 4710
7213 bnx2x_phy_init(bp); 4711 bnx2x_initial_phy_init(bp);
7214 4712
7215 /* Start fast path */ 4713 /* Start fast path */
7216 if (req_irq) { /* IRQ is only requested from bnx2x_open */ 4714 if (req_irq) { /* IRQ is only requested from bnx2x_open */
@@ -7435,7 +4933,7 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int free_irq)
7435 } 4933 }
7436 4934
7437unload_error: 4935unload_error:
7438 bnx2x_link_reset(bp); 4936 bnx2x__link_reset(bp);
7439 4937
7440 if (!nomcp) 4938 if (!nomcp)
7441 reset_code = bnx2x_fw_command(bp, reset_code); 4939 reset_code = bnx2x_fw_command(bp, reset_code);
@@ -7477,13 +4975,12 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7477 int port = bp->port; 4975 int port = bp->port;
7478 u32 ext_phy_type; 4976 u32 ext_phy_type;
7479 4977
7480 bp->phy_flags = 0;
7481
7482 switch (switch_cfg) { 4978 switch (switch_cfg) {
7483 case SWITCH_CFG_1G: 4979 case SWITCH_CFG_1G:
7484 BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg); 4980 BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg);
7485 4981
7486 ext_phy_type = SERDES_EXT_PHY_TYPE(bp); 4982 ext_phy_type =
4983 SERDES_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7487 switch (ext_phy_type) { 4984 switch (ext_phy_type) {
7488 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT: 4985 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
7489 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n", 4986 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
@@ -7505,8 +5002,6 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7505 BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n", 5002 BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n",
7506 ext_phy_type); 5003 ext_phy_type);
7507 5004
7508 bp->phy_flags |= PHY_SGMII_FLAG;
7509
7510 bp->supported |= (SUPPORTED_10baseT_Half | 5005 bp->supported |= (SUPPORTED_10baseT_Half |
7511 SUPPORTED_10baseT_Full | 5006 SUPPORTED_10baseT_Full |
7512 SUPPORTED_100baseT_Half | 5007 SUPPORTED_100baseT_Half |
@@ -7521,7 +5016,7 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7521 default: 5016 default:
7522 BNX2X_ERR("NVRAM config error. " 5017 BNX2X_ERR("NVRAM config error. "
7523 "BAD SerDes ext_phy_config 0x%x\n", 5018 "BAD SerDes ext_phy_config 0x%x\n",
7524 bp->ext_phy_config); 5019 bp->link_params.ext_phy_config);
7525 return; 5020 return;
7526 } 5021 }
7527 5022
@@ -7533,9 +5028,8 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7533 case SWITCH_CFG_10G: 5028 case SWITCH_CFG_10G:
7534 BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg); 5029 BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg);
7535 5030
7536 bp->phy_flags |= PHY_XGXS_FLAG; 5031 ext_phy_type =
7537 5032 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7538 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
7539 switch (ext_phy_type) { 5033 switch (ext_phy_type) {
7540 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 5034 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7541 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n", 5035 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
@@ -7588,6 +5082,19 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7588 SUPPORTED_Asym_Pause); 5082 SUPPORTED_Asym_Pause);
7589 break; 5083 break;
7590 5084
5085 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
5086 BNX2X_DEV_INFO("ext_phy_type 0x%x (8073)\n",
5087 ext_phy_type);
5088
5089 bp->supported |= (SUPPORTED_10000baseT_Full |
5090 SUPPORTED_2500baseX_Full |
5091 SUPPORTED_1000baseT_Full |
5092 SUPPORTED_FIBRE |
5093 SUPPORTED_Autoneg |
5094 SUPPORTED_Pause |
5095 SUPPORTED_Asym_Pause);
5096 break;
5097
7591 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 5098 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7592 BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n", 5099 BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
7593 ext_phy_type); 5100 ext_phy_type);
@@ -7599,10 +5106,15 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7599 SUPPORTED_Asym_Pause); 5106 SUPPORTED_Asym_Pause);
7600 break; 5107 break;
7601 5108
5109 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
5110 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
5111 bp->link_params.ext_phy_config);
5112 break;
5113
7602 default: 5114 default:
7603 BNX2X_ERR("NVRAM config error. " 5115 BNX2X_ERR("NVRAM config error. "
7604 "BAD XGXS ext_phy_config 0x%x\n", 5116 "BAD XGXS ext_phy_config 0x%x\n",
7605 bp->ext_phy_config); 5117 bp->link_params.ext_phy_config);
7606 return; 5118 return;
7607 } 5119 }
7608 5120
@@ -7610,17 +5122,6 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7610 port*0x18); 5122 port*0x18);
7611 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->phy_addr); 5123 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->phy_addr);
7612 5124
7613 bp->ser_lane = ((bp->lane_config &
7614 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
7615 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
7616 bp->rx_lane_swap = ((bp->lane_config &
7617 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
7618 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
7619 bp->tx_lane_swap = ((bp->lane_config &
7620 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
7621 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
7622 BNX2X_DEV_INFO("rx_lane_swap 0x%x tx_lane_swap 0x%x\n",
7623 bp->rx_lane_swap, bp->tx_lane_swap);
7624 break; 5125 break;
7625 5126
7626 default: 5127 default:
@@ -7628,32 +5129,36 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7628 bp->link_config); 5129 bp->link_config);
7629 return; 5130 return;
7630 } 5131 }
5132 bp->link_params.phy_addr = bp->phy_addr;
7631 5133
7632 /* mask what we support according to speed_cap_mask */ 5134 /* mask what we support according to speed_cap_mask */
7633 if (!(bp->speed_cap_mask & 5135 if (!(bp->link_params.speed_cap_mask &
7634 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 5136 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
7635 bp->supported &= ~SUPPORTED_10baseT_Half; 5137 bp->supported &= ~SUPPORTED_10baseT_Half;
7636 5138
7637 if (!(bp->speed_cap_mask & 5139 if (!(bp->link_params.speed_cap_mask &
7638 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 5140 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
7639 bp->supported &= ~SUPPORTED_10baseT_Full; 5141 bp->supported &= ~SUPPORTED_10baseT_Full;
7640 5142
7641 if (!(bp->speed_cap_mask & 5143 if (!(bp->link_params.speed_cap_mask &
7642 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 5144 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
7643 bp->supported &= ~SUPPORTED_100baseT_Half; 5145 bp->supported &= ~SUPPORTED_100baseT_Half;
7644 5146
7645 if (!(bp->speed_cap_mask & 5147 if (!(bp->link_params.speed_cap_mask &
7646 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 5148 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
7647 bp->supported &= ~SUPPORTED_100baseT_Full; 5149 bp->supported &= ~SUPPORTED_100baseT_Full;
7648 5150
7649 if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 5151 if (!(bp->link_params.speed_cap_mask &
5152 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
7650 bp->supported &= ~(SUPPORTED_1000baseT_Half | 5153 bp->supported &= ~(SUPPORTED_1000baseT_Half |
7651 SUPPORTED_1000baseT_Full); 5154 SUPPORTED_1000baseT_Full);
7652 5155
7653 if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 5156 if (!(bp->link_params.speed_cap_mask &
5157 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7654 bp->supported &= ~SUPPORTED_2500baseX_Full; 5158 bp->supported &= ~SUPPORTED_2500baseX_Full;
7655 5159
7656 if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 5160 if (!(bp->link_params.speed_cap_mask &
5161 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
7657 bp->supported &= ~SUPPORTED_10000baseT_Full; 5162 bp->supported &= ~SUPPORTED_10000baseT_Full;
7658 5163
7659 BNX2X_DEV_INFO("supported 0x%x\n", bp->supported); 5164 BNX2X_DEV_INFO("supported 0x%x\n", bp->supported);
@@ -7661,20 +5166,23 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7661 5166
7662static void bnx2x_link_settings_requested(struct bnx2x *bp) 5167static void bnx2x_link_settings_requested(struct bnx2x *bp)
7663{ 5168{
7664 bp->req_autoneg = 0; 5169 bp->link_params.req_duplex = DUPLEX_FULL;
7665 bp->req_duplex = DUPLEX_FULL;
7666 5170
7667 switch (bp->link_config & PORT_FEATURE_LINK_SPEED_MASK) { 5171 switch (bp->link_config & PORT_FEATURE_LINK_SPEED_MASK) {
7668 case PORT_FEATURE_LINK_SPEED_AUTO: 5172 case PORT_FEATURE_LINK_SPEED_AUTO:
7669 if (bp->supported & SUPPORTED_Autoneg) { 5173 if (bp->supported & SUPPORTED_Autoneg) {
7670 bp->req_autoneg |= AUTONEG_SPEED; 5174 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
7671 bp->req_line_speed = 0;
7672 bp->advertising = bp->supported; 5175 bp->advertising = bp->supported;
7673 } else { 5176 } else {
7674 if (XGXS_EXT_PHY_TYPE(bp) == 5177 u32 ext_phy_type =
7675 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) { 5178 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
5179
5180 if ((ext_phy_type ==
5181 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
5182 (ext_phy_type ==
5183 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706)) {
7676 /* force 10G, no AN */ 5184 /* force 10G, no AN */
7677 bp->req_line_speed = SPEED_10000; 5185 bp->link_params.req_line_speed = SPEED_10000;
7678 bp->advertising = 5186 bp->advertising =
7679 (ADVERTISED_10000baseT_Full | 5187 (ADVERTISED_10000baseT_Full |
7680 ADVERTISED_FIBRE); 5188 ADVERTISED_FIBRE);
@@ -7690,86 +5198,92 @@ static void bnx2x_link_settings_requested(struct bnx2x *bp)
7690 5198
7691 case PORT_FEATURE_LINK_SPEED_10M_FULL: 5199 case PORT_FEATURE_LINK_SPEED_10M_FULL:
7692 if (bp->supported & SUPPORTED_10baseT_Full) { 5200 if (bp->supported & SUPPORTED_10baseT_Full) {
7693 bp->req_line_speed = SPEED_10; 5201 bp->link_params.req_line_speed = SPEED_10;
7694 bp->advertising = (ADVERTISED_10baseT_Full | 5202 bp->advertising = (ADVERTISED_10baseT_Full |
7695 ADVERTISED_TP); 5203 ADVERTISED_TP);
7696 } else { 5204 } else {
7697 BNX2X_ERR("NVRAM config error. " 5205 BNX2X_ERR("NVRAM config error. "
7698 "Invalid link_config 0x%x" 5206 "Invalid link_config 0x%x"
7699 " speed_cap_mask 0x%x\n", 5207 " speed_cap_mask 0x%x\n",
7700 bp->link_config, bp->speed_cap_mask); 5208 bp->link_config,
5209 bp->link_params.speed_cap_mask);
7701 return; 5210 return;
7702 } 5211 }
7703 break; 5212 break;
7704 5213
7705 case PORT_FEATURE_LINK_SPEED_10M_HALF: 5214 case PORT_FEATURE_LINK_SPEED_10M_HALF:
7706 if (bp->supported & SUPPORTED_10baseT_Half) { 5215 if (bp->supported & SUPPORTED_10baseT_Half) {
7707 bp->req_line_speed = SPEED_10; 5216 bp->link_params.req_line_speed = SPEED_10;
7708 bp->req_duplex = DUPLEX_HALF; 5217 bp->link_params.req_duplex = DUPLEX_HALF;
7709 bp->advertising = (ADVERTISED_10baseT_Half | 5218 bp->advertising = (ADVERTISED_10baseT_Half |
7710 ADVERTISED_TP); 5219 ADVERTISED_TP);
7711 } else { 5220 } else {
7712 BNX2X_ERR("NVRAM config error. " 5221 BNX2X_ERR("NVRAM config error. "
7713 "Invalid link_config 0x%x" 5222 "Invalid link_config 0x%x"
7714 " speed_cap_mask 0x%x\n", 5223 " speed_cap_mask 0x%x\n",
7715 bp->link_config, bp->speed_cap_mask); 5224 bp->link_config,
5225 bp->link_params.speed_cap_mask);
7716 return; 5226 return;
7717 } 5227 }
7718 break; 5228 break;
7719 5229
7720 case PORT_FEATURE_LINK_SPEED_100M_FULL: 5230 case PORT_FEATURE_LINK_SPEED_100M_FULL:
7721 if (bp->supported & SUPPORTED_100baseT_Full) { 5231 if (bp->supported & SUPPORTED_100baseT_Full) {
7722 bp->req_line_speed = SPEED_100; 5232 bp->link_params.req_line_speed = SPEED_100;
7723 bp->advertising = (ADVERTISED_100baseT_Full | 5233 bp->advertising = (ADVERTISED_100baseT_Full |
7724 ADVERTISED_TP); 5234 ADVERTISED_TP);
7725 } else { 5235 } else {
7726 BNX2X_ERR("NVRAM config error. " 5236 BNX2X_ERR("NVRAM config error. "
7727 "Invalid link_config 0x%x" 5237 "Invalid link_config 0x%x"
7728 " speed_cap_mask 0x%x\n", 5238 " speed_cap_mask 0x%x\n",
7729 bp->link_config, bp->speed_cap_mask); 5239 bp->link_config,
5240 bp->link_params.speed_cap_mask);
7730 return; 5241 return;
7731 } 5242 }
7732 break; 5243 break;
7733 5244
7734 case PORT_FEATURE_LINK_SPEED_100M_HALF: 5245 case PORT_FEATURE_LINK_SPEED_100M_HALF:
7735 if (bp->supported & SUPPORTED_100baseT_Half) { 5246 if (bp->supported & SUPPORTED_100baseT_Half) {
7736 bp->req_line_speed = SPEED_100; 5247 bp->link_params.req_line_speed = SPEED_100;
7737 bp->req_duplex = DUPLEX_HALF; 5248 bp->link_params.req_duplex = DUPLEX_HALF;
7738 bp->advertising = (ADVERTISED_100baseT_Half | 5249 bp->advertising = (ADVERTISED_100baseT_Half |
7739 ADVERTISED_TP); 5250 ADVERTISED_TP);
7740 } else { 5251 } else {
7741 BNX2X_ERR("NVRAM config error. " 5252 BNX2X_ERR("NVRAM config error. "
7742 "Invalid link_config 0x%x" 5253 "Invalid link_config 0x%x"
7743 " speed_cap_mask 0x%x\n", 5254 " speed_cap_mask 0x%x\n",
7744 bp->link_config, bp->speed_cap_mask); 5255 bp->link_config,
5256 bp->link_params.speed_cap_mask);
7745 return; 5257 return;
7746 } 5258 }
7747 break; 5259 break;
7748 5260
7749 case PORT_FEATURE_LINK_SPEED_1G: 5261 case PORT_FEATURE_LINK_SPEED_1G:
7750 if (bp->supported & SUPPORTED_1000baseT_Full) { 5262 if (bp->supported & SUPPORTED_1000baseT_Full) {
7751 bp->req_line_speed = SPEED_1000; 5263 bp->link_params.req_line_speed = SPEED_1000;
7752 bp->advertising = (ADVERTISED_1000baseT_Full | 5264 bp->advertising = (ADVERTISED_1000baseT_Full |
7753 ADVERTISED_TP); 5265 ADVERTISED_TP);
7754 } else { 5266 } else {
7755 BNX2X_ERR("NVRAM config error. " 5267 BNX2X_ERR("NVRAM config error. "
7756 "Invalid link_config 0x%x" 5268 "Invalid link_config 0x%x"
7757 " speed_cap_mask 0x%x\n", 5269 " speed_cap_mask 0x%x\n",
7758 bp->link_config, bp->speed_cap_mask); 5270 bp->link_config,
5271 bp->link_params.speed_cap_mask);
7759 return; 5272 return;
7760 } 5273 }
7761 break; 5274 break;
7762 5275
7763 case PORT_FEATURE_LINK_SPEED_2_5G: 5276 case PORT_FEATURE_LINK_SPEED_2_5G:
7764 if (bp->supported & SUPPORTED_2500baseX_Full) { 5277 if (bp->supported & SUPPORTED_2500baseX_Full) {
7765 bp->req_line_speed = SPEED_2500; 5278 bp->link_params.req_line_speed = SPEED_2500;
7766 bp->advertising = (ADVERTISED_2500baseX_Full | 5279 bp->advertising = (ADVERTISED_2500baseX_Full |
7767 ADVERTISED_TP); 5280 ADVERTISED_TP);
7768 } else { 5281 } else {
7769 BNX2X_ERR("NVRAM config error. " 5282 BNX2X_ERR("NVRAM config error. "
7770 "Invalid link_config 0x%x" 5283 "Invalid link_config 0x%x"
7771 " speed_cap_mask 0x%x\n", 5284 " speed_cap_mask 0x%x\n",
7772 bp->link_config, bp->speed_cap_mask); 5285 bp->link_config,
5286 bp->link_params.speed_cap_mask);
7773 return; 5287 return;
7774 } 5288 }
7775 break; 5289 break;
@@ -7778,14 +5292,15 @@ static void bnx2x_link_settings_requested(struct bnx2x *bp)
7778 case PORT_FEATURE_LINK_SPEED_10G_KX4: 5292 case PORT_FEATURE_LINK_SPEED_10G_KX4:
7779 case PORT_FEATURE_LINK_SPEED_10G_KR: 5293 case PORT_FEATURE_LINK_SPEED_10G_KR:
7780 if (bp->supported & SUPPORTED_10000baseT_Full) { 5294 if (bp->supported & SUPPORTED_10000baseT_Full) {
7781 bp->req_line_speed = SPEED_10000; 5295 bp->link_params.req_line_speed = SPEED_10000;
7782 bp->advertising = (ADVERTISED_10000baseT_Full | 5296 bp->advertising = (ADVERTISED_10000baseT_Full |
7783 ADVERTISED_FIBRE); 5297 ADVERTISED_FIBRE);
7784 } else { 5298 } else {
7785 BNX2X_ERR("NVRAM config error. " 5299 BNX2X_ERR("NVRAM config error. "
7786 "Invalid link_config 0x%x" 5300 "Invalid link_config 0x%x"
7787 " speed_cap_mask 0x%x\n", 5301 " speed_cap_mask 0x%x\n",
7788 bp->link_config, bp->speed_cap_mask); 5302 bp->link_config,
5303 bp->link_params.speed_cap_mask);
7789 return; 5304 return;
7790 } 5305 }
7791 break; 5306 break;
@@ -7794,30 +5309,28 @@ static void bnx2x_link_settings_requested(struct bnx2x *bp)
7794 BNX2X_ERR("NVRAM config error. " 5309 BNX2X_ERR("NVRAM config error. "
7795 "BAD link speed link_config 0x%x\n", 5310 "BAD link speed link_config 0x%x\n",
7796 bp->link_config); 5311 bp->link_config);
7797 bp->req_autoneg |= AUTONEG_SPEED; 5312 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
7798 bp->req_line_speed = 0;
7799 bp->advertising = bp->supported; 5313 bp->advertising = bp->supported;
7800 break; 5314 break;
7801 } 5315 }
7802 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d\n",
7803 bp->req_line_speed, bp->req_duplex);
7804 5316
7805 bp->req_flow_ctrl = (bp->link_config & 5317 bp->link_params.req_flow_ctrl = (bp->link_config &
7806 PORT_FEATURE_FLOW_CONTROL_MASK); 5318 PORT_FEATURE_FLOW_CONTROL_MASK);
7807 if ((bp->req_flow_ctrl == FLOW_CTRL_AUTO) && 5319 if ((bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) &&
7808 (bp->supported & SUPPORTED_Autoneg)) 5320 (!bp->supported & SUPPORTED_Autoneg))
7809 bp->req_autoneg |= AUTONEG_FLOW_CTRL; 5321 bp->link_params.req_flow_ctrl = FLOW_CTRL_NONE;
7810 5322
7811 BNX2X_DEV_INFO("req_autoneg 0x%x req_flow_ctrl 0x%x" 5323 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x"
7812 " advertising 0x%x\n", 5324 " advertising 0x%x\n",
7813 bp->req_autoneg, bp->req_flow_ctrl, bp->advertising); 5325 bp->link_params.req_line_speed,
5326 bp->link_params.req_duplex,
5327 bp->link_params.req_flow_ctrl, bp->advertising);
7814} 5328}
7815 5329
7816static void bnx2x_get_hwinfo(struct bnx2x *bp) 5330static void bnx2x_get_hwinfo(struct bnx2x *bp)
7817{ 5331{
7818 u32 val, val2, val3, val4, id; 5332 u32 val, val2, val3, val4, id;
7819 int port = bp->port; 5333 int port = bp->port;
7820 u32 switch_cfg;
7821 5334
7822 bp->shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 5335 bp->shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7823 BNX2X_DEV_INFO("shmem offset is %x\n", bp->shmem_base); 5336 BNX2X_DEV_INFO("shmem offset is %x\n", bp->shmem_base);
@@ -7835,6 +5348,8 @@ static void bnx2x_get_hwinfo(struct bnx2x *bp)
7835 bp->chip_id = id; 5348 bp->chip_id = id;
7836 BNX2X_DEV_INFO("chip ID is %x\n", id); 5349 BNX2X_DEV_INFO("chip ID is %x\n", id);
7837 5350
5351 bp->link_params.bp = bp;
5352
7838 if (!bp->shmem_base || (bp->shmem_base != 0xAF900)) { 5353 if (!bp->shmem_base || (bp->shmem_base != 0xAF900)) {
7839 BNX2X_DEV_INFO("MCP not active\n"); 5354 BNX2X_DEV_INFO("MCP not active\n");
7840 nomcp = 1; 5355 nomcp = 1;
@@ -7851,35 +5366,32 @@ static void bnx2x_get_hwinfo(struct bnx2x *bp)
7851 5366
7852 bp->hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 5367 bp->hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
7853 bp->board = SHMEM_RD(bp, dev_info.shared_hw_config.board); 5368 bp->board = SHMEM_RD(bp, dev_info.shared_hw_config.board);
7854 bp->serdes_config = 5369 bp->link_params.serdes_config =
7855 SHMEM_RD(bp, dev_info.port_hw_config[port].serdes_config); 5370 SHMEM_RD(bp, dev_info.port_hw_config[port].serdes_config);
7856 bp->lane_config = 5371 bp->link_params.lane_config =
7857 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 5372 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
7858 bp->ext_phy_config = 5373 bp->link_params.ext_phy_config =
7859 SHMEM_RD(bp, 5374 SHMEM_RD(bp,
7860 dev_info.port_hw_config[port].external_phy_config); 5375 dev_info.port_hw_config[port].external_phy_config);
7861 bp->speed_cap_mask = 5376 bp->link_params.speed_cap_mask =
7862 SHMEM_RD(bp, 5377 SHMEM_RD(bp,
7863 dev_info.port_hw_config[port].speed_capability_mask); 5378 dev_info.port_hw_config[port].speed_capability_mask);
7864 5379
7865 bp->link_config = 5380 bp->link_config =
7866 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 5381 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
7867 5382
7868 BNX2X_DEV_INFO("hw_config (%08x) board (%08x) serdes_config (%08x)\n" 5383 BNX2X_DEV_INFO("serdes_config (%08x) lane_config (%08x)\n"
7869 KERN_INFO " lane_config (%08x) ext_phy_config (%08x)\n" 5384 KERN_INFO " ext_phy_config (%08x) speed_cap_mask (%08x)"
7870 KERN_INFO " speed_cap_mask (%08x) link_config (%08x)" 5385 " link_config (%08x)\n",
7871 " fw_seq (%08x)\n", 5386 bp->link_params.serdes_config,
7872 bp->hw_config, bp->board, bp->serdes_config, 5387 bp->link_params.lane_config,
7873 bp->lane_config, bp->ext_phy_config, 5388 bp->link_params.ext_phy_config,
7874 bp->speed_cap_mask, bp->link_config, bp->fw_seq); 5389 bp->link_params.speed_cap_mask,
7875 5390 bp->link_config);
7876 switch_cfg = (bp->link_config & PORT_FEATURE_CONNECTED_SWITCH_MASK);
7877 bnx2x_link_settings_supported(bp, switch_cfg);
7878 5391
7879 bp->autoneg = (bp->hw_config & SHARED_HW_CFG_AN_ENABLE_MASK); 5392 bp->link_params.switch_cfg = (bp->link_config &
7880 /* for now disable cl73 */ 5393 PORT_FEATURE_CONNECTED_SWITCH_MASK);
7881 bp->autoneg &= ~SHARED_HW_CFG_AN_ENABLE_CL73; 5394 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
7882 BNX2X_DEV_INFO("autoneg 0x%x\n", bp->autoneg);
7883 5395
7884 bnx2x_link_settings_requested(bp); 5396 bnx2x_link_settings_requested(bp);
7885 5397
@@ -7891,8 +5403,9 @@ static void bnx2x_get_hwinfo(struct bnx2x *bp)
7891 bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff); 5403 bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
7892 bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff); 5404 bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff);
7893 bp->dev->dev_addr[5] = (u8)(val & 0xff); 5405 bp->dev->dev_addr[5] = (u8)(val & 0xff);
5406 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
5407 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
7894 5408
7895 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, 6);
7896 5409
7897 5410
7898 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 5411 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
@@ -7945,21 +5458,23 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7945 cmd->advertising = bp->advertising; 5458 cmd->advertising = bp->advertising;
7946 5459
7947 if (netif_carrier_ok(dev)) { 5460 if (netif_carrier_ok(dev)) {
7948 cmd->speed = bp->line_speed; 5461 cmd->speed = bp->link_vars.line_speed;
7949 cmd->duplex = bp->duplex; 5462 cmd->duplex = bp->link_vars.duplex;
7950 } else { 5463 } else {
7951 cmd->speed = bp->req_line_speed; 5464 cmd->speed = bp->link_params.req_line_speed;
7952 cmd->duplex = bp->req_duplex; 5465 cmd->duplex = bp->link_params.req_duplex;
7953 } 5466 }
7954 5467
7955 if (bp->phy_flags & PHY_XGXS_FLAG) { 5468 if (bp->link_params.switch_cfg == SWITCH_CFG_10G) {
7956 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp); 5469 u32 ext_phy_type =
5470 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7957 5471
7958 switch (ext_phy_type) { 5472 switch (ext_phy_type) {
7959 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 5473 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7960 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 5474 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7961 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 5475 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7962 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: 5476 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
5477 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7963 cmd->port = PORT_FIBRE; 5478 cmd->port = PORT_FIBRE;
7964 break; 5479 break;
7965 5480
@@ -7967,9 +5482,15 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7967 cmd->port = PORT_TP; 5482 cmd->port = PORT_TP;
7968 break; 5483 break;
7969 5484
5485 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
5486 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
5487 bp->link_params.ext_phy_config);
5488 break;
5489
7970 default: 5490 default:
7971 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n", 5491 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
7972 bp->ext_phy_config); 5492 bp->link_params.ext_phy_config);
5493 break;
7973 } 5494 }
7974 } else 5495 } else
7975 cmd->port = PORT_TP; 5496 cmd->port = PORT_TP;
@@ -7977,7 +5498,7 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7977 cmd->phy_address = bp->phy_addr; 5498 cmd->phy_address = bp->phy_addr;
7978 cmd->transceiver = XCVR_INTERNAL; 5499 cmd->transceiver = XCVR_INTERNAL;
7979 5500
7980 if (bp->req_autoneg & AUTONEG_SPEED) 5501 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
7981 cmd->autoneg = AUTONEG_ENABLE; 5502 cmd->autoneg = AUTONEG_ENABLE;
7982 else 5503 else
7983 cmd->autoneg = AUTONEG_DISABLE; 5504 cmd->autoneg = AUTONEG_DISABLE;
@@ -8018,9 +5539,8 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8018 /* advertise the requested speed and duplex if supported */ 5539 /* advertise the requested speed and duplex if supported */
8019 cmd->advertising &= bp->supported; 5540 cmd->advertising &= bp->supported;
8020 5541
8021 bp->req_autoneg |= AUTONEG_SPEED; 5542 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
8022 bp->req_line_speed = 0; 5543 bp->link_params.req_duplex = DUPLEX_FULL;
8023 bp->req_duplex = DUPLEX_FULL;
8024 bp->advertising |= (ADVERTISED_Autoneg | cmd->advertising); 5544 bp->advertising |= (ADVERTISED_Autoneg | cmd->advertising);
8025 5545
8026 } else { /* forced speed */ 5546 } else { /* forced speed */
@@ -8126,34 +5646,45 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8126 return -EINVAL; 5646 return -EINVAL;
8127 } 5647 }
8128 5648
8129 bp->req_autoneg &= ~AUTONEG_SPEED; 5649 bp->link_params.req_line_speed = cmd->speed;
8130 bp->req_line_speed = cmd->speed; 5650 bp->link_params.req_duplex = cmd->duplex;
8131 bp->req_duplex = cmd->duplex;
8132 bp->advertising = advertising; 5651 bp->advertising = advertising;
8133 } 5652 }
8134 5653
8135 DP(NETIF_MSG_LINK, "req_autoneg 0x%x req_line_speed %d\n" 5654 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
8136 DP_LEVEL " req_duplex %d advertising 0x%x\n", 5655 DP_LEVEL " req_duplex %d advertising 0x%x\n",
8137 bp->req_autoneg, bp->req_line_speed, bp->req_duplex, 5656 bp->link_params.req_line_speed, bp->link_params.req_duplex,
8138 bp->advertising); 5657 bp->advertising);
8139 5658
8140 bnx2x_stop_stats(bp); 5659 bnx2x_stop_stats(bp);
8141 bnx2x_link_initialize(bp); 5660 bnx2x_link_set(bp);
8142 5661
8143 return 0; 5662 return 0;
8144} 5663}
8145 5664
5665#define PHY_FW_VER_LEN 10
5666
8146static void bnx2x_get_drvinfo(struct net_device *dev, 5667static void bnx2x_get_drvinfo(struct net_device *dev,
8147 struct ethtool_drvinfo *info) 5668 struct ethtool_drvinfo *info)
8148{ 5669{
8149 struct bnx2x *bp = netdev_priv(dev); 5670 struct bnx2x *bp = netdev_priv(dev);
5671 char phy_fw_ver[PHY_FW_VER_LEN];
8150 5672
8151 strcpy(info->driver, DRV_MODULE_NAME); 5673 strcpy(info->driver, DRV_MODULE_NAME);
8152 strcpy(info->version, DRV_MODULE_VERSION); 5674 strcpy(info->version, DRV_MODULE_VERSION);
8153 snprintf(info->fw_version, 32, "%d.%d.%d:%d (BC VER %x)", 5675
5676 phy_fw_ver[0] = '\0';
5677 bnx2x_phy_hw_lock(bp);
5678 bnx2x_get_ext_phy_fw_version(&bp->link_params,
5679 (bp->state != BNX2X_STATE_CLOSED),
5680 phy_fw_ver, PHY_FW_VER_LEN);
5681 bnx2x_phy_hw_unlock(bp);
5682
5683 snprintf(info->fw_version, 32, "%d.%d.%d:%d BC:%x%s%s",
8154 BCM_5710_FW_MAJOR_VERSION, BCM_5710_FW_MINOR_VERSION, 5684 BCM_5710_FW_MAJOR_VERSION, BCM_5710_FW_MINOR_VERSION,
8155 BCM_5710_FW_REVISION_VERSION, BCM_5710_FW_COMPILE_FLAGS, 5685 BCM_5710_FW_REVISION_VERSION,
8156 bp->bc_ver); 5686 BCM_5710_FW_COMPILE_FLAGS, bp->bc_ver,
5687 ((phy_fw_ver[0] != '\0')? " PHY:":""), phy_fw_ver);
8157 strcpy(info->bus_info, pci_name(bp->pdev)); 5688 strcpy(info->bus_info, pci_name(bp->pdev));
8158 info->n_stats = BNX2X_NUM_STATS; 5689 info->n_stats = BNX2X_NUM_STATS;
8159 info->testinfo_len = BNX2X_NUM_TESTS; 5690 info->testinfo_len = BNX2X_NUM_TESTS;
@@ -8221,7 +5752,7 @@ static int bnx2x_nway_reset(struct net_device *dev)
8221 } 5752 }
8222 5753
8223 bnx2x_stop_stats(bp); 5754 bnx2x_stop_stats(bp);
8224 bnx2x_link_initialize(bp); 5755 bnx2x_link_set(bp);
8225 5756
8226 return 0; 5757 return 0;
8227} 5758}
@@ -8605,7 +6136,22 @@ static int bnx2x_set_eeprom(struct net_device *dev,
8605 6136
8606 /* parameters already validated in ethtool_set_eeprom */ 6137 /* parameters already validated in ethtool_set_eeprom */
8607 6138
8608 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 6139 /* If the magic number is PHY (0x00504859) upgrade the PHY FW */
6140 if (eeprom->magic == 0x00504859) {
6141
6142 bnx2x_phy_hw_lock(bp);
6143 rc = bnx2x_flash_download(bp, bp->port,
6144 bp->link_params.ext_phy_config,
6145 (bp->state != BNX2X_STATE_CLOSED),
6146 eebuf, eeprom->len);
6147 rc |= bnx2x_link_reset(&bp->link_params,
6148 &bp->link_vars);
6149 rc |= bnx2x_phy_init(&bp->link_params,
6150 &bp->link_vars);
6151 bnx2x_phy_hw_unlock(bp);
6152
6153 } else
6154 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
8609 6155
8610 return rc; 6156 return rc;
8611} 6157}
@@ -8691,10 +6237,13 @@ static void bnx2x_get_pauseparam(struct net_device *dev,
8691{ 6237{
8692 struct bnx2x *bp = netdev_priv(dev); 6238 struct bnx2x *bp = netdev_priv(dev);
8693 6239
8694 epause->autoneg = 6240 epause->autoneg = (bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) &&
8695 ((bp->req_autoneg & AUTONEG_FLOW_CTRL) == AUTONEG_FLOW_CTRL); 6241 (bp->link_params.req_line_speed == SPEED_AUTO_NEG);
8696 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) == FLOW_CTRL_RX); 6242
8697 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) == FLOW_CTRL_TX); 6243 epause->rx_pause = ((bp->link_vars.flow_ctrl & FLOW_CTRL_RX) ==
6244 FLOW_CTRL_RX);
6245 epause->tx_pause = ((bp->link_vars.flow_ctrl & FLOW_CTRL_TX) ==
6246 FLOW_CTRL_TX);
8698 6247
8699 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n" 6248 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
8700 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n", 6249 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
@@ -8710,32 +6259,31 @@ static int bnx2x_set_pauseparam(struct net_device *dev,
8710 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n", 6259 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
8711 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 6260 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
8712 6261
8713 if (epause->autoneg) { 6262 bp->link_params.req_flow_ctrl = FLOW_CTRL_AUTO;
8714 if (!(bp->supported & SUPPORTED_Autoneg)) {
8715 DP(NETIF_MSG_LINK, "Aotoneg not supported\n");
8716 return -EINVAL;
8717 }
8718
8719 bp->req_autoneg |= AUTONEG_FLOW_CTRL;
8720 } else
8721 bp->req_autoneg &= ~AUTONEG_FLOW_CTRL;
8722
8723 bp->req_flow_ctrl = FLOW_CTRL_AUTO;
8724 6263
8725 if (epause->rx_pause) 6264 if (epause->rx_pause)
8726 bp->req_flow_ctrl |= FLOW_CTRL_RX; 6265 bp->link_params.req_flow_ctrl |= FLOW_CTRL_RX;
6266
8727 if (epause->tx_pause) 6267 if (epause->tx_pause)
8728 bp->req_flow_ctrl |= FLOW_CTRL_TX; 6268 bp->link_params.req_flow_ctrl |= FLOW_CTRL_TX;
8729 6269
8730 if (!(bp->req_autoneg & AUTONEG_FLOW_CTRL) && 6270 if (bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO)
8731 (bp->req_flow_ctrl == FLOW_CTRL_AUTO)) 6271 bp->link_params.req_flow_ctrl = FLOW_CTRL_NONE;
8732 bp->req_flow_ctrl = FLOW_CTRL_NONE;
8733 6272
8734 DP(NETIF_MSG_LINK, "req_autoneg 0x%x req_flow_ctrl 0x%x\n", 6273 if (epause->autoneg) {
8735 bp->req_autoneg, bp->req_flow_ctrl); 6274 if (!(bp->supported & SUPPORTED_Autoneg)) {
6275 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
6276 return -EINVAL;
6277 }
6278
6279 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
6280 bp->link_params.req_flow_ctrl = FLOW_CTRL_AUTO;
6281 }
8736 6282
6283 DP(NETIF_MSG_LINK,
6284 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl);
8737 bnx2x_stop_stats(bp); 6285 bnx2x_stop_stats(bp);
8738 bnx2x_link_initialize(bp); 6286 bnx2x_link_set(bp);
8739 6287
8740 return 0; 6288 return 0;
8741} 6289}
@@ -8943,18 +6491,25 @@ static int bnx2x_phys_id(struct net_device *dev, u32 data)
8943 data = 2; 6491 data = 2;
8944 6492
8945 for (i = 0; i < (data * 2); i++) { 6493 for (i = 0; i < (data * 2); i++) {
8946 if ((i % 2) == 0) { 6494 if ((i % 2) == 0)
8947 bnx2x_leds_set(bp, SPEED_1000); 6495 bnx2x_set_led(bp, bp->port, LED_MODE_OPER, SPEED_1000,
8948 } else { 6496 bp->link_params.hw_led_mode,
8949 bnx2x_leds_unset(bp); 6497 bp->link_params.chip_id);
8950 } 6498 else
6499 bnx2x_set_led(bp, bp->port, LED_MODE_OFF, 0,
6500 bp->link_params.hw_led_mode,
6501 bp->link_params.chip_id);
6502
8951 msleep_interruptible(500); 6503 msleep_interruptible(500);
8952 if (signal_pending(current)) 6504 if (signal_pending(current))
8953 break; 6505 break;
8954 } 6506 }
8955 6507
8956 if (bp->link_up) 6508 if (bp->link_vars.link_up)
8957 bnx2x_leds_set(bp, bp->line_speed); 6509 bnx2x_set_led(bp, bp->port, LED_MODE_OPER,
6510 bp->link_vars.line_speed,
6511 bp->link_params.hw_led_mode,
6512 bp->link_params.chip_id);
8958 6513
8959 return 0; 6514 return 0;
8960} 6515}
@@ -9470,7 +7025,7 @@ static int bnx2x_change_mac_addr(struct net_device *dev, void *p)
9470 return 0; 7025 return 0;
9471} 7026}
9472 7027
9473/* Called with rtnl_lock */ 7028/* called with rtnl_lock */
9474static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 7029static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9475{ 7030{
9476 struct mii_ioctl_data *data = if_mii(ifr); 7031 struct mii_ioctl_data *data = if_mii(ifr);
@@ -9482,19 +7037,19 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9482 data->phy_id = bp->phy_addr; 7037 data->phy_id = bp->phy_addr;
9483 7038
9484 /* fallthrough */ 7039 /* fallthrough */
7040
9485 case SIOCGMIIREG: { 7041 case SIOCGMIIREG: {
9486 u32 mii_regval; 7042 u16 mii_regval;
9487 7043
9488 spin_lock_bh(&bp->phy_lock); 7044 if (!netif_running(dev))
9489 if (bp->state == BNX2X_STATE_OPEN) { 7045 return -EAGAIN;
9490 err = bnx2x_mdio22_read(bp, data->reg_num & 0x1f,
9491 &mii_regval);
9492 7046
9493 data->val_out = mii_regval; 7047 mutex_lock(&bp->phy_mutex);
9494 } else { 7048 err = bnx2x_cl45_read(bp, bp->port, 0, bp->phy_addr,
9495 err = -EAGAIN; 7049 DEFAULT_PHY_DEV_ADDR,
9496 } 7050 (data->reg_num & 0x1f), &mii_regval);
9497 spin_unlock_bh(&bp->phy_lock); 7051 data->val_out = mii_regval;
7052 mutex_unlock(&bp->phy_mutex);
9498 return err; 7053 return err;
9499 } 7054 }
9500 7055
@@ -9502,14 +7057,14 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9502 if (!capable(CAP_NET_ADMIN)) 7057 if (!capable(CAP_NET_ADMIN))
9503 return -EPERM; 7058 return -EPERM;
9504 7059
9505 spin_lock_bh(&bp->phy_lock); 7060 if (!netif_running(dev))
9506 if (bp->state == BNX2X_STATE_OPEN) { 7061 return -EAGAIN;
9507 err = bnx2x_mdio22_write(bp, data->reg_num & 0x1f, 7062
9508 data->val_in); 7063 mutex_lock(&bp->phy_mutex);
9509 } else { 7064 err = bnx2x_cl45_write(bp, bp->port, 0, bp->phy_addr,
9510 err = -EAGAIN; 7065 DEFAULT_PHY_DEV_ADDR,
9511 } 7066 (data->reg_num & 0x1f), data->val_in);
9512 spin_unlock_bh(&bp->phy_lock); 7067 mutex_unlock(&bp->phy_mutex);
9513 return err; 7068 return err;
9514 7069
9515 default: 7070 default:
@@ -9682,8 +7237,6 @@ static int __devinit bnx2x_init_board(struct pci_dev *pdev,
9682 bp->dev = dev; 7237 bp->dev = dev;
9683 bp->pdev = pdev; 7238 bp->pdev = pdev;
9684 7239
9685 spin_lock_init(&bp->phy_lock);
9686
9687 INIT_WORK(&bp->reset_task, bnx2x_reset_task); 7240 INIT_WORK(&bp->reset_task, bnx2x_reset_task);
9688 INIT_WORK(&bp->sp_task, bnx2x_sp_task); 7241 INIT_WORK(&bp->sp_task, bnx2x_sp_task);
9689 7242
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 11:22:33 -0500