diff options
Diffstat (limited to 'drivers/net/bnx2x_main.c')
-rw-r--r-- | drivers/net/bnx2x_main.c | 67 |
1 files changed, 53 insertions, 14 deletions
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c index b404a9b66d59..197dbe4dad21 100644 --- a/drivers/net/bnx2x_main.c +++ b/drivers/net/bnx2x_main.c | |||
@@ -2637,7 +2637,7 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) | |||
2637 | { | 2637 | { |
2638 | int port = BP_PORT(bp); | 2638 | int port = BP_PORT(bp); |
2639 | int reg_offset; | 2639 | int reg_offset; |
2640 | u32 val; | 2640 | u32 val, swap_val, swap_override; |
2641 | 2641 | ||
2642 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : | 2642 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
2643 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | 2643 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); |
@@ -2661,6 +2661,17 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) | |||
2661 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); | 2661 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
2662 | break; | 2662 | break; |
2663 | 2663 | ||
2664 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | ||
2665 | /* The PHY reset is controlled by GPIO 1 */ | ||
2666 | /* fake the port number to cancel the swap done in | ||
2667 | set_gpio() */ | ||
2668 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | ||
2669 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | ||
2670 | port = (swap_val && swap_override) ^ 1; | ||
2671 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | ||
2672 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); | ||
2673 | break; | ||
2674 | |||
2664 | default: | 2675 | default: |
2665 | break; | 2676 | break; |
2666 | } | 2677 | } |
@@ -5562,6 +5573,8 @@ static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) | |||
5562 | ((phy_type == | 5573 | ((phy_type == |
5563 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) || | 5574 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) || |
5564 | (phy_type == | 5575 | (phy_type == |
5576 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || | ||
5577 | (phy_type == | ||
5565 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481)); | 5578 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481)); |
5566 | } | 5579 | } |
5567 | 5580 | ||
@@ -5812,6 +5825,7 @@ static int bnx2x_init_common(struct bnx2x *bp) | |||
5812 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: | 5825 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: |
5813 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: | 5826 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: |
5814 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | 5827 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: |
5828 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | ||
5815 | bp->port.need_hw_lock = 1; | 5829 | bp->port.need_hw_lock = 1; |
5816 | break; | 5830 | break; |
5817 | 5831 | ||
@@ -6050,10 +6064,15 @@ static int bnx2x_init_port(struct bnx2x *bp) | |||
6050 | break; | 6064 | break; |
6051 | 6065 | ||
6052 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: | 6066 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: |
6067 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | ||
6053 | /* add SPIO 5 to group 0 */ | 6068 | /* add SPIO 5 to group 0 */ |
6054 | val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | 6069 | { |
6070 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : | ||
6071 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | ||
6072 | val = REG_RD(bp, reg_addr); | ||
6055 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; | 6073 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
6056 | REG_WR(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, val); | 6074 | REG_WR(bp, reg_addr, val); |
6075 | } | ||
6057 | break; | 6076 | break; |
6058 | 6077 | ||
6059 | default: | 6078 | default: |
@@ -6203,7 +6222,7 @@ init_hw_err: | |||
6203 | } | 6222 | } |
6204 | 6223 | ||
6205 | /* send the MCP a request, block until there is a reply */ | 6224 | /* send the MCP a request, block until there is a reply */ |
6206 | static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command) | 6225 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command) |
6207 | { | 6226 | { |
6208 | int func = BP_FUNC(bp); | 6227 | int func = BP_FUNC(bp); |
6209 | u32 seq = ++bp->fw_seq; | 6228 | u32 seq = ++bp->fw_seq; |
@@ -7676,6 +7695,9 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) | |||
7676 | BNX2X_ERR("This driver needs bc_ver %X but found %X," | 7695 | BNX2X_ERR("This driver needs bc_ver %X but found %X," |
7677 | " please upgrade BC\n", BNX2X_BC_VER, val); | 7696 | " please upgrade BC\n", BNX2X_BC_VER, val); |
7678 | } | 7697 | } |
7698 | bp->link_params.feature_config_flags |= | ||
7699 | (val >= REQ_BC_VER_4_VRFY_OPT_MDL) ? | ||
7700 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; | ||
7679 | 7701 | ||
7680 | if (BP_E1HVN(bp) == 0) { | 7702 | if (BP_E1HVN(bp) == 0) { |
7681 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); | 7703 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); |
@@ -7836,6 +7858,18 @@ static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, | |||
7836 | SUPPORTED_Asym_Pause); | 7858 | SUPPORTED_Asym_Pause); |
7837 | break; | 7859 | break; |
7838 | 7860 | ||
7861 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | ||
7862 | BNX2X_DEV_INFO("ext_phy_type 0x%x (8727)\n", | ||
7863 | ext_phy_type); | ||
7864 | |||
7865 | bp->port.supported |= (SUPPORTED_10000baseT_Full | | ||
7866 | SUPPORTED_1000baseT_Full | | ||
7867 | SUPPORTED_Autoneg | | ||
7868 | SUPPORTED_FIBRE | | ||
7869 | SUPPORTED_Pause | | ||
7870 | SUPPORTED_Asym_Pause); | ||
7871 | break; | ||
7872 | |||
7839 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: | 7873 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: |
7840 | BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n", | 7874 | BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n", |
7841 | ext_phy_type); | 7875 | ext_phy_type); |
@@ -8099,6 +8133,17 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) | |||
8099 | bp->link_params.ext_phy_config = | 8133 | bp->link_params.ext_phy_config = |
8100 | SHMEM_RD(bp, | 8134 | SHMEM_RD(bp, |
8101 | dev_info.port_hw_config[port].external_phy_config); | 8135 | dev_info.port_hw_config[port].external_phy_config); |
8136 | /* BCM8727_NOC => BCM8727 no over current */ | ||
8137 | if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) == | ||
8138 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC) { | ||
8139 | bp->link_params.ext_phy_config &= | ||
8140 | ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | ||
8141 | bp->link_params.ext_phy_config |= | ||
8142 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727; | ||
8143 | bp->link_params.feature_config_flags |= | ||
8144 | FEATURE_CONFIG_BCM8727_NOC; | ||
8145 | } | ||
8146 | |||
8102 | bp->link_params.speed_cap_mask = | 8147 | bp->link_params.speed_cap_mask = |
8103 | SHMEM_RD(bp, | 8148 | SHMEM_RD(bp, |
8104 | dev_info.port_hw_config[port].speed_capability_mask); | 8149 | dev_info.port_hw_config[port].speed_capability_mask); |
@@ -8119,17 +8164,10 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) | |||
8119 | bp->link_params.xgxs_config_tx[(i << 1) + 1] = (val & 0xffff); | 8164 | bp->link_params.xgxs_config_tx[(i << 1) + 1] = (val & 0xffff); |
8120 | } | 8165 | } |
8121 | 8166 | ||
8122 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); | ||
8123 | if (config & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_ENABLED) | ||
8124 | bp->link_params.feature_config_flags |= | ||
8125 | FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED; | ||
8126 | else | ||
8127 | bp->link_params.feature_config_flags &= | ||
8128 | ~FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED; | ||
8129 | |||
8130 | /* If the device is capable of WoL, set the default state according | 8167 | /* If the device is capable of WoL, set the default state according |
8131 | * to the HW | 8168 | * to the HW |
8132 | */ | 8169 | */ |
8170 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); | ||
8133 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && | 8171 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
8134 | (config & PORT_FEATURE_WOL_ENABLED)); | 8172 | (config & PORT_FEATURE_WOL_ENABLED)); |
8135 | 8173 | ||
@@ -8139,8 +8177,8 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) | |||
8139 | bp->link_params.ext_phy_config, | 8177 | bp->link_params.ext_phy_config, |
8140 | bp->link_params.speed_cap_mask, bp->port.link_config); | 8178 | bp->link_params.speed_cap_mask, bp->port.link_config); |
8141 | 8179 | ||
8142 | bp->link_params.switch_cfg = (bp->port.link_config & | 8180 | bp->link_params.switch_cfg |= (bp->port.link_config & |
8143 | PORT_FEATURE_CONNECTED_SWITCH_MASK); | 8181 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
8144 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); | 8182 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
8145 | 8183 | ||
8146 | bnx2x_link_settings_requested(bp); | 8184 | bnx2x_link_settings_requested(bp); |
@@ -8336,6 +8374,7 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
8336 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: | 8374 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: |
8337 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: | 8375 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: |
8338 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | 8376 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: |
8377 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | ||
8339 | cmd->port = PORT_FIBRE; | 8378 | cmd->port = PORT_FIBRE; |
8340 | break; | 8379 | break; |
8341 | 8380 | ||