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path: root/drivers/net/bnx2x_link.c
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Diffstat (limited to 'drivers/net/bnx2x_link.c')
-rw-r--r--drivers/net/bnx2x_link.c321
1 files changed, 206 insertions, 115 deletions
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
index e32d3370862e..cf5778919b4b 100644
--- a/drivers/net/bnx2x_link.c
+++ b/drivers/net/bnx2x_link.c
@@ -1107,18 +1107,21 @@ static void bnx2x_set_parallel_detection(struct link_params *params,
1107 MDIO_REG_BANK_SERDES_DIGITAL, 1107 MDIO_REG_BANK_SERDES_DIGITAL,
1108 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 1108 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1109 &control2); 1109 &control2);
1110 1110 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1111 1111 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1112 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 1112 else
1113 1113 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1114 1114 DP(NETIF_MSG_LINK, "params->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1115 params->speed_cap_mask, control2);
1115 CL45_WR_OVER_CL22(bp, params->port, 1116 CL45_WR_OVER_CL22(bp, params->port,
1116 params->phy_addr, 1117 params->phy_addr,
1117 MDIO_REG_BANK_SERDES_DIGITAL, 1118 MDIO_REG_BANK_SERDES_DIGITAL,
1118 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 1119 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1119 control2); 1120 control2);
1120 1121
1121 if (phy_flags & PHY_XGXS_FLAG) { 1122 if ((phy_flags & PHY_XGXS_FLAG) &&
1123 (params->speed_cap_mask &
1124 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
1122 DP(NETIF_MSG_LINK, "XGXS\n"); 1125 DP(NETIF_MSG_LINK, "XGXS\n");
1123 1126
1124 CL45_WR_OVER_CL22(bp, params->port, 1127 CL45_WR_OVER_CL22(bp, params->port,
@@ -1225,7 +1228,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
1225 params->phy_addr, 1228 params->phy_addr,
1226 MDIO_REG_BANK_CL73_USERB0, 1229 MDIO_REG_BANK_CL73_USERB0,
1227 MDIO_CL73_USERB0_CL73_UCTRL, 1230 MDIO_CL73_USERB0_CL73_UCTRL,
1228 MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL); 1231 0xe);
1229 1232
1230 /* Enable BAM Station Manager*/ 1233 /* Enable BAM Station Manager*/
1231 CL45_WR_OVER_CL22(bp, params->port, 1234 CL45_WR_OVER_CL22(bp, params->port,
@@ -1236,29 +1239,25 @@ static void bnx2x_set_autoneg(struct link_params *params,
1236 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | 1239 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1237 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); 1240 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
1238 1241
1239 /* Merge CL73 and CL37 aneg resolution */ 1242 /* Advertise CL73 link speeds */
1240 CL45_RD_OVER_CL22(bp, params->port,
1241 params->phy_addr,
1242 MDIO_REG_BANK_CL73_USERB0,
1243 MDIO_CL73_USERB0_CL73_BAM_CTRL3,
1244 &reg_val);
1245
1246 if (params->speed_cap_mask &
1247 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
1248 /* Set the CL73 AN speed */
1249 CL45_RD_OVER_CL22(bp, params->port, 1243 CL45_RD_OVER_CL22(bp, params->port,
1250 params->phy_addr, 1244 params->phy_addr,
1251 MDIO_REG_BANK_CL73_IEEEB1, 1245 MDIO_REG_BANK_CL73_IEEEB1,
1252 MDIO_CL73_IEEEB1_AN_ADV2, 1246 MDIO_CL73_IEEEB1_AN_ADV2,
1253 &reg_val); 1247 &reg_val);
1248 if (params->speed_cap_mask &
1249 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1250 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
1251 if (params->speed_cap_mask &
1252 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1253 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
1254 1254
1255 CL45_WR_OVER_CL22(bp, params->port, 1255 CL45_WR_OVER_CL22(bp, params->port,
1256 params->phy_addr, 1256 params->phy_addr,
1257 MDIO_REG_BANK_CL73_IEEEB1, 1257 MDIO_REG_BANK_CL73_IEEEB1,
1258 MDIO_CL73_IEEEB1_AN_ADV2, 1258 MDIO_CL73_IEEEB1_AN_ADV2,
1259 reg_val | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4); 1259 reg_val);
1260 1260
1261 }
1262 /* CL73 Autoneg Enabled */ 1261 /* CL73 Autoneg Enabled */
1263 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; 1262 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
1264 1263
@@ -1351,6 +1350,7 @@ static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
1351 1350
1352static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u16 *ieee_fc) 1351static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u16 *ieee_fc)
1353{ 1352{
1353 struct bnx2x *bp = params->bp;
1354 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; 1354 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
1355 /* resolve pause mode and advertisement 1355 /* resolve pause mode and advertisement
1356 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */ 1356 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
@@ -1380,18 +1380,30 @@ static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u16 *ieee_fc)
1380 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; 1380 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
1381 break; 1381 break;
1382 } 1382 }
1383 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
1383} 1384}
1384 1385
1385static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params, 1386static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
1386 u16 ieee_fc) 1387 u16 ieee_fc)
1387{ 1388{
1388 struct bnx2x *bp = params->bp; 1389 struct bnx2x *bp = params->bp;
1390 u16 val;
1389 /* for AN, we are always publishing full duplex */ 1391 /* for AN, we are always publishing full duplex */
1390 1392
1391 CL45_WR_OVER_CL22(bp, params->port, 1393 CL45_WR_OVER_CL22(bp, params->port,
1392 params->phy_addr, 1394 params->phy_addr,
1393 MDIO_REG_BANK_COMBO_IEEE0, 1395 MDIO_REG_BANK_COMBO_IEEE0,
1394 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); 1396 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
1397 CL45_RD_OVER_CL22(bp, params->port,
1398 params->phy_addr,
1399 MDIO_REG_BANK_CL73_IEEEB1,
1400 MDIO_CL73_IEEEB1_AN_ADV1, &val);
1401 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
1402 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
1403 CL45_WR_OVER_CL22(bp, params->port,
1404 params->phy_addr,
1405 MDIO_REG_BANK_CL73_IEEEB1,
1406 MDIO_CL73_IEEEB1_AN_ADV1, val);
1395} 1407}
1396 1408
1397static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73) 1409static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73)
@@ -1609,6 +1621,39 @@ static u8 bnx2x_ext_phy_resolve_fc(struct link_params *params,
1609 return ret; 1621 return ret;
1610} 1622}
1611 1623
1624static u8 bnx2x_direct_parallel_detect_used(struct link_params *params)
1625{
1626 struct bnx2x *bp = params->bp;
1627 u16 pd_10g, status2_1000x;
1628 CL45_RD_OVER_CL22(bp, params->port,
1629 params->phy_addr,
1630 MDIO_REG_BANK_SERDES_DIGITAL,
1631 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
1632 &status2_1000x);
1633 CL45_RD_OVER_CL22(bp, params->port,
1634 params->phy_addr,
1635 MDIO_REG_BANK_SERDES_DIGITAL,
1636 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
1637 &status2_1000x);
1638 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
1639 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
1640 params->port);
1641 return 1;
1642 }
1643
1644 CL45_RD_OVER_CL22(bp, params->port,
1645 params->phy_addr,
1646 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1647 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
1648 &pd_10g);
1649
1650 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
1651 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
1652 params->port);
1653 return 1;
1654 }
1655 return 0;
1656}
1612 1657
1613static void bnx2x_flow_ctrl_resolve(struct link_params *params, 1658static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1614 struct link_vars *vars, 1659 struct link_vars *vars,
@@ -1627,21 +1672,53 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1627 (!(vars->phy_flags & PHY_SGMII_FLAG)) && 1672 (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
1628 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == 1673 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1629 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) { 1674 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
1630 CL45_RD_OVER_CL22(bp, params->port, 1675 if (bnx2x_direct_parallel_detect_used(params)) {
1631 params->phy_addr, 1676 vars->flow_ctrl = params->req_fc_auto_adv;
1632 MDIO_REG_BANK_COMBO_IEEE0, 1677 return;
1633 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, 1678 }
1634 &ld_pause); 1679 if ((gp_status &
1635 CL45_RD_OVER_CL22(bp, params->port, 1680 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
1636 params->phy_addr, 1681 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
1637 MDIO_REG_BANK_COMBO_IEEE0, 1682 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
1638 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, 1683 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
1639 &lp_pause); 1684
1640 pause_result = (ld_pause & 1685 CL45_RD_OVER_CL22(bp, params->port,
1686 params->phy_addr,
1687 MDIO_REG_BANK_CL73_IEEEB1,
1688 MDIO_CL73_IEEEB1_AN_ADV1,
1689 &ld_pause);
1690 CL45_RD_OVER_CL22(bp, params->port,
1691 params->phy_addr,
1692 MDIO_REG_BANK_CL73_IEEEB1,
1693 MDIO_CL73_IEEEB1_AN_LP_ADV1,
1694 &lp_pause);
1695 pause_result = (ld_pause &
1696 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
1697 >> 8;
1698 pause_result |= (lp_pause &
1699 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
1700 >> 10;
1701 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
1702 pause_result);
1703 } else {
1704
1705 CL45_RD_OVER_CL22(bp, params->port,
1706 params->phy_addr,
1707 MDIO_REG_BANK_COMBO_IEEE0,
1708 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1709 &ld_pause);
1710 CL45_RD_OVER_CL22(bp, params->port,
1711 params->phy_addr,
1712 MDIO_REG_BANK_COMBO_IEEE0,
1713 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1714 &lp_pause);
1715 pause_result = (ld_pause &
1641 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; 1716 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
1642 pause_result |= (lp_pause & 1717 pause_result |= (lp_pause &
1643 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; 1718 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
1644 DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result); 1719 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
1720 pause_result);
1721 }
1645 bnx2x_pause_resolve(vars, pause_result); 1722 bnx2x_pause_resolve(vars, pause_result);
1646 } else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) && 1723 } else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
1647 (bnx2x_ext_phy_resolve_fc(params, vars))) { 1724 (bnx2x_ext_phy_resolve_fc(params, vars))) {
@@ -1853,6 +1930,8 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
1853 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == 1930 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1854 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) || 1931 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
1855 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == 1932 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1933 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) ||
1934 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1856 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) { 1935 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) {
1857 vars->autoneg = AUTO_NEG_ENABLED; 1936 vars->autoneg = AUTO_NEG_ENABLED;
1858 1937
@@ -1987,8 +2066,7 @@ static u8 bnx2x_emac_program(struct link_params *params,
1987 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, 2066 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
1988 mode); 2067 mode);
1989 2068
1990 bnx2x_set_led(bp, params->port, LED_MODE_OPER, 2069 bnx2x_set_led(params, LED_MODE_OPER, line_speed);
1991 line_speed, params->hw_led_mode, params->chip_id);
1992 return 0; 2070 return 0;
1993} 2071}
1994 2072
@@ -2122,6 +2200,8 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
2122 MDIO_PMA_REG_CTRL, 2200 MDIO_PMA_REG_CTRL,
2123 1<<15); 2201 1<<15);
2124 break; 2202 break;
2203 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
2204 break;
2125 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 2205 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
2126 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n"); 2206 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n");
2127 break; 2207 break;
@@ -2512,16 +2592,11 @@ static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
2512 /* Need to wait 100ms after reset */ 2592 /* Need to wait 100ms after reset */
2513 msleep(100); 2593 msleep(100);
2514 2594
2515 /* Set serial boot control for external load */
2516 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2517 MDIO_PMA_DEVAD,
2518 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2519
2520 /* Micro controller re-boot */ 2595 /* Micro controller re-boot */
2521 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2596 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2522 MDIO_PMA_DEVAD, 2597 MDIO_PMA_DEVAD,
2523 MDIO_PMA_REG_GEN_CTRL, 2598 MDIO_PMA_REG_GEN_CTRL,
2524 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 2599 0x018B);
2525 2600
2526 /* Set soft reset */ 2601 /* Set soft reset */
2527 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2602 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
@@ -2529,14 +2604,10 @@ static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
2529 MDIO_PMA_REG_GEN_CTRL, 2604 MDIO_PMA_REG_GEN_CTRL,
2530 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 2605 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2531 2606
2532 /* Set PLL register value to be same like in P13 ver */
2533 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2607 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2534 MDIO_PMA_DEVAD, 2608 MDIO_PMA_DEVAD,
2535 MDIO_PMA_REG_PLL_CTRL, 2609 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2536 0x73A0);
2537 2610
2538 /* Clear soft reset.
2539 Will automatically reset micro-controller re-boot */
2540 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2611 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2541 MDIO_PMA_DEVAD, 2612 MDIO_PMA_DEVAD,
2542 MDIO_PMA_REG_GEN_CTRL, 2613 MDIO_PMA_REG_GEN_CTRL,
@@ -3462,8 +3533,8 @@ static void bnx2x_8481_set_10G_led_mode(struct link_params *params,
3462 MDIO_PMA_REG_8481_LINK_SIGNAL, 3533 MDIO_PMA_REG_8481_LINK_SIGNAL,
3463 &val1); 3534 &val1);
3464 /* Set bit 2 to 0, and bits [1:0] to 10 */ 3535 /* Set bit 2 to 0, and bits [1:0] to 10 */
3465 val1 &= ~((1<<0) | (1<<2)); /* Clear bits 0,2*/ 3536 val1 &= ~((1<<0) | (1<<2) | (1<<7)); /* Clear bits 0,2,7*/
3466 val1 |= (1<<1); /* Set bit 1 */ 3537 val1 |= ((1<<1) | (1<<6)); /* Set bit 1, 6 */
3467 3538
3468 bnx2x_cl45_write(bp, params->port, 3539 bnx2x_cl45_write(bp, params->port,
3469 ext_phy_type, 3540 ext_phy_type,
@@ -3497,36 +3568,19 @@ static void bnx2x_8481_set_10G_led_mode(struct link_params *params,
3497 MDIO_PMA_REG_8481_LED2_MASK, 3568 MDIO_PMA_REG_8481_LED2_MASK,
3498 0); 3569 0);
3499 3570
3500 /* LED3 (10G/1G/100/10G Activity) */ 3571 /* Unmask LED3 for 10G link */
3501 bnx2x_cl45_read(bp, params->port,
3502 ext_phy_type,
3503 ext_phy_addr,
3504 MDIO_PMA_DEVAD,
3505 MDIO_PMA_REG_8481_LINK_SIGNAL,
3506 &val1);
3507 /* Enable blink based on source 4(Activity) */
3508 val1 &= ~((1<<7) | (1<<8)); /* Clear bits 7,8 */
3509 val1 |= (1<<6); /* Set only bit 6 */
3510 bnx2x_cl45_write(bp, params->port, 3572 bnx2x_cl45_write(bp, params->port,
3511 ext_phy_type, 3573 ext_phy_type,
3512 ext_phy_addr, 3574 ext_phy_addr,
3513 MDIO_PMA_DEVAD, 3575 MDIO_PMA_DEVAD,
3514 MDIO_PMA_REG_8481_LINK_SIGNAL,
3515 val1);
3516
3517 bnx2x_cl45_read(bp, params->port,
3518 ext_phy_type,
3519 ext_phy_addr,
3520 MDIO_PMA_DEVAD,
3521 MDIO_PMA_REG_8481_LED3_MASK, 3576 MDIO_PMA_REG_8481_LED3_MASK,
3522 &val1); 3577 0x6);
3523 val1 |= (1<<4); /* Unmask LED3 for 10G link */
3524 bnx2x_cl45_write(bp, params->port, 3578 bnx2x_cl45_write(bp, params->port,
3525 ext_phy_type, 3579 ext_phy_type,
3526 ext_phy_addr, 3580 ext_phy_addr,
3527 MDIO_PMA_DEVAD, 3581 MDIO_PMA_DEVAD,
3528 MDIO_PMA_REG_8481_LED3_MASK, 3582 MDIO_PMA_REG_8481_LED3_BLINK,
3529 val1); 3583 0);
3530} 3584}
3531 3585
3532 3586
@@ -3544,7 +3598,10 @@ static void bnx2x_init_internal_phy(struct link_params *params,
3544 bnx2x_set_preemphasis(params); 3598 bnx2x_set_preemphasis(params);
3545 3599
3546 /* forced speed requested? */ 3600 /* forced speed requested? */
3547 if (vars->line_speed != SPEED_AUTO_NEG) { 3601 if (vars->line_speed != SPEED_AUTO_NEG ||
3602 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
3603 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3604 params->loopback_mode == LOOPBACK_EXT)) {
3548 DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); 3605 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3549 3606
3550 /* disable autoneg */ 3607 /* disable autoneg */
@@ -3693,19 +3750,6 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3693 } 3750 }
3694 } 3751 }
3695 /* Force speed */ 3752 /* Force speed */
3696 /* First enable LASI */
3697 bnx2x_cl45_write(bp, params->port,
3698 ext_phy_type,
3699 ext_phy_addr,
3700 MDIO_PMA_DEVAD,
3701 MDIO_PMA_REG_RX_ALARM_CTRL,
3702 0x0400);
3703 bnx2x_cl45_write(bp, params->port,
3704 ext_phy_type,
3705 ext_phy_addr,
3706 MDIO_PMA_DEVAD,
3707 MDIO_PMA_REG_LASI_CTRL, 0x0004);
3708
3709 if (params->req_line_speed == SPEED_10000) { 3753 if (params->req_line_speed == SPEED_10000) {
3710 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); 3754 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
3711 3755
@@ -3715,6 +3759,9 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3715 MDIO_PMA_DEVAD, 3759 MDIO_PMA_DEVAD,
3716 MDIO_PMA_REG_DIGITAL_CTRL, 3760 MDIO_PMA_REG_DIGITAL_CTRL,
3717 0x400); 3761 0x400);
3762 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3763 ext_phy_addr, MDIO_PMA_DEVAD,
3764 MDIO_PMA_REG_LASI_CTRL, 1);
3718 } else { 3765 } else {
3719 /* Force 1Gbps using autoneg with 1G 3766 /* Force 1Gbps using autoneg with 1G
3720 advertisment */ 3767 advertisment */
@@ -3756,6 +3803,17 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3756 MDIO_AN_DEVAD, 3803 MDIO_AN_DEVAD,
3757 MDIO_AN_REG_CTRL, 3804 MDIO_AN_REG_CTRL,
3758 0x1200); 3805 0x1200);
3806 bnx2x_cl45_write(bp, params->port,
3807 ext_phy_type,
3808 ext_phy_addr,
3809 MDIO_PMA_DEVAD,
3810 MDIO_PMA_REG_RX_ALARM_CTRL,
3811 0x0400);
3812 bnx2x_cl45_write(bp, params->port,
3813 ext_phy_type,
3814 ext_phy_addr,
3815 MDIO_PMA_DEVAD,
3816 MDIO_PMA_REG_LASI_CTRL, 0x0004);
3759 3817
3760 } 3818 }
3761 bnx2x_save_bcm_spirom_ver(bp, params->port, 3819 bnx2x_save_bcm_spirom_ver(bp, params->port,
@@ -4291,6 +4349,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4291 break; 4349 break;
4292 } 4350 }
4293 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 4351 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
4352 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
4294 /* This phy uses the NIG latch mechanism since link 4353 /* This phy uses the NIG latch mechanism since link
4295 indication arrives through its LED4 and not via 4354 indication arrives through its LED4 and not via
4296 its LASI signal, so we get steady signal 4355 its LASI signal, so we get steady signal
@@ -4298,6 +4357,12 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4298 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, 4357 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
4299 1 << NIG_LATCH_BC_ENABLE_MI_INT); 4358 1 << NIG_LATCH_BC_ENABLE_MI_INT);
4300 4359
4360 bnx2x_cl45_write(bp, params->port,
4361 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
4362 ext_phy_addr,
4363 MDIO_PMA_DEVAD,
4364 MDIO_PMA_REG_CTRL, 0x0000);
4365
4301 bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr); 4366 bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr);
4302 if (params->req_line_speed == SPEED_AUTO_NEG) { 4367 if (params->req_line_speed == SPEED_AUTO_NEG) {
4303 4368
@@ -4394,17 +4459,12 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4394 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) { 4459 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
4395 DP(NETIF_MSG_LINK, "Advertising 10G\n"); 4460 DP(NETIF_MSG_LINK, "Advertising 10G\n");
4396 /* Restart autoneg for 10G*/ 4461 /* Restart autoneg for 10G*/
4397 bnx2x_cl45_read(bp, params->port, 4462
4398 ext_phy_type,
4399 ext_phy_addr,
4400 MDIO_AN_DEVAD,
4401 MDIO_AN_REG_CTRL, &val);
4402 val |= 0x200;
4403 bnx2x_cl45_write(bp, params->port, 4463 bnx2x_cl45_write(bp, params->port,
4404 ext_phy_type, 4464 ext_phy_type,
4405 ext_phy_addr, 4465 ext_phy_addr,
4406 MDIO_AN_DEVAD, 4466 MDIO_AN_DEVAD,
4407 MDIO_AN_REG_CTRL, val); 4467 MDIO_AN_REG_CTRL, 0x3200);
4408 } 4468 }
4409 } else { 4469 } else {
4410 /* Force speed */ 4470 /* Force speed */
@@ -4657,8 +4717,8 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4657 0xc809, &val1); 4717 0xc809, &val1);
4658 4718
4659 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); 4719 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4660 ext_phy_link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) 4720 ext_phy_link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) &&
4661 && ((val1 & (1<<8)) == 0)); 4721 ((val1 & (1<<8)) == 0));
4662 if (ext_phy_link_up) 4722 if (ext_phy_link_up)
4663 vars->line_speed = SPEED_10000; 4723 vars->line_speed = SPEED_10000;
4664 break; 4724 break;
@@ -5148,6 +5208,7 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
5148 } 5208 }
5149 break; 5209 break;
5150 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 5210 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
5211 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
5151 /* Check 10G-BaseT link status */ 5212 /* Check 10G-BaseT link status */
5152 /* Check PMD signal ok */ 5213 /* Check PMD signal ok */
5153 bnx2x_cl45_read(bp, params->port, ext_phy_type, 5214 bnx2x_cl45_read(bp, params->port, ext_phy_type,
@@ -5363,8 +5424,10 @@ static void bnx2x_link_int_ack(struct link_params *params,
5363 (NIG_STATUS_XGXS0_LINK10G | 5424 (NIG_STATUS_XGXS0_LINK10G |
5364 NIG_STATUS_XGXS0_LINK_STATUS | 5425 NIG_STATUS_XGXS0_LINK_STATUS |
5365 NIG_STATUS_SERDES0_LINK_STATUS)); 5426 NIG_STATUS_SERDES0_LINK_STATUS));
5366 if (XGXS_EXT_PHY_TYPE(params->ext_phy_config) 5427 if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config)
5367 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) { 5428 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) ||
5429 (XGXS_EXT_PHY_TYPE(params->ext_phy_config)
5430 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823)) {
5368 bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int); 5431 bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int);
5369 } 5432 }
5370 if (vars->phy_link_up) { 5433 if (vars->phy_link_up) {
@@ -5477,6 +5540,7 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5477 status = bnx2x_format_ver(spirom_ver, version, len); 5540 status = bnx2x_format_ver(spirom_ver, version, len);
5478 break; 5541 break;
5479 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 5542 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
5543 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
5480 spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 | 5544 spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 |
5481 (spirom_ver & 0x7F); 5545 (spirom_ver & 0x7F);
5482 status = bnx2x_format_ver(spirom_ver, version, len); 5546 status = bnx2x_format_ver(spirom_ver, version, len);
@@ -5728,13 +5792,15 @@ u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port,
5728} 5792}
5729 5793
5730 5794
5731u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed, 5795u8 bnx2x_set_led(struct link_params *params, u8 mode, u32 speed)
5732 u16 hw_led_mode, u32 chip_id)
5733{ 5796{
5797 u8 port = params->port;
5798 u16 hw_led_mode = params->hw_led_mode;
5734 u8 rc = 0; 5799 u8 rc = 0;
5735 u32 tmp; 5800 u32 tmp;
5736 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 5801 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5737 5802 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5803 struct bnx2x *bp = params->bp;
5738 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); 5804 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5739 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", 5805 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5740 speed, hw_led_mode); 5806 speed, hw_led_mode);
@@ -5749,7 +5815,14 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
5749 break; 5815 break;
5750 5816
5751 case LED_MODE_OPER: 5817 case LED_MODE_OPER:
5752 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode); 5818 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5819 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5820 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5821 } else {
5822 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5823 hw_led_mode);
5824 }
5825
5753 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + 5826 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
5754 port*4, 0); 5827 port*4, 0);
5755 /* Set blinking rate to ~15.9Hz */ 5828 /* Set blinking rate to ~15.9Hz */
@@ -5761,7 +5834,7 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
5761 EMAC_WR(bp, EMAC_REG_EMAC_LED, 5834 EMAC_WR(bp, EMAC_REG_EMAC_LED,
5762 (tmp & (~EMAC_LED_OVERRIDE))); 5835 (tmp & (~EMAC_LED_OVERRIDE)));
5763 5836
5764 if (!CHIP_IS_E1H(bp) && 5837 if (CHIP_IS_E1(bp) &&
5765 ((speed == SPEED_2500) || 5838 ((speed == SPEED_2500) ||
5766 (speed == SPEED_1000) || 5839 (speed == SPEED_1000) ||
5767 (speed == SPEED_100) || 5840 (speed == SPEED_100) ||
@@ -5864,6 +5937,7 @@ static u8 bnx2x_link_initialize(struct link_params *params,
5864 5937
5865 if (non_ext_phy || 5938 if (non_ext_phy ||
5866 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) || 5939 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
5940 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) ||
5867 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) || 5941 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
5868 (params->loopback_mode == LOOPBACK_EXT_PHY)) { 5942 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
5869 if (params->req_line_speed == SPEED_AUTO_NEG) 5943 if (params->req_line_speed == SPEED_AUTO_NEG)
@@ -6030,10 +6104,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
6030 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + 6104 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6031 params->port*4, 0); 6105 params->port*4, 0);
6032 6106
6033 bnx2x_set_led(bp, params->port, LED_MODE_OPER, 6107 bnx2x_set_led(params, LED_MODE_OPER, vars->line_speed);
6034 vars->line_speed, params->hw_led_mode,
6035 params->chip_id);
6036
6037 } else 6108 } else
6038 /* No loopback */ 6109 /* No loopback */
6039 { 6110 {
@@ -6091,15 +6162,13 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6091{ 6162{
6092 struct bnx2x *bp = params->bp; 6163 struct bnx2x *bp = params->bp;
6093 u32 ext_phy_config = params->ext_phy_config; 6164 u32 ext_phy_config = params->ext_phy_config;
6094 u16 hw_led_mode = params->hw_led_mode;
6095 u32 chip_id = params->chip_id;
6096 u8 port = params->port; 6165 u8 port = params->port;
6097 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 6166 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
6098 u32 val = REG_RD(bp, params->shmem_base + 6167 u32 val = REG_RD(bp, params->shmem_base +
6099 offsetof(struct shmem_region, dev_info. 6168 offsetof(struct shmem_region, dev_info.
6100 port_feature_config[params->port]. 6169 port_feature_config[params->port].
6101 config)); 6170 config));
6102 6171 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
6103 /* disable attentions */ 6172 /* disable attentions */
6104 vars->link_status = 0; 6173 vars->link_status = 0;
6105 bnx2x_update_mng(params, vars->link_status); 6174 bnx2x_update_mng(params, vars->link_status);
@@ -6127,7 +6196,7 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6127 * Hold it as vars low 6196 * Hold it as vars low
6128 */ 6197 */
6129 /* clear link led */ 6198 /* clear link led */
6130 bnx2x_set_led(bp, port, LED_MODE_OFF, 0, hw_led_mode, chip_id); 6199 bnx2x_set_led(params, LED_MODE_OFF, 0);
6131 if (reset_ext_phy) { 6200 if (reset_ext_phy) {
6132 switch (ext_phy_type) { 6201 switch (ext_phy_type) {
6133 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 6202 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
@@ -6163,6 +6232,22 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6163 bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr); 6232 bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr);
6164 break; 6233 break;
6165 } 6234 }
6235 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
6236 {
6237 u8 ext_phy_addr =
6238 XGXS_EXT_PHY_ADDR(params->ext_phy_config);
6239 bnx2x_cl45_write(bp, port,
6240 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
6241 ext_phy_addr,
6242 MDIO_AN_DEVAD,
6243 MDIO_AN_REG_CTRL, 0x0000);
6244 bnx2x_cl45_write(bp, port,
6245 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
6246 ext_phy_addr,
6247 MDIO_PMA_DEVAD,
6248 MDIO_PMA_REG_CTRL, 1);
6249 break;
6250 }
6166 default: 6251 default:
6167 /* HW reset */ 6252 /* HW reset */
6168 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6253 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
@@ -6198,9 +6283,7 @@ static u8 bnx2x_update_link_down(struct link_params *params,
6198 u8 port = params->port; 6283 u8 port = params->port;
6199 6284
6200 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); 6285 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6201 bnx2x_set_led(bp, port, LED_MODE_OFF, 6286 bnx2x_set_led(params, LED_MODE_OFF, 0);
6202 0, params->hw_led_mode,
6203 params->chip_id);
6204 6287
6205 /* indicate no mac active */ 6288 /* indicate no mac active */
6206 vars->mac_type = MAC_TYPE_NONE; 6289 vars->mac_type = MAC_TYPE_NONE;
@@ -6237,15 +6320,13 @@ static u8 bnx2x_update_link_up(struct link_params *params,
6237 vars->link_status |= LINK_STATUS_LINK_UP; 6320 vars->link_status |= LINK_STATUS_LINK_UP;
6238 if (link_10g) { 6321 if (link_10g) {
6239 bnx2x_bmac_enable(params, vars, 0); 6322 bnx2x_bmac_enable(params, vars, 0);
6240 bnx2x_set_led(bp, port, LED_MODE_OPER, 6323 bnx2x_set_led(params, LED_MODE_OPER, SPEED_10000);
6241 SPEED_10000, params->hw_led_mode,
6242 params->chip_id);
6243
6244 } else { 6324 } else {
6245 bnx2x_emac_enable(params, vars, 0);
6246 rc = bnx2x_emac_program(params, vars->line_speed, 6325 rc = bnx2x_emac_program(params, vars->line_speed,
6247 vars->duplex); 6326 vars->duplex);
6248 6327
6328 bnx2x_emac_enable(params, vars, 0);
6329
6249 /* AN complete? */ 6330 /* AN complete? */
6250 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) { 6331 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
6251 if (!(vars->phy_flags & 6332 if (!(vars->phy_flags &
@@ -6343,6 +6424,7 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6343 6424
6344 if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) && 6425 if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
6345 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) && 6426 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
6427 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) &&
6346 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) && 6428 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) &&
6347 (ext_phy_link_up && !vars->phy_link_up)) 6429 (ext_phy_link_up && !vars->phy_link_up))
6348 bnx2x_init_internal_phy(params, vars, 0); 6430 bnx2x_init_internal_phy(params, vars, 0);
@@ -6578,6 +6660,13 @@ static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6578 return 0; 6660 return 0;
6579} 6661}
6580 6662
6663
6664static u8 bnx2x_84823_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6665{
6666 /* HW reset */
6667 bnx2x_ext_phy_hw_reset(bp, 1);
6668 return 0;
6669}
6581u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base) 6670u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6582{ 6671{
6583 u8 rc = 0; 6672 u8 rc = 0;
@@ -6607,7 +6696,9 @@ u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6607 /* GPIO1 affects both ports, so there's need to pull 6696 /* GPIO1 affects both ports, so there's need to pull
6608 it for single port alone */ 6697 it for single port alone */
6609 rc = bnx2x_8726_common_init_phy(bp, shmem_base); 6698 rc = bnx2x_8726_common_init_phy(bp, shmem_base);
6610 6699 break;
6700 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
6701 rc = bnx2x_84823_common_init_phy(bp, shmem_base);
6611 break; 6702 break;
6612 default: 6703 default:
6613 DP(NETIF_MSG_LINK, 6704 DP(NETIF_MSG_LINK,
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-03 13:51:51 -0400