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path: root/drivers/net/bnx2x_link.c
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Diffstat (limited to 'drivers/net/bnx2x_link.c')
-rw-r--r--drivers/net/bnx2x_link.c427
1 files changed, 0 insertions, 427 deletions
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
index 98e3e8fc0ef7..dc3b69e1fd1d 100644
--- a/drivers/net/bnx2x_link.c
+++ b/drivers/net/bnx2x_link.c
@@ -5471,59 +5471,6 @@ static u8 bnx2x_format_ver(u32 num, u8 *str, u16 len)
5471 return 0; 5471 return 0;
5472} 5472}
5473 5473
5474
5475static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr,
5476 u32 ext_phy_type)
5477{
5478 u32 cnt = 0;
5479 u16 ctrl = 0;
5480 /* Enable EMAC0 in to enable MDIO */
5481 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
5482 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
5483 msleep(5);
5484
5485 /* take ext phy out of reset */
5486 bnx2x_set_gpio(bp,
5487 MISC_REGISTERS_GPIO_2,
5488 MISC_REGISTERS_GPIO_HIGH,
5489 port);
5490
5491 bnx2x_set_gpio(bp,
5492 MISC_REGISTERS_GPIO_1,
5493 MISC_REGISTERS_GPIO_HIGH,
5494 port);
5495
5496 /* wait for 5ms */
5497 msleep(5);
5498
5499 for (cnt = 0; cnt < 1000; cnt++) {
5500 msleep(1);
5501 bnx2x_cl45_read(bp, port,
5502 ext_phy_type,
5503 ext_phy_addr,
5504 MDIO_PMA_DEVAD,
5505 MDIO_PMA_REG_CTRL,
5506 &ctrl);
5507 if (!(ctrl & (1<<15))) {
5508 DP(NETIF_MSG_LINK, "Reset completed\n\n");
5509 break;
5510 }
5511 }
5512}
5513
5514static void bnx2x_turn_off_sf(struct bnx2x *bp, u8 port)
5515{
5516 /* put sf to reset */
5517 bnx2x_set_gpio(bp,
5518 MISC_REGISTERS_GPIO_1,
5519 MISC_REGISTERS_GPIO_LOW,
5520 port);
5521 bnx2x_set_gpio(bp,
5522 MISC_REGISTERS_GPIO_2,
5523 MISC_REGISTERS_GPIO_LOW,
5524 port);
5525}
5526
5527u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, 5474u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5528 u8 *version, u16 len) 5475 u8 *version, u16 len)
5529{ 5476{
@@ -6743,377 +6690,3 @@ void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr)
6743 break; 6690 break;
6744 } 6691 }
6745} 6692}
6746#define RESERVED_SIZE 256
6747/* max application is 160K bytes - data at end of RAM */
6748#define MAX_APP_SIZE (160*1024 - RESERVED_SIZE)
6749
6750/* Header is 14 bytes */
6751#define HEADER_SIZE 14
6752#define DATA_OFFSET HEADER_SIZE
6753
6754#define SPI_START_TRANSFER(bp, port, ext_phy_addr) \
6755 bnx2x_cl45_write(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, \
6756 ext_phy_addr, \
6757 MDIO_PCS_DEVAD, \
6758 MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 1)
6759
6760/* Programs an image to DSP's flash via the SPI port*/
6761static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
6762 u8 ext_phy_addr,
6763 char data[], u32 size)
6764{
6765 const u16 num_trans = size/4; /* 4 bytes can be sent at a time */
6766 /* Doesn't include last trans!*/
6767 const u16 last_trans_size = size%4; /* Num bytes on last trans */
6768 u16 trans_cnt, byte_cnt;
6769 u32 data_index;
6770 u16 tmp;
6771 u16 code_started = 0;
6772 u16 image_revision1, image_revision2;
6773 u16 cnt;
6774
6775 DP(NETIF_MSG_LINK, "bnx2x_sfx7101_flash_download file_size=%d\n", size);
6776 /* Going to flash*/
6777 if ((size-HEADER_SIZE) > MAX_APP_SIZE) {
6778 /* This very often will be the case, because the image is built
6779 with 160Kbytes size whereas the total image size must actually
6780 be 160Kbytes-RESERVED_SIZE */
6781 DP(NETIF_MSG_LINK, "Warning, file size was %d bytes "
6782 "truncated to %d bytes\n", size, MAX_APP_SIZE);
6783 size = MAX_APP_SIZE+HEADER_SIZE;
6784 }
6785 DP(NETIF_MSG_LINK, "File version is %c%c\n", data[0x14e], data[0x14f]);
6786 DP(NETIF_MSG_LINK, " %c%c\n", data[0x150], data[0x151]);
6787 /* Put the DSP in download mode by setting FLASH_CFG[2] to 1
6788 and issuing a reset.*/
6789
6790 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
6791 MISC_REGISTERS_GPIO_HIGH, port);
6792
6793 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
6794
6795 /* wait 0.5 sec */
6796 for (cnt = 0; cnt < 100; cnt++)
6797 msleep(5);
6798
6799 /* Make sure we can access the DSP
6800 And it's in the correct mode (waiting for download) */
6801
6802 bnx2x_cl45_read(bp, port,
6803 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6804 ext_phy_addr,
6805 MDIO_PCS_DEVAD,
6806 MDIO_PCS_REG_7101_DSP_ACCESS, &tmp);
6807
6808 if (tmp != 0x000A) {
6809 DP(NETIF_MSG_LINK, "DSP is not in waiting on download mode. "
6810 "Expected 0x000A, read 0x%04X\n", tmp);
6811 DP(NETIF_MSG_LINK, "Download failed\n");
6812 return -EINVAL;
6813 }
6814
6815 /* Mux the SPI interface away from the internal processor */
6816 bnx2x_cl45_write(bp, port,
6817 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6818 ext_phy_addr,
6819 MDIO_PCS_DEVAD,
6820 MDIO_PCS_REG_7101_SPI_MUX, 1);
6821
6822 /* Reset the SPI port */
6823 bnx2x_cl45_write(bp, port,
6824 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6825 ext_phy_addr,
6826 MDIO_PCS_DEVAD,
6827 MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 0);
6828 bnx2x_cl45_write(bp, port,
6829 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6830 ext_phy_addr,
6831 MDIO_PCS_DEVAD,
6832 MDIO_PCS_REG_7101_SPI_CTRL_ADDR,
6833 (1<<MDIO_PCS_REG_7101_SPI_RESET_BIT));
6834 bnx2x_cl45_write(bp, port,
6835 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6836 ext_phy_addr,
6837 MDIO_PCS_DEVAD,
6838 MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 0);
6839
6840 /* Erase the flash */
6841 bnx2x_cl45_write(bp, port,
6842 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6843 ext_phy_addr,
6844 MDIO_PCS_DEVAD,
6845 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6846 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
6847
6848 bnx2x_cl45_write(bp, port,
6849 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6850 ext_phy_addr,
6851 MDIO_PCS_DEVAD,
6852 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6853 1);
6854
6855 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6856 bnx2x_cl45_write(bp, port,
6857 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6858 ext_phy_addr,
6859 MDIO_PCS_DEVAD,
6860 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6861 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD);
6862
6863 bnx2x_cl45_write(bp, port,
6864 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6865 ext_phy_addr,
6866 MDIO_PCS_DEVAD,
6867 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6868 1);
6869 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6870
6871 /* Wait 10 seconds, the maximum time for the erase to complete */
6872 DP(NETIF_MSG_LINK, "Erasing flash, this takes 10 seconds...\n");
6873 for (cnt = 0; cnt < 1000; cnt++)
6874 msleep(10);
6875
6876 DP(NETIF_MSG_LINK, "Downloading flash, please wait...\n");
6877 data_index = 0;
6878 for (trans_cnt = 0; trans_cnt < num_trans; trans_cnt++) {
6879 bnx2x_cl45_write(bp, port,
6880 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6881 ext_phy_addr,
6882 MDIO_PCS_DEVAD,
6883 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6884 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
6885
6886 bnx2x_cl45_write(bp, port,
6887 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6888 ext_phy_addr,
6889 MDIO_PCS_DEVAD,
6890 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6891 1);
6892 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6893
6894 bnx2x_cl45_write(bp, port,
6895 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6896 ext_phy_addr,
6897 MDIO_PCS_DEVAD,
6898 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6899 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD);
6900
6901 /* Bits 23-16 of address */
6902 bnx2x_cl45_write(bp, port,
6903 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6904 ext_phy_addr,
6905 MDIO_PCS_DEVAD,
6906 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6907 (data_index>>16));
6908 /* Bits 15-8 of address */
6909 bnx2x_cl45_write(bp, port,
6910 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6911 ext_phy_addr,
6912 MDIO_PCS_DEVAD,
6913 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6914 (data_index>>8));
6915
6916 /* Bits 7-0 of address */
6917 bnx2x_cl45_write(bp, port,
6918 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6919 ext_phy_addr,
6920 MDIO_PCS_DEVAD,
6921 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6922 ((u16)data_index));
6923
6924 byte_cnt = 0;
6925 while (byte_cnt < 4 && data_index < size) {
6926 bnx2x_cl45_write(bp, port,
6927 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6928 ext_phy_addr,
6929 MDIO_PCS_DEVAD,
6930 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6931 data[data_index++]);
6932 byte_cnt++;
6933 }
6934
6935 bnx2x_cl45_write(bp, port,
6936 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6937 ext_phy_addr,
6938 MDIO_PCS_DEVAD,
6939 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6940 byte_cnt+4);
6941
6942 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6943 msleep(5); /* Wait 5 ms minimum between transs */
6944
6945 /* Let the user know something's going on.*/
6946 /* a pacifier ever 4K */
6947 if ((data_index % 1023) == 0)
6948 DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size);
6949 }
6950
6951 DP(NETIF_MSG_LINK, "\n");
6952 /* Transfer the last block if there is data remaining */
6953 if (last_trans_size) {
6954 bnx2x_cl45_write(bp, port,
6955 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6956 ext_phy_addr,
6957 MDIO_PCS_DEVAD,
6958 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6959 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
6960
6961 bnx2x_cl45_write(bp, port,
6962 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6963 ext_phy_addr,
6964 MDIO_PCS_DEVAD,
6965 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6966 1);
6967
6968 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6969
6970 bnx2x_cl45_write(bp, port,
6971 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6972 ext_phy_addr,
6973 MDIO_PCS_DEVAD,
6974 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6975 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD);
6976
6977 /* Bits 23-16 of address */
6978 bnx2x_cl45_write(bp, port,
6979 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6980 ext_phy_addr,
6981 MDIO_PCS_DEVAD,
6982 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6983 (data_index>>16));
6984 /* Bits 15-8 of address */
6985 bnx2x_cl45_write(bp, port,
6986 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6987 ext_phy_addr,
6988 MDIO_PCS_DEVAD,
6989 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6990 (data_index>>8));
6991
6992 /* Bits 7-0 of address */
6993 bnx2x_cl45_write(bp, port,
6994 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6995 ext_phy_addr,
6996 MDIO_PCS_DEVAD,
6997 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6998 ((u16)data_index));
6999
7000 byte_cnt = 0;
7001 while (byte_cnt < last_trans_size && data_index < size) {
7002 /* Bits 7-0 of address */
7003 bnx2x_cl45_write(bp, port,
7004 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
7005 ext_phy_addr,
7006 MDIO_PCS_DEVAD,
7007 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
7008 data[data_index++]);
7009 byte_cnt++;
7010 }
7011
7012 bnx2x_cl45_write(bp, port,
7013 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
7014 ext_phy_addr,
7015 MDIO_PCS_DEVAD,
7016 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
7017 byte_cnt+4);
7018
7019 SPI_START_TRANSFER(bp, port, ext_phy_addr);
7020 }
7021
7022 /* DSP Remove Download Mode */
7023 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
7024 MISC_REGISTERS_GPIO_LOW, port);
7025
7026 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
7027
7028 /* wait 0.5 sec to allow it to run */
7029 for (cnt = 0; cnt < 100; cnt++)
7030 msleep(5);
7031
7032 bnx2x_ext_phy_hw_reset(bp, port);
7033
7034 for (cnt = 0; cnt < 100; cnt++)
7035 msleep(5);
7036
7037 /* Check that the code is started. In case the download
7038 checksum failed, the code won't be started. */
7039 bnx2x_cl45_read(bp, port,
7040 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
7041 ext_phy_addr,
7042 MDIO_PCS_DEVAD,
7043 MDIO_PCS_REG_7101_DSP_ACCESS,
7044 &tmp);
7045
7046 code_started = (tmp & (1<<4));
7047 if (!code_started) {
7048 DP(NETIF_MSG_LINK, "Download failed. Please check file.\n");
7049 return -EINVAL;
7050 }
7051
7052 /* Verify that the file revision is now equal to the image
7053 revision within the DSP */
7054 bnx2x_cl45_read(bp, port,
7055 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
7056 ext_phy_addr,
7057 MDIO_PMA_DEVAD,
7058 MDIO_PMA_REG_7101_VER1,
7059 &image_revision1);
7060
7061 bnx2x_cl45_read(bp, port,
7062 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
7063 ext_phy_addr,
7064 MDIO_PMA_DEVAD,
7065 MDIO_PMA_REG_7101_VER2,
7066 &image_revision2);
7067
7068 if (data[0x14e] != (image_revision2&0xFF) ||
7069 data[0x14f] != ((image_revision2&0xFF00)>>8) ||
7070 data[0x150] != (image_revision1&0xFF) ||
7071 data[0x151] != ((image_revision1&0xFF00)>>8)) {
7072 DP(NETIF_MSG_LINK, "Download failed.\n");
7073 return -EINVAL;
7074 }
7075 DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size);
7076 return 0;
7077}
7078
7079u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
7080 u8 driver_loaded, char data[], u32 size)
7081{
7082 u8 rc = 0;
7083 u32 ext_phy_type;
7084 u8 ext_phy_addr;
7085 ext_phy_addr = ((ext_phy_config &
7086 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
7087 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
7088
7089 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
7090
7091 switch (ext_phy_type) {
7092 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
7093 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7094 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7095 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7096 DP(NETIF_MSG_LINK,
7097 "Flash download not supported for this ext phy\n");
7098 rc = -EINVAL;
7099 break;
7100 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7101 /* Take ext phy out of reset */
7102 if (!driver_loaded)
7103 bnx2x_turn_on_ef(bp, port, ext_phy_addr, ext_phy_type);
7104 rc = bnx2x_sfx7101_flash_download(bp, port, ext_phy_addr,
7105 data, size);
7106 if (!driver_loaded)
7107 bnx2x_turn_off_sf(bp, port);
7108 break;
7109 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7110 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7111 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
7112 default:
7113 DP(NETIF_MSG_LINK, "Invalid ext phy type\n");
7114 rc = -EINVAL;
7115 break;
7116 }
7117 return rc;
7118}
7119
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 02:25:07 -0500