aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/bnx2x_init.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/bnx2x_init.h')
-rw-r--r--drivers/net/bnx2x_init.h564
1 files changed, 564 insertions, 0 deletions
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
new file mode 100644
index 000000000000..04f93bff2ef4
--- /dev/null
+++ b/drivers/net/bnx2x_init.h
@@ -0,0 +1,564 @@
1/* bnx2x_init.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Eliezer Tamir <eliezert@broadcom.com>
10 */
11
12#ifndef BNX2X_INIT_H
13#define BNX2X_INIT_H
14
15#define COMMON 0x1
16#define PORT0 0x2
17#define PORT1 0x4
18
19#define INIT_EMULATION 0x1
20#define INIT_FPGA 0x2
21#define INIT_ASIC 0x4
22#define INIT_HARDWARE 0x7
23
24#define STORM_INTMEM_SIZE (0x5800 / 4)
25#define TSTORM_INTMEM_ADDR 0x1a0000
26#define CSTORM_INTMEM_ADDR 0x220000
27#define XSTORM_INTMEM_ADDR 0x2a0000
28#define USTORM_INTMEM_ADDR 0x320000
29
30
31/* Init operation types and structures */
32
33#define OP_RD 0x1 /* read single register */
34#define OP_WR 0x2 /* write single register */
35#define OP_IW 0x3 /* write single register using mailbox */
36#define OP_SW 0x4 /* copy a string to the device */
37#define OP_SI 0x5 /* copy a string using mailbox */
38#define OP_ZR 0x6 /* clear memory */
39#define OP_ZP 0x7 /* unzip then copy with DMAE */
40#define OP_WB 0x8 /* copy a string using DMAE */
41
42struct raw_op {
43 u32 op :8;
44 u32 offset :24;
45 u32 raw_data;
46};
47
48struct op_read {
49 u32 op :8;
50 u32 offset :24;
51 u32 pad;
52};
53
54struct op_write {
55 u32 op :8;
56 u32 offset :24;
57 u32 val;
58};
59
60struct op_string_write {
61 u32 op :8;
62 u32 offset :24;
63#ifdef __LITTLE_ENDIAN
64 u16 data_off;
65 u16 data_len;
66#else /* __BIG_ENDIAN */
67 u16 data_len;
68 u16 data_off;
69#endif
70};
71
72struct op_zero {
73 u32 op :8;
74 u32 offset :24;
75 u32 len;
76};
77
78union init_op {
79 struct op_read read;
80 struct op_write write;
81 struct op_string_write str_wr;
82 struct op_zero zero;
83 struct raw_op raw;
84};
85
86#include "bnx2x_init_values.h"
87
88static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
89
90static void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
91 u32 dst_addr, u32 len32);
92
93static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len);
94
95static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
96 u32 len)
97{
98 int i;
99
100 for (i = 0; i < len; i++) {
101 REG_WR(bp, addr + i*4, data[i]);
102 if (!(i % 10000)) {
103 touch_softlockup_watchdog();
104 cpu_relax();
105 }
106 }
107}
108
109#define INIT_MEM_WR(reg, data, reg_off, len) \
110 bnx2x_init_str_wr(bp, reg + reg_off*4, data, len)
111
112static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
113 u16 len)
114{
115 int i;
116
117 for (i = 0; i < len; i++) {
118 REG_WR_IND(bp, addr + i*4, data[i]);
119 if (!(i % 10000)) {
120 touch_softlockup_watchdog();
121 cpu_relax();
122 }
123 }
124}
125
126static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
127 u32 len, int gunzip)
128{
129 int offset = 0;
130
131 if (gunzip) {
132 int rc;
133#ifdef __BIG_ENDIAN
134 int i, size;
135 u32 *temp;
136
137 temp = kmalloc(len, GFP_KERNEL);
138 size = (len / 4) + ((len % 4) ? 1 : 0);
139 for (i = 0; i < size; i++)
140 temp[i] = swab32(data[i]);
141 data = temp;
142#endif
143 rc = bnx2x_gunzip(bp, (u8 *)data, len);
144 if (rc) {
145 DP(NETIF_MSG_HW, "gunzip failed ! rc %d\n", rc);
146 return;
147 }
148 len = bp->gunzip_outlen;
149#ifdef __BIG_ENDIAN
150 kfree(temp);
151 for (i = 0; i < len; i++)
152 ((u32 *)bp->gunzip_buf)[i] =
153 swab32(((u32 *)bp->gunzip_buf)[i]);
154#endif
155 } else {
156 if ((len * 4) > FW_BUF_SIZE) {
157 BNX2X_ERR("LARGE DMAE OPERATION ! len 0x%x\n", len*4);
158 return;
159 }
160 memcpy(bp->gunzip_buf, data, len * 4);
161 }
162
163 while (len > DMAE_LEN32_MAX) {
164 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
165 addr + offset, DMAE_LEN32_MAX);
166 offset += DMAE_LEN32_MAX * 4;
167 len -= DMAE_LEN32_MAX;
168 }
169 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, addr + offset, len);
170}
171
172#define INIT_MEM_WB(reg, data, reg_off, len) \
173 bnx2x_init_wr_wb(bp, reg + reg_off*4, data, len, 0)
174
175#define INIT_GUNZIP_DMAE(reg, data, reg_off, len) \
176 bnx2x_init_wr_wb(bp, reg + reg_off*4, data, len, 1)
177
178static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
179{
180 int offset = 0;
181
182 if ((len * 4) > FW_BUF_SIZE) {
183 BNX2X_ERR("LARGE DMAE OPERATION ! len 0x%x\n", len * 4);
184 return;
185 }
186 memset(bp->gunzip_buf, fill, len * 4);
187
188 while (len > DMAE_LEN32_MAX) {
189 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
190 addr + offset, DMAE_LEN32_MAX);
191 offset += DMAE_LEN32_MAX * 4;
192 len -= DMAE_LEN32_MAX;
193 }
194 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, addr + offset, len);
195}
196
197static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
198{
199 int i;
200 union init_op *op;
201 u32 op_type, addr, len;
202 const u32 *data;
203
204 for (i = op_start; i < op_end; i++) {
205
206 op = (union init_op *)&(init_ops[i]);
207
208 op_type = op->str_wr.op;
209 addr = op->str_wr.offset;
210 len = op->str_wr.data_len;
211 data = init_data + op->str_wr.data_off;
212
213 switch (op_type) {
214 case OP_RD:
215 REG_RD(bp, addr);
216 break;
217 case OP_WR:
218 REG_WR(bp, addr, op->write.val);
219 break;
220 case OP_SW:
221 bnx2x_init_str_wr(bp, addr, data, len);
222 break;
223 case OP_WB:
224 bnx2x_init_wr_wb(bp, addr, data, len, 0);
225 break;
226 case OP_SI:
227 bnx2x_init_ind_wr(bp, addr, data, len);
228 break;
229 case OP_ZR:
230 bnx2x_init_fill(bp, addr, 0, op->zero.len);
231 break;
232 case OP_ZP:
233 bnx2x_init_wr_wb(bp, addr, data, len, 1);
234 break;
235 default:
236 BNX2X_ERR("BAD init operation!\n");
237 }
238 }
239}
240
241
242/****************************************************************************
243* PXP
244****************************************************************************/
245/*
246 * This code configures the PCI read/write arbiter
247 * which implements a wighted round robin
248 * between the virtual queues in the chip.
249 *
250 * The values were derived for each PCI max payload and max request size.
251 * since max payload and max request size are only known at run time,
252 * this is done as a separate init stage.
253 */
254
255#define NUM_WR_Q 13
256#define NUM_RD_Q 29
257#define MAX_RD_ORD 3
258#define MAX_WR_ORD 2
259
260/* configuration for one arbiter queue */
261struct arb_line {
262 int l;
263 int add;
264 int ubound;
265};
266
267/* derived configuration for each read queue for each max request size */
268static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
269 {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} },
270 {{4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4} },
271 {{4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3} },
272 {{8 , 3 , 6}, {16 , 3 , 11}, {16 , 3 , 11}, {16 , 3 , 11} },
273 {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} },
274 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },
275 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },
276 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },
277 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },
278 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
279 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
280 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
281 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
282 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
283 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
284 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
285 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
286 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
287 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
288 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
289 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
290 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
291 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
292 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
293 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
294 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
295 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
296 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
297 {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81}, {64 , 64 , 120} }
298};
299
300/* derived configuration for each write queue for each max request size */
301static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
302 {{4 , 6 , 3}, {4 , 6 , 3}, {4 , 6 , 3} },
303 {{4 , 2 , 3}, {4 , 2 , 3}, {4 , 2 , 3} },
304 {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} },
305 {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} },
306 {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} },
307 {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} },
308 {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25} },
309 {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} },
310 {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} },
311 {{8 , 9 , 6}, {16 , 9 , 11}, {32 , 9 , 21} },
312 {{8 , 47 , 19}, {16 , 47 , 19}, {32 , 47 , 21} },
313 {{8 , 9 , 6}, {16 , 9 , 11}, {16 , 9 , 11} },
314 {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81} }
315};
316
317/* register adresses for read queues */
318static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
319 {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
320 PXP2_REG_RQ_BW_RD_UBOUND0},
321 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
322 PXP2_REG_PSWRQ_BW_UB1},
323 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
324 PXP2_REG_PSWRQ_BW_UB2},
325 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
326 PXP2_REG_PSWRQ_BW_UB3},
327 {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
328 PXP2_REG_RQ_BW_RD_UBOUND4},
329 {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
330 PXP2_REG_RQ_BW_RD_UBOUND5},
331 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
332 PXP2_REG_PSWRQ_BW_UB6},
333 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
334 PXP2_REG_PSWRQ_BW_UB7},
335 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
336 PXP2_REG_PSWRQ_BW_UB8},
337 {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
338 PXP2_REG_PSWRQ_BW_UB9},
339 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
340 PXP2_REG_PSWRQ_BW_UB10},
341 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
342 PXP2_REG_PSWRQ_BW_UB11},
343 {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
344 PXP2_REG_RQ_BW_RD_UBOUND12},
345 {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
346 PXP2_REG_RQ_BW_RD_UBOUND13},
347 {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
348 PXP2_REG_RQ_BW_RD_UBOUND14},
349 {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
350 PXP2_REG_RQ_BW_RD_UBOUND15},
351 {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
352 PXP2_REG_RQ_BW_RD_UBOUND16},
353 {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
354 PXP2_REG_RQ_BW_RD_UBOUND17},
355 {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
356 PXP2_REG_RQ_BW_RD_UBOUND18},
357 {PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
358 PXP2_REG_RQ_BW_RD_UBOUND19},
359 {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
360 PXP2_REG_RQ_BW_RD_UBOUND20},
361 {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
362 PXP2_REG_RQ_BW_RD_UBOUND22},
363 {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
364 PXP2_REG_RQ_BW_RD_UBOUND23},
365 {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
366 PXP2_REG_RQ_BW_RD_UBOUND24},
367 {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
368 PXP2_REG_RQ_BW_RD_UBOUND25},
369 {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
370 PXP2_REG_RQ_BW_RD_UBOUND26},
371 {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
372 PXP2_REG_RQ_BW_RD_UBOUND27},
373 {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
374 PXP2_REG_PSWRQ_BW_UB28}
375};
376
377/* register adresses for wrtie queues */
378static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
379 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
380 PXP2_REG_PSWRQ_BW_UB1},
381 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
382 PXP2_REG_PSWRQ_BW_UB2},
383 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
384 PXP2_REG_PSWRQ_BW_UB3},
385 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
386 PXP2_REG_PSWRQ_BW_UB6},
387 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
388 PXP2_REG_PSWRQ_BW_UB7},
389 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
390 PXP2_REG_PSWRQ_BW_UB8},
391 {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
392 PXP2_REG_PSWRQ_BW_UB9},
393 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
394 PXP2_REG_PSWRQ_BW_UB10},
395 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
396 PXP2_REG_PSWRQ_BW_UB11},
397 {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
398 PXP2_REG_PSWRQ_BW_UB28},
399 {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
400 PXP2_REG_RQ_BW_WR_UBOUND29},
401 {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
402 PXP2_REG_RQ_BW_WR_UBOUND30}
403};
404
405static void bnx2x_init_pxp(struct bnx2x *bp)
406{
407 int r_order, w_order;
408 u32 val, i;
409
410 pci_read_config_word(bp->pdev,
411 bp->pcie_cap + PCI_EXP_DEVCTL, (u16 *)&val);
412 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", val);
413 w_order = ((val & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
414 r_order = ((val & PCI_EXP_DEVCTL_READRQ) >> 12);
415
416 if (r_order > MAX_RD_ORD) {
417 DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n",
418 r_order, MAX_RD_ORD);
419 r_order = MAX_RD_ORD;
420 }
421 if (w_order > MAX_WR_ORD) {
422 DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n",
423 w_order, MAX_WR_ORD);
424 w_order = MAX_WR_ORD;
425 }
426 DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order);
427
428 for (i = 0; i < NUM_RD_Q-1; i++) {
429 REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l);
430 REG_WR(bp, read_arb_addr[i].add,
431 read_arb_data[i][r_order].add);
432 REG_WR(bp, read_arb_addr[i].ubound,
433 read_arb_data[i][r_order].ubound);
434 }
435
436 for (i = 0; i < NUM_WR_Q-1; i++) {
437 if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
438 (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
439
440 REG_WR(bp, write_arb_addr[i].l,
441 write_arb_data[i][w_order].l);
442
443 REG_WR(bp, write_arb_addr[i].add,
444 write_arb_data[i][w_order].add);
445
446 REG_WR(bp, write_arb_addr[i].ubound,
447 write_arb_data[i][w_order].ubound);
448 } else {
449
450 val = REG_RD(bp, write_arb_addr[i].l);
451 REG_WR(bp, write_arb_addr[i].l,
452 val | (write_arb_data[i][w_order].l << 10));
453
454 val = REG_RD(bp, write_arb_addr[i].add);
455 REG_WR(bp, write_arb_addr[i].add,
456 val | (write_arb_data[i][w_order].add << 10));
457
458 val = REG_RD(bp, write_arb_addr[i].ubound);
459 REG_WR(bp, write_arb_addr[i].ubound,
460 val | (write_arb_data[i][w_order].ubound << 7));
461 }
462 }
463
464 val = write_arb_data[NUM_WR_Q-1][w_order].add;
465 val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
466 val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
467 REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val);
468
469 val = read_arb_data[NUM_RD_Q-1][r_order].add;
470 val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
471 val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
472 REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val);
473
474 REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order);
475 REG_WR(bp, PXP2_REG_RQ_WR_MBS0 + 8, w_order);
476 REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order);
477 REG_WR(bp, PXP2_REG_RQ_RD_MBS0 + 8, r_order);
478
479 REG_WR(bp, PXP2_REG_WR_DMAE_TH, (128 << w_order)/16);
480}
481
482
483/****************************************************************************
484* CDU
485****************************************************************************/
486
487#define CDU_REGION_NUMBER_XCM_AG 2
488#define CDU_REGION_NUMBER_UCM_AG 4
489
490/**
491 * String-to-compress [31:8] = CID (all 24 bits)
492 * String-to-compress [7:4] = Region
493 * String-to-compress [3:0] = Type
494 */
495#define CDU_VALID_DATA(_cid, _region, _type) \
496 (((_cid) << 8) | (((_region) & 0xf) << 4) | (((_type) & 0xf)))
497#define CDU_CRC8(_cid, _region, _type) \
498 calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)
499#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \
500 (0x80 | (CDU_CRC8(_cid, _region, _type) & 0x7f))
501#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \
502 (0x80 | ((_type) & 0xf << 3) | (CDU_CRC8(_cid, _region, _type) & 0x7))
503#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
504
505/*****************************************************************************
506 * Description:
507 * Calculates crc 8 on a word value: polynomial 0-1-2-8
508 * Code was translated from Verilog.
509 ****************************************************************************/
510static u8 calc_crc8(u32 data, u8 crc)
511{
512 u8 D[32];
513 u8 NewCRC[8];
514 u8 C[8];
515 u8 crc_res;
516 u8 i;
517
518 /* split the data into 31 bits */
519 for (i = 0; i < 32; i++) {
520 D[i] = data & 1;
521 data = data >> 1;
522 }
523
524 /* split the crc into 8 bits */
525 for (i = 0; i < 8; i++) {
526 C[i] = crc & 1;
527 crc = crc >> 1;
528 }
529
530 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
531 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
532 C[6] ^ C[7];
533 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
534 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
535 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6];
536 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
537 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
538 C[0] ^ C[1] ^ C[4] ^ C[5];
539 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
540 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
541 C[1] ^ C[2] ^ C[5] ^ C[6];
542 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
543 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
544 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
545 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
546 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
547 C[3] ^ C[4] ^ C[7];
548 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
549 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
550 C[5];
551 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
552 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
553 C[6];
554
555 crc_res = 0;
556 for (i = 0; i < 8; i++)
557 crc_res |= (NewCRC[i] << i);
558
559 return crc_res;
560}
561
562
563#endif /* BNX2X_INIT_H */
564
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 20:21:08 -0500