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-rw-r--r--drivers/net/bnx2x_hsi.h428
1 files changed, 231 insertions, 197 deletions
diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h
index 6fd959c34d1f..b21075ccb52e 100644
--- a/drivers/net/bnx2x_hsi.h
+++ b/drivers/net/bnx2x_hsi.h
@@ -1,6 +1,6 @@
1/* bnx2x_hsi.h: Broadcom Everest network driver. 1/* bnx2x_hsi.h: Broadcom Everest network driver.
2 * 2 *
3 * Copyright (c) 2007 Broadcom Corporation 3 * Copyright (c) 2007-2008 Broadcom Corporation
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by 6 * it under the terms of the GNU General Public License as published by
@@ -8,169 +8,9 @@
8 */ 8 */
9 9
10 10
11#define FUNC_0 0 11#define PORT_0 0
12#define FUNC_1 1 12#define PORT_1 1
13#define FUNC_MAX 2 13#define PORT_MAX 2
14
15
16/* This value (in milliseconds) determines the frequency of the driver
17 * issuing the PULSE message code. The firmware monitors this periodic
18 * pulse to determine when to switch to an OS-absent mode. */
19#define DRV_PULSE_PERIOD_MS 250
20
21/* This value (in milliseconds) determines how long the driver should
22 * wait for an acknowledgement from the firmware before timing out. Once
23 * the firmware has timed out, the driver will assume there is no firmware
24 * running and there won't be any firmware-driver synchronization during a
25 * driver reset. */
26#define FW_ACK_TIME_OUT_MS 5000
27
28#define FW_ACK_POLL_TIME_MS 1
29
30#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
31
32/* LED Blink rate that will achieve ~15.9Hz */
33#define LED_BLINK_RATE_VAL 480
34
35/****************************************************************************
36 * Driver <-> FW Mailbox *
37 ****************************************************************************/
38struct drv_fw_mb {
39 u32 drv_mb_header;
40#define DRV_MSG_CODE_MASK 0xffff0000
41#define DRV_MSG_CODE_LOAD_REQ 0x10000000
42#define DRV_MSG_CODE_LOAD_DONE 0x11000000
43#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
44#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
45#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
46#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
47#define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
48#define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
49#define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
50#define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
51#define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
52#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
53#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
54
55#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
56
57 u32 drv_mb_param;
58
59 u32 fw_mb_header;
60#define FW_MSG_CODE_MASK 0xffff0000
61#define FW_MSG_CODE_DRV_LOAD_COMMON 0x11000000
62#define FW_MSG_CODE_DRV_LOAD_PORT 0x12000000
63#define FW_MSG_CODE_DRV_LOAD_REFUSED 0x13000000
64#define FW_MSG_CODE_DRV_LOAD_DONE 0x14000000
65#define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x21000000
66#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x22000000
67#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x23000000
68#define FW_MSG_CODE_DIAG_ENTER_DONE 0x50000000
69#define FW_MSG_CODE_DIAG_REFUSE 0x51000000
70#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70000000
71#define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x71000000
72#define FW_MSG_CODE_GET_KEY_DONE 0x80000000
73#define FW_MSG_CODE_NO_KEY 0x8f000000
74#define FW_MSG_CODE_LIC_INFO_NOT_READY 0x8f800000
75#define FW_MSG_CODE_L2B_PRAM_LOADED 0x90000000
76#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x91000000
77#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x92000000
78#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x93000000
79#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x94000000
80
81#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
82
83 u32 fw_mb_param;
84
85 u32 link_status;
86 /* Driver should update this field on any link change event */
87
88#define LINK_STATUS_LINK_FLAG_MASK 0x00000001
89#define LINK_STATUS_LINK_UP 0x00000001
90#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
91#define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
92#define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
93#define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
94#define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
95#define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
96#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
97#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
98#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
99#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
100#define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
101#define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
102#define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
103#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
104#define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
105#define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1)
106#define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1)
107#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1)
108#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1)
109#define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1)
110#define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1)
111#define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1)
112#define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1)
113#define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1)
114#define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1)
115
116#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
117#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
118
119#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
120#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
121#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
122
123#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
124#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
125#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
126#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
127#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
128#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
129#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
130
131#define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
132#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
133
134#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
135#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
136
137#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
138#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
139#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
140#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
141#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
142
143#define LINK_STATUS_SERDES_LINK 0x00100000
144
145#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
146#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
147#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
148#define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
149#define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
150#define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
151#define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
152#define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
153
154 u32 drv_pulse_mb;
155#define DRV_PULSE_SEQ_MASK 0x00007fff
156#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
157 /* The system time is in the format of
158 * (year-2001)*12*32 + month*32 + day. */
159#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
160 /* Indicate to the firmware not to go into the
161 * OS-absent when it is not getting driver pulse.
162 * This is used for debugging as well for PXE(MBA). */
163
164 u32 mcp_pulse_mb;
165#define MCP_PULSE_SEQ_MASK 0x00007fff
166#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
167 /* Indicates to the driver not to assert due to lack
168 * of MCP response */
169#define MCP_EVENT_MASK 0xffff0000
170#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
171
172};
173
174 14
175/**************************************************************************** 15/****************************************************************************
176 * Shared HW configuration * 16 * Shared HW configuration *
@@ -249,7 +89,7 @@ struct shared_hw_cfg { /* NVRAM Offset */
249#define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 89#define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
250#define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 90#define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
251 91
252#define SHARED_HW_CFG_HIDE_FUNC1 0x00002000 92#define SHARED_HW_CFG_HIDE_PORT1 0x00002000
253 93
254 u32 power_dissipated; /* 0x11c */ 94 u32 power_dissipated; /* 0x11c */
255#define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 95#define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
@@ -290,6 +130,8 @@ struct shared_hw_cfg { /* NVRAM Offset */
290#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G 0x00000006 130#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G 0x00000006
291#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G 0x00000007 131#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G 0x00000007
292#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008 132#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008
133#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G 0x00000009
134#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G 0x0000000a
293 135
294#define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000 136#define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000
295#define SHARED_HW_CFG_BOARD_VER_SHIFT 16 137#define SHARED_HW_CFG_BOARD_VER_SHIFT 16
@@ -304,13 +146,12 @@ struct shared_hw_cfg { /* NVRAM Offset */
304 146
305}; 147};
306 148
149
307/**************************************************************************** 150/****************************************************************************
308 * Port HW configuration * 151 * Port HW configuration *
309 ****************************************************************************/ 152 ****************************************************************************/
310struct port_hw_cfg { /* function 0: 0x12c-0x2bb, function 1: 0x2bc-0x44b */ 153struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
311 154
312 /* Fields below are port specific (in anticipation of dual port
313 devices */
314 u32 pci_id; 155 u32 pci_id;
315#define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 156#define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
316#define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff 157#define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
@@ -420,6 +261,8 @@ struct port_hw_cfg { /* function 0: 0x12c-0x2bb, function 1: 0x2bc-0x44b */
420#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 261#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
421#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276 0x00000600 262#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276 0x00000600
422#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 263#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
264#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
265#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
423#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 266#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
424 267
425#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff 268#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
@@ -462,11 +305,13 @@ struct port_hw_cfg { /* function 0: 0x12c-0x2bb, function 1: 0x2bc-0x44b */
462 305
463}; 306};
464 307
308
465/**************************************************************************** 309/****************************************************************************
466 * Shared Feature configuration * 310 * Shared Feature configuration *
467 ****************************************************************************/ 311 ****************************************************************************/
468struct shared_feat_cfg { /* NVRAM Offset */ 312struct shared_feat_cfg { /* NVRAM Offset */
469 u32 bmc_common; /* 0x450 */ 313
314 u32 config; /* 0x450 */
470#define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 315#define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
471 316
472}; 317};
@@ -475,7 +320,8 @@ struct shared_feat_cfg { /* NVRAM Offset */
475/**************************************************************************** 320/****************************************************************************
476 * Port Feature configuration * 321 * Port Feature configuration *
477 ****************************************************************************/ 322 ****************************************************************************/
478struct port_feat_cfg { /* function 0: 0x454-0x4c7, function 1: 0x4c8-0x53b */ 323struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
324
479 u32 config; 325 u32 config;
480#define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f 326#define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
481#define PORT_FEATURE_BAR1_SIZE_SHIFT 0 327#define PORT_FEATURE_BAR1_SIZE_SHIFT 0
@@ -609,8 +455,7 @@ struct port_feat_cfg { /* function 0: 0x454-0x4c7, function 1: 0x4c8-0x53b */
609#define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 455#define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
610#define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 456#define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
611 457
612 u32 iscsib_boot_cfg; 458 u32 reserved1;
613#define PORT_FEATURE_ISCSIB_SKIP_TARGET_BOOT 0x00000001
614 459
615 u32 link_config; /* Used as HW defaults for the driver */ 460 u32 link_config; /* Used as HW defaults for the driver */
616#define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 461#define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
@@ -657,20 +502,201 @@ struct port_feat_cfg { /* function 0: 0x454-0x4c7, function 1: 0x4c8-0x53b */
657}; 502};
658 503
659 504
505/*****************************************************************************
506 * Device Information *
507 *****************************************************************************/
508struct dev_info { /* size */
509
510 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
511
512 struct shared_hw_cfg shared_hw_config; /* 40 */
513
514 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
515
516 struct shared_feat_cfg shared_feature_config; /* 4 */
517
518 struct port_feat_cfg port_feature_config[PORT_MAX]; /* 116*2=232 */
519
520};
521
522
523#define FUNC_0 0
524#define FUNC_1 1
525#define E1_FUNC_MAX 2
526#define FUNC_MAX E1_FUNC_MAX
527
528
529/* This value (in milliseconds) determines the frequency of the driver
530 * issuing the PULSE message code. The firmware monitors this periodic
531 * pulse to determine when to switch to an OS-absent mode. */
532#define DRV_PULSE_PERIOD_MS 250
533
534/* This value (in milliseconds) determines how long the driver should
535 * wait for an acknowledgement from the firmware before timing out. Once
536 * the firmware has timed out, the driver will assume there is no firmware
537 * running and there won't be any firmware-driver synchronization during a
538 * driver reset. */
539#define FW_ACK_TIME_OUT_MS 5000
540
541#define FW_ACK_POLL_TIME_MS 1
542
543#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
544
545/* LED Blink rate that will achieve ~15.9Hz */
546#define LED_BLINK_RATE_VAL 480
547
660/**************************************************************************** 548/****************************************************************************
661 * Device Information * 549 * Driver <-> FW Mailbox *
662 ****************************************************************************/ 550 ****************************************************************************/
663struct dev_info { /* size */ 551struct drv_port_mb {
552
553 u32 link_status;
554 /* Driver should update this field on any link change event */
555
556#define LINK_STATUS_LINK_FLAG_MASK 0x00000001
557#define LINK_STATUS_LINK_UP 0x00000001
558#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
559#define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
560#define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
561#define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
562#define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
563#define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
564#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
565#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
566#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
567#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
568#define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
569#define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
570#define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
571#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
572#define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
573#define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1)
574#define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1)
575#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1)
576#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1)
577#define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1)
578#define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1)
579#define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1)
580#define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1)
581#define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1)
582#define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1)
583
584#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
585#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
586
587#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
588#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
589#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
590
591#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
592#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
593#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
594#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
595#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
596#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
597#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
598
599#define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
600#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
601
602#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
603#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
604
605#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
606#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
607#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
608#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
609#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
610
611#define LINK_STATUS_SERDES_LINK 0x00100000
612
613#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
614#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
615#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
616#define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
617#define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
618#define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
619#define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
620#define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
664 621
665 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 622 u32 reserved[3];
666 623
667 struct shared_hw_cfg shared_hw_config; /* 40 */ 624};
625
626
627struct drv_func_mb {
628
629 u32 drv_mb_header;
630#define DRV_MSG_CODE_MASK 0xffff0000
631#define DRV_MSG_CODE_LOAD_REQ 0x10000000
632#define DRV_MSG_CODE_LOAD_DONE 0x11000000
633#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
634#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
635#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
636#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
637#define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
638#define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
639#define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
640#define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
641#define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
642#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
643#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
644
645#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
646
647 u32 drv_mb_param;
648
649 u32 fw_mb_header;
650#define FW_MSG_CODE_MASK 0xffff0000
651#define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
652#define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
653#define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
654#define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
655#define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
656#define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
657#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
658#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
659#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
660#define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
661#define FW_MSG_CODE_DIAG_REFUSE 0x50200000
662#define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
663#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
664#define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
665#define FW_MSG_CODE_GET_KEY_DONE 0x80100000
666#define FW_MSG_CODE_NO_KEY 0x80f00000
667#define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
668#define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
669#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
670#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
671#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
672#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
673
674#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
675
676 u32 fw_mb_param;
677
678 u32 drv_pulse_mb;
679#define DRV_PULSE_SEQ_MASK 0x00007fff
680#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
681 /* The system time is in the format of
682 * (year-2001)*12*32 + month*32 + day. */
683#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
684 /* Indicate to the firmware not to go into the
685 * OS-absent when it is not getting driver pulse.
686 * This is used for debugging as well for PXE(MBA). */
668 687
669 struct port_hw_cfg port_hw_config[FUNC_MAX]; /* 400*2=800 */ 688 u32 mcp_pulse_mb;
689#define MCP_PULSE_SEQ_MASK 0x00007fff
690#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
691 /* Indicates to the driver not to assert due to lack
692 * of MCP response */
693#define MCP_EVENT_MASK 0xffff0000
694#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
670 695
671 struct shared_feat_cfg shared_feature_config; /* 4 */ 696 u32 iscsi_boot_signature;
697 u32 iscsi_boot_block_offset;
672 698
673 struct port_feat_cfg port_feature_config[FUNC_MAX];/* 116*2=232 */ 699 u32 reserved[3];
674 700
675}; 701};
676 702
@@ -678,9 +704,8 @@ struct dev_info { /* size */
678/**************************************************************************** 704/****************************************************************************
679 * Management firmware state * 705 * Management firmware state *
680 ****************************************************************************/ 706 ****************************************************************************/
681/* Allocate 320 bytes for management firmware: still not known exactly 707/* Allocate 440 bytes for management firmware */
682 * how much IMD needs. */ 708#define MGMTFW_STATE_WORD_SIZE 110
683#define MGMTFW_STATE_WORD_SIZE 80
684 709
685struct mgmtfw_state { 710struct mgmtfw_state {
686 u32 opaque[MGMTFW_STATE_WORD_SIZE]; 711 u32 opaque[MGMTFW_STATE_WORD_SIZE];
@@ -691,31 +716,40 @@ struct mgmtfw_state {
691 * Shared Memory Region * 716 * Shared Memory Region *
692 ****************************************************************************/ 717 ****************************************************************************/
693struct shmem_region { /* SharedMem Offset (size) */ 718struct shmem_region { /* SharedMem Offset (size) */
694 u32 validity_map[FUNC_MAX]; /* 0x0 (4 * 2 = 0x8) */ 719
695#define SHR_MEM_VALIDITY_PCI_CFG 0x00000001 720 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
696#define SHR_MEM_VALIDITY_MB 0x00000002 721#define SHR_MEM_FORMAT_REV_ID ('A'<<24)
697#define SHR_MEM_VALIDITY_DEV_INFO 0x00000004 722#define SHR_MEM_FORMAT_REV_MASK 0xff000000
723 /* validity bits */
724#define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
725#define SHR_MEM_VALIDITY_MB 0x00200000
726#define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
727#define SHR_MEM_VALIDITY_RESERVED 0x00000007
698 /* One licensing bit should be set */ 728 /* One licensing bit should be set */
699#define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 729#define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
700#define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 730#define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
701#define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 731#define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
702#define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 732#define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
733 /* Active MFW */
734#define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
735#define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
736#define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
737#define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
738#define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
739#define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
703 740
704 struct drv_fw_mb drv_fw_mb[FUNC_MAX]; /* 0x8 (28 * 2 = 0x38) */ 741 struct dev_info dev_info; /* 0x8 (0x438) */
705
706 struct dev_info dev_info; /* 0x40 (0x438) */
707 742
708#ifdef _LICENSE_H 743 u8 reserved[52*PORT_MAX];
709 license_key_t drv_lic_key[FUNC_MAX]; /* 0x478 (52 * 2 = 0x68) */
710#else /* Linux! */
711 u8 reserved[52*FUNC_MAX];
712#endif
713 744
714 /* FW information (for internal FW use) */ 745 /* FW information (for internal FW use) */
715 u32 fw_info_fio_offset; /* 0x4e0 (0x4) */ 746 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
716 struct mgmtfw_state mgmtfw_state; /* 0x4e4 (0x140) */ 747 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
748
749 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
750 struct drv_func_mb func_mb[FUNC_MAX]; /* 0x684 (44*2=0x58) */
717 751
718}; /* 0x624 */ 752}; /* 0x6dc */
719 753
720 754
721#define BCM_5710_FW_MAJOR_VERSION 4 755#define BCM_5710_FW_MAJOR_VERSION 4
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 05:22:07 -0500