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Diffstat (limited to 'drivers/net/bnx2x_fw_defs.h')
-rw-r--r--drivers/net/bnx2x_fw_defs.h70
1 files changed, 36 insertions, 34 deletions
diff --git a/drivers/net/bnx2x_fw_defs.h b/drivers/net/bnx2x_fw_defs.h
index 192fa981b930..2fe14a25ea3e 100644
--- a/drivers/net/bnx2x_fw_defs.h
+++ b/drivers/net/bnx2x_fw_defs.h
@@ -50,8 +50,10 @@
50#define TSTORM_ASSERT_LIST_OFFSET(idx) \ 50#define TSTORM_ASSERT_LIST_OFFSET(idx) \
51 (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) 51 (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
52#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \ 52#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
53 (IS_E1H_OFFSET ? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) \ 53 (IS_E1H_OFFSET ? (0x3350 + (port * 0x190) + (client_id * 0x10)) \
54 : (0x9c8 + (port * 0x2f8) + (client_id * 0x28))) 54 : (0x9c0 + (port * 0x130) + (client_id * 0x10)))
55#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \
56 (IS_E1H_OFFSET ? 0x1ad8 : 0xffffffff)
55#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ 57#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
56 (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \ 58 (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
57 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ 59 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
@@ -81,43 +83,43 @@
81 (function * 0x38))) 83 (function * 0x38)))
82#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ 84#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
83 (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \ 85 (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \
84 0x50)) : (0x4000 + (port * 0x3f0) + (stats_counter_id * 0x38))) 86 0x50)) : (0x4080 + (port * 0x5b0) + (stats_counter_id * 0x50)))
85#define TSTORM_RX_PRODS_OFFSET(port, client_id) \
86 (IS_E1H_OFFSET ? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) \
87 : (0x9c0 + (port * 0x2f8) + (client_id * 0x28)))
88#define TSTORM_STATS_FLAGS_OFFSET(function) \ 87#define TSTORM_STATS_FLAGS_OFFSET(function) \
89 (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \ 88 (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \
90 (function * 0x8))) 89 (function * 0x8)))
91#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3b30 : 0x1c20) 90#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3680 : 0x1c20)
92#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10) 91#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10)
93#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200) 92#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200)
94#define USTORM_ASSERT_LIST_INDEX_OFFSET \ 93#define USTORM_ASSERT_LIST_INDEX_OFFSET \
95 (IS_E1H_OFFSET ? 0x8000 : 0x1000) 94 (IS_E1H_OFFSET ? 0x8960 : 0x1000)
96#define USTORM_ASSERT_LIST_OFFSET(idx) \ 95#define USTORM_ASSERT_LIST_OFFSET(idx) \
97 (IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) 96 (IS_E1H_OFFSET ? (0x8980 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
98#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \ 97#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
99 (IS_E1H_OFFSET ? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \ 98 (IS_E1H_OFFSET ? (0x8018 + (port * 0x4b0) + (clientId * 0x30)) : \
100 (0x5450 + (port * 0x1c8) + (clientId * 0x18))) 99 (0x5330 + (port * 0x260) + (clientId * 0x20)))
101#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ 100#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
102 (IS_E1H_OFFSET ? (0x951a + ((function>>1) * 0x28) + \ 101 (IS_E1H_OFFSET ? (0x9522 + ((function>>1) * 0x40) + \
103 ((function&1) * 0xa0) + (index * 0x4)) : (0x191a + (function * \ 102 ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
104 0x28) + (index * 0x4))) 103 0x40) + (index * 0x4)))
105#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ 104#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
106 (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x28) + \ 105 (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x40) + \
107 ((function&1) * 0xa0)) : (0x1900 + (function * 0x28))) 106 ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
108#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ 107#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
109 (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x28) + \ 108 (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x40) + \
110 ((function&1) * 0xa0)) : (0x1908 + (function * 0x28))) 109 ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
111#define USTORM_FUNCTION_MODE_OFFSET \ 110#define USTORM_FUNCTION_MODE_OFFSET \
112 (IS_E1H_OFFSET ? 0x2448 : 0xffffffff) 111 (IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
113#define USTORM_HC_BTR_OFFSET(port) \ 112#define USTORM_HC_BTR_OFFSET(port) \
114 (IS_E1H_OFFSET ? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8))) 113 (IS_E1H_OFFSET ? (0x9704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
115#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \ 114#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
116 (IS_E1H_OFFSET ? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \ 115 (IS_E1H_OFFSET ? (0x8010 + (port * 0x4b0) + (clientId * 0x30)) : \
117 (0x5448 + (port * 0x1c8) + (clientId * 0x18))) 116 (0x5328 + (port * 0x260) + (clientId * 0x20)))
118#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \ 117#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
119 (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5408 + \ 118 (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5308 + \
120 (function * 0x8))) 119 (function * 0x8)))
120#define USTORM_RX_PRODS_OFFSET(port, client_id) \
121 (IS_E1H_OFFSET ? (0x8000 + (port * 0x4b0) + (client_id * 0x30)) \
122 : (0x5318 + (port * 0x260) + (client_id * 0x20)))
121#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \ 123#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
122 (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \ 124 (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
123 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \ 125 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
@@ -137,7 +139,7 @@
137#define XSTORM_ASSERT_LIST_OFFSET(idx) \ 139#define XSTORM_ASSERT_LIST_OFFSET(idx) \
138 (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) 140 (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
139#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \ 141#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
140 (IS_E1H_OFFSET ? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40))) 142 (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3ba0 + (port * 0x50)))
141#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ 143#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
142 (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \ 144 (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
143 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ 145 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
@@ -149,23 +151,23 @@
149 (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \ 151 (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
150 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) 152 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
151#define XSTORM_E1HOV_OFFSET(function) \ 153#define XSTORM_E1HOV_OFFSET(function) \
152 (IS_E1H_OFFSET ? (0x2ab8 + (function * 0x2)) : 0xffffffff) 154 (IS_E1H_OFFSET ? (0x2c10 + (function * 0x2)) : 0xffffffff)
153#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ 155#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
154 (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \ 156 (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \
155 (function * 0x8))) 157 (function * 0x8)))
156#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \ 158#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
157 (IS_E1H_OFFSET ? (0x2568 + (function * 0x70)) : (0x3c60 + \ 159 (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3c80 + \
158 (function * 0x70))) 160 (function * 0x90)))
159#define XSTORM_FUNCTION_MODE_OFFSET \ 161#define XSTORM_FUNCTION_MODE_OFFSET \
160 (IS_E1H_OFFSET ? 0x2ac8 : 0xffffffff) 162 (IS_E1H_OFFSET ? 0x2c20 : 0xffffffff)
161#define XSTORM_HC_BTR_OFFSET(port) \ 163#define XSTORM_HC_BTR_OFFSET(port) \
162 (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18))) 164 (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
163#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ 165#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
164 (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \ 166 (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \
165 0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38))) 167 0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38)))
166#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \ 168#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
167 (IS_E1H_OFFSET ? (0x2528 + (function * 0x70)) : (0x3c20 + \ 169 (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3c40 + \
168 (function * 0x70))) 170 (function * 0x90)))
169#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \ 171#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
170 (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \ 172 (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
171 (function * 0x10))) 173 (function * 0x10)))
@@ -278,9 +280,6 @@
278#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) 280#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
279#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) 281#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
280#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) 282#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
281#define ISCSI_STATE \
282 (ISCSI_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
283#define FCOE_STATE (FCOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
284 283
285/* microcode fixed page page size 4K (chains and ring segments) */ 284/* microcode fixed page page size 4K (chains and ring segments) */
286#define MC_PAGE_SIZE (4096) 285#define MC_PAGE_SIZE (4096)
@@ -289,7 +288,7 @@
289/* Host coalescing constants */ 288/* Host coalescing constants */
290 289
291/* index numbers */ 290/* index numbers */
292#define HC_USTORM_DEF_SB_NUM_INDICES 4 291#define HC_USTORM_DEF_SB_NUM_INDICES 8
293#define HC_CSTORM_DEF_SB_NUM_INDICES 8 292#define HC_CSTORM_DEF_SB_NUM_INDICES 8
294#define HC_XSTORM_DEF_SB_NUM_INDICES 4 293#define HC_XSTORM_DEF_SB_NUM_INDICES 4
295#define HC_TSTORM_DEF_SB_NUM_INDICES 4 294#define HC_TSTORM_DEF_SB_NUM_INDICES 4
@@ -386,9 +385,12 @@
386#define FW_LOG_LIST_SIZE (50) 385#define FW_LOG_LIST_SIZE (50)
387 386
388#define NUM_OF_PROTOCOLS 4 387#define NUM_OF_PROTOCOLS 4
389#define MAX_COS_NUMBER 16 388#define NUM_OF_SAFC_BITS 16
389#define MAX_COS_NUMBER 4
390#define MAX_T_STAT_COUNTER_ID 18 390#define MAX_T_STAT_COUNTER_ID 18
391#define MAX_X_STAT_COUNTER_ID 18 391#define MAX_X_STAT_COUNTER_ID 18
392#define MAX_U_STAT_COUNTER_ID 18
393
392 394
393#define UNKNOWN_ADDRESS 0 395#define UNKNOWN_ADDRESS 0
394#define UNICAST_ADDRESS 1 396#define UNICAST_ADDRESS 1