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-rw-r--r--drivers/net/bnx2x/bnx2x_main.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c
index 150709111548..1f5467f9548c 100644
--- a/drivers/net/bnx2x/bnx2x_main.c
+++ b/drivers/net/bnx2x/bnx2x_main.c
@@ -5798,6 +5798,12 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
5798 5798
5799 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp)); 5799 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
5800 5800
5801 /*
5802 * take the UNDI lock to protect undi_unload flow from accessing
5803 * registers while we're resetting the chip
5804 */
5805 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
5806
5801 bnx2x_reset_common(bp); 5807 bnx2x_reset_common(bp);
5802 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 5808 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5803 5809
@@ -5808,6 +5814,8 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
5808 } 5814 }
5809 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 5815 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5810 5816
5817 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
5818
5811 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 5819 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
5812 5820
5813 if (!CHIP_IS_E1x(bp)) { 5821 if (!CHIP_IS_E1x(bp)) {