diff options
Diffstat (limited to 'drivers/net/bnx2x')
-rw-r--r-- | drivers/net/bnx2x/bnx2x_hsi.h | 1 | ||||
-rw-r--r-- | drivers/net/bnx2x/bnx2x_link.c | 110 |
2 files changed, 84 insertions, 27 deletions
diff --git a/drivers/net/bnx2x/bnx2x_hsi.h b/drivers/net/bnx2x/bnx2x_hsi.h index 34e313cf3e25..7c35f4ee3858 100644 --- a/drivers/net/bnx2x/bnx2x_hsi.h +++ b/drivers/net/bnx2x/bnx2x_hsi.h | |||
@@ -459,6 +459,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ | |||
459 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 | 459 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 |
460 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 | 460 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 |
461 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 | 461 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 |
462 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 | ||
462 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 | 463 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 |
463 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 | 464 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 |
464 | 465 | ||
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c index a089b62d3df6..7d3e7e2c75c6 100644 --- a/drivers/net/bnx2x/bnx2x_link.c +++ b/drivers/net/bnx2x/bnx2x_link.c | |||
@@ -5992,19 +5992,23 @@ static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, | |||
5992 | static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, | 5992 | static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, |
5993 | struct link_params *params) | 5993 | struct link_params *params) |
5994 | { | 5994 | { |
5995 | u16 val, fw_ver1, fw_ver2, cnt; | 5995 | u16 val, fw_ver1, fw_ver2, cnt, adj; |
5996 | struct bnx2x *bp = params->bp; | 5996 | struct bnx2x *bp = params->bp; |
5997 | 5997 | ||
5998 | adj = 0; | ||
5999 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | ||
6000 | adj = -1; | ||
6001 | |||
5998 | /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/ | 6002 | /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/ |
5999 | /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ | 6003 | /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ |
6000 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014); | 6004 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819 + adj, 0x0014); |
6001 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); | 6005 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A + adj, 0xc200); |
6002 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000); | 6006 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B + adj, 0x0000); |
6003 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300); | 6007 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C + adj, 0x0300); |
6004 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009); | 6008 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817 + adj, 0x0009); |
6005 | 6009 | ||
6006 | for (cnt = 0; cnt < 100; cnt++) { | 6010 | for (cnt = 0; cnt < 100; cnt++) { |
6007 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | 6011 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818 + adj, &val); |
6008 | if (val & 1) | 6012 | if (val & 1) |
6009 | break; | 6013 | break; |
6010 | udelay(5); | 6014 | udelay(5); |
@@ -6018,11 +6022,11 @@ static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, | |||
6018 | 6022 | ||
6019 | 6023 | ||
6020 | /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ | 6024 | /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ |
6021 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); | 6025 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819 + adj, 0x0000); |
6022 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); | 6026 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A + adj, 0xc200); |
6023 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); | 6027 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817 + adj, 0x000A); |
6024 | for (cnt = 0; cnt < 100; cnt++) { | 6028 | for (cnt = 0; cnt < 100; cnt++) { |
6025 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | 6029 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818 + adj, &val); |
6026 | if (val & 1) | 6030 | if (val & 1) |
6027 | break; | 6031 | break; |
6028 | udelay(5); | 6032 | udelay(5); |
@@ -6035,9 +6039,9 @@ static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, | |||
6035 | } | 6039 | } |
6036 | 6040 | ||
6037 | /* lower 16 bits of the register SPI_FW_STATUS */ | 6041 | /* lower 16 bits of the register SPI_FW_STATUS */ |
6038 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); | 6042 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B + adj, &fw_ver1); |
6039 | /* upper 16 bits of register SPI_FW_STATUS */ | 6043 | /* upper 16 bits of register SPI_FW_STATUS */ |
6040 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); | 6044 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C + adj, &fw_ver2); |
6041 | 6045 | ||
6042 | bnx2x_save_spirom_version(bp, params->port, (fw_ver2<<16) | fw_ver1, | 6046 | bnx2x_save_spirom_version(bp, params->port, (fw_ver2<<16) | fw_ver1, |
6043 | phy->ver_addr); | 6047 | phy->ver_addr); |
@@ -6046,49 +6050,53 @@ static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, | |||
6046 | static void bnx2x_848xx_set_led(struct bnx2x *bp, | 6050 | static void bnx2x_848xx_set_led(struct bnx2x *bp, |
6047 | struct bnx2x_phy *phy) | 6051 | struct bnx2x_phy *phy) |
6048 | { | 6052 | { |
6049 | u16 val; | 6053 | u16 val, adj; |
6054 | |||
6055 | adj = 0; | ||
6056 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | ||
6057 | adj = -1; | ||
6050 | 6058 | ||
6051 | /* PHYC_CTL_LED_CTL */ | 6059 | /* PHYC_CTL_LED_CTL */ |
6052 | bnx2x_cl45_read(bp, phy, | 6060 | bnx2x_cl45_read(bp, phy, |
6053 | MDIO_PMA_DEVAD, | 6061 | MDIO_PMA_DEVAD, |
6054 | MDIO_PMA_REG_8481_LINK_SIGNAL, &val); | 6062 | MDIO_PMA_REG_8481_LINK_SIGNAL + adj, &val); |
6055 | val &= 0xFE00; | 6063 | val &= 0xFE00; |
6056 | val |= 0x0092; | 6064 | val |= 0x0092; |
6057 | 6065 | ||
6058 | bnx2x_cl45_write(bp, phy, | 6066 | bnx2x_cl45_write(bp, phy, |
6059 | MDIO_PMA_DEVAD, | 6067 | MDIO_PMA_DEVAD, |
6060 | MDIO_PMA_REG_8481_LINK_SIGNAL, val); | 6068 | MDIO_PMA_REG_8481_LINK_SIGNAL + adj, val); |
6061 | 6069 | ||
6062 | bnx2x_cl45_write(bp, phy, | 6070 | bnx2x_cl45_write(bp, phy, |
6063 | MDIO_PMA_DEVAD, | 6071 | MDIO_PMA_DEVAD, |
6064 | MDIO_PMA_REG_8481_LED1_MASK, | 6072 | MDIO_PMA_REG_8481_LED1_MASK + adj, |
6065 | 0x80); | 6073 | 0x80); |
6066 | 6074 | ||
6067 | bnx2x_cl45_write(bp, phy, | 6075 | bnx2x_cl45_write(bp, phy, |
6068 | MDIO_PMA_DEVAD, | 6076 | MDIO_PMA_DEVAD, |
6069 | MDIO_PMA_REG_8481_LED2_MASK, | 6077 | MDIO_PMA_REG_8481_LED2_MASK + adj, |
6070 | 0x18); | 6078 | 0x18); |
6071 | 6079 | ||
6072 | /* Select activity source by Tx and Rx, as suggested by PHY AE */ | 6080 | /* Select activity source by Tx and Rx, as suggested by PHY AE */ |
6073 | bnx2x_cl45_write(bp, phy, | 6081 | bnx2x_cl45_write(bp, phy, |
6074 | MDIO_PMA_DEVAD, | 6082 | MDIO_PMA_DEVAD, |
6075 | MDIO_PMA_REG_8481_LED3_MASK, | 6083 | MDIO_PMA_REG_8481_LED3_MASK + adj, |
6076 | 0x0006); | 6084 | 0x0006); |
6077 | 6085 | ||
6078 | /* Select the closest activity blink rate to that in 10/100/1000 */ | 6086 | /* Select the closest activity blink rate to that in 10/100/1000 */ |
6079 | bnx2x_cl45_write(bp, phy, | 6087 | bnx2x_cl45_write(bp, phy, |
6080 | MDIO_PMA_DEVAD, | 6088 | MDIO_PMA_DEVAD, |
6081 | MDIO_PMA_REG_8481_LED3_BLINK, | 6089 | MDIO_PMA_REG_8481_LED3_BLINK + adj, |
6082 | 0); | 6090 | 0); |
6083 | 6091 | ||
6084 | bnx2x_cl45_read(bp, phy, | 6092 | bnx2x_cl45_read(bp, phy, |
6085 | MDIO_PMA_DEVAD, | 6093 | MDIO_PMA_DEVAD, |
6086 | MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val); | 6094 | MDIO_PMA_REG_84823_CTL_LED_CTL_1 + adj, &val); |
6087 | val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/ | 6095 | val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/ |
6088 | 6096 | ||
6089 | bnx2x_cl45_write(bp, phy, | 6097 | bnx2x_cl45_write(bp, phy, |
6090 | MDIO_PMA_DEVAD, | 6098 | MDIO_PMA_DEVAD, |
6091 | MDIO_PMA_REG_84823_CTL_LED_CTL_1, val); | 6099 | MDIO_PMA_REG_84823_CTL_LED_CTL_1 + adj, val); |
6092 | 6100 | ||
6093 | /* 'Interrupt Mask' */ | 6101 | /* 'Interrupt Mask' */ |
6094 | bnx2x_cl45_write(bp, phy, | 6102 | bnx2x_cl45_write(bp, phy, |
@@ -6247,12 +6255,15 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy, | |||
6247 | { | 6255 | { |
6248 | struct bnx2x *bp = params->bp; | 6256 | struct bnx2x *bp = params->bp; |
6249 | u8 port, initialize = 1; | 6257 | u8 port, initialize = 1; |
6250 | u16 val; | 6258 | u16 val, adj; |
6251 | u16 temp; | 6259 | u16 temp; |
6252 | u32 actual_phy_selection; | 6260 | u32 actual_phy_selection; |
6253 | u8 rc = 0; | 6261 | u8 rc = 0; |
6254 | 6262 | ||
6255 | /* This is just for MDIO_CTL_REG_84823_MEDIA register. */ | 6263 | /* This is just for MDIO_CTL_REG_84823_MEDIA register. */ |
6264 | adj = 0; | ||
6265 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | ||
6266 | adj = 3; | ||
6256 | 6267 | ||
6257 | msleep(1); | 6268 | msleep(1); |
6258 | if (CHIP_IS_E2(bp)) | 6269 | if (CHIP_IS_E2(bp)) |
@@ -6277,7 +6288,7 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy, | |||
6277 | /* Set dual-media configuration according to configuration */ | 6288 | /* Set dual-media configuration according to configuration */ |
6278 | 6289 | ||
6279 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, | 6290 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
6280 | MDIO_CTL_REG_84823_MEDIA, &val); | 6291 | MDIO_CTL_REG_84823_MEDIA + adj, &val); |
6281 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | | 6292 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | |
6282 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK | | 6293 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK | |
6283 | MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | | 6294 | MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | |
@@ -6310,7 +6321,7 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy, | |||
6310 | val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; | 6321 | val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; |
6311 | 6322 | ||
6312 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | 6323 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
6313 | MDIO_CTL_REG_84823_MEDIA, val); | 6324 | MDIO_CTL_REG_84823_MEDIA + adj, val); |
6314 | DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", | 6325 | DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", |
6315 | params->multi_phy_config, val); | 6326 | params->multi_phy_config, val); |
6316 | 6327 | ||
@@ -6326,15 +6337,20 @@ static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, | |||
6326 | struct link_vars *vars) | 6337 | struct link_vars *vars) |
6327 | { | 6338 | { |
6328 | struct bnx2x *bp = params->bp; | 6339 | struct bnx2x *bp = params->bp; |
6329 | u16 val, val1, val2; | 6340 | u16 val, val1, val2, adj; |
6330 | u8 link_up = 0; | 6341 | u8 link_up = 0; |
6331 | 6342 | ||
6343 | /* Reg offset adjustment for 84833 */ | ||
6344 | adj = 0; | ||
6345 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | ||
6346 | adj = -1; | ||
6347 | |||
6332 | /* Check 10G-BaseT link status */ | 6348 | /* Check 10G-BaseT link status */ |
6333 | /* Check PMD signal ok */ | 6349 | /* Check PMD signal ok */ |
6334 | bnx2x_cl45_read(bp, phy, | 6350 | bnx2x_cl45_read(bp, phy, |
6335 | MDIO_AN_DEVAD, 0xFFFA, &val1); | 6351 | MDIO_AN_DEVAD, 0xFFFA, &val1); |
6336 | bnx2x_cl45_read(bp, phy, | 6352 | bnx2x_cl45_read(bp, phy, |
6337 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, | 6353 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL + adj, |
6338 | &val2); | 6354 | &val2); |
6339 | DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); | 6355 | DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); |
6340 | 6356 | ||
@@ -7159,6 +7175,43 @@ static struct bnx2x_phy phy_84823 = { | |||
7159 | .phy_specific_func = (phy_specific_func_t)NULL | 7175 | .phy_specific_func = (phy_specific_func_t)NULL |
7160 | }; | 7176 | }; |
7161 | 7177 | ||
7178 | static struct bnx2x_phy phy_84833 = { | ||
7179 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, | ||
7180 | .addr = 0xff, | ||
7181 | .flags = FLAGS_FAN_FAILURE_DET_REQ | | ||
7182 | FLAGS_REARM_LATCH_SIGNAL, | ||
7183 | .def_md_devad = 0, | ||
7184 | .reserved = 0, | ||
7185 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | ||
7186 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | ||
7187 | .mdio_ctrl = 0, | ||
7188 | .supported = (SUPPORTED_10baseT_Half | | ||
7189 | SUPPORTED_10baseT_Full | | ||
7190 | SUPPORTED_100baseT_Half | | ||
7191 | SUPPORTED_100baseT_Full | | ||
7192 | SUPPORTED_1000baseT_Full | | ||
7193 | SUPPORTED_10000baseT_Full | | ||
7194 | SUPPORTED_TP | | ||
7195 | SUPPORTED_Autoneg | | ||
7196 | SUPPORTED_Pause | | ||
7197 | SUPPORTED_Asym_Pause), | ||
7198 | .media_type = ETH_PHY_BASE_T, | ||
7199 | .ver_addr = 0, | ||
7200 | .req_flow_ctrl = 0, | ||
7201 | .req_line_speed = 0, | ||
7202 | .speed_cap_mask = 0, | ||
7203 | .req_duplex = 0, | ||
7204 | .rsrv = 0, | ||
7205 | .config_init = (config_init_t)bnx2x_848x3_config_init, | ||
7206 | .read_status = (read_status_t)bnx2x_848xx_read_status, | ||
7207 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, | ||
7208 | .config_loopback = (config_loopback_t)NULL, | ||
7209 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | ||
7210 | .hw_reset = (hw_reset_t)NULL, | ||
7211 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, | ||
7212 | .phy_specific_func = (phy_specific_func_t)NULL | ||
7213 | }; | ||
7214 | |||
7162 | /*****************************************************************/ | 7215 | /*****************************************************************/ |
7163 | /* */ | 7216 | /* */ |
7164 | /* Populate the phy according. Main function: bnx2x_populate_phy */ | 7217 | /* Populate the phy according. Main function: bnx2x_populate_phy */ |
@@ -7312,6 +7365,9 @@ static u8 bnx2x_populate_ext_phy(struct bnx2x *bp, | |||
7312 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: | 7365 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: |
7313 | *phy = phy_84823; | 7366 | *phy = phy_84823; |
7314 | break; | 7367 | break; |
7368 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: | ||
7369 | *phy = phy_84833; | ||
7370 | break; | ||
7315 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: | 7371 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: |
7316 | *phy = phy_7101; | 7372 | *phy = phy_7101; |
7317 | break; | 7373 | break; |