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path: root/drivers/net/bnx2x/bnx2x_main.c
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Diffstat (limited to 'drivers/net/bnx2x/bnx2x_main.c')
-rw-r--r--drivers/net/bnx2x/bnx2x_main.c1958
1 files changed, 4 insertions, 1954 deletions
diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c
index 0c00e50787f9..3abfce2d467e 100644
--- a/drivers/net/bnx2x/bnx2x_main.c
+++ b/drivers/net/bnx2x/bnx2x_main.c
@@ -55,12 +55,8 @@
55#include "bnx2x.h" 55#include "bnx2x.h"
56#include "bnx2x_init.h" 56#include "bnx2x_init.h"
57#include "bnx2x_init_ops.h" 57#include "bnx2x_init_ops.h"
58#include "bnx2x_dump.h"
59#include "bnx2x_cmn.h" 58#include "bnx2x_cmn.h"
60 59
61#define DRV_MODULE_VERSION "1.52.53-1"
62#define DRV_MODULE_RELDATE "2010/18/04"
63#define BNX2X_BC_VER 0x040200
64 60
65#include <linux/firmware.h> 61#include <linux/firmware.h>
66#include "bnx2x_fw_file_hdr.h" 62#include "bnx2x_fw_file_hdr.h"
@@ -7182,8 +7178,6 @@ reset_task_exit:
7182 7178
7183/* end of nic load/unload */ 7179/* end of nic load/unload */
7184 7180
7185/* ethtool_ops */
7186
7187/* 7181/*
7188 * Init service functions 7182 * Init service functions
7189 */ 7183 */
@@ -8172,1954 +8166,10 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8172 return rc; 8166 return rc;
8173} 8167}
8174 8168
8175/*
8176 * ethtool service functions
8177 */
8178
8179/* All ethtool functions called with rtnl_lock */
8180
8181static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8182{
8183 struct bnx2x *bp = netdev_priv(dev);
8184
8185 cmd->supported = bp->port.supported;
8186 cmd->advertising = bp->port.advertising;
8187
8188 if ((bp->state == BNX2X_STATE_OPEN) &&
8189 !(bp->flags & MF_FUNC_DIS) &&
8190 (bp->link_vars.link_up)) {
8191 cmd->speed = bp->link_vars.line_speed;
8192 cmd->duplex = bp->link_vars.duplex;
8193 if (IS_E1HMF(bp)) {
8194 u16 vn_max_rate;
8195
8196 vn_max_rate =
8197 ((bp->mf_config & FUNC_MF_CFG_MAX_BW_MASK) >>
8198 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
8199 if (vn_max_rate < cmd->speed)
8200 cmd->speed = vn_max_rate;
8201 }
8202 } else {
8203 cmd->speed = -1;
8204 cmd->duplex = -1;
8205 }
8206
8207 if (bp->link_params.switch_cfg == SWITCH_CFG_10G) {
8208 u32 ext_phy_type =
8209 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
8210
8211 switch (ext_phy_type) {
8212 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8213 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
8214 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
8215 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
8216 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
8217 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8218 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8219 cmd->port = PORT_FIBRE;
8220 break;
8221
8222 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
8223 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
8224 cmd->port = PORT_TP;
8225 break;
8226
8227 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
8228 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
8229 bp->link_params.ext_phy_config);
8230 break;
8231
8232 default:
8233 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
8234 bp->link_params.ext_phy_config);
8235 break;
8236 }
8237 } else
8238 cmd->port = PORT_TP;
8239
8240 cmd->phy_address = bp->mdio.prtad;
8241 cmd->transceiver = XCVR_INTERNAL;
8242
8243 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
8244 cmd->autoneg = AUTONEG_ENABLE;
8245 else
8246 cmd->autoneg = AUTONEG_DISABLE;
8247
8248 cmd->maxtxpkt = 0;
8249 cmd->maxrxpkt = 0;
8250
8251 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
8252 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
8253 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
8254 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
8255 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
8256 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
8257 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
8258
8259 return 0;
8260}
8261
8262static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8263{
8264 struct bnx2x *bp = netdev_priv(dev);
8265 u32 advertising;
8266
8267 if (IS_E1HMF(bp))
8268 return 0;
8269
8270 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
8271 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
8272 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
8273 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
8274 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
8275 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
8276 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
8277
8278 if (cmd->autoneg == AUTONEG_ENABLE) {
8279 if (!(bp->port.supported & SUPPORTED_Autoneg)) {
8280 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
8281 return -EINVAL;
8282 }
8283
8284 /* advertise the requested speed and duplex if supported */
8285 cmd->advertising &= bp->port.supported;
8286
8287 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
8288 bp->link_params.req_duplex = DUPLEX_FULL;
8289 bp->port.advertising |= (ADVERTISED_Autoneg |
8290 cmd->advertising);
8291
8292 } else { /* forced speed */
8293 /* advertise the requested speed and duplex if supported */
8294 switch (cmd->speed) {
8295 case SPEED_10:
8296 if (cmd->duplex == DUPLEX_FULL) {
8297 if (!(bp->port.supported &
8298 SUPPORTED_10baseT_Full)) {
8299 DP(NETIF_MSG_LINK,
8300 "10M full not supported\n");
8301 return -EINVAL;
8302 }
8303
8304 advertising = (ADVERTISED_10baseT_Full |
8305 ADVERTISED_TP);
8306 } else {
8307 if (!(bp->port.supported &
8308 SUPPORTED_10baseT_Half)) {
8309 DP(NETIF_MSG_LINK,
8310 "10M half not supported\n");
8311 return -EINVAL;
8312 }
8313
8314 advertising = (ADVERTISED_10baseT_Half |
8315 ADVERTISED_TP);
8316 }
8317 break;
8318
8319 case SPEED_100:
8320 if (cmd->duplex == DUPLEX_FULL) {
8321 if (!(bp->port.supported &
8322 SUPPORTED_100baseT_Full)) {
8323 DP(NETIF_MSG_LINK,
8324 "100M full not supported\n");
8325 return -EINVAL;
8326 }
8327
8328 advertising = (ADVERTISED_100baseT_Full |
8329 ADVERTISED_TP);
8330 } else {
8331 if (!(bp->port.supported &
8332 SUPPORTED_100baseT_Half)) {
8333 DP(NETIF_MSG_LINK,
8334 "100M half not supported\n");
8335 return -EINVAL;
8336 }
8337
8338 advertising = (ADVERTISED_100baseT_Half |
8339 ADVERTISED_TP);
8340 }
8341 break;
8342
8343 case SPEED_1000:
8344 if (cmd->duplex != DUPLEX_FULL) {
8345 DP(NETIF_MSG_LINK, "1G half not supported\n");
8346 return -EINVAL;
8347 }
8348
8349 if (!(bp->port.supported & SUPPORTED_1000baseT_Full)) {
8350 DP(NETIF_MSG_LINK, "1G full not supported\n");
8351 return -EINVAL;
8352 }
8353
8354 advertising = (ADVERTISED_1000baseT_Full |
8355 ADVERTISED_TP);
8356 break;
8357
8358 case SPEED_2500:
8359 if (cmd->duplex != DUPLEX_FULL) {
8360 DP(NETIF_MSG_LINK,
8361 "2.5G half not supported\n");
8362 return -EINVAL;
8363 }
8364
8365 if (!(bp->port.supported & SUPPORTED_2500baseX_Full)) {
8366 DP(NETIF_MSG_LINK,
8367 "2.5G full not supported\n");
8368 return -EINVAL;
8369 }
8370
8371 advertising = (ADVERTISED_2500baseX_Full |
8372 ADVERTISED_TP);
8373 break;
8374
8375 case SPEED_10000:
8376 if (cmd->duplex != DUPLEX_FULL) {
8377 DP(NETIF_MSG_LINK, "10G half not supported\n");
8378 return -EINVAL;
8379 }
8380
8381 if (!(bp->port.supported & SUPPORTED_10000baseT_Full)) {
8382 DP(NETIF_MSG_LINK, "10G full not supported\n");
8383 return -EINVAL;
8384 }
8385
8386 advertising = (ADVERTISED_10000baseT_Full |
8387 ADVERTISED_FIBRE);
8388 break;
8389
8390 default:
8391 DP(NETIF_MSG_LINK, "Unsupported speed\n");
8392 return -EINVAL;
8393 }
8394
8395 bp->link_params.req_line_speed = cmd->speed;
8396 bp->link_params.req_duplex = cmd->duplex;
8397 bp->port.advertising = advertising;
8398 }
8399
8400 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
8401 DP_LEVEL " req_duplex %d advertising 0x%x\n",
8402 bp->link_params.req_line_speed, bp->link_params.req_duplex,
8403 bp->port.advertising);
8404
8405 if (netif_running(dev)) {
8406 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
8407 bnx2x_link_set(bp);
8408 }
8409
8410 return 0;
8411}
8412
8413#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
8414#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
8415
8416static int bnx2x_get_regs_len(struct net_device *dev)
8417{
8418 struct bnx2x *bp = netdev_priv(dev);
8419 int regdump_len = 0;
8420 int i;
8421
8422 if (CHIP_IS_E1(bp)) {
8423 for (i = 0; i < REGS_COUNT; i++)
8424 if (IS_E1_ONLINE(reg_addrs[i].info))
8425 regdump_len += reg_addrs[i].size;
8426
8427 for (i = 0; i < WREGS_COUNT_E1; i++)
8428 if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
8429 regdump_len += wreg_addrs_e1[i].size *
8430 (1 + wreg_addrs_e1[i].read_regs_count);
8431
8432 } else { /* E1H */
8433 for (i = 0; i < REGS_COUNT; i++)
8434 if (IS_E1H_ONLINE(reg_addrs[i].info))
8435 regdump_len += reg_addrs[i].size;
8436
8437 for (i = 0; i < WREGS_COUNT_E1H; i++)
8438 if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
8439 regdump_len += wreg_addrs_e1h[i].size *
8440 (1 + wreg_addrs_e1h[i].read_regs_count);
8441 }
8442 regdump_len *= 4;
8443 regdump_len += sizeof(struct dump_hdr);
8444
8445 return regdump_len;
8446}
8447
8448static void bnx2x_get_regs(struct net_device *dev,
8449 struct ethtool_regs *regs, void *_p)
8450{
8451 u32 *p = _p, i, j;
8452 struct bnx2x *bp = netdev_priv(dev);
8453 struct dump_hdr dump_hdr = {0};
8454
8455 regs->version = 0;
8456 memset(p, 0, regs->len);
8457
8458 if (!netif_running(bp->dev))
8459 return;
8460
8461 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
8462 dump_hdr.dump_sign = dump_sign_all;
8463 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
8464 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
8465 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
8466 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
8467 dump_hdr.info = CHIP_IS_E1(bp) ? RI_E1_ONLINE : RI_E1H_ONLINE;
8468
8469 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
8470 p += dump_hdr.hdr_size + 1;
8471
8472 if (CHIP_IS_E1(bp)) {
8473 for (i = 0; i < REGS_COUNT; i++)
8474 if (IS_E1_ONLINE(reg_addrs[i].info))
8475 for (j = 0; j < reg_addrs[i].size; j++)
8476 *p++ = REG_RD(bp,
8477 reg_addrs[i].addr + j*4);
8478
8479 } else { /* E1H */
8480 for (i = 0; i < REGS_COUNT; i++)
8481 if (IS_E1H_ONLINE(reg_addrs[i].info))
8482 for (j = 0; j < reg_addrs[i].size; j++)
8483 *p++ = REG_RD(bp,
8484 reg_addrs[i].addr + j*4);
8485 }
8486}
8487
8488#define PHY_FW_VER_LEN 10
8489
8490static void bnx2x_get_drvinfo(struct net_device *dev,
8491 struct ethtool_drvinfo *info)
8492{
8493 struct bnx2x *bp = netdev_priv(dev);
8494 u8 phy_fw_ver[PHY_FW_VER_LEN];
8495
8496 strcpy(info->driver, DRV_MODULE_NAME);
8497 strcpy(info->version, DRV_MODULE_VERSION);
8498
8499 phy_fw_ver[0] = '\0';
8500 if (bp->port.pmf) {
8501 bnx2x_acquire_phy_lock(bp);
8502 bnx2x_get_ext_phy_fw_version(&bp->link_params,
8503 (bp->state != BNX2X_STATE_CLOSED),
8504 phy_fw_ver, PHY_FW_VER_LEN);
8505 bnx2x_release_phy_lock(bp);
8506 }
8507
8508 strncpy(info->fw_version, bp->fw_ver, 32);
8509 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
8510 "bc %d.%d.%d%s%s",
8511 (bp->common.bc_ver & 0xff0000) >> 16,
8512 (bp->common.bc_ver & 0xff00) >> 8,
8513 (bp->common.bc_ver & 0xff),
8514 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
8515 strcpy(info->bus_info, pci_name(bp->pdev));
8516 info->n_stats = BNX2X_NUM_STATS;
8517 info->testinfo_len = BNX2X_NUM_TESTS;
8518 info->eedump_len = bp->common.flash_size;
8519 info->regdump_len = bnx2x_get_regs_len(dev);
8520}
8521
8522static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8523{
8524 struct bnx2x *bp = netdev_priv(dev);
8525
8526 if (bp->flags & NO_WOL_FLAG) {
8527 wol->supported = 0;
8528 wol->wolopts = 0;
8529 } else {
8530 wol->supported = WAKE_MAGIC;
8531 if (bp->wol)
8532 wol->wolopts = WAKE_MAGIC;
8533 else
8534 wol->wolopts = 0;
8535 }
8536 memset(&wol->sopass, 0, sizeof(wol->sopass));
8537}
8538
8539static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8540{
8541 struct bnx2x *bp = netdev_priv(dev);
8542
8543 if (wol->wolopts & ~WAKE_MAGIC)
8544 return -EINVAL;
8545
8546 if (wol->wolopts & WAKE_MAGIC) {
8547 if (bp->flags & NO_WOL_FLAG)
8548 return -EINVAL;
8549
8550 bp->wol = 1;
8551 } else
8552 bp->wol = 0;
8553
8554 return 0;
8555}
8556
8557static u32 bnx2x_get_msglevel(struct net_device *dev)
8558{
8559 struct bnx2x *bp = netdev_priv(dev);
8560
8561 return bp->msg_enable;
8562}
8563
8564static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
8565{
8566 struct bnx2x *bp = netdev_priv(dev);
8567
8568 if (capable(CAP_NET_ADMIN))
8569 bp->msg_enable = level;
8570}
8571
8572static int bnx2x_nway_reset(struct net_device *dev)
8573{
8574 struct bnx2x *bp = netdev_priv(dev);
8575
8576 if (!bp->port.pmf)
8577 return 0;
8578
8579 if (netif_running(dev)) {
8580 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
8581 bnx2x_link_set(bp);
8582 }
8583
8584 return 0;
8585}
8586
8587static u32 bnx2x_get_link(struct net_device *dev)
8588{
8589 struct bnx2x *bp = netdev_priv(dev);
8590
8591 if (bp->flags & MF_FUNC_DIS)
8592 return 0;
8593
8594 return bp->link_vars.link_up;
8595}
8596
8597static int bnx2x_get_eeprom_len(struct net_device *dev)
8598{
8599 struct bnx2x *bp = netdev_priv(dev);
8600
8601 return bp->common.flash_size;
8602}
8603
8604static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
8605{
8606 int port = BP_PORT(bp);
8607 int count, i;
8608 u32 val = 0;
8609
8610 /* adjust timeout for emulation/FPGA */
8611 count = NVRAM_TIMEOUT_COUNT;
8612 if (CHIP_REV_IS_SLOW(bp))
8613 count *= 100;
8614
8615 /* request access to nvram interface */
8616 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
8617 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
8618
8619 for (i = 0; i < count*10; i++) {
8620 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
8621 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
8622 break;
8623
8624 udelay(5);
8625 }
8626
8627 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
8628 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
8629 return -EBUSY;
8630 }
8631
8632 return 0;
8633}
8634
8635static int bnx2x_release_nvram_lock(struct bnx2x *bp)
8636{
8637 int port = BP_PORT(bp);
8638 int count, i;
8639 u32 val = 0;
8640
8641 /* adjust timeout for emulation/FPGA */
8642 count = NVRAM_TIMEOUT_COUNT;
8643 if (CHIP_REV_IS_SLOW(bp))
8644 count *= 100;
8645
8646 /* relinquish nvram interface */
8647 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
8648 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
8649
8650 for (i = 0; i < count*10; i++) {
8651 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
8652 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
8653 break;
8654
8655 udelay(5);
8656 }
8657
8658 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
8659 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
8660 return -EBUSY;
8661 }
8662
8663 return 0;
8664}
8665
8666static void bnx2x_enable_nvram_access(struct bnx2x *bp)
8667{
8668 u32 val;
8669
8670 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
8671
8672 /* enable both bits, even on read */
8673 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
8674 (val | MCPR_NVM_ACCESS_ENABLE_EN |
8675 MCPR_NVM_ACCESS_ENABLE_WR_EN));
8676}
8677
8678static void bnx2x_disable_nvram_access(struct bnx2x *bp)
8679{
8680 u32 val;
8681
8682 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
8683
8684 /* disable both bits, even after read */
8685 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
8686 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
8687 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
8688}
8689
8690static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
8691 u32 cmd_flags)
8692{
8693 int count, i, rc;
8694 u32 val;
8695
8696 /* build the command word */
8697 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
8698
8699 /* need to clear DONE bit separately */
8700 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
8701
8702 /* address of the NVRAM to read from */
8703 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
8704 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
8705
8706 /* issue a read command */
8707 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
8708
8709 /* adjust timeout for emulation/FPGA */
8710 count = NVRAM_TIMEOUT_COUNT;
8711 if (CHIP_REV_IS_SLOW(bp))
8712 count *= 100;
8713
8714 /* wait for completion */
8715 *ret_val = 0;
8716 rc = -EBUSY;
8717 for (i = 0; i < count; i++) {
8718 udelay(5);
8719 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
8720
8721 if (val & MCPR_NVM_COMMAND_DONE) {
8722 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
8723 /* we read nvram data in cpu order
8724 * but ethtool sees it as an array of bytes
8725 * converting to big-endian will do the work */
8726 *ret_val = cpu_to_be32(val);
8727 rc = 0;
8728 break;
8729 }
8730 }
8731
8732 return rc;
8733}
8734
8735static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
8736 int buf_size)
8737{
8738 int rc;
8739 u32 cmd_flags;
8740 __be32 val;
8741
8742 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
8743 DP(BNX2X_MSG_NVM,
8744 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
8745 offset, buf_size);
8746 return -EINVAL;
8747 }
8748
8749 if (offset + buf_size > bp->common.flash_size) {
8750 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
8751 " buf_size (0x%x) > flash_size (0x%x)\n",
8752 offset, buf_size, bp->common.flash_size);
8753 return -EINVAL;
8754 }
8755
8756 /* request access to nvram interface */
8757 rc = bnx2x_acquire_nvram_lock(bp);
8758 if (rc)
8759 return rc;
8760
8761 /* enable access to nvram interface */
8762 bnx2x_enable_nvram_access(bp);
8763
8764 /* read the first word(s) */
8765 cmd_flags = MCPR_NVM_COMMAND_FIRST;
8766 while ((buf_size > sizeof(u32)) && (rc == 0)) {
8767 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
8768 memcpy(ret_buf, &val, 4);
8769
8770 /* advance to the next dword */
8771 offset += sizeof(u32);
8772 ret_buf += sizeof(u32);
8773 buf_size -= sizeof(u32);
8774 cmd_flags = 0;
8775 }
8776
8777 if (rc == 0) {
8778 cmd_flags |= MCPR_NVM_COMMAND_LAST;
8779 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
8780 memcpy(ret_buf, &val, 4);
8781 }
8782
8783 /* disable access to nvram interface */
8784 bnx2x_disable_nvram_access(bp);
8785 bnx2x_release_nvram_lock(bp);
8786
8787 return rc;
8788}
8789
8790static int bnx2x_get_eeprom(struct net_device *dev,
8791 struct ethtool_eeprom *eeprom, u8 *eebuf)
8792{
8793 struct bnx2x *bp = netdev_priv(dev);
8794 int rc;
8795
8796 if (!netif_running(dev))
8797 return -EAGAIN;
8798
8799 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
8800 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
8801 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
8802 eeprom->len, eeprom->len);
8803
8804 /* parameters already validated in ethtool_get_eeprom */
8805
8806 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
8807
8808 return rc;
8809}
8810
8811static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
8812 u32 cmd_flags)
8813{
8814 int count, i, rc;
8815
8816 /* build the command word */
8817 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
8818
8819 /* need to clear DONE bit separately */
8820 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
8821
8822 /* write the data */
8823 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
8824
8825 /* address of the NVRAM to write to */
8826 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
8827 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
8828
8829 /* issue the write command */
8830 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
8831
8832 /* adjust timeout for emulation/FPGA */
8833 count = NVRAM_TIMEOUT_COUNT;
8834 if (CHIP_REV_IS_SLOW(bp))
8835 count *= 100;
8836
8837 /* wait for completion */
8838 rc = -EBUSY;
8839 for (i = 0; i < count; i++) {
8840 udelay(5);
8841 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
8842 if (val & MCPR_NVM_COMMAND_DONE) {
8843 rc = 0;
8844 break;
8845 }
8846 }
8847
8848 return rc;
8849}
8850
8851#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
8852
8853static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
8854 int buf_size)
8855{
8856 int rc;
8857 u32 cmd_flags;
8858 u32 align_offset;
8859 __be32 val;
8860
8861 if (offset + buf_size > bp->common.flash_size) {
8862 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
8863 " buf_size (0x%x) > flash_size (0x%x)\n",
8864 offset, buf_size, bp->common.flash_size);
8865 return -EINVAL;
8866 }
8867
8868 /* request access to nvram interface */
8869 rc = bnx2x_acquire_nvram_lock(bp);
8870 if (rc)
8871 return rc;
8872
8873 /* enable access to nvram interface */
8874 bnx2x_enable_nvram_access(bp);
8875
8876 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
8877 align_offset = (offset & ~0x03);
8878 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
8879
8880 if (rc == 0) {
8881 val &= ~(0xff << BYTE_OFFSET(offset));
8882 val |= (*data_buf << BYTE_OFFSET(offset));
8883
8884 /* nvram data is returned as an array of bytes
8885 * convert it back to cpu order */
8886 val = be32_to_cpu(val);
8887
8888 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
8889 cmd_flags);
8890 }
8891
8892 /* disable access to nvram interface */
8893 bnx2x_disable_nvram_access(bp);
8894 bnx2x_release_nvram_lock(bp);
8895
8896 return rc;
8897}
8898
8899static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
8900 int buf_size)
8901{
8902 int rc;
8903 u32 cmd_flags;
8904 u32 val;
8905 u32 written_so_far;
8906
8907 if (buf_size == 1) /* ethtool */
8908 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
8909
8910 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
8911 DP(BNX2X_MSG_NVM,
8912 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
8913 offset, buf_size);
8914 return -EINVAL;
8915 }
8916
8917 if (offset + buf_size > bp->common.flash_size) {
8918 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
8919 " buf_size (0x%x) > flash_size (0x%x)\n",
8920 offset, buf_size, bp->common.flash_size);
8921 return -EINVAL;
8922 }
8923
8924 /* request access to nvram interface */
8925 rc = bnx2x_acquire_nvram_lock(bp);
8926 if (rc)
8927 return rc;
8928
8929 /* enable access to nvram interface */
8930 bnx2x_enable_nvram_access(bp);
8931
8932 written_so_far = 0;
8933 cmd_flags = MCPR_NVM_COMMAND_FIRST;
8934 while ((written_so_far < buf_size) && (rc == 0)) {
8935 if (written_so_far == (buf_size - sizeof(u32)))
8936 cmd_flags |= MCPR_NVM_COMMAND_LAST;
8937 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
8938 cmd_flags |= MCPR_NVM_COMMAND_LAST;
8939 else if ((offset % NVRAM_PAGE_SIZE) == 0)
8940 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
8941
8942 memcpy(&val, data_buf, 4);
8943
8944 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
8945
8946 /* advance to the next dword */
8947 offset += sizeof(u32);
8948 data_buf += sizeof(u32);
8949 written_so_far += sizeof(u32);
8950 cmd_flags = 0;
8951 }
8952
8953 /* disable access to nvram interface */
8954 bnx2x_disable_nvram_access(bp);
8955 bnx2x_release_nvram_lock(bp);
8956
8957 return rc;
8958}
8959
8960static int bnx2x_set_eeprom(struct net_device *dev,
8961 struct ethtool_eeprom *eeprom, u8 *eebuf)
8962{
8963 struct bnx2x *bp = netdev_priv(dev);
8964 int port = BP_PORT(bp);
8965 int rc = 0;
8966
8967 if (!netif_running(dev))
8968 return -EAGAIN;
8969
8970 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
8971 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
8972 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
8973 eeprom->len, eeprom->len);
8974
8975 /* parameters already validated in ethtool_set_eeprom */
8976
8977 /* PHY eeprom can be accessed only by the PMF */
8978 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
8979 !bp->port.pmf)
8980 return -EINVAL;
8981
8982 if (eeprom->magic == 0x50485950) {
8983 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
8984 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
8985
8986 bnx2x_acquire_phy_lock(bp);
8987 rc |= bnx2x_link_reset(&bp->link_params,
8988 &bp->link_vars, 0);
8989 if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
8990 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
8991 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
8992 MISC_REGISTERS_GPIO_HIGH, port);
8993 bnx2x_release_phy_lock(bp);
8994 bnx2x_link_report(bp);
8995
8996 } else if (eeprom->magic == 0x50485952) {
8997 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
8998 if (bp->state == BNX2X_STATE_OPEN) {
8999 bnx2x_acquire_phy_lock(bp);
9000 rc |= bnx2x_link_reset(&bp->link_params,
9001 &bp->link_vars, 1);
9002
9003 rc |= bnx2x_phy_init(&bp->link_params,
9004 &bp->link_vars);
9005 bnx2x_release_phy_lock(bp);
9006 bnx2x_calc_fc_adv(bp);
9007 }
9008 } else if (eeprom->magic == 0x53985943) {
9009 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
9010 if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
9011 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
9012 u8 ext_phy_addr =
9013 XGXS_EXT_PHY_ADDR(bp->link_params.ext_phy_config);
9014
9015 /* DSP Remove Download Mode */
9016 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
9017 MISC_REGISTERS_GPIO_LOW, port);
9018
9019 bnx2x_acquire_phy_lock(bp);
9020
9021 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
9022
9023 /* wait 0.5 sec to allow it to run */
9024 msleep(500);
9025 bnx2x_ext_phy_hw_reset(bp, port);
9026 msleep(500);
9027 bnx2x_release_phy_lock(bp);
9028 }
9029 } else
9030 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
9031
9032 return rc;
9033}
9034
9035static int bnx2x_get_coalesce(struct net_device *dev,
9036 struct ethtool_coalesce *coal)
9037{
9038 struct bnx2x *bp = netdev_priv(dev);
9039
9040 memset(coal, 0, sizeof(struct ethtool_coalesce));
9041
9042 coal->rx_coalesce_usecs = bp->rx_ticks;
9043 coal->tx_coalesce_usecs = bp->tx_ticks;
9044
9045 return 0;
9046}
9047
9048static int bnx2x_set_coalesce(struct net_device *dev,
9049 struct ethtool_coalesce *coal)
9050{
9051 struct bnx2x *bp = netdev_priv(dev);
9052
9053 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
9054 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
9055 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
9056
9057 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
9058 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
9059 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
9060
9061 if (netif_running(dev))
9062 bnx2x_update_coalesce(bp);
9063
9064 return 0;
9065}
9066
9067static void bnx2x_get_ringparam(struct net_device *dev,
9068 struct ethtool_ringparam *ering)
9069{
9070 struct bnx2x *bp = netdev_priv(dev);
9071
9072 ering->rx_max_pending = MAX_RX_AVAIL;
9073 ering->rx_mini_max_pending = 0;
9074 ering->rx_jumbo_max_pending = 0;
9075
9076 ering->rx_pending = bp->rx_ring_size;
9077 ering->rx_mini_pending = 0;
9078 ering->rx_jumbo_pending = 0;
9079
9080 ering->tx_max_pending = MAX_TX_AVAIL;
9081 ering->tx_pending = bp->tx_ring_size;
9082}
9083
9084static int bnx2x_set_ringparam(struct net_device *dev,
9085 struct ethtool_ringparam *ering)
9086{
9087 struct bnx2x *bp = netdev_priv(dev);
9088 int rc = 0;
9089
9090 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
9091 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
9092 return -EAGAIN;
9093 }
9094
9095 if ((ering->rx_pending > MAX_RX_AVAIL) ||
9096 (ering->tx_pending > MAX_TX_AVAIL) ||
9097 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
9098 return -EINVAL;
9099
9100 bp->rx_ring_size = ering->rx_pending;
9101 bp->tx_ring_size = ering->tx_pending;
9102
9103 if (netif_running(dev)) {
9104 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
9105 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
9106 }
9107
9108 return rc;
9109}
9110
9111static void bnx2x_get_pauseparam(struct net_device *dev,
9112 struct ethtool_pauseparam *epause)
9113{
9114 struct bnx2x *bp = netdev_priv(dev);
9115
9116 epause->autoneg = (bp->link_params.req_flow_ctrl ==
9117 BNX2X_FLOW_CTRL_AUTO) &&
9118 (bp->link_params.req_line_speed == SPEED_AUTO_NEG);
9119
9120 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
9121 BNX2X_FLOW_CTRL_RX);
9122 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
9123 BNX2X_FLOW_CTRL_TX);
9124
9125 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
9126 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
9127 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
9128}
9129
9130static int bnx2x_set_pauseparam(struct net_device *dev,
9131 struct ethtool_pauseparam *epause)
9132{
9133 struct bnx2x *bp = netdev_priv(dev);
9134
9135 if (IS_E1HMF(bp))
9136 return 0;
9137
9138 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
9139 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
9140 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
9141
9142 bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
9143
9144 if (epause->rx_pause)
9145 bp->link_params.req_flow_ctrl |= BNX2X_FLOW_CTRL_RX;
9146
9147 if (epause->tx_pause)
9148 bp->link_params.req_flow_ctrl |= BNX2X_FLOW_CTRL_TX;
9149
9150 if (bp->link_params.req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO)
9151 bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
9152
9153 if (epause->autoneg) {
9154 if (!(bp->port.supported & SUPPORTED_Autoneg)) {
9155 DP(NETIF_MSG_LINK, "autoneg not supported\n");
9156 return -EINVAL;
9157 }
9158
9159 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
9160 bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
9161 }
9162
9163 DP(NETIF_MSG_LINK,
9164 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl);
9165
9166 if (netif_running(dev)) {
9167 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
9168 bnx2x_link_set(bp);
9169 }
9170
9171 return 0;
9172}
9173
9174static int bnx2x_set_flags(struct net_device *dev, u32 data)
9175{
9176 struct bnx2x *bp = netdev_priv(dev);
9177 int changed = 0;
9178 int rc = 0;
9179
9180 if (data & ~(ETH_FLAG_LRO | ETH_FLAG_RXHASH))
9181 return -EINVAL;
9182
9183 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
9184 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
9185 return -EAGAIN;
9186 }
9187
9188 /* TPA requires Rx CSUM offloading */
9189 if ((data & ETH_FLAG_LRO) && bp->rx_csum) {
9190 if (!bp->disable_tpa) {
9191 if (!(dev->features & NETIF_F_LRO)) {
9192 dev->features |= NETIF_F_LRO;
9193 bp->flags |= TPA_ENABLE_FLAG;
9194 changed = 1;
9195 }
9196 } else
9197 rc = -EINVAL;
9198 } else if (dev->features & NETIF_F_LRO) {
9199 dev->features &= ~NETIF_F_LRO;
9200 bp->flags &= ~TPA_ENABLE_FLAG;
9201 changed = 1;
9202 }
9203
9204 if (data & ETH_FLAG_RXHASH)
9205 dev->features |= NETIF_F_RXHASH;
9206 else
9207 dev->features &= ~NETIF_F_RXHASH;
9208
9209 if (changed && netif_running(dev)) {
9210 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
9211 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
9212 }
9213
9214 return rc;
9215}
9216
9217static u32 bnx2x_get_rx_csum(struct net_device *dev)
9218{
9219 struct bnx2x *bp = netdev_priv(dev);
9220
9221 return bp->rx_csum;
9222}
9223
9224static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
9225{
9226 struct bnx2x *bp = netdev_priv(dev);
9227 int rc = 0;
9228
9229 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
9230 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
9231 return -EAGAIN;
9232 }
9233
9234 bp->rx_csum = data;
9235
9236 /* Disable TPA, when Rx CSUM is disabled. Otherwise all
9237 TPA'ed packets will be discarded due to wrong TCP CSUM */
9238 if (!data) {
9239 u32 flags = ethtool_op_get_flags(dev);
9240
9241 rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO));
9242 }
9243
9244 return rc;
9245}
9246
9247static int bnx2x_set_tso(struct net_device *dev, u32 data)
9248{
9249 if (data) {
9250 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9251 dev->features |= NETIF_F_TSO6;
9252 } else {
9253 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
9254 dev->features &= ~NETIF_F_TSO6;
9255 }
9256
9257 return 0;
9258}
9259
9260static const struct {
9261 char string[ETH_GSTRING_LEN];
9262} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
9263 { "register_test (offline)" },
9264 { "memory_test (offline)" },
9265 { "loopback_test (offline)" },
9266 { "nvram_test (online)" },
9267 { "interrupt_test (online)" },
9268 { "link_test (online)" },
9269 { "idle check (online)" }
9270};
9271
9272static int bnx2x_test_registers(struct bnx2x *bp)
9273{
9274 int idx, i, rc = -ENODEV;
9275 u32 wr_val = 0;
9276 int port = BP_PORT(bp);
9277 static const struct {
9278 u32 offset0;
9279 u32 offset1;
9280 u32 mask;
9281 } reg_tbl[] = {
9282/* 0 */ { BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
9283 { DORQ_REG_DB_ADDR0, 4, 0xffffffff },
9284 { HC_REG_AGG_INT_0, 4, 0x000003ff },
9285 { PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
9286 { PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
9287 { PRS_REG_CID_PORT_0, 4, 0x00ffffff },
9288 { PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
9289 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
9290 { PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
9291 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
9292/* 10 */ { PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
9293 { QM_REG_CONNNUM_0, 4, 0x000fffff },
9294 { TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
9295 { SRC_REG_KEYRSS0_0, 40, 0xffffffff },
9296 { SRC_REG_KEYRSS0_7, 40, 0xffffffff },
9297 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
9298 { XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
9299 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
9300 { NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
9301 { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
9302/* 20 */ { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
9303 { NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
9304 { NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
9305 { NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
9306 { NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
9307 { NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
9308 { NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
9309 { NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
9310 { NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
9311 { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
9312/* 30 */ { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
9313 { NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
9314 { NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
9315 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
9316 { NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
9317 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
9318 { NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
9319
9320 { 0xffffffff, 0, 0x00000000 }
9321 };
9322
9323 if (!netif_running(bp->dev))
9324 return rc;
9325
9326 /* Repeat the test twice:
9327 First by writing 0x00000000, second by writing 0xffffffff */
9328 for (idx = 0; idx < 2; idx++) {
9329
9330 switch (idx) {
9331 case 0:
9332 wr_val = 0;
9333 break;
9334 case 1:
9335 wr_val = 0xffffffff;
9336 break;
9337 }
9338
9339 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
9340 u32 offset, mask, save_val, val;
9341
9342 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
9343 mask = reg_tbl[i].mask;
9344
9345 save_val = REG_RD(bp, offset);
9346
9347 REG_WR(bp, offset, (wr_val & mask));
9348 val = REG_RD(bp, offset);
9349
9350 /* Restore the original register's value */
9351 REG_WR(bp, offset, save_val);
9352
9353 /* verify value is as expected */
9354 if ((val & mask) != (wr_val & mask)) {
9355 DP(NETIF_MSG_PROBE,
9356 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
9357 offset, val, wr_val, mask);
9358 goto test_reg_exit;
9359 }
9360 }
9361 }
9362
9363 rc = 0;
9364
9365test_reg_exit:
9366 return rc;
9367}
9368
9369static int bnx2x_test_memory(struct bnx2x *bp)
9370{
9371 int i, j, rc = -ENODEV;
9372 u32 val;
9373 static const struct {
9374 u32 offset;
9375 int size;
9376 } mem_tbl[] = {
9377 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
9378 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
9379 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
9380 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
9381 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
9382 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
9383 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
9384
9385 { 0xffffffff, 0 }
9386 };
9387 static const struct {
9388 char *name;
9389 u32 offset;
9390 u32 e1_mask;
9391 u32 e1h_mask;
9392 } prty_tbl[] = {
9393 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0 },
9394 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2 },
9395 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0 },
9396 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0 },
9397 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0 },
9398 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0 },
9399
9400 { NULL, 0xffffffff, 0, 0 }
9401 };
9402
9403 if (!netif_running(bp->dev))
9404 return rc;
9405
9406 /* Go through all the memories */
9407 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
9408 for (j = 0; j < mem_tbl[i].size; j++)
9409 REG_RD(bp, mem_tbl[i].offset + j*4);
9410
9411 /* Check the parity status */
9412 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
9413 val = REG_RD(bp, prty_tbl[i].offset);
9414 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
9415 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask)))) {
9416 DP(NETIF_MSG_HW,
9417 "%s is 0x%x\n", prty_tbl[i].name, val);
9418 goto test_mem_exit;
9419 }
9420 }
9421
9422 rc = 0;
9423
9424test_mem_exit:
9425 return rc;
9426}
9427
9428static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up)
9429{
9430 int cnt = 1000;
9431
9432 if (link_up)
9433 while (bnx2x_link_test(bp) && cnt--)
9434 msleep(10);
9435}
9436
9437static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
9438{
9439 unsigned int pkt_size, num_pkts, i;
9440 struct sk_buff *skb;
9441 unsigned char *packet;
9442 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
9443 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
9444 u16 tx_start_idx, tx_idx;
9445 u16 rx_start_idx, rx_idx;
9446 u16 pkt_prod, bd_prod;
9447 struct sw_tx_bd *tx_buf;
9448 struct eth_tx_start_bd *tx_start_bd;
9449 struct eth_tx_parse_bd *pbd = NULL;
9450 dma_addr_t mapping;
9451 union eth_rx_cqe *cqe;
9452 u8 cqe_fp_flags;
9453 struct sw_rx_bd *rx_buf;
9454 u16 len;
9455 int rc = -ENODEV;
9456
9457 /* check the loopback mode */
9458 switch (loopback_mode) {
9459 case BNX2X_PHY_LOOPBACK:
9460 if (bp->link_params.loopback_mode != LOOPBACK_XGXS_10)
9461 return -EINVAL;
9462 break;
9463 case BNX2X_MAC_LOOPBACK:
9464 bp->link_params.loopback_mode = LOOPBACK_BMAC;
9465 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
9466 break;
9467 default:
9468 return -EINVAL;
9469 }
9470
9471 /* prepare the loopback packet */
9472 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
9473 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
9474 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
9475 if (!skb) {
9476 rc = -ENOMEM;
9477 goto test_loopback_exit;
9478 }
9479 packet = skb_put(skb, pkt_size);
9480 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
9481 memset(packet + ETH_ALEN, 0, ETH_ALEN);
9482 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
9483 for (i = ETH_HLEN; i < pkt_size; i++)
9484 packet[i] = (unsigned char) (i & 0xff);
9485
9486 /* send the loopback packet */
9487 num_pkts = 0;
9488 tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
9489 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
9490
9491 pkt_prod = fp_tx->tx_pkt_prod++;
9492 tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
9493 tx_buf->first_bd = fp_tx->tx_bd_prod;
9494 tx_buf->skb = skb;
9495 tx_buf->flags = 0;
9496
9497 bd_prod = TX_BD(fp_tx->tx_bd_prod);
9498 tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
9499 mapping = dma_map_single(&bp->pdev->dev, skb->data,
9500 skb_headlen(skb), DMA_TO_DEVICE);
9501 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
9502 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9503 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
9504 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
9505 tx_start_bd->vlan = cpu_to_le16(pkt_prod);
9506 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
9507 tx_start_bd->general_data = ((UNICAST_ADDRESS <<
9508 ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT) | 1);
9509
9510 /* turn on parsing and get a BD */
9511 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9512 pbd = &fp_tx->tx_desc_ring[bd_prod].parse_bd;
9513
9514 memset(pbd, 0, sizeof(struct eth_tx_parse_bd));
9515
9516 wmb();
9517
9518 fp_tx->tx_db.data.prod += 2;
9519 barrier();
9520 DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
9521
9522 mmiowb();
9523
9524 num_pkts++;
9525 fp_tx->tx_bd_prod += 2; /* start + pbd */
9526
9527 udelay(100);
9528
9529 tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
9530 if (tx_idx != tx_start_idx + num_pkts)
9531 goto test_loopback_exit;
9532
9533 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
9534 if (rx_idx != rx_start_idx + num_pkts)
9535 goto test_loopback_exit;
9536
9537 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
9538 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
9539 if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
9540 goto test_loopback_rx_exit;
9541
9542 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
9543 if (len != pkt_size)
9544 goto test_loopback_rx_exit;
9545
9546 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
9547 skb = rx_buf->skb;
9548 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
9549 for (i = ETH_HLEN; i < pkt_size; i++)
9550 if (*(skb->data + i) != (unsigned char) (i & 0xff))
9551 goto test_loopback_rx_exit;
9552
9553 rc = 0;
9554
9555test_loopback_rx_exit:
9556
9557 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
9558 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
9559 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
9560 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
9561
9562 /* Update producers */
9563 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
9564 fp_rx->rx_sge_prod);
9565
9566test_loopback_exit:
9567 bp->link_params.loopback_mode = LOOPBACK_NONE;
9568
9569 return rc;
9570}
9571
9572static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
9573{
9574 int rc = 0, res;
9575
9576 if (BP_NOMCP(bp))
9577 return rc;
9578
9579 if (!netif_running(bp->dev))
9580 return BNX2X_LOOPBACK_FAILED;
9581
9582 bnx2x_netif_stop(bp, 1);
9583 bnx2x_acquire_phy_lock(bp);
9584
9585 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
9586 if (res) {
9587 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
9588 rc |= BNX2X_PHY_LOOPBACK_FAILED;
9589 }
9590
9591 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
9592 if (res) {
9593 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
9594 rc |= BNX2X_MAC_LOOPBACK_FAILED;
9595 }
9596
9597 bnx2x_release_phy_lock(bp);
9598 bnx2x_netif_start(bp);
9599
9600 return rc;
9601}
9602
9603#define CRC32_RESIDUAL 0xdebb20e3
9604
9605static int bnx2x_test_nvram(struct bnx2x *bp)
9606{
9607 static const struct {
9608 int offset;
9609 int size;
9610 } nvram_tbl[] = {
9611 { 0, 0x14 }, /* bootstrap */
9612 { 0x14, 0xec }, /* dir */
9613 { 0x100, 0x350 }, /* manuf_info */
9614 { 0x450, 0xf0 }, /* feature_info */
9615 { 0x640, 0x64 }, /* upgrade_key_info */
9616 { 0x6a4, 0x64 },
9617 { 0x708, 0x70 }, /* manuf_key_info */
9618 { 0x778, 0x70 },
9619 { 0, 0 }
9620 };
9621 __be32 buf[0x350 / 4];
9622 u8 *data = (u8 *)buf;
9623 int i, rc;
9624 u32 magic, crc;
9625
9626 if (BP_NOMCP(bp))
9627 return 0;
9628
9629 rc = bnx2x_nvram_read(bp, 0, data, 4);
9630 if (rc) {
9631 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
9632 goto test_nvram_exit;
9633 }
9634
9635 magic = be32_to_cpu(buf[0]);
9636 if (magic != 0x669955aa) {
9637 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
9638 rc = -ENODEV;
9639 goto test_nvram_exit;
9640 }
9641
9642 for (i = 0; nvram_tbl[i].size; i++) {
9643
9644 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
9645 nvram_tbl[i].size);
9646 if (rc) {
9647 DP(NETIF_MSG_PROBE,
9648 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
9649 goto test_nvram_exit;
9650 }
9651
9652 crc = ether_crc_le(nvram_tbl[i].size, data);
9653 if (crc != CRC32_RESIDUAL) {
9654 DP(NETIF_MSG_PROBE,
9655 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
9656 rc = -ENODEV;
9657 goto test_nvram_exit;
9658 }
9659 }
9660
9661test_nvram_exit:
9662 return rc;
9663}
9664
9665static int bnx2x_test_intr(struct bnx2x *bp)
9666{
9667 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
9668 int i, rc;
9669
9670 if (!netif_running(bp->dev))
9671 return -ENODEV;
9672
9673 config->hdr.length = 0;
9674 if (CHIP_IS_E1(bp))
9675 /* use last unicast entries */
9676 config->hdr.offset = (BP_PORT(bp) ? 63 : 31);
9677 else
9678 config->hdr.offset = BP_FUNC(bp);
9679 config->hdr.client_id = bp->fp->cl_id;
9680 config->hdr.reserved1 = 0;
9681
9682 bp->set_mac_pending++;
9683 smp_wmb();
9684 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
9685 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
9686 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
9687 if (rc == 0) {
9688 for (i = 0; i < 10; i++) {
9689 if (!bp->set_mac_pending)
9690 break;
9691 smp_rmb();
9692 msleep_interruptible(10);
9693 }
9694 if (i == 10)
9695 rc = -ENODEV;
9696 }
9697
9698 return rc;
9699}
9700
9701static void bnx2x_self_test(struct net_device *dev,
9702 struct ethtool_test *etest, u64 *buf)
9703{
9704 struct bnx2x *bp = netdev_priv(dev);
9705
9706 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
9707 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
9708 etest->flags |= ETH_TEST_FL_FAILED;
9709 return;
9710 }
9711
9712 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
9713
9714 if (!netif_running(dev))
9715 return;
9716
9717 /* offline tests are not supported in MF mode */
9718 if (IS_E1HMF(bp))
9719 etest->flags &= ~ETH_TEST_FL_OFFLINE;
9720
9721 if (etest->flags & ETH_TEST_FL_OFFLINE) {
9722 int port = BP_PORT(bp);
9723 u32 val;
9724 u8 link_up;
9725
9726 /* save current value of input enable for TX port IF */
9727 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
9728 /* disable input for TX port IF */
9729 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
9730
9731 link_up = (bnx2x_link_test(bp) == 0);
9732 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
9733 bnx2x_nic_load(bp, LOAD_DIAG);
9734 /* wait until link state is restored */
9735 bnx2x_wait_for_link(bp, link_up);
9736
9737 if (bnx2x_test_registers(bp) != 0) {
9738 buf[0] = 1;
9739 etest->flags |= ETH_TEST_FL_FAILED;
9740 }
9741 if (bnx2x_test_memory(bp) != 0) {
9742 buf[1] = 1;
9743 etest->flags |= ETH_TEST_FL_FAILED;
9744 }
9745 buf[2] = bnx2x_test_loopback(bp, link_up);
9746 if (buf[2] != 0)
9747 etest->flags |= ETH_TEST_FL_FAILED;
9748
9749 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
9750
9751 /* restore input for TX port IF */
9752 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
9753
9754 bnx2x_nic_load(bp, LOAD_NORMAL);
9755 /* wait until link state is restored */
9756 bnx2x_wait_for_link(bp, link_up);
9757 }
9758 if (bnx2x_test_nvram(bp) != 0) {
9759 buf[3] = 1;
9760 etest->flags |= ETH_TEST_FL_FAILED;
9761 }
9762 if (bnx2x_test_intr(bp) != 0) {
9763 buf[4] = 1;
9764 etest->flags |= ETH_TEST_FL_FAILED;
9765 }
9766 if (bp->port.pmf)
9767 if (bnx2x_link_test(bp) != 0) {
9768 buf[5] = 1;
9769 etest->flags |= ETH_TEST_FL_FAILED;
9770 }
9771
9772#ifdef BNX2X_EXTRA_DEBUG
9773 bnx2x_panic_dump(bp);
9774#endif
9775}
9776
9777static const struct {
9778 long offset;
9779 int size;
9780 u8 string[ETH_GSTRING_LEN];
9781} bnx2x_q_stats_arr[BNX2X_NUM_Q_STATS] = {
9782/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%d]: rx_bytes" },
9783 { Q_STATS_OFFSET32(error_bytes_received_hi),
9784 8, "[%d]: rx_error_bytes" },
9785 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
9786 8, "[%d]: rx_ucast_packets" },
9787 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
9788 8, "[%d]: rx_mcast_packets" },
9789 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
9790 8, "[%d]: rx_bcast_packets" },
9791 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%d]: rx_discards" },
9792 { Q_STATS_OFFSET32(rx_err_discard_pkt),
9793 4, "[%d]: rx_phy_ip_err_discards"},
9794 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
9795 4, "[%d]: rx_skb_alloc_discard" },
9796 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%d]: rx_csum_offload_errors" },
9797
9798/* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%d]: tx_bytes" },
9799 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
9800 8, "[%d]: tx_ucast_packets" },
9801 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
9802 8, "[%d]: tx_mcast_packets" },
9803 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
9804 8, "[%d]: tx_bcast_packets" }
9805};
9806
9807static const struct {
9808 long offset;
9809 int size;
9810 u32 flags;
9811#define STATS_FLAGS_PORT 1
9812#define STATS_FLAGS_FUNC 2
9813#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
9814 u8 string[ETH_GSTRING_LEN];
9815} bnx2x_stats_arr[BNX2X_NUM_STATS] = {
9816/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
9817 8, STATS_FLAGS_BOTH, "rx_bytes" },
9818 { STATS_OFFSET32(error_bytes_received_hi),
9819 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
9820 { STATS_OFFSET32(total_unicast_packets_received_hi),
9821 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
9822 { STATS_OFFSET32(total_multicast_packets_received_hi),
9823 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
9824 { STATS_OFFSET32(total_broadcast_packets_received_hi),
9825 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
9826 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
9827 8, STATS_FLAGS_PORT, "rx_crc_errors" },
9828 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
9829 8, STATS_FLAGS_PORT, "rx_align_errors" },
9830 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
9831 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
9832 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
9833 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
9834/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
9835 8, STATS_FLAGS_PORT, "rx_fragments" },
9836 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
9837 8, STATS_FLAGS_PORT, "rx_jabbers" },
9838 { STATS_OFFSET32(no_buff_discard_hi),
9839 8, STATS_FLAGS_BOTH, "rx_discards" },
9840 { STATS_OFFSET32(mac_filter_discard),
9841 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
9842 { STATS_OFFSET32(xxoverflow_discard),
9843 4, STATS_FLAGS_PORT, "rx_fw_discards" },
9844 { STATS_OFFSET32(brb_drop_hi),
9845 8, STATS_FLAGS_PORT, "rx_brb_discard" },
9846 { STATS_OFFSET32(brb_truncate_hi),
9847 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
9848 { STATS_OFFSET32(pause_frames_received_hi),
9849 8, STATS_FLAGS_PORT, "rx_pause_frames" },
9850 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
9851 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
9852 { STATS_OFFSET32(nig_timer_max),
9853 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
9854/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
9855 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
9856 { STATS_OFFSET32(rx_skb_alloc_failed),
9857 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
9858 { STATS_OFFSET32(hw_csum_err),
9859 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
9860
9861 { STATS_OFFSET32(total_bytes_transmitted_hi),
9862 8, STATS_FLAGS_BOTH, "tx_bytes" },
9863 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
9864 8, STATS_FLAGS_PORT, "tx_error_bytes" },
9865 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
9866 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
9867 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
9868 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
9869 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
9870 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
9871 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
9872 8, STATS_FLAGS_PORT, "tx_mac_errors" },
9873 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
9874 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
9875/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
9876 8, STATS_FLAGS_PORT, "tx_single_collisions" },
9877 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
9878 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
9879 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
9880 8, STATS_FLAGS_PORT, "tx_deferred" },
9881 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
9882 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
9883 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
9884 8, STATS_FLAGS_PORT, "tx_late_collisions" },
9885 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
9886 8, STATS_FLAGS_PORT, "tx_total_collisions" },
9887 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
9888 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
9889 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
9890 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
9891 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
9892 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
9893 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
9894 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
9895/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
9896 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
9897 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
9898 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
9899 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
9900 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
9901 { STATS_OFFSET32(pause_frames_sent_hi),
9902 8, STATS_FLAGS_PORT, "tx_pause_frames" }
9903};
9904
9905#define IS_PORT_STAT(i) \
9906 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
9907#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
9908#define IS_E1HMF_MODE_STAT(bp) \
9909 (IS_E1HMF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
9910
9911static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
9912{
9913 struct bnx2x *bp = netdev_priv(dev);
9914 int i, num_stats;
9915
9916 switch (stringset) {
9917 case ETH_SS_STATS:
9918 if (is_multi(bp)) {
9919 num_stats = BNX2X_NUM_Q_STATS * bp->num_queues;
9920 if (!IS_E1HMF_MODE_STAT(bp))
9921 num_stats += BNX2X_NUM_STATS;
9922 } else {
9923 if (IS_E1HMF_MODE_STAT(bp)) {
9924 num_stats = 0;
9925 for (i = 0; i < BNX2X_NUM_STATS; i++)
9926 if (IS_FUNC_STAT(i))
9927 num_stats++;
9928 } else
9929 num_stats = BNX2X_NUM_STATS;
9930 }
9931 return num_stats;
9932
9933 case ETH_SS_TEST:
9934 return BNX2X_NUM_TESTS;
9935
9936 default:
9937 return -EINVAL;
9938 }
9939}
9940
9941static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
9942{
9943 struct bnx2x *bp = netdev_priv(dev);
9944 int i, j, k;
9945
9946 switch (stringset) {
9947 case ETH_SS_STATS:
9948 if (is_multi(bp)) {
9949 k = 0;
9950 for_each_queue(bp, i) {
9951 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
9952 sprintf(buf + (k + j)*ETH_GSTRING_LEN,
9953 bnx2x_q_stats_arr[j].string, i);
9954 k += BNX2X_NUM_Q_STATS;
9955 }
9956 if (IS_E1HMF_MODE_STAT(bp))
9957 break;
9958 for (j = 0; j < BNX2X_NUM_STATS; j++)
9959 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
9960 bnx2x_stats_arr[j].string);
9961 } else {
9962 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
9963 if (IS_E1HMF_MODE_STAT(bp) && IS_PORT_STAT(i))
9964 continue;
9965 strcpy(buf + j*ETH_GSTRING_LEN,
9966 bnx2x_stats_arr[i].string);
9967 j++;
9968 }
9969 }
9970 break;
9971
9972 case ETH_SS_TEST:
9973 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
9974 break;
9975 }
9976}
9977
9978static void bnx2x_get_ethtool_stats(struct net_device *dev,
9979 struct ethtool_stats *stats, u64 *buf)
9980{
9981 struct bnx2x *bp = netdev_priv(dev);
9982 u32 *hw_stats, *offset;
9983 int i, j, k;
9984
9985 if (is_multi(bp)) {
9986 k = 0;
9987 for_each_queue(bp, i) {
9988 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
9989 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
9990 if (bnx2x_q_stats_arr[j].size == 0) {
9991 /* skip this counter */
9992 buf[k + j] = 0;
9993 continue;
9994 }
9995 offset = (hw_stats +
9996 bnx2x_q_stats_arr[j].offset);
9997 if (bnx2x_q_stats_arr[j].size == 4) {
9998 /* 4-byte counter */
9999 buf[k + j] = (u64) *offset;
10000 continue;
10001 }
10002 /* 8-byte counter */
10003 buf[k + j] = HILO_U64(*offset, *(offset + 1));
10004 }
10005 k += BNX2X_NUM_Q_STATS;
10006 }
10007 if (IS_E1HMF_MODE_STAT(bp))
10008 return;
10009 hw_stats = (u32 *)&bp->eth_stats;
10010 for (j = 0; j < BNX2X_NUM_STATS; j++) {
10011 if (bnx2x_stats_arr[j].size == 0) {
10012 /* skip this counter */
10013 buf[k + j] = 0;
10014 continue;
10015 }
10016 offset = (hw_stats + bnx2x_stats_arr[j].offset);
10017 if (bnx2x_stats_arr[j].size == 4) {
10018 /* 4-byte counter */
10019 buf[k + j] = (u64) *offset;
10020 continue;
10021 }
10022 /* 8-byte counter */
10023 buf[k + j] = HILO_U64(*offset, *(offset + 1));
10024 }
10025 } else {
10026 hw_stats = (u32 *)&bp->eth_stats;
10027 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
10028 if (IS_E1HMF_MODE_STAT(bp) && IS_PORT_STAT(i))
10029 continue;
10030 if (bnx2x_stats_arr[i].size == 0) {
10031 /* skip this counter */
10032 buf[j] = 0;
10033 j++;
10034 continue;
10035 }
10036 offset = (hw_stats + bnx2x_stats_arr[i].offset);
10037 if (bnx2x_stats_arr[i].size == 4) {
10038 /* 4-byte counter */
10039 buf[j] = (u64) *offset;
10040 j++;
10041 continue;
10042 }
10043 /* 8-byte counter */
10044 buf[j] = HILO_U64(*offset, *(offset + 1));
10045 j++;
10046 }
10047 }
10048}
10049
10050static int bnx2x_phys_id(struct net_device *dev, u32 data)
10051{
10052 struct bnx2x *bp = netdev_priv(dev);
10053 int i;
10054
10055 if (!netif_running(dev))
10056 return 0;
10057
10058 if (!bp->port.pmf)
10059 return 0;
10060
10061 if (data == 0)
10062 data = 2;
10063
10064 for (i = 0; i < (data * 2); i++) {
10065 if ((i % 2) == 0)
10066 bnx2x_set_led(&bp->link_params, LED_MODE_OPER,
10067 SPEED_1000);
10068 else
10069 bnx2x_set_led(&bp->link_params, LED_MODE_OFF, 0);
10070
10071 msleep_interruptible(500);
10072 if (signal_pending(current))
10073 break;
10074 }
10075
10076 if (bp->link_vars.link_up)
10077 bnx2x_set_led(&bp->link_params, LED_MODE_OPER,
10078 bp->link_vars.line_speed);
10079
10080 return 0;
10081}
10082
10083static const struct ethtool_ops bnx2x_ethtool_ops = {
10084 .get_settings = bnx2x_get_settings,
10085 .set_settings = bnx2x_set_settings,
10086 .get_drvinfo = bnx2x_get_drvinfo,
10087 .get_regs_len = bnx2x_get_regs_len,
10088 .get_regs = bnx2x_get_regs,
10089 .get_wol = bnx2x_get_wol,
10090 .set_wol = bnx2x_set_wol,
10091 .get_msglevel = bnx2x_get_msglevel,
10092 .set_msglevel = bnx2x_set_msglevel,
10093 .nway_reset = bnx2x_nway_reset,
10094 .get_link = bnx2x_get_link,
10095 .get_eeprom_len = bnx2x_get_eeprom_len,
10096 .get_eeprom = bnx2x_get_eeprom,
10097 .set_eeprom = bnx2x_set_eeprom,
10098 .get_coalesce = bnx2x_get_coalesce,
10099 .set_coalesce = bnx2x_set_coalesce,
10100 .get_ringparam = bnx2x_get_ringparam,
10101 .set_ringparam = bnx2x_set_ringparam,
10102 .get_pauseparam = bnx2x_get_pauseparam,
10103 .set_pauseparam = bnx2x_set_pauseparam,
10104 .get_rx_csum = bnx2x_get_rx_csum,
10105 .set_rx_csum = bnx2x_set_rx_csum,
10106 .get_tx_csum = ethtool_op_get_tx_csum,
10107 .set_tx_csum = ethtool_op_set_tx_hw_csum,
10108 .set_flags = bnx2x_set_flags,
10109 .get_flags = ethtool_op_get_flags,
10110 .get_sg = ethtool_op_get_sg,
10111 .set_sg = ethtool_op_set_sg,
10112 .get_tso = ethtool_op_get_tso,
10113 .set_tso = bnx2x_set_tso,
10114 .self_test = bnx2x_self_test,
10115 .get_sset_count = bnx2x_get_sset_count,
10116 .get_strings = bnx2x_get_strings,
10117 .phys_id = bnx2x_phys_id,
10118 .get_ethtool_stats = bnx2x_get_ethtool_stats,
10119};
10120
10121/* end of ethtool_ops */
10122 8169
8170/****************************************************************************
8171* General service functions
8172****************************************************************************/
10123 8173
10124/* called with rtnl_lock */ 8174/* called with rtnl_lock */
10125static int bnx2x_open(struct net_device *dev) 8175static int bnx2x_open(struct net_device *dev)
@@ -10523,7 +8573,7 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10523 dev->watchdog_timeo = TX_TIMEOUT; 8573 dev->watchdog_timeo = TX_TIMEOUT;
10524 8574
10525 dev->netdev_ops = &bnx2x_netdev_ops; 8575 dev->netdev_ops = &bnx2x_netdev_ops;
10526 dev->ethtool_ops = &bnx2x_ethtool_ops; 8576 bnx2x_set_ethtool_ops(dev);
10527 dev->features |= NETIF_F_SG; 8577 dev->features |= NETIF_F_SG;
10528 dev->features |= NETIF_F_HW_CSUM; 8578 dev->features |= NETIF_F_HW_CSUM;
10529 if (bp->flags & USING_DAC_FLAG) 8579 if (bp->flags & USING_DAC_FLAG)
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-06 23:20:07 -0500