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Diffstat (limited to 'drivers/net/bnx2x/bnx2x_link.h')
-rw-r--r--drivers/net/bnx2x/bnx2x_link.h59
1 files changed, 49 insertions, 10 deletions
diff --git a/drivers/net/bnx2x/bnx2x_link.h b/drivers/net/bnx2x/bnx2x_link.h
index 40c2981de8ed..9bfe7fa452bc 100644
--- a/drivers/net/bnx2x/bnx2x_link.h
+++ b/drivers/net/bnx2x/bnx2x_link.h
@@ -1,4 +1,4 @@
1/* Copyright 2008-2009 Broadcom Corporation 1/* Copyright 2008-2010 Broadcom Corporation
2 * 2 *
3 * Unless you and Broadcom execute a separate written software license 3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you 4 * agreement governing use of this software, this software is licensed to you
@@ -46,9 +46,35 @@
46#define SFP_EEPROM_PART_NO_ADDR 0x28 46#define SFP_EEPROM_PART_NO_ADDR 0x28
47#define SFP_EEPROM_PART_NO_SIZE 16 47#define SFP_EEPROM_PART_NO_SIZE 16
48#define PWR_FLT_ERR_MSG_LEN 250 48#define PWR_FLT_ERR_MSG_LEN 250
49/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
50#define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
51/* Single Media board contains single external phy */
52#define SINGLE_MEDIA(params) (params->num_phys == 2)
49/***********************************************************/ 53/***********************************************************/
50/* Structs */ 54/* Structs */
51/***********************************************************/ 55/***********************************************************/
56#define INT_PHY 0
57#define EXT_PHY1 1
58
59#define MAX_PHYS 2
60
61/***********************************************************/
62/* bnx2x_phy struct */
63/* Defines the required arguments and function per phy */
64/***********************************************************/
65struct link_vars;
66struct link_params;
67struct bnx2x_phy;
68
69struct bnx2x_phy {
70 u32 type;
71
72 /* Loaded during init */
73 u8 addr;
74
75 u32 mdio_ctrl;
76};
77
52/* Inputs parameters to the CLC */ 78/* Inputs parameters to the CLC */
53struct link_params { 79struct link_params {
54 80
@@ -106,6 +132,11 @@ struct link_params {
106#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0) 132#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
107#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2) 133#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
108#define FEATURE_CONFIG_BCM8727_NOC (1<<3) 134#define FEATURE_CONFIG_BCM8727_NOC (1<<3)
135 /* Will be populated during common init */
136 struct bnx2x_phy phy[MAX_PHYS];
137
138 /* Will be populated during common init */
139 u8 num_phys;
109 140
110 /* Device pointer passed to all callback functions */ 141 /* Device pointer passed to all callback functions */
111 struct bnx2x *bp; 142 struct bnx2x *bp;
@@ -155,17 +186,20 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
155/* bnx2x_link_update should be called upon link interrupt */ 186/* bnx2x_link_update should be called upon link interrupt */
156u8 bnx2x_link_update(struct link_params *input, struct link_vars *output); 187u8 bnx2x_link_update(struct link_params *input, struct link_vars *output);
157 188
158/* use the following cl45 functions to read/write from external_phy 189/* use the following phy functions to read/write from external_phy
159 In order to use it to read/write internal phy registers, use 190 In order to use it to read/write internal phy registers, use
160 DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as 191 DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
161 Use ext_phy_type of 0 in case of cl22 over cl45
162 the register */ 192 the register */
163u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type, 193u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
164 u8 phy_addr, u8 devad, u16 reg, u16 *ret_val); 194 u8 devad, u16 reg, u16 *ret_val);
165 195
166u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type, 196u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
167 u8 phy_addr, u8 devad, u16 reg, u16 val); 197 u8 devad, u16 reg, u16 val);
198u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
199 u8 devad, u16 reg, u16 *ret_val);
168 200
201u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
202 u8 devad, u16 reg, u16 val);
169/* Reads the link_status from the shmem, 203/* Reads the link_status from the shmem,
170 and update the link vars accordingly */ 204 and update the link vars accordingly */
171void bnx2x_link_status_update(struct link_params *input, 205void bnx2x_link_status_update(struct link_params *input,
@@ -198,9 +232,14 @@ u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base);
198/* Reset the external PHY using GPIO */ 232/* Reset the external PHY using GPIO */
199void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port); 233void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
200 234
201void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr); 235/* Reset the external of SFX7101 */
236void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);
202 237
203u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr, 238u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
239 struct link_params *params, u16 addr,
204 u8 byte_cnt, u8 *o_buf); 240 u8 byte_cnt, u8 *o_buf);
205 241/* Returns the aggregative supported attributes of the phys on board */
242u32 bnx2x_supported_attr(struct link_params *params, u8 phy_idx);
243/* Probe the phys on board, and populate them in "params" */
244u8 bnx2x_phy_probe(struct link_params *params);
206#endif /* BNX2X_LINK_H */ 245#endif /* BNX2X_LINK_H */