diff options
Diffstat (limited to 'drivers/net/bnx2x/bnx2x_fw_defs.h')
-rw-r--r-- | drivers/net/bnx2x/bnx2x_fw_defs.h | 594 |
1 files changed, 594 insertions, 0 deletions
diff --git a/drivers/net/bnx2x/bnx2x_fw_defs.h b/drivers/net/bnx2x/bnx2x_fw_defs.h new file mode 100644 index 000000000000..08d71bf438d6 --- /dev/null +++ b/drivers/net/bnx2x/bnx2x_fw_defs.h | |||
@@ -0,0 +1,594 @@ | |||
1 | /* bnx2x_fw_defs.h: Broadcom Everest network driver. | ||
2 | * | ||
3 | * Copyright (c) 2007-2010 Broadcom Corporation | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License as published by | ||
7 | * the Free Software Foundation. | ||
8 | */ | ||
9 | |||
10 | |||
11 | #define CSTORM_ASSERT_LIST_INDEX_OFFSET \ | ||
12 | (IS_E1H_OFFSET ? 0x7000 : 0x1000) | ||
13 | #define CSTORM_ASSERT_LIST_OFFSET(idx) \ | ||
14 | (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) | ||
15 | #define CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(function, index) \ | ||
16 | (IS_E1H_OFFSET ? (0x8622 + ((function>>1) * 0x40) + \ | ||
17 | ((function&1) * 0x100) + (index * 0x4)) : (0x3562 + (function * \ | ||
18 | 0x40) + (index * 0x4))) | ||
19 | #define CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(function, index) \ | ||
20 | (IS_E1H_OFFSET ? (0x8822 + ((function>>1) * 0x80) + \ | ||
21 | ((function&1) * 0x200) + (index * 0x4)) : (0x35e2 + (function * \ | ||
22 | 0x80) + (index * 0x4))) | ||
23 | #define CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(function) \ | ||
24 | (IS_E1H_OFFSET ? (0x8600 + ((function>>1) * 0x40) + \ | ||
25 | ((function&1) * 0x100)) : (0x3540 + (function * 0x40))) | ||
26 | #define CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(function) \ | ||
27 | (IS_E1H_OFFSET ? (0x8800 + ((function>>1) * 0x80) + \ | ||
28 | ((function&1) * 0x200)) : (0x35c0 + (function * 0x80))) | ||
29 | #define CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(function) \ | ||
30 | (IS_E1H_OFFSET ? (0x8608 + ((function>>1) * 0x40) + \ | ||
31 | ((function&1) * 0x100)) : (0x3548 + (function * 0x40))) | ||
32 | #define CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(function) \ | ||
33 | (IS_E1H_OFFSET ? (0x8808 + ((function>>1) * 0x80) + \ | ||
34 | ((function&1) * 0x200)) : (0x35c8 + (function * 0x80))) | ||
35 | #define CSTORM_FUNCTION_MODE_OFFSET \ | ||
36 | (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff) | ||
37 | #define CSTORM_HC_BTR_C_OFFSET(port) \ | ||
38 | (IS_E1H_OFFSET ? (0x8c04 + (port * 0xf0)) : (0x36c4 + (port * 0xc0))) | ||
39 | #define CSTORM_HC_BTR_U_OFFSET(port) \ | ||
40 | (IS_E1H_OFFSET ? (0x8de4 + (port * 0xf0)) : (0x3844 + (port * 0xc0))) | ||
41 | #define CSTORM_ISCSI_CQ_SIZE_OFFSET(function) \ | ||
42 | (IS_E1H_OFFSET ? (0x6680 + (function * 0x8)) : (0x25a0 + \ | ||
43 | (function * 0x8))) | ||
44 | #define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \ | ||
45 | (IS_E1H_OFFSET ? (0x66c0 + (function * 0x8)) : (0x25b0 + \ | ||
46 | (function * 0x8))) | ||
47 | #define CSTORM_ISCSI_EQ_CONS_OFFSET(function, eqIdx) \ | ||
48 | (IS_E1H_OFFSET ? (0x6040 + (function * 0xc0) + (eqIdx * 0x18)) : \ | ||
49 | (0x2410 + (function * 0xc0) + (eqIdx * 0x18))) | ||
50 | #define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(function, eqIdx) \ | ||
51 | (IS_E1H_OFFSET ? (0x6044 + (function * 0xc0) + (eqIdx * 0x18)) : \ | ||
52 | (0x2414 + (function * 0xc0) + (eqIdx * 0x18))) | ||
53 | #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(function, eqIdx) \ | ||
54 | (IS_E1H_OFFSET ? (0x604c + (function * 0xc0) + (eqIdx * 0x18)) : \ | ||
55 | (0x241c + (function * 0xc0) + (eqIdx * 0x18))) | ||
56 | #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(function, eqIdx) \ | ||
57 | (IS_E1H_OFFSET ? (0x6057 + (function * 0xc0) + (eqIdx * 0x18)) : \ | ||
58 | (0x2427 + (function * 0xc0) + (eqIdx * 0x18))) | ||
59 | #define CSTORM_ISCSI_EQ_PROD_OFFSET(function, eqIdx) \ | ||
60 | (IS_E1H_OFFSET ? (0x6042 + (function * 0xc0) + (eqIdx * 0x18)) : \ | ||
61 | (0x2412 + (function * 0xc0) + (eqIdx * 0x18))) | ||
62 | #define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(function, eqIdx) \ | ||
63 | (IS_E1H_OFFSET ? (0x6056 + (function * 0xc0) + (eqIdx * 0x18)) : \ | ||
64 | (0x2426 + (function * 0xc0) + (eqIdx * 0x18))) | ||
65 | #define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(function, eqIdx) \ | ||
66 | (IS_E1H_OFFSET ? (0x6054 + (function * 0xc0) + (eqIdx * 0x18)) : \ | ||
67 | (0x2424 + (function * 0xc0) + (eqIdx * 0x18))) | ||
68 | #define CSTORM_ISCSI_HQ_SIZE_OFFSET(function) \ | ||
69 | (IS_E1H_OFFSET ? (0x6640 + (function * 0x8)) : (0x2590 + \ | ||
70 | (function * 0x8))) | ||
71 | #define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \ | ||
72 | (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x2404 + \ | ||
73 | (function * 0x8))) | ||
74 | #define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \ | ||
75 | (IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x2402 + \ | ||
76 | (function * 0x8))) | ||
77 | #define CSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \ | ||
78 | (IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x2400 + \ | ||
79 | (function * 0x8))) | ||
80 | #define CSTORM_SB_HC_DISABLE_C_OFFSET(port, cpu_id, index) \ | ||
81 | (IS_E1H_OFFSET ? (0x811a + (port * 0x280) + (cpu_id * 0x28) + \ | ||
82 | (index * 0x4)) : (0x305a + (port * 0x280) + (cpu_id * 0x28) + \ | ||
83 | (index * 0x4))) | ||
84 | #define CSTORM_SB_HC_DISABLE_U_OFFSET(port, cpu_id, index) \ | ||
85 | (IS_E1H_OFFSET ? (0xb01a + (port * 0x800) + (cpu_id * 0x80) + \ | ||
86 | (index * 0x4)) : (0x401a + (port * 0x800) + (cpu_id * 0x80) + \ | ||
87 | (index * 0x4))) | ||
88 | #define CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, cpu_id, index) \ | ||
89 | (IS_E1H_OFFSET ? (0x8118 + (port * 0x280) + (cpu_id * 0x28) + \ | ||
90 | (index * 0x4)) : (0x3058 + (port * 0x280) + (cpu_id * 0x28) + \ | ||
91 | (index * 0x4))) | ||
92 | #define CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, cpu_id, index) \ | ||
93 | (IS_E1H_OFFSET ? (0xb018 + (port * 0x800) + (cpu_id * 0x80) + \ | ||
94 | (index * 0x4)) : (0x4018 + (port * 0x800) + (cpu_id * 0x80) + \ | ||
95 | (index * 0x4))) | ||
96 | #define CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, cpu_id) \ | ||
97 | (IS_E1H_OFFSET ? (0x8100 + (port * 0x280) + (cpu_id * 0x28)) : \ | ||
98 | (0x3040 + (port * 0x280) + (cpu_id * 0x28))) | ||
99 | #define CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, cpu_id) \ | ||
100 | (IS_E1H_OFFSET ? (0xb000 + (port * 0x800) + (cpu_id * 0x80)) : \ | ||
101 | (0x4000 + (port * 0x800) + (cpu_id * 0x80))) | ||
102 | #define CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, cpu_id) \ | ||
103 | (IS_E1H_OFFSET ? (0x8108 + (port * 0x280) + (cpu_id * 0x28)) : \ | ||
104 | (0x3048 + (port * 0x280) + (cpu_id * 0x28))) | ||
105 | #define CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, cpu_id) \ | ||
106 | (IS_E1H_OFFSET ? (0xb008 + (port * 0x800) + (cpu_id * 0x80)) : \ | ||
107 | (0x4008 + (port * 0x800) + (cpu_id * 0x80))) | ||
108 | #define CSTORM_SB_STATUS_BLOCK_C_SIZE 0x10 | ||
109 | #define CSTORM_SB_STATUS_BLOCK_U_SIZE 0x60 | ||
110 | #define CSTORM_STATS_FLAGS_OFFSET(function) \ | ||
111 | (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \ | ||
112 | (function * 0x8))) | ||
113 | #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \ | ||
114 | (IS_E1H_OFFSET ? (0x3200 + (function * 0x20)) : 0xffffffff) | ||
115 | #define TSTORM_ASSERT_LIST_INDEX_OFFSET \ | ||
116 | (IS_E1H_OFFSET ? 0xa000 : 0x1000) | ||
117 | #define TSTORM_ASSERT_LIST_OFFSET(idx) \ | ||
118 | (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) | ||
119 | #define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \ | ||
120 | (IS_E1H_OFFSET ? (0x33a0 + (port * 0x1a0) + (client_id * 0x10)) \ | ||
121 | : (0x9c0 + (port * 0x120) + (client_id * 0x10))) | ||
122 | #define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \ | ||
123 | (IS_E1H_OFFSET ? 0x1ed8 : 0xffffffff) | ||
124 | #define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \ | ||
125 | (IS_E1H_OFFSET ? 0x1eda : 0xffffffff) | ||
126 | #define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ | ||
127 | (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \ | ||
128 | ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ | ||
129 | 0x28) + (index * 0x4))) | ||
130 | #define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ | ||
131 | (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \ | ||
132 | ((function&1) * 0xa0)) : (0x1400 + (function * 0x28))) | ||
133 | #define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ | ||
134 | (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \ | ||
135 | ((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) | ||
136 | #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ | ||
137 | (IS_E1H_OFFSET ? (0x2940 + (function * 0x8)) : (0x4928 + \ | ||
138 | (function * 0x8))) | ||
139 | #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \ | ||
140 | (IS_E1H_OFFSET ? (0x3000 + (function * 0x40)) : (0x1500 + \ | ||
141 | (function * 0x40))) | ||
142 | #define TSTORM_FUNCTION_MODE_OFFSET \ | ||
143 | (IS_E1H_OFFSET ? 0x1ed0 : 0xffffffff) | ||
144 | #define TSTORM_HC_BTR_OFFSET(port) \ | ||
145 | (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18))) | ||
146 | #define TSTORM_INDIRECTION_TABLE_OFFSET(function) \ | ||
147 | (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \ | ||
148 | (function * 0x80))) | ||
149 | #define TSTORM_INDIRECTION_TABLE_SIZE 0x80 | ||
150 | #define TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(function, pblEntry) \ | ||
151 | (IS_E1H_OFFSET ? (0x60c0 + (function * 0x40) + (pblEntry * 0x8)) \ | ||
152 | : (0x4c30 + (function * 0x40) + (pblEntry * 0x8))) | ||
153 | #define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \ | ||
154 | (IS_E1H_OFFSET ? (0x6340 + (function * 0x8)) : (0x4cd0 + \ | ||
155 | (function * 0x8))) | ||
156 | #define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \ | ||
157 | (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x4c04 + \ | ||
158 | (function * 0x8))) | ||
159 | #define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \ | ||
160 | (IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x4c02 + \ | ||
161 | (function * 0x8))) | ||
162 | #define TSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \ | ||
163 | (IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x4c00 + \ | ||
164 | (function * 0x8))) | ||
165 | #define TSTORM_ISCSI_RQ_SIZE_OFFSET(function) \ | ||
166 | (IS_E1H_OFFSET ? (0x6080 + (function * 0x8)) : (0x4c20 + \ | ||
167 | (function * 0x8))) | ||
168 | #define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \ | ||
169 | (IS_E1H_OFFSET ? (0x6040 + (function * 0x8)) : (0x4c10 + \ | ||
170 | (function * 0x8))) | ||
171 | #define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(function) \ | ||
172 | (IS_E1H_OFFSET ? (0x6042 + (function * 0x8)) : (0x4c12 + \ | ||
173 | (function * 0x8))) | ||
174 | #define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(function) \ | ||
175 | (IS_E1H_OFFSET ? (0x6044 + (function * 0x8)) : (0x4c14 + \ | ||
176 | (function * 0x8))) | ||
177 | #define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \ | ||
178 | (IS_E1H_OFFSET ? (0x3008 + (function * 0x40)) : (0x1508 + \ | ||
179 | (function * 0x40))) | ||
180 | #define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ | ||
181 | (IS_E1H_OFFSET ? (0x2010 + (port * 0x490) + (stats_counter_id * \ | ||
182 | 0x40)) : (0x4010 + (port * 0x490) + (stats_counter_id * 0x40))) | ||
183 | #define TSTORM_STATS_FLAGS_OFFSET(function) \ | ||
184 | (IS_E1H_OFFSET ? (0x29c0 + (function * 0x8)) : (0x4948 + \ | ||
185 | (function * 0x8))) | ||
186 | #define TSTORM_TCP_MAX_CWND_OFFSET(function) \ | ||
187 | (IS_E1H_OFFSET ? (0x4004 + (function * 0x8)) : (0x1fb4 + \ | ||
188 | (function * 0x8))) | ||
189 | #define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa000 : 0x3000) | ||
190 | #define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2000 : 0x1000) | ||
191 | #define USTORM_ASSERT_LIST_INDEX_OFFSET \ | ||
192 | (IS_E1H_OFFSET ? 0x8000 : 0x1000) | ||
193 | #define USTORM_ASSERT_LIST_OFFSET(idx) \ | ||
194 | (IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) | ||
195 | #define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \ | ||
196 | (IS_E1H_OFFSET ? (0x1010 + (port * 0x680) + (clientId * 0x40)) : \ | ||
197 | (0x4010 + (port * 0x360) + (clientId * 0x30))) | ||
198 | #define USTORM_CQE_PAGE_NEXT_OFFSET(port, clientId) \ | ||
199 | (IS_E1H_OFFSET ? (0x1028 + (port * 0x680) + (clientId * 0x40)) : \ | ||
200 | (0x4028 + (port * 0x360) + (clientId * 0x30))) | ||
201 | #define USTORM_ETH_PAUSE_ENABLED_OFFSET(port) \ | ||
202 | (IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff) | ||
203 | #define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \ | ||
204 | (IS_E1H_OFFSET ? (0x1030 + (port * 0x680) + (clientId * 0x40)) : \ | ||
205 | 0xffffffff) | ||
206 | #define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ | ||
207 | (IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1dd0 + \ | ||
208 | (function * 0x8))) | ||
209 | #define USTORM_FUNCTION_MODE_OFFSET \ | ||
210 | (IS_E1H_OFFSET ? 0x2448 : 0xffffffff) | ||
211 | #define USTORM_ISCSI_CQ_SIZE_OFFSET(function) \ | ||
212 | (IS_E1H_OFFSET ? (0x7044 + (function * 0x8)) : (0x2414 + \ | ||
213 | (function * 0x8))) | ||
214 | #define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \ | ||
215 | (IS_E1H_OFFSET ? (0x7046 + (function * 0x8)) : (0x2416 + \ | ||
216 | (function * 0x8))) | ||
217 | #define USTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \ | ||
218 | (IS_E1H_OFFSET ? (0x7688 + (function * 0x8)) : (0x29c8 + \ | ||
219 | (function * 0x8))) | ||
220 | #define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(function) \ | ||
221 | (IS_E1H_OFFSET ? (0x7648 + (function * 0x8)) : (0x29b8 + \ | ||
222 | (function * 0x8))) | ||
223 | #define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \ | ||
224 | (IS_E1H_OFFSET ? (0x7004 + (function * 0x8)) : (0x2404 + \ | ||
225 | (function * 0x8))) | ||
226 | #define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \ | ||
227 | (IS_E1H_OFFSET ? (0x7002 + (function * 0x8)) : (0x2402 + \ | ||
228 | (function * 0x8))) | ||
229 | #define USTORM_ISCSI_PAGE_SIZE_OFFSET(function) \ | ||
230 | (IS_E1H_OFFSET ? (0x7000 + (function * 0x8)) : (0x2400 + \ | ||
231 | (function * 0x8))) | ||
232 | #define USTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \ | ||
233 | (IS_E1H_OFFSET ? (0x7040 + (function * 0x8)) : (0x2410 + \ | ||
234 | (function * 0x8))) | ||
235 | #define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(function) \ | ||
236 | (IS_E1H_OFFSET ? (0x7080 + (function * 0x8)) : (0x2420 + \ | ||
237 | (function * 0x8))) | ||
238 | #define USTORM_ISCSI_RQ_SIZE_OFFSET(function) \ | ||
239 | (IS_E1H_OFFSET ? (0x7084 + (function * 0x8)) : (0x2424 + \ | ||
240 | (function * 0x8))) | ||
241 | #define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \ | ||
242 | (IS_E1H_OFFSET ? (0x1018 + (port * 0x680) + (clientId * 0x40)) : \ | ||
243 | (0x4018 + (port * 0x360) + (clientId * 0x30))) | ||
244 | #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \ | ||
245 | (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x1da8 + \ | ||
246 | (function * 0x8))) | ||
247 | #define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ | ||
248 | (IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \ | ||
249 | 0x28)) : (0x1500 + (port * 0x2d0) + (stats_counter_id * 0x28))) | ||
250 | #define USTORM_RX_PRODS_OFFSET(port, client_id) \ | ||
251 | (IS_E1H_OFFSET ? (0x1000 + (port * 0x680) + (client_id * 0x40)) \ | ||
252 | : (0x4000 + (port * 0x360) + (client_id * 0x30))) | ||
253 | #define USTORM_STATS_FLAGS_OFFSET(function) \ | ||
254 | (IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1db8 + \ | ||
255 | (function * 0x8))) | ||
256 | #define USTORM_TPA_BTR_OFFSET (IS_E1H_OFFSET ? 0x3da5 : 0x5095) | ||
257 | #define USTORM_TPA_BTR_SIZE 0x1 | ||
258 | #define XSTORM_ASSERT_LIST_INDEX_OFFSET \ | ||
259 | (IS_E1H_OFFSET ? 0x9000 : 0x1000) | ||
260 | #define XSTORM_ASSERT_LIST_OFFSET(idx) \ | ||
261 | (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) | ||
262 | #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \ | ||
263 | (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3a80 + (port * 0x50))) | ||
264 | #define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ | ||
265 | (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \ | ||
266 | ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ | ||
267 | 0x28) + (index * 0x4))) | ||
268 | #define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ | ||
269 | (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \ | ||
270 | ((function&1) * 0xa0)) : (0x1400 + (function * 0x28))) | ||
271 | #define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ | ||
272 | (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \ | ||
273 | ((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) | ||
274 | #define XSTORM_E1HOV_OFFSET(function) \ | ||
275 | (IS_E1H_OFFSET ? (0x2c10 + (function * 0x8)) : 0xffffffff) | ||
276 | #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ | ||
277 | (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3a50 + \ | ||
278 | (function * 0x8))) | ||
279 | #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \ | ||
280 | (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3b60 + \ | ||
281 | (function * 0x90))) | ||
282 | #define XSTORM_FUNCTION_MODE_OFFSET \ | ||
283 | (IS_E1H_OFFSET ? 0x2c50 : 0xffffffff) | ||
284 | #define XSTORM_HC_BTR_OFFSET(port) \ | ||
285 | (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18))) | ||
286 | #define XSTORM_ISCSI_HQ_SIZE_OFFSET(function) \ | ||
287 | (IS_E1H_OFFSET ? (0x80c0 + (function * 0x8)) : (0x1c30 + \ | ||
288 | (function * 0x8))) | ||
289 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(function) \ | ||
290 | (IS_E1H_OFFSET ? (0x8080 + (function * 0x8)) : (0x1c20 + \ | ||
291 | (function * 0x8))) | ||
292 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(function) \ | ||
293 | (IS_E1H_OFFSET ? (0x8081 + (function * 0x8)) : (0x1c21 + \ | ||
294 | (function * 0x8))) | ||
295 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(function) \ | ||
296 | (IS_E1H_OFFSET ? (0x8082 + (function * 0x8)) : (0x1c22 + \ | ||
297 | (function * 0x8))) | ||
298 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(function) \ | ||
299 | (IS_E1H_OFFSET ? (0x8083 + (function * 0x8)) : (0x1c23 + \ | ||
300 | (function * 0x8))) | ||
301 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(function) \ | ||
302 | (IS_E1H_OFFSET ? (0x8084 + (function * 0x8)) : (0x1c24 + \ | ||
303 | (function * 0x8))) | ||
304 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(function) \ | ||
305 | (IS_E1H_OFFSET ? (0x8085 + (function * 0x8)) : (0x1c25 + \ | ||
306 | (function * 0x8))) | ||
307 | #define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(function) \ | ||
308 | (IS_E1H_OFFSET ? (0x8086 + (function * 0x8)) : (0x1c26 + \ | ||
309 | (function * 0x8))) | ||
310 | #define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \ | ||
311 | (IS_E1H_OFFSET ? (0x8004 + (function * 0x8)) : (0x1c04 + \ | ||
312 | (function * 0x8))) | ||
313 | #define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \ | ||
314 | (IS_E1H_OFFSET ? (0x8002 + (function * 0x8)) : (0x1c02 + \ | ||
315 | (function * 0x8))) | ||
316 | #define XSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \ | ||
317 | (IS_E1H_OFFSET ? (0x8000 + (function * 0x8)) : (0x1c00 + \ | ||
318 | (function * 0x8))) | ||
319 | #define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \ | ||
320 | (IS_E1H_OFFSET ? (0x80c4 + (function * 0x8)) : (0x1c34 + \ | ||
321 | (function * 0x8))) | ||
322 | #define XSTORM_ISCSI_SQ_SIZE_OFFSET(function) \ | ||
323 | (IS_E1H_OFFSET ? (0x80c2 + (function * 0x8)) : (0x1c32 + \ | ||
324 | (function * 0x8))) | ||
325 | #define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(function) \ | ||
326 | (IS_E1H_OFFSET ? (0x8043 + (function * 0x8)) : (0x1c13 + \ | ||
327 | (function * 0x8))) | ||
328 | #define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \ | ||
329 | (IS_E1H_OFFSET ? (0x8042 + (function * 0x8)) : (0x1c12 + \ | ||
330 | (function * 0x8))) | ||
331 | #define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(function) \ | ||
332 | (IS_E1H_OFFSET ? (0x8041 + (function * 0x8)) : (0x1c11 + \ | ||
333 | (function * 0x8))) | ||
334 | #define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(function) \ | ||
335 | (IS_E1H_OFFSET ? (0x8040 + (function * 0x8)) : (0x1c10 + \ | ||
336 | (function * 0x8))) | ||
337 | #define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ | ||
338 | (IS_E1H_OFFSET ? (0xc000 + (port * 0x360) + (stats_counter_id * \ | ||
339 | 0x30)) : (0x3378 + (port * 0x360) + (stats_counter_id * 0x30))) | ||
340 | #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \ | ||
341 | (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3b20 + \ | ||
342 | (function * 0x90))) | ||
343 | #define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \ | ||
344 | (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \ | ||
345 | (function * 0x10))) | ||
346 | #define XSTORM_SPQ_PROD_OFFSET(function) \ | ||
347 | (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \ | ||
348 | (function * 0x10))) | ||
349 | #define XSTORM_STATS_FLAGS_OFFSET(function) \ | ||
350 | (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3a40 + \ | ||
351 | (function * 0x8))) | ||
352 | #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port) \ | ||
353 | (IS_E1H_OFFSET ? (0x4000 + (port * 0x8)) : (0x1960 + (port * 0x8))) | ||
354 | #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port) \ | ||
355 | (IS_E1H_OFFSET ? (0x4001 + (port * 0x8)) : (0x1961 + (port * 0x8))) | ||
356 | #define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(function) \ | ||
357 | (IS_E1H_OFFSET ? (0x4060 + ((function>>1) * 0x8) + ((function&1) \ | ||
358 | * 0x4)) : (0x1978 + (function * 0x4))) | ||
359 | #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 | ||
360 | |||
361 | /** | ||
362 | * This file defines HSI constants for the ETH flow | ||
363 | */ | ||
364 | #ifdef _EVEREST_MICROCODE | ||
365 | #include "microcode_constants.h" | ||
366 | #include "eth_rx_bd.h" | ||
367 | #include "eth_tx_bd.h" | ||
368 | #include "eth_rx_cqe.h" | ||
369 | #include "eth_rx_sge.h" | ||
370 | #include "eth_rx_cqe_next_page.h" | ||
371 | #endif | ||
372 | |||
373 | /* RSS hash types */ | ||
374 | #define DEFAULT_HASH_TYPE 0 | ||
375 | #define IPV4_HASH_TYPE 1 | ||
376 | #define TCP_IPV4_HASH_TYPE 2 | ||
377 | #define IPV6_HASH_TYPE 3 | ||
378 | #define TCP_IPV6_HASH_TYPE 4 | ||
379 | #define VLAN_PRI_HASH_TYPE 5 | ||
380 | #define E1HOV_PRI_HASH_TYPE 6 | ||
381 | #define DSCP_HASH_TYPE 7 | ||
382 | |||
383 | |||
384 | /* Ethernet Ring parameters */ | ||
385 | #define X_ETH_LOCAL_RING_SIZE 13 | ||
386 | #define FIRST_BD_IN_PKT 0 | ||
387 | #define PARSE_BD_INDEX 1 | ||
388 | #define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8)) | ||
389 | #define U_ETH_NUM_OF_SGES_TO_FETCH 8 | ||
390 | #define U_ETH_MAX_SGES_FOR_PACKET 3 | ||
391 | |||
392 | /* Rx ring params */ | ||
393 | #define U_ETH_LOCAL_BD_RING_SIZE 8 | ||
394 | #define U_ETH_LOCAL_SGE_RING_SIZE 10 | ||
395 | #define U_ETH_SGL_SIZE 8 | ||
396 | |||
397 | |||
398 | #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \ | ||
399 | (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1)) | ||
400 | |||
401 | #define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8)) | ||
402 | #define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8)) | ||
403 | #define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8)) | ||
404 | |||
405 | #define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1) | ||
406 | #define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1) | ||
407 | #define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1) | ||
408 | |||
409 | #define U_ETH_UNDEFINED_Q 0xFF | ||
410 | |||
411 | /* values of command IDs in the ramrod message */ | ||
412 | #define RAMROD_CMD_ID_ETH_PORT_SETUP 80 | ||
413 | #define RAMROD_CMD_ID_ETH_CLIENT_SETUP 85 | ||
414 | #define RAMROD_CMD_ID_ETH_STAT_QUERY 90 | ||
415 | #define RAMROD_CMD_ID_ETH_UPDATE 100 | ||
416 | #define RAMROD_CMD_ID_ETH_HALT 105 | ||
417 | #define RAMROD_CMD_ID_ETH_SET_MAC 110 | ||
418 | #define RAMROD_CMD_ID_ETH_CFC_DEL 115 | ||
419 | #define RAMROD_CMD_ID_ETH_PORT_DEL 120 | ||
420 | #define RAMROD_CMD_ID_ETH_FORWARD_SETUP 125 | ||
421 | |||
422 | |||
423 | /* command values for set mac command */ | ||
424 | #define T_ETH_MAC_COMMAND_SET 0 | ||
425 | #define T_ETH_MAC_COMMAND_INVALIDATE 1 | ||
426 | |||
427 | #define T_ETH_INDIRECTION_TABLE_SIZE 128 | ||
428 | |||
429 | /*The CRC32 seed, that is used for the hash(reduction) multicast address */ | ||
430 | #define T_ETH_CRC32_HASH_SEED 0x00000000 | ||
431 | |||
432 | /* Maximal L2 clients supported */ | ||
433 | #define ETH_MAX_RX_CLIENTS_E1 18 | ||
434 | #define ETH_MAX_RX_CLIENTS_E1H 26 | ||
435 | |||
436 | /* Maximal aggregation queues supported */ | ||
437 | #define ETH_MAX_AGGREGATION_QUEUES_E1 32 | ||
438 | #define ETH_MAX_AGGREGATION_QUEUES_E1H 64 | ||
439 | |||
440 | /* ETH RSS modes */ | ||
441 | #define ETH_RSS_MODE_DISABLED 0 | ||
442 | #define ETH_RSS_MODE_REGULAR 1 | ||
443 | #define ETH_RSS_MODE_VLAN_PRI 2 | ||
444 | #define ETH_RSS_MODE_E1HOV_PRI 3 | ||
445 | #define ETH_RSS_MODE_IP_DSCP 4 | ||
446 | |||
447 | |||
448 | /** | ||
449 | * This file defines HSI constants common to all microcode flows | ||
450 | */ | ||
451 | |||
452 | /* Connection types */ | ||
453 | #define ETH_CONNECTION_TYPE 0 | ||
454 | #define TOE_CONNECTION_TYPE 1 | ||
455 | #define RDMA_CONNECTION_TYPE 2 | ||
456 | #define ISCSI_CONNECTION_TYPE 3 | ||
457 | #define FCOE_CONNECTION_TYPE 4 | ||
458 | #define RESERVED_CONNECTION_TYPE_0 5 | ||
459 | #define RESERVED_CONNECTION_TYPE_1 6 | ||
460 | #define RESERVED_CONNECTION_TYPE_2 7 | ||
461 | |||
462 | |||
463 | #define PROTOCOL_STATE_BIT_OFFSET 6 | ||
464 | |||
465 | #define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) | ||
466 | #define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) | ||
467 | #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) | ||
468 | |||
469 | /* microcode fixed page page size 4K (chains and ring segments) */ | ||
470 | #define MC_PAGE_SIZE 4096 | ||
471 | |||
472 | |||
473 | /* Host coalescing constants */ | ||
474 | #define HC_IGU_BC_MODE 0 | ||
475 | #define HC_IGU_NBC_MODE 1 | ||
476 | |||
477 | #define HC_REGULAR_SEGMENT 0 | ||
478 | #define HC_DEFAULT_SEGMENT 1 | ||
479 | |||
480 | /* index numbers */ | ||
481 | #define HC_USTORM_DEF_SB_NUM_INDICES 8 | ||
482 | #define HC_CSTORM_DEF_SB_NUM_INDICES 8 | ||
483 | #define HC_XSTORM_DEF_SB_NUM_INDICES 4 | ||
484 | #define HC_TSTORM_DEF_SB_NUM_INDICES 4 | ||
485 | #define HC_USTORM_SB_NUM_INDICES 4 | ||
486 | #define HC_CSTORM_SB_NUM_INDICES 4 | ||
487 | |||
488 | /* index values - which counter to update */ | ||
489 | |||
490 | #define HC_INDEX_U_TOE_RX_CQ_CONS 0 | ||
491 | #define HC_INDEX_U_ETH_RX_CQ_CONS 1 | ||
492 | #define HC_INDEX_U_ETH_RX_BD_CONS 2 | ||
493 | #define HC_INDEX_U_FCOE_EQ_CONS 3 | ||
494 | |||
495 | #define HC_INDEX_C_TOE_TX_CQ_CONS 0 | ||
496 | #define HC_INDEX_C_ETH_TX_CQ_CONS 1 | ||
497 | #define HC_INDEX_C_ISCSI_EQ_CONS 2 | ||
498 | |||
499 | #define HC_INDEX_DEF_X_SPQ_CONS 0 | ||
500 | |||
501 | #define HC_INDEX_DEF_C_RDMA_EQ_CONS 0 | ||
502 | #define HC_INDEX_DEF_C_RDMA_NAL_PROD 1 | ||
503 | #define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2 | ||
504 | #define HC_INDEX_DEF_C_ETH_SLOW_PATH 3 | ||
505 | #define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4 | ||
506 | #define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5 | ||
507 | #define HC_INDEX_DEF_C_ETH_FCOE_CQ_CONS 6 | ||
508 | |||
509 | #define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0 | ||
510 | #define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1 | ||
511 | #define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2 | ||
512 | #define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3 | ||
513 | #define HC_INDEX_DEF_U_ETH_FCOE_RX_CQ_CONS 4 | ||
514 | #define HC_INDEX_DEF_U_ETH_FCOE_RX_BD_CONS 5 | ||
515 | |||
516 | /* used by the driver to get the SB offset */ | ||
517 | #define USTORM_ID 0 | ||
518 | #define CSTORM_ID 1 | ||
519 | #define XSTORM_ID 2 | ||
520 | #define TSTORM_ID 3 | ||
521 | #define ATTENTION_ID 4 | ||
522 | |||
523 | /* max number of slow path commands per port */ | ||
524 | #define MAX_RAMRODS_PER_PORT 8 | ||
525 | |||
526 | /* values for RX ETH CQE type field */ | ||
527 | #define RX_ETH_CQE_TYPE_ETH_FASTPATH 0 | ||
528 | #define RX_ETH_CQE_TYPE_ETH_RAMROD 1 | ||
529 | |||
530 | |||
531 | /**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ | ||
532 | #define EMULATION_FREQUENCY_FACTOR 1600 | ||
533 | #define FPGA_FREQUENCY_FACTOR 100 | ||
534 | |||
535 | #define TIMERS_TICK_SIZE_CHIP (1e-3) | ||
536 | #define TIMERS_TICK_SIZE_EMUL \ | ||
537 | ((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR))) | ||
538 | #define TIMERS_TICK_SIZE_FPGA \ | ||
539 | ((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR))) | ||
540 | |||
541 | #define TSEMI_CLK1_RESUL_CHIP (1e-3) | ||
542 | #define TSEMI_CLK1_RESUL_EMUL \ | ||
543 | ((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR)) | ||
544 | #define TSEMI_CLK1_RESUL_FPGA \ | ||
545 | ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) | ||
546 | |||
547 | #define USEMI_CLK1_RESUL_CHIP (TIMERS_TICK_SIZE_CHIP) | ||
548 | #define USEMI_CLK1_RESUL_EMUL (TIMERS_TICK_SIZE_EMUL) | ||
549 | #define USEMI_CLK1_RESUL_FPGA (TIMERS_TICK_SIZE_FPGA) | ||
550 | |||
551 | #define XSEMI_CLK1_RESUL_CHIP (1e-3) | ||
552 | #define XSEMI_CLK1_RESUL_EMUL \ | ||
553 | ((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR)) | ||
554 | #define XSEMI_CLK1_RESUL_FPGA \ | ||
555 | ((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) | ||
556 | |||
557 | #define XSEMI_CLK2_RESUL_CHIP (1e-6) | ||
558 | #define XSEMI_CLK2_RESUL_EMUL \ | ||
559 | ((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR)) | ||
560 | #define XSEMI_CLK2_RESUL_FPGA \ | ||
561 | ((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) | ||
562 | |||
563 | #define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6)) | ||
564 | #define SDM_TIMER_TICK_RESUL_EMUL \ | ||
565 | ((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR)) | ||
566 | #define SDM_TIMER_TICK_RESUL_FPGA \ | ||
567 | ((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) | ||
568 | |||
569 | |||
570 | /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ | ||
571 | #define XSTORM_IP_ID_ROLL_HALF 0x8000 | ||
572 | #define XSTORM_IP_ID_ROLL_ALL 0 | ||
573 | |||
574 | #define FW_LOG_LIST_SIZE 50 | ||
575 | |||
576 | #define NUM_OF_PROTOCOLS 4 | ||
577 | #define NUM_OF_SAFC_BITS 16 | ||
578 | #define MAX_COS_NUMBER 4 | ||
579 | #define MAX_T_STAT_COUNTER_ID 18 | ||
580 | #define MAX_X_STAT_COUNTER_ID 18 | ||
581 | #define MAX_U_STAT_COUNTER_ID 18 | ||
582 | |||
583 | |||
584 | #define UNKNOWN_ADDRESS 0 | ||
585 | #define UNICAST_ADDRESS 1 | ||
586 | #define MULTICAST_ADDRESS 2 | ||
587 | #define BROADCAST_ADDRESS 3 | ||
588 | |||
589 | #define SINGLE_FUNCTION 0 | ||
590 | #define MULTI_FUNCTION 1 | ||
591 | |||
592 | #define IP_V4 0 | ||
593 | #define IP_V6 1 | ||
594 | |||