diff options
Diffstat (limited to 'drivers/net/bnx2x.h')
-rw-r--r-- | drivers/net/bnx2x.h | 739 |
1 files changed, 437 insertions, 302 deletions
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h index 0979ca0ae408..e08b9439a933 100644 --- a/drivers/net/bnx2x.h +++ b/drivers/net/bnx2x.h | |||
@@ -14,39 +14,46 @@ | |||
14 | #ifndef BNX2X_H | 14 | #ifndef BNX2X_H |
15 | #define BNX2X_H | 15 | #define BNX2X_H |
16 | 16 | ||
17 | /* compilation time flags */ | ||
18 | |||
19 | /* define this to make the driver freeze on error to allow getting debug info | ||
20 | * (you will need to reboot afterwards) */ | ||
21 | /* #define BNX2X_STOP_ON_ERROR */ | ||
22 | |||
17 | /* error/debug prints */ | 23 | /* error/debug prints */ |
18 | 24 | ||
19 | #define DRV_MODULE_NAME "bnx2x" | 25 | #define DRV_MODULE_NAME "bnx2x" |
20 | #define PFX DRV_MODULE_NAME ": " | 26 | #define PFX DRV_MODULE_NAME ": " |
21 | 27 | ||
22 | /* for messages that are currently off */ | 28 | /* for messages that are currently off */ |
23 | #define BNX2X_MSG_OFF 0 | 29 | #define BNX2X_MSG_OFF 0 |
24 | #define BNX2X_MSG_MCP 0x10000 /* was: NETIF_MSG_HW */ | 30 | #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ |
25 | #define BNX2X_MSG_STATS 0x20000 /* was: NETIF_MSG_TIMER */ | 31 | #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ |
26 | #define NETIF_MSG_NVM 0x40000 /* was: NETIF_MSG_HW */ | 32 | #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ |
27 | #define NETIF_MSG_DMAE 0x80000 /* was: NETIF_MSG_HW */ | 33 | #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ |
28 | #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ | 34 | #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ |
29 | #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ | 35 | #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ |
30 | 36 | ||
31 | #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ | 37 | #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ |
32 | 38 | ||
33 | /* regular debug print */ | 39 | /* regular debug print */ |
34 | #define DP(__mask, __fmt, __args...) do { \ | 40 | #define DP(__mask, __fmt, __args...) do { \ |
35 | if (bp->msglevel & (__mask)) \ | 41 | if (bp->msglevel & (__mask)) \ |
36 | printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __FUNCTION__, \ | 42 | printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ |
37 | __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \ | 43 | bp->dev?(bp->dev->name):"?", ##__args); \ |
38 | } while (0) | 44 | } while (0) |
39 | 45 | ||
40 | /* for errors (never masked) */ | 46 | /* errors debug print */ |
41 | #define BNX2X_ERR(__fmt, __args...) do { \ | 47 | #define BNX2X_DBG_ERR(__fmt, __args...) do { \ |
42 | printk(KERN_ERR "[%s:%d(%s)]" __fmt, __FUNCTION__, \ | 48 | if (bp->msglevel & NETIF_MSG_PROBE) \ |
43 | __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \ | 49 | printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ |
50 | bp->dev?(bp->dev->name):"?", ##__args); \ | ||
44 | } while (0) | 51 | } while (0) |
45 | 52 | ||
46 | /* for logging (never masked) */ | 53 | /* for errors (never masked) */ |
47 | #define BNX2X_LOG(__fmt, __args...) do { \ | 54 | #define BNX2X_ERR(__fmt, __args...) do { \ |
48 | printk(KERN_NOTICE "[%s:%d(%s)]" __fmt, __FUNCTION__, \ | 55 | printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ |
49 | __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \ | 56 | bp->dev?(bp->dev->name):"?", ##__args); \ |
50 | } while (0) | 57 | } while (0) |
51 | 58 | ||
52 | /* before we have a dev->name use dev_info() */ | 59 | /* before we have a dev->name use dev_info() */ |
@@ -60,7 +67,7 @@ | |||
60 | #define bnx2x_panic() do { \ | 67 | #define bnx2x_panic() do { \ |
61 | bp->panic = 1; \ | 68 | bp->panic = 1; \ |
62 | BNX2X_ERR("driver assert\n"); \ | 69 | BNX2X_ERR("driver assert\n"); \ |
63 | bnx2x_disable_int(bp); \ | 70 | bnx2x_int_disable(bp); \ |
64 | bnx2x_panic_dump(bp); \ | 71 | bnx2x_panic_dump(bp); \ |
65 | } while (0) | 72 | } while (0) |
66 | #else | 73 | #else |
@@ -71,24 +78,29 @@ | |||
71 | #endif | 78 | #endif |
72 | 79 | ||
73 | 80 | ||
74 | #define U64_LO(x) (((u64)x) & 0xffffffff) | 81 | #ifdef NETIF_F_HW_VLAN_TX |
75 | #define U64_HI(x) (((u64)x) >> 32) | 82 | #define BCM_VLAN 1 |
76 | #define HILO_U64(hi, lo) (((u64)hi << 32) + lo) | 83 | #endif |
84 | |||
77 | 85 | ||
86 | #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) | ||
87 | #define U64_HI(x) (u32)(((u64)(x)) >> 32) | ||
88 | #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) | ||
78 | 89 | ||
79 | #define REG_ADDR(bp, offset) (bp->regview + offset) | ||
80 | 90 | ||
81 | #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) | 91 | #define REG_ADDR(bp, offset) (bp->regview + offset) |
82 | #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) | ||
83 | #define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset)) | ||
84 | 92 | ||
85 | #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) | 93 | #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) |
94 | #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) | ||
95 | #define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset)) | ||
96 | |||
97 | #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) | ||
86 | #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) | 98 | #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) |
87 | #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) | 99 | #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) |
88 | #define REG_WR32(bp, offset, val) REG_WR(bp, offset, val) | 100 | #define REG_WR32(bp, offset, val) REG_WR(bp, offset, val) |
89 | 101 | ||
90 | #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) | 102 | #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) |
91 | #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) | 103 | #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) |
92 | 104 | ||
93 | #define REG_RD_DMAE(bp, offset, valp, len32) \ | 105 | #define REG_RD_DMAE(bp, offset, valp, len32) \ |
94 | do { \ | 106 | do { \ |
@@ -96,28 +108,28 @@ | |||
96 | memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \ | 108 | memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \ |
97 | } while (0) | 109 | } while (0) |
98 | 110 | ||
99 | #define REG_WR_DMAE(bp, offset, val, len32) \ | 111 | #define REG_WR_DMAE(bp, offset, valp, len32) \ |
100 | do { \ | 112 | do { \ |
101 | memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \ | 113 | memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \ |
102 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ | 114 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ |
103 | offset, len32); \ | 115 | offset, len32); \ |
104 | } while (0) | 116 | } while (0) |
105 | 117 | ||
106 | #define SHMEM_RD(bp, type) \ | 118 | #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ |
107 | REG_RD(bp, bp->shmem_base + offsetof(struct shmem_region, type)) | 119 | offsetof(struct shmem_region, field)) |
108 | #define SHMEM_WR(bp, type, val) \ | 120 | #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) |
109 | REG_WR(bp, bp->shmem_base + offsetof(struct shmem_region, type), val) | 121 | #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) |
110 | 122 | ||
111 | #define NIG_WR(reg, val) REG_WR(bp, reg, val) | 123 | #define NIG_WR(reg, val) REG_WR(bp, reg, val) |
112 | #define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val) | 124 | #define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val) |
113 | #define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val) | 125 | #define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val) |
114 | 126 | ||
115 | 127 | ||
116 | #define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++) | 128 | #define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++) |
117 | 129 | ||
118 | #define for_each_nondefault_queue(bp, var) \ | 130 | #define for_each_nondefault_queue(bp, var) \ |
119 | for (var = 1; var < bp->num_queues; var++) | 131 | for (var = 1; var < bp->num_queues; var++) |
120 | #define is_multi(bp) (bp->num_queues > 1) | 132 | #define is_multi(bp) (bp->num_queues > 1) |
121 | 133 | ||
122 | 134 | ||
123 | struct regp { | 135 | struct regp { |
@@ -358,210 +370,122 @@ struct bnx2x_eth_stats { | |||
358 | u32 number_of_bugs_found_in_stats_spec; /* just kidding */ | 370 | u32 number_of_bugs_found_in_stats_spec; /* just kidding */ |
359 | }; | 371 | }; |
360 | 372 | ||
361 | #define MAC_STX_NA 0xffffffff | ||
362 | |||
363 | #ifdef BNX2X_MULTI | ||
364 | #define MAX_CONTEXT 16 | ||
365 | #else | ||
366 | #define MAX_CONTEXT 1 | ||
367 | #endif | ||
368 | |||
369 | union cdu_context { | ||
370 | struct eth_context eth; | ||
371 | char pad[1024]; | ||
372 | }; | ||
373 | |||
374 | #define MAX_DMAE_C 5 | ||
375 | |||
376 | /* DMA memory not used in fastpath */ | ||
377 | struct bnx2x_slowpath { | ||
378 | union cdu_context context[MAX_CONTEXT]; | ||
379 | struct eth_stats_query fw_stats; | ||
380 | struct mac_configuration_cmd mac_config; | ||
381 | struct mac_configuration_cmd mcast_config; | ||
382 | |||
383 | /* used by dmae command executer */ | ||
384 | struct dmae_command dmae[MAX_DMAE_C]; | ||
385 | |||
386 | union mac_stats mac_stats; | ||
387 | struct nig_stats nig; | ||
388 | struct bnx2x_eth_stats eth_stats; | ||
389 | |||
390 | u32 wb_comp; | ||
391 | #define BNX2X_WB_COMP_VAL 0xe0d0d0ae | ||
392 | u32 wb_data[4]; | ||
393 | }; | ||
394 | |||
395 | #define bnx2x_sp(bp, var) (&bp->slowpath->var) | ||
396 | #define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : NULL) | 373 | #define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : NULL) |
397 | #define bnx2x_sp_mapping(bp, var) \ | ||
398 | (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) | ||
399 | |||
400 | |||
401 | struct sw_rx_bd { | 374 | struct sw_rx_bd { |
402 | struct sk_buff *skb; | 375 | struct sk_buff *skb; |
403 | DECLARE_PCI_UNMAP_ADDR(mapping) | 376 | DECLARE_PCI_UNMAP_ADDR(mapping) |
404 | }; | 377 | }; |
405 | 378 | ||
406 | struct sw_tx_bd { | 379 | struct sw_tx_bd { |
407 | struct sk_buff *skb; | 380 | struct sk_buff *skb; |
408 | u16 first_bd; | 381 | u16 first_bd; |
409 | }; | 382 | }; |
410 | 383 | ||
411 | struct bnx2x_fastpath { | 384 | struct bnx2x_fastpath { |
412 | 385 | ||
413 | struct napi_struct napi; | 386 | struct napi_struct napi; |
414 | 387 | ||
415 | struct host_status_block *status_blk; | 388 | struct host_status_block *status_blk; |
416 | dma_addr_t status_blk_mapping; | 389 | dma_addr_t status_blk_mapping; |
417 | 390 | ||
418 | struct eth_tx_db_data *hw_tx_prods; | 391 | struct eth_tx_db_data *hw_tx_prods; |
419 | dma_addr_t tx_prods_mapping; | 392 | dma_addr_t tx_prods_mapping; |
420 | 393 | ||
421 | struct sw_tx_bd *tx_buf_ring; | 394 | struct sw_tx_bd *tx_buf_ring; |
422 | 395 | ||
423 | struct eth_tx_bd *tx_desc_ring; | 396 | struct eth_tx_bd *tx_desc_ring; |
424 | dma_addr_t tx_desc_mapping; | 397 | dma_addr_t tx_desc_mapping; |
425 | 398 | ||
426 | struct sw_rx_bd *rx_buf_ring; | 399 | struct sw_rx_bd *rx_buf_ring; |
427 | 400 | ||
428 | struct eth_rx_bd *rx_desc_ring; | 401 | struct eth_rx_bd *rx_desc_ring; |
429 | dma_addr_t rx_desc_mapping; | 402 | dma_addr_t rx_desc_mapping; |
430 | 403 | ||
431 | union eth_rx_cqe *rx_comp_ring; | 404 | union eth_rx_cqe *rx_comp_ring; |
432 | dma_addr_t rx_comp_mapping; | 405 | dma_addr_t rx_comp_mapping; |
433 | 406 | ||
434 | int state; | 407 | int state; |
435 | #define BNX2X_FP_STATE_CLOSED 0 | 408 | #define BNX2X_FP_STATE_CLOSED 0 |
436 | #define BNX2X_FP_STATE_IRQ 0x80000 | 409 | #define BNX2X_FP_STATE_IRQ 0x80000 |
437 | #define BNX2X_FP_STATE_OPENING 0x90000 | 410 | #define BNX2X_FP_STATE_OPENING 0x90000 |
438 | #define BNX2X_FP_STATE_OPEN 0xa0000 | 411 | #define BNX2X_FP_STATE_OPEN 0xa0000 |
439 | #define BNX2X_FP_STATE_HALTING 0xb0000 | 412 | #define BNX2X_FP_STATE_HALTING 0xb0000 |
440 | #define BNX2X_FP_STATE_HALTED 0xc0000 | 413 | #define BNX2X_FP_STATE_HALTED 0xc0000 |
441 | 414 | ||
442 | int index; | 415 | u8 index; /* number in fp array */ |
443 | 416 | u8 cl_id; /* eth client id */ | |
444 | u16 tx_pkt_prod; | 417 | u8 sb_id; /* status block number in HW */ |
445 | u16 tx_pkt_cons; | 418 | #define FP_IDX(fp) (fp->index) |
446 | u16 tx_bd_prod; | 419 | #define FP_CL_ID(fp) (fp->cl_id) |
447 | u16 tx_bd_cons; | 420 | #define BP_CL_ID(bp) (bp->fp[0].cl_id) |
448 | u16 *tx_cons_sb; | 421 | #define FP_SB_ID(fp) (fp->sb_id) |
449 | 422 | #define CNIC_SB_ID 0 | |
450 | u16 fp_c_idx; | 423 | |
451 | u16 fp_u_idx; | 424 | u16 tx_pkt_prod; |
452 | 425 | u16 tx_pkt_cons; | |
453 | u16 rx_bd_prod; | 426 | u16 tx_bd_prod; |
454 | u16 rx_bd_cons; | 427 | u16 tx_bd_cons; |
455 | u16 rx_comp_prod; | 428 | u16 *tx_cons_sb; |
456 | u16 rx_comp_cons; | 429 | |
457 | u16 *rx_cons_sb; | 430 | u16 fp_c_idx; |
458 | 431 | u16 fp_u_idx; | |
459 | unsigned long tx_pkt, | 432 | |
433 | u16 rx_bd_prod; | ||
434 | u16 rx_bd_cons; | ||
435 | u16 rx_comp_prod; | ||
436 | u16 rx_comp_cons; | ||
437 | u16 *rx_cons_sb; | ||
438 | |||
439 | unsigned long tx_pkt, | ||
460 | rx_pkt, | 440 | rx_pkt, |
461 | rx_calls; | 441 | rx_calls; |
462 | 442 | ||
463 | struct bnx2x *bp; /* parent */ | 443 | struct bnx2x *bp; /* parent */ |
464 | }; | ||
465 | |||
466 | #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) | ||
467 | |||
468 | |||
469 | /* attn group wiring */ | ||
470 | #define MAX_DYNAMIC_ATTN_GRPS 8 | ||
471 | |||
472 | struct attn_route { | ||
473 | u32 sig[4]; | ||
474 | }; | 444 | }; |
475 | 445 | ||
476 | struct bnx2x { | 446 | #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) |
477 | /* Fields used in the tx and intr/napi performance paths | 447 | /* This is needed for determening of last_max */ |
478 | * are grouped together in the beginning of the structure | 448 | #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) |
479 | */ | ||
480 | struct bnx2x_fastpath *fp; | ||
481 | void __iomem *regview; | ||
482 | void __iomem *doorbells; | ||
483 | |||
484 | struct net_device *dev; | ||
485 | struct pci_dev *pdev; | ||
486 | |||
487 | atomic_t intr_sem; | ||
488 | struct msix_entry msix_table[MAX_CONTEXT+1]; | ||
489 | |||
490 | int tx_ring_size; | ||
491 | 449 | ||
492 | #ifdef BCM_VLAN | 450 | /* stuff added to make the code fit 80Col */ |
493 | struct vlan_group *vlgrp; | ||
494 | #endif | ||
495 | |||
496 | u32 rx_csum; | ||
497 | u32 rx_offset; | ||
498 | u32 rx_buf_use_size; /* useable size */ | ||
499 | u32 rx_buf_size; /* with alignment */ | ||
500 | #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */ | ||
501 | #define ETH_MIN_PACKET_SIZE 60 | ||
502 | #define ETH_MAX_PACKET_SIZE 1500 | ||
503 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | ||
504 | 451 | ||
505 | struct host_def_status_block *def_status_blk; | 452 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
506 | #define DEF_SB_ID 16 | ||
507 | u16 def_c_idx; | ||
508 | u16 def_u_idx; | ||
509 | u16 def_t_idx; | ||
510 | u16 def_x_idx; | ||
511 | u16 def_att_idx; | ||
512 | u32 attn_state; | ||
513 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; | ||
514 | u32 aeu_mask; | ||
515 | u32 nig_mask; | ||
516 | 453 | ||
517 | /* slow path ring */ | 454 | #define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \ |
518 | struct eth_spe *spq; | 455 | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \ |
519 | dma_addr_t spq_mapping; | 456 | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG) |
520 | u16 spq_prod_idx; | ||
521 | struct eth_spe *spq_prod_bd; | ||
522 | struct eth_spe *spq_last_bd; | ||
523 | u16 *dsb_sp_prod; | ||
524 | u16 spq_left; /* serialize spq */ | ||
525 | spinlock_t spq_lock; | ||
526 | |||
527 | /* Flag for marking that there is either | ||
528 | * STAT_QUERY or CFC DELETE ramrod pending | ||
529 | */ | ||
530 | u8 stat_pending; | ||
531 | 457 | ||
532 | /* End of fields used in the performance code paths */ | ||
533 | 458 | ||
534 | int panic; | 459 | #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS |
535 | int msglevel; | 460 | #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS |
461 | #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS | ||
536 | 462 | ||
537 | u32 flags; | 463 | #define BNX2X_RX_SB_INDEX \ |
538 | #define PCIX_FLAG 1 | 464 | (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]) |
539 | #define PCI_32BIT_FLAG 2 | ||
540 | #define ONE_TDMA_FLAG 4 /* no longer used */ | ||
541 | #define NO_WOL_FLAG 8 | ||
542 | #define USING_DAC_FLAG 0x10 | ||
543 | #define USING_MSIX_FLAG 0x20 | ||
544 | #define ASF_ENABLE_FLAG 0x40 | ||
545 | 465 | ||
546 | int port; | 466 | #define BNX2X_RX_SB_BD_INDEX \ |
467 | (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX]) | ||
547 | 468 | ||
548 | int pm_cap; | 469 | #define BNX2X_RX_SB_INDEX_NUM \ |
549 | int pcie_cap; | 470 | (((U_SB_ETH_RX_CQ_INDEX << \ |
471 | USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \ | ||
472 | USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \ | ||
473 | ((U_SB_ETH_RX_BD_INDEX << \ | ||
474 | USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \ | ||
475 | USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER)) | ||
550 | 476 | ||
551 | struct work_struct sp_task; | 477 | #define BNX2X_TX_SB_INDEX \ |
552 | struct work_struct reset_task; | 478 | (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]) |
553 | 479 | ||
554 | struct timer_list timer; | 480 | /* common */ |
555 | int timer_interval; | ||
556 | int current_interval; | ||
557 | 481 | ||
558 | u32 shmem_base; | 482 | struct bnx2x_common { |
559 | 483 | ||
560 | u32 chip_id; | 484 | u32 chip_id; |
561 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | 485 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
562 | #define CHIP_ID(bp) (bp->chip_id & 0xfffffff0) | 486 | #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) |
563 | 487 | ||
564 | #define CHIP_NUM(bp) (bp->chip_id >> 16) | 488 | #define CHIP_NUM(bp) (bp->common.chip_id >> 16) |
565 | #define CHIP_NUM_57710 0x164e | 489 | #define CHIP_NUM_57710 0x164e |
566 | #define CHIP_NUM_57711 0x164f | 490 | #define CHIP_NUM_57711 0x164f |
567 | #define CHIP_NUM_57711E 0x1650 | 491 | #define CHIP_NUM_57711E 0x1650 |
@@ -572,7 +496,7 @@ struct bnx2x { | |||
572 | CHIP_IS_57711E(bp)) | 496 | CHIP_IS_57711E(bp)) |
573 | #define IS_E1H_OFFSET CHIP_IS_E1H(bp) | 497 | #define IS_E1H_OFFSET CHIP_IS_E1H(bp) |
574 | 498 | ||
575 | #define CHIP_REV(bp) (bp->chip_id & 0x0000f000) | 499 | #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000) |
576 | #define CHIP_REV_Ax 0x00000000 | 500 | #define CHIP_REV_Ax 0x00000000 |
577 | /* assume maximum 5 revisions */ | 501 | /* assume maximum 5 revisions */ |
578 | #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000) | 502 | #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000) |
@@ -586,86 +510,250 @@ struct bnx2x { | |||
586 | #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ | 510 | #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ |
587 | ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) | 511 | ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) |
588 | 512 | ||
589 | #define CHIP_METAL(bp) (bp->chip_id & 0x00000ff0) | 513 | #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) |
590 | #define CHIP_BOND_ID(bp) (bp->chip_id & 0x0000000f) | 514 | #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) |
591 | 515 | ||
592 | u16 fw_seq; | 516 | int flash_size; |
593 | u16 fw_drv_pulse_wr_seq; | 517 | #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ |
594 | u32 fw_mb; | 518 | #define NVRAM_TIMEOUT_COUNT 30000 |
519 | #define NVRAM_PAGE_SIZE 256 | ||
595 | 520 | ||
596 | u32 hw_config; | 521 | u32 shmem_base; |
522 | |||
523 | u32 hw_config; | ||
597 | u32 board; | 524 | u32 board; |
598 | 525 | ||
599 | struct link_params link_params; | 526 | u32 bc_ver; |
527 | |||
528 | char *name; | ||
529 | }; | ||
600 | 530 | ||
601 | struct link_vars link_vars; | 531 | |
532 | /* end of common */ | ||
533 | |||
534 | /* port */ | ||
535 | |||
536 | struct bnx2x_port { | ||
537 | u32 pmf; | ||
602 | 538 | ||
603 | u32 link_config; | 539 | u32 link_config; |
604 | 540 | ||
605 | u32 supported; | 541 | u32 supported; |
542 | /* link settings - missing defines */ | ||
543 | #define SUPPORTED_2500baseX_Full (1 << 15) | ||
544 | |||
545 | u32 advertising; | ||
606 | /* link settings - missing defines */ | 546 | /* link settings - missing defines */ |
607 | #define SUPPORTED_2500baseT_Full (1 << 15) | 547 | #define ADVERTISED_2500baseX_Full (1 << 15) |
608 | 548 | ||
609 | u32 phy_addr; | 549 | u32 phy_addr; |
610 | 550 | ||
611 | /* used to synchronize phy accesses */ | 551 | /* used to synchronize phy accesses */ |
612 | struct mutex phy_mutex; | 552 | struct mutex phy_mutex; |
613 | 553 | ||
614 | u32 phy_id; | 554 | u32 port_stx; |
615 | 555 | ||
556 | struct nig_stats old_nig_stats; | ||
557 | }; | ||
616 | 558 | ||
617 | u32 advertising; | 559 | /* end of port */ |
618 | /* link settings - missing defines */ | 560 | |
619 | #define ADVERTISED_2500baseT_Full (1 << 15) | 561 | #define MAC_STX_NA 0xffffffff |
562 | |||
563 | #ifdef BNX2X_MULTI | ||
564 | #define MAX_CONTEXT 16 | ||
565 | #else | ||
566 | #define MAX_CONTEXT 1 | ||
567 | #endif | ||
568 | |||
569 | union cdu_context { | ||
570 | struct eth_context eth; | ||
571 | char pad[1024]; | ||
572 | }; | ||
573 | |||
574 | #define MAX_DMAE_C 6 | ||
575 | |||
576 | /* DMA memory not used in fastpath */ | ||
577 | struct bnx2x_slowpath { | ||
578 | union cdu_context context[MAX_CONTEXT]; | ||
579 | struct eth_stats_query fw_stats; | ||
580 | struct mac_configuration_cmd mac_config; | ||
581 | struct mac_configuration_cmd mcast_config; | ||
582 | |||
583 | /* used by dmae command executer */ | ||
584 | struct dmae_command dmae[MAX_DMAE_C]; | ||
585 | |||
586 | union mac_stats mac_stats; | ||
587 | struct nig_stats nig; | ||
588 | struct bnx2x_eth_stats eth_stats; | ||
589 | |||
590 | u32 wb_comp; | ||
591 | #define BNX2X_WB_COMP_VAL 0xe0d0d0ae | ||
592 | u32 wb_data[4]; | ||
593 | }; | ||
594 | |||
595 | #define bnx2x_sp(bp, var) (&bp->slowpath->var) | ||
596 | #define bnx2x_sp_mapping(bp, var) \ | ||
597 | (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) | ||
598 | |||
599 | |||
600 | /* attn group wiring */ | ||
601 | #define MAX_DYNAMIC_ATTN_GRPS 8 | ||
602 | |||
603 | struct attn_route { | ||
604 | u32 sig[4]; | ||
605 | }; | ||
606 | |||
607 | struct bnx2x { | ||
608 | /* Fields used in the tx and intr/napi performance paths | ||
609 | * are grouped together in the beginning of the structure | ||
610 | */ | ||
611 | struct bnx2x_fastpath fp[MAX_CONTEXT]; | ||
612 | void __iomem *regview; | ||
613 | void __iomem *doorbells; | ||
614 | #define BNX2X_DB_SIZE (16*2048) | ||
615 | |||
616 | struct net_device *dev; | ||
617 | struct pci_dev *pdev; | ||
618 | |||
619 | atomic_t intr_sem; | ||
620 | struct msix_entry msix_table[MAX_CONTEXT+1]; | ||
621 | |||
622 | int tx_ring_size; | ||
623 | |||
624 | #ifdef BCM_VLAN | ||
625 | struct vlan_group *vlgrp; | ||
626 | #endif | ||
620 | 627 | ||
628 | u32 rx_csum; | ||
629 | u32 rx_offset; | ||
630 | u32 rx_buf_use_size; /* useable size */ | ||
631 | u32 rx_buf_size; /* with alignment */ | ||
632 | #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */ | ||
633 | #define ETH_MIN_PACKET_SIZE 60 | ||
634 | #define ETH_MAX_PACKET_SIZE 1500 | ||
635 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | ||
621 | 636 | ||
622 | u32 bc_ver; | 637 | struct host_def_status_block *def_status_blk; |
638 | #define DEF_SB_ID 16 | ||
639 | u16 def_c_idx; | ||
640 | u16 def_u_idx; | ||
641 | u16 def_x_idx; | ||
642 | u16 def_t_idx; | ||
643 | u16 def_att_idx; | ||
644 | u32 attn_state; | ||
645 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; | ||
646 | u32 aeu_mask; | ||
647 | u32 nig_mask; | ||
648 | |||
649 | /* slow path ring */ | ||
650 | struct eth_spe *spq; | ||
651 | dma_addr_t spq_mapping; | ||
652 | u16 spq_prod_idx; | ||
653 | struct eth_spe *spq_prod_bd; | ||
654 | struct eth_spe *spq_last_bd; | ||
655 | u16 *dsb_sp_prod; | ||
656 | u16 spq_left; /* serialize spq */ | ||
657 | /* used to synchronize spq accesses */ | ||
658 | spinlock_t spq_lock; | ||
659 | |||
660 | /* Flag for marking that there is either | ||
661 | * STAT_QUERY or CFC DELETE ramrod pending | ||
662 | */ | ||
663 | u8 stat_pending; | ||
664 | |||
665 | /* End of fileds used in the performance code paths */ | ||
666 | |||
667 | int panic; | ||
668 | int msglevel; | ||
669 | |||
670 | u32 flags; | ||
671 | #define PCIX_FLAG 1 | ||
672 | #define PCI_32BIT_FLAG 2 | ||
673 | #define ONE_TDMA_FLAG 4 /* no longer used */ | ||
674 | #define NO_WOL_FLAG 8 | ||
675 | #define USING_DAC_FLAG 0x10 | ||
676 | #define USING_MSIX_FLAG 0x20 | ||
677 | #define ASF_ENABLE_FLAG 0x40 | ||
678 | #define NO_MCP_FLAG 0x100 | ||
679 | #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) | ||
680 | |||
681 | int func; | ||
682 | #define BP_PORT(bp) (bp->func % PORT_MAX) | ||
683 | #define BP_FUNC(bp) (bp->func) | ||
684 | #define BP_E1HVN(bp) (bp->func >> 1) | ||
685 | #define BP_L_ID(bp) (BP_E1HVN(bp) << 2) | ||
686 | /* assorted E1HVN */ | ||
687 | #define IS_E1HMF(bp) (bp->e1hmf != 0) | ||
688 | #define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16) | ||
689 | |||
690 | int pm_cap; | ||
691 | int pcie_cap; | ||
692 | |||
693 | struct work_struct sp_task; | ||
694 | struct work_struct reset_task; | ||
695 | |||
696 | struct timer_list timer; | ||
697 | int timer_interval; | ||
698 | int current_interval; | ||
699 | |||
700 | u16 fw_seq; | ||
701 | u16 fw_drv_pulse_wr_seq; | ||
702 | u32 func_stx; | ||
703 | |||
704 | struct link_params link_params; | ||
705 | struct link_vars link_vars; | ||
623 | 706 | ||
624 | int flash_size; | 707 | struct bnx2x_common common; |
625 | #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ | 708 | struct bnx2x_port port; |
626 | #define NVRAM_TIMEOUT_COUNT 30000 | 709 | |
627 | #define NVRAM_PAGE_SIZE 256 | 710 | u32 mf_config; |
711 | u16 e1hov; | ||
712 | u8 e1hmf; | ||
628 | 713 | ||
629 | u8 wol; | 714 | u8 wol; |
630 | 715 | ||
631 | int rx_ring_size; | 716 | int rx_ring_size; |
632 | 717 | ||
633 | u16 tx_quick_cons_trip_int; | 718 | u16 tx_quick_cons_trip_int; |
634 | u16 tx_quick_cons_trip; | 719 | u16 tx_quick_cons_trip; |
635 | u16 tx_ticks_int; | 720 | u16 tx_ticks_int; |
636 | u16 tx_ticks; | 721 | u16 tx_ticks; |
637 | 722 | ||
638 | u16 rx_quick_cons_trip_int; | 723 | u16 rx_quick_cons_trip_int; |
639 | u16 rx_quick_cons_trip; | 724 | u16 rx_quick_cons_trip; |
640 | u16 rx_ticks_int; | 725 | u16 rx_ticks_int; |
641 | u16 rx_ticks; | 726 | u16 rx_ticks; |
642 | 727 | ||
643 | u32 stats_ticks; | 728 | u32 stats_ticks; |
729 | u32 lin_cnt; | ||
644 | 730 | ||
645 | int state; | 731 | int state; |
646 | #define BNX2X_STATE_CLOSED 0x0 | 732 | #define BNX2X_STATE_CLOSED 0x0 |
647 | #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 | 733 | #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 |
648 | #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 | 734 | #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 |
649 | #define BNX2X_STATE_OPEN 0x3000 | 735 | #define BNX2X_STATE_OPEN 0x3000 |
650 | #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 | 736 | #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 |
651 | #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 | 737 | #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 |
652 | #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000 | 738 | #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000 |
653 | #define BNX2X_STATE_ERROR 0xF000 | 739 | #define BNX2X_STATE_DISABLED 0xd000 |
740 | #define BNX2X_STATE_DIAG 0xe000 | ||
741 | #define BNX2X_STATE_ERROR 0xf000 | ||
654 | 742 | ||
655 | int num_queues; | 743 | int num_queues; |
656 | 744 | ||
657 | u32 rx_mode; | 745 | u32 rx_mode; |
658 | #define BNX2X_RX_MODE_NONE 0 | 746 | #define BNX2X_RX_MODE_NONE 0 |
659 | #define BNX2X_RX_MODE_NORMAL 1 | 747 | #define BNX2X_RX_MODE_NORMAL 1 |
660 | #define BNX2X_RX_MODE_ALLMULTI 2 | 748 | #define BNX2X_RX_MODE_ALLMULTI 2 |
661 | #define BNX2X_RX_MODE_PROMISC 3 | 749 | #define BNX2X_RX_MODE_PROMISC 3 |
662 | #define BNX2X_MAX_MULTICAST 64 | 750 | #define BNX2X_MAX_MULTICAST 64 |
663 | #define BNX2X_MAX_EMUL_MULTI 16 | 751 | #define BNX2X_MAX_EMUL_MULTI 16 |
664 | 752 | ||
665 | dma_addr_t def_status_blk_mapping; | 753 | dma_addr_t def_status_blk_mapping; |
666 | 754 | ||
667 | struct bnx2x_slowpath *slowpath; | 755 | struct bnx2x_slowpath *slowpath; |
668 | dma_addr_t slowpath_mapping; | 756 | dma_addr_t slowpath_mapping; |
669 | 757 | ||
670 | #ifdef BCM_ISCSI | 758 | #ifdef BCM_ISCSI |
671 | void *t1; | 759 | void *t1; |
@@ -742,8 +830,10 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode); | |||
742 | 830 | ||
743 | /* MC hsi */ | 831 | /* MC hsi */ |
744 | #define RX_COPY_THRESH 92 | 832 | #define RX_COPY_THRESH 92 |
745 | #define BCM_PAGE_BITS 12 | 833 | #define BCM_PAGE_SHIFT 12 |
746 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS) | 834 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) |
835 | #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) | ||
836 | #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) | ||
747 | 837 | ||
748 | #define NUM_TX_RINGS 16 | 838 | #define NUM_TX_RINGS 16 |
749 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd)) | 839 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd)) |
@@ -795,26 +885,11 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode); | |||
795 | 885 | ||
796 | 886 | ||
797 | /* must be used on a CID before placing it on a HW ring */ | 887 | /* must be used on a CID before placing it on a HW ring */ |
798 | #define HW_CID(bp, x) (x | (bp->port << 23)) | 888 | #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x) |
799 | 889 | ||
800 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) | 890 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) |
801 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) | 891 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) |
802 | 892 | ||
803 | #define ATTN_NIG_FOR_FUNC (1L << 8) | ||
804 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) | ||
805 | #define GPIO_2_FUNC (1L << 10) | ||
806 | #define GPIO_3_FUNC (1L << 11) | ||
807 | #define GPIO_4_FUNC (1L << 12) | ||
808 | #define ATTN_GENERAL_ATTN_1 (1L << 13) | ||
809 | #define ATTN_GENERAL_ATTN_2 (1L << 14) | ||
810 | #define ATTN_GENERAL_ATTN_3 (1L << 15) | ||
811 | #define ATTN_GENERAL_ATTN_4 (1L << 13) | ||
812 | #define ATTN_GENERAL_ATTN_5 (1L << 14) | ||
813 | #define ATTN_GENERAL_ATTN_6 (1L << 15) | ||
814 | |||
815 | #define ATTN_HARD_WIRED_MASK 0xff00 | ||
816 | #define ATTENTION_ID 4 | ||
817 | |||
818 | 893 | ||
819 | #define BNX2X_BTR 3 | 894 | #define BNX2X_BTR 3 |
820 | #define MAX_SPQ_PENDING 8 | 895 | #define MAX_SPQ_PENDING 8 |
@@ -831,6 +906,31 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode); | |||
831 | DPM_TRIGER_TYPE); \ | 906 | DPM_TRIGER_TYPE); \ |
832 | } while (0) | 907 | } while (0) |
833 | 908 | ||
909 | static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, | ||
910 | int wait) | ||
911 | { | ||
912 | u32 val; | ||
913 | |||
914 | do { | ||
915 | val = REG_RD(bp, reg); | ||
916 | if (val == expected) | ||
917 | break; | ||
918 | ms -= wait; | ||
919 | msleep(wait); | ||
920 | |||
921 | } while (ms > 0); | ||
922 | |||
923 | return val; | ||
924 | } | ||
925 | |||
926 | |||
927 | /* load/unload mode */ | ||
928 | #define LOAD_NORMAL 0 | ||
929 | #define LOAD_OPEN 1 | ||
930 | #define LOAD_DIAG 2 | ||
931 | #define UNLOAD_NORMAL 0 | ||
932 | #define UNLOAD_CLOSE 1 | ||
933 | |||
834 | /* DMAE command defines */ | 934 | /* DMAE command defines */ |
835 | #define DMAE_CMD_SRC_PCI 0 | 935 | #define DMAE_CMD_SRC_PCI 0 |
836 | #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC | 936 | #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC |
@@ -877,23 +977,48 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode); | |||
877 | 977 | ||
878 | #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) | 978 | #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) |
879 | 979 | ||
880 | /* stuff added to make the code fit 80Col */ | 980 | /* must be used on a CID before placing it on a HW ring */ |
881 | 981 | ||
882 | #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG | ||
883 | #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG | ||
884 | #define TPA_TYPE(cqe) (cqe->fast_path_cqe.error_type_flags & \ | ||
885 | (TPA_TYPE_START | TPA_TYPE_END)) | ||
886 | #define BNX2X_RX_SUM_OK(cqe) \ | 982 | #define BNX2X_RX_SUM_OK(cqe) \ |
887 | (!(cqe->fast_path_cqe.status_flags & \ | 983 | (!(cqe->fast_path_cqe.status_flags & \ |
888 | (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \ | 984 | (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \ |
889 | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG))) | 985 | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG))) |
890 | 986 | ||
891 | #define BNX2X_RX_SUM_FIX(cqe) \ | 987 | /* CMNG constants |
892 | ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \ | 988 | derived from lab experiments, and not from system spec calculations !!! */ |
893 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \ | 989 | #define DEF_MIN_RATE 100 |
894 | (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT)) | 990 | /* resolution of the rate shaping timer - 100 usec */ |
991 | #define RS_PERIODIC_TIMEOUT_USEC 100 | ||
992 | /* resolution of fairness algorithm in usecs - | ||
993 | coefficient for clauclating the actuall t fair */ | ||
994 | #define T_FAIR_COEF 10000000 | ||
995 | /* number of bytes in single QM arbitration cycle - | ||
996 | coeffiecnt for calculating the fairness timer */ | ||
997 | #define QM_ARB_BYTES 40000 | ||
998 | #define FAIR_MEM 2 | ||
999 | |||
1000 | |||
1001 | #define ATTN_NIG_FOR_FUNC (1L << 8) | ||
1002 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) | ||
1003 | #define GPIO_2_FUNC (1L << 10) | ||
1004 | #define GPIO_3_FUNC (1L << 11) | ||
1005 | #define GPIO_4_FUNC (1L << 12) | ||
1006 | #define ATTN_GENERAL_ATTN_1 (1L << 13) | ||
1007 | #define ATTN_GENERAL_ATTN_2 (1L << 14) | ||
1008 | #define ATTN_GENERAL_ATTN_3 (1L << 15) | ||
1009 | #define ATTN_GENERAL_ATTN_4 (1L << 13) | ||
1010 | #define ATTN_GENERAL_ATTN_5 (1L << 14) | ||
1011 | #define ATTN_GENERAL_ATTN_6 (1L << 15) | ||
1012 | |||
1013 | #define ATTN_HARD_WIRED_MASK 0xff00 | ||
1014 | #define ATTENTION_ID 4 | ||
895 | 1015 | ||
896 | 1016 | ||
1017 | /* stuff added to make the code fit 80Col */ | ||
1018 | |||
1019 | #define BNX2X_PMF_LINK_ASSERT \ | ||
1020 | GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) | ||
1021 | |||
897 | #define BNX2X_MC_ASSERT_BITS \ | 1022 | #define BNX2X_MC_ASSERT_BITS \ |
898 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | 1023 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ |
899 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | 1024 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ |
@@ -906,12 +1031,20 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode); | |||
906 | #define BNX2X_DOORQ_ASSERT \ | 1031 | #define BNX2X_DOORQ_ASSERT \ |
907 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT | 1032 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT |
908 | 1033 | ||
1034 | #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) | ||
1035 | #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ | ||
1036 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ | ||
1037 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ | ||
1038 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ | ||
1039 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ | ||
1040 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) | ||
1041 | |||
909 | #define HW_INTERRUT_ASSERT_SET_0 \ | 1042 | #define HW_INTERRUT_ASSERT_SET_0 \ |
910 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ | 1043 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ |
911 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ | 1044 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ |
912 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ | 1045 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ |
913 | AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT) | 1046 | AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT) |
914 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ | 1047 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ |
915 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ | 1048 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ |
916 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ | 1049 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ |
917 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ | 1050 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ |
@@ -928,7 +1061,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode); | |||
928 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ | 1061 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ |
929 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ | 1062 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ |
930 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) | 1063 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) |
931 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\ | 1064 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\ |
932 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ | 1065 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ |
933 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ | 1066 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ |
934 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ | 1067 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ |
@@ -945,7 +1078,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode); | |||
945 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ | 1078 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ |
946 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ | 1079 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ |
947 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) | 1080 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) |
948 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ | 1081 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ |
949 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ | 1082 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ |
950 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ | 1083 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ |
951 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ | 1084 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ |
@@ -954,42 +1087,44 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode); | |||
954 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) | 1087 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) |
955 | 1088 | ||
956 | 1089 | ||
957 | #define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \ | ||
958 | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \ | ||
959 | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG) | ||
960 | |||
961 | |||
962 | #define MULTI_FLAGS \ | 1090 | #define MULTI_FLAGS \ |
963 | (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ | 1091 | (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ |
964 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ | 1092 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ |
965 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ | 1093 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ |
966 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ | 1094 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ |
967 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE) | 1095 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE) |
968 | 1096 | ||
969 | #define MULTI_MASK 0x7f | 1097 | #define MULTI_MASK 0x7f |
970 | 1098 | ||
971 | 1099 | ||
972 | #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS | 1100 | #define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES) |
973 | #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS | 1101 | #define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES) |
974 | #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH | 1102 | #define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES) |
975 | 1103 | #define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES) | |
976 | #define BNX2X_RX_SB_INDEX \ | ||
977 | &fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX] | ||
978 | 1104 | ||
979 | #define BNX2X_TX_SB_INDEX \ | 1105 | #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH |
980 | &fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX] | ||
981 | 1106 | ||
982 | #define BNX2X_SP_DSB_INDEX \ | 1107 | #define BNX2X_SP_DSB_INDEX \ |
983 | &bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX] | 1108 | (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]) |
984 | 1109 | ||
985 | 1110 | ||
986 | #define CAM_IS_INVALID(x) \ | 1111 | #define CAM_IS_INVALID(x) \ |
987 | (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) | 1112 | (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) |
988 | 1113 | ||
989 | #define CAM_INVALIDATE(x) \ | 1114 | #define CAM_INVALIDATE(x) \ |
990 | x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE | 1115 | (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) |
1116 | |||
1117 | |||
1118 | /* Number of u32 elements in MC hash array */ | ||
1119 | #define MC_HASH_SIZE 8 | ||
1120 | #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ | ||
1121 | TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) | ||
991 | 1122 | ||
992 | 1123 | ||
1124 | #ifndef PXP2_REG_PXP2_INT_STS | ||
1125 | #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 | ||
1126 | #endif | ||
1127 | |||
993 | /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */ | 1128 | /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */ |
994 | 1129 | ||
995 | #endif /* bnx2x.h */ | 1130 | #endif /* bnx2x.h */ |