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Diffstat (limited to 'drivers/net/bnx2x.h')
-rw-r--r--drivers/net/bnx2x.h10
1 files changed, 0 insertions, 10 deletions
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 88eeee9197c8..e07d91582cf2 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -96,12 +96,10 @@
96 96
97#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 97#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
98#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 98#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
99#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
100 99
101#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 100#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
102#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 101#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
103#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 102#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
104#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
105 103
106#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 104#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
107#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 105#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
@@ -267,11 +265,6 @@ struct bnx2x_fastpath {
267 u8 index; /* number in fp array */ 265 u8 index; /* number in fp array */
268 u8 cl_id; /* eth client id */ 266 u8 cl_id; /* eth client id */
269 u8 sb_id; /* status block number in HW */ 267 u8 sb_id; /* status block number in HW */
270#define FP_IDX(fp) (fp->index)
271#define FP_CL_ID(fp) (fp->cl_id)
272#define BP_CL_ID(bp) (bp->fp[0].cl_id)
273#define FP_SB_ID(fp) (fp->sb_id)
274#define CNIC_SB_ID 0
275 268
276 u16 tx_pkt_prod; 269 u16 tx_pkt_prod;
277 u16 tx_pkt_cons; 270 u16 tx_pkt_cons;
@@ -1128,9 +1121,6 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1128#define BNX2X_MCP_ASSERT \ 1121#define BNX2X_MCP_ASSERT \
1129 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 1122 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1130 1123
1131#define BNX2X_DOORQ_ASSERT \
1132 AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
1133
1134#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 1124#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1135#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 1125#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1136 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 1126 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \