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Diffstat (limited to 'drivers/net/bnx2x.h')
-rw-r--r--drivers/net/bnx2x.h56
1 files changed, 30 insertions, 26 deletions
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 4f7ae6f77452..4f0c0d31e7c1 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -1,6 +1,6 @@
1/* bnx2x.h: Broadcom Everest network driver. 1/* bnx2x.h: Broadcom Everest network driver.
2 * 2 *
3 * Copyright (c) 2007 Broadcom Corporation 3 * Copyright (c) 2007-2008 Broadcom Corporation
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by 6 * it under the terms of the GNU General Public License as published by
@@ -24,6 +24,8 @@
24#define BNX2X_MSG_STATS 0x20000 /* was: NETIF_MSG_TIMER */ 24#define BNX2X_MSG_STATS 0x20000 /* was: NETIF_MSG_TIMER */
25#define NETIF_MSG_NVM 0x40000 /* was: NETIF_MSG_HW */ 25#define NETIF_MSG_NVM 0x40000 /* was: NETIF_MSG_HW */
26#define NETIF_MSG_DMAE 0x80000 /* was: NETIF_MSG_HW */ 26#define NETIF_MSG_DMAE 0x80000 /* was: NETIF_MSG_HW */
27#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
28#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
27 29
28#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ 30#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
29 31
@@ -40,6 +42,12 @@
40 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \ 42 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
41 } while (0) 43 } while (0)
42 44
45/* for logging (never masked) */
46#define BNX2X_LOG(__fmt, __args...) do { \
47 printk(KERN_NOTICE "[%s:%d(%s)]" __fmt, __FUNCTION__, \
48 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
49 } while (0)
50
43/* before we have a dev->name use dev_info() */ 51/* before we have a dev->name use dev_info() */
44#define BNX2X_DEV_INFO(__fmt, __args...) do { \ 52#define BNX2X_DEV_INFO(__fmt, __args...) do { \
45 if (bp->msglevel & NETIF_MSG_PROBE) \ 53 if (bp->msglevel & NETIF_MSG_PROBE) \
@@ -423,8 +431,6 @@ struct bnx2x_fastpath {
423#define BNX2X_FP_STATE_OPEN 0xa0000 431#define BNX2X_FP_STATE_OPEN 0xa0000
424#define BNX2X_FP_STATE_HALTING 0xb0000 432#define BNX2X_FP_STATE_HALTING 0xb0000
425#define BNX2X_FP_STATE_HALTED 0xc0000 433#define BNX2X_FP_STATE_HALTED 0xc0000
426#define BNX2X_FP_STATE_DELETED 0xd0000
427#define BNX2X_FP_STATE_CLOSE_IRQ 0xe0000
428 434
429 int index; 435 int index;
430 436
@@ -505,7 +511,6 @@ struct bnx2x {
505 struct eth_spe *spq; 511 struct eth_spe *spq;
506 dma_addr_t spq_mapping; 512 dma_addr_t spq_mapping;
507 u16 spq_prod_idx; 513 u16 spq_prod_idx;
508 u16 dsb_sp_prod_idx;
509 struct eth_spe *spq_prod_bd; 514 struct eth_spe *spq_prod_bd;
510 struct eth_spe *spq_last_bd; 515 struct eth_spe *spq_last_bd;
511 u16 *dsb_sp_prod; 516 u16 *dsb_sp_prod;
@@ -517,7 +522,7 @@ struct bnx2x {
517 */ 522 */
518 u8 stat_pending; 523 u8 stat_pending;
519 524
520 /* End of fileds used in the performance code paths */ 525 /* End of fields used in the performance code paths */
521 526
522 int panic; 527 int panic;
523 int msglevel; 528 int msglevel;
@@ -540,8 +545,6 @@ struct bnx2x {
540 spinlock_t phy_lock; 545 spinlock_t phy_lock;
541 546
542 struct work_struct reset_task; 547 struct work_struct reset_task;
543 u16 in_reset_task;
544
545 struct work_struct sp_task; 548 struct work_struct sp_task;
546 549
547 struct timer_list timer; 550 struct timer_list timer;
@@ -555,7 +558,6 @@ struct bnx2x {
555#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0) 558#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
556 559
557#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000) 560#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
558#define CHIP_NUM_5710 0x57100000
559 561
560#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000) 562#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
561#define CHIP_REV_Ax 0x00000000 563#define CHIP_REV_Ax 0x00000000
@@ -574,7 +576,8 @@ struct bnx2x {
574 u32 fw_mb; 576 u32 fw_mb;
575 577
576 u32 hw_config; 578 u32 hw_config;
577 u32 serdes_config; 579 u32 board;
580 u32 serdes_config;
578 u32 lane_config; 581 u32 lane_config;
579 u32 ext_phy_config; 582 u32 ext_phy_config;
580#define XGXS_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \ 583#define XGXS_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \
@@ -595,11 +598,11 @@ struct bnx2x {
595 u8 tx_lane_swap; 598 u8 tx_lane_swap;
596 599
597 u8 link_up; 600 u8 link_up;
601 u8 phy_link_up;
598 602
599 u32 supported; 603 u32 supported;
600/* link settings - missing defines */ 604/* link settings - missing defines */
601#define SUPPORTED_2500baseT_Full (1 << 15) 605#define SUPPORTED_2500baseT_Full (1 << 15)
602#define SUPPORTED_CX4 (1 << 16)
603 606
604 u32 phy_flags; 607 u32 phy_flags;
605/*#define PHY_SERDES_FLAG 0x1*/ 608/*#define PHY_SERDES_FLAG 0x1*/
@@ -644,16 +647,9 @@ struct bnx2x {
644#define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH 647#define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
645#define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE 648#define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
646 649
647 u32 pause_mode;
648#define PAUSE_NONE 0
649#define PAUSE_SYMMETRIC 1
650#define PAUSE_ASYMMETRIC 2
651#define PAUSE_BOTH 3
652
653 u32 advertising; 650 u32 advertising;
654/* link settings - missing defines */ 651/* link settings - missing defines */
655#define ADVERTISED_2500baseT_Full (1 << 15) 652#define ADVERTISED_2500baseT_Full (1 << 15)
656#define ADVERTISED_CX4 (1 << 16)
657 653
658 u32 link_status; 654 u32 link_status;
659 u32 line_speed; 655 u32 line_speed;
@@ -667,6 +663,8 @@ struct bnx2x {
667#define NVRAM_TIMEOUT_COUNT 30000 663#define NVRAM_TIMEOUT_COUNT 30000
668#define NVRAM_PAGE_SIZE 256 664#define NVRAM_PAGE_SIZE 256
669 665
666 u8 wol;
667
670 int rx_ring_size; 668 int rx_ring_size;
671 669
672 u16 tx_quick_cons_trip_int; 670 u16 tx_quick_cons_trip_int;
@@ -718,9 +716,6 @@ struct bnx2x {
718#endif 716#endif
719 717
720 char *name; 718 char *name;
721 u16 bus_speed_mhz;
722 u8 wol;
723 u8 pad;
724 719
725 /* used to synchronize stats collecting */ 720 /* used to synchronize stats collecting */
726 int stats_state; 721 int stats_state;
@@ -856,8 +851,8 @@ struct bnx2x {
856#define MAX_SPQ_PENDING 8 851#define MAX_SPQ_PENDING 8
857 852
858 853
859#define BNX2X_NUM_STATS 31 854#define BNX2X_NUM_STATS 34
860#define BNX2X_NUM_TESTS 2 855#define BNX2X_NUM_TESTS 1
861 856
862 857
863#define DPM_TRIGER_TYPE 0x40 858#define DPM_TRIGER_TYPE 0x40
@@ -867,6 +862,15 @@ struct bnx2x {
867 DPM_TRIGER_TYPE); \ 862 DPM_TRIGER_TYPE); \
868 } while (0) 863 } while (0)
869 864
865/* PCIE link and speed */
866#define PCICFG_LINK_WIDTH 0x1f00000
867#define PCICFG_LINK_WIDTH_SHIFT 20
868#define PCICFG_LINK_SPEED 0xf0000
869#define PCICFG_LINK_SPEED_SHIFT 16
870
871#define BMAC_CONTROL_RX_ENABLE 2
872
873#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
870 874
871/* stuff added to make the code fit 80Col */ 875/* stuff added to make the code fit 80Col */
872 876
@@ -939,13 +943,13 @@ struct bnx2x {
939#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD 943#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
940#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD 944#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
941 945
942#define NIG_STATUS_INTERRUPT_XGXS0_LINK10G \ 946#define NIG_STATUS_XGXS0_LINK10G \
943 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G 947 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
944#define NIG_XGXS0_LINK_STATUS \ 948#define NIG_STATUS_XGXS0_LINK_STATUS \
945 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS 949 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
946#define NIG_XGXS0_LINK_STATUS_SIZE \ 950#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
947 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 951 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
948#define NIG_SERDES0_LINK_STATUS \ 952#define NIG_STATUS_SERDES0_LINK_STATUS \
949 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS 953 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
950#define NIG_MASK_MI_INT \ 954#define NIG_MASK_MI_INT \
951 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT 955 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT