1 files changed, 84 insertions, 31 deletions

diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index 2377cc13bf61..c3c579f98ed0 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -309,6 +309,7 @@ struct l2_fhdr {
 #endif
 };
 
+#define BNX2_RX_OFFSET          (sizeof(struct l2_fhdr) + 2)
 
 /*
  *  l2_context definition
@@ -4157,6 +4158,23 @@ struct l2_fhdr {
 
 
 /*
+ *  rlup_reg definition
+ *  offset: 0x2000
+ */
+#define BNX2_RLUP_RSS_CONFIG                            0x0000201c
+#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_XI            (0x3L<<0)
+#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI        (0L<<0)
+#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI        (1L<<0)
+#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_IP_ONLY_XI    (2L<<0)
+#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_RES_XI        (3L<<0)
+#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_XI            (0x3L<<2)
+#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI        (0L<<2)
+#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI        (1L<<2)
+#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI    (2L<<2)
+#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI        (3L<<2)
+
+
+/*
  *  rbuf_reg definition
  *  offset: 0x200000
  */
@@ -5527,6 +5545,9 @@ struct l2_fhdr {
 #define BNX2_HC_TX_QUICK_CONS_TRIP_OFF  (BNX2_HC_TX_QUICK_CONS_TRIP_1 - \
                                          BNX2_HC_SB_CONFIG_1)
 #define BNX2_HC_TX_TICKS_OFF    (BNX2_HC_TX_TICKS_1 - BNX2_HC_SB_CONFIG_1)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_OFF  (BNX2_HC_RX_QUICK_CONS_TRIP_1 - \
+                                         BNX2_HC_SB_CONFIG_1)
+#define BNX2_HC_RX_TICKS_OFF    (BNX2_HC_RX_TICKS_1 - BNX2_HC_SB_CONFIG_1)
 
 
 /*
@@ -5855,6 +5876,9 @@ struct l2_fhdr {
 #define BNX2_RXP_FTQ_CTL_CUR_DEPTH                       (0x3ffL<<22)
 
 #define BNX2_RXP_SCRATCH                                0x000e0000
+#define BNX2_RXP_SCRATCH_RSS_TBL_SZ                      0x000e0038
+#define BNX2_RXP_SCRATCH_RSS_TBL                         0x000e003c
+#define BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES             128
 
 
 /*
@@ -6412,10 +6436,15 @@ struct l2_fhdr {
 #define MAX_ETHERNET_PACKET_SIZE        1514
 #define MAX_ETHERNET_JUMBO_PACKET_SIZE  9014
 
-#define RX_COPY_THRESH                  128
+#define BNX2_RX_COPY_THRESH             128
 
 #define BNX2_MISC_ENABLE_DEFAULT        0x17ffffff
 
+#define BNX2_START_UNICAST_ADDRESS_INDEX        4
+#define BNX2_END_UNICAST_ADDRESS_INDEX          7
+#define BNX2_MAX_UNICAST_ADDRESSES      (BNX2_END_UNICAST_ADDRESS_INDEX - \
+                                         BNX2_START_UNICAST_ADDRESS_INDEX + 1)
+
 #define DMA_READ_CHANS  5
 #define DMA_WRITE_CHANS 3
 
@@ -6478,6 +6507,11 @@ struct l2_fhdr {
 #define TX_CID          16
 #define TX_TSS_CID      32
 #define RX_CID          0
+#define RX_RSS_CID      4
+#define RX_MAX_RSS_RINGS        7
+#define RX_MAX_RINGS            (RX_MAX_RSS_RINGS + 1)
+#define TX_MAX_TSS_RINGS        7
+#define TX_MAX_RINGS            (TX_MAX_TSS_RINGS + 1)
 
 #define MB_TX_CID_ADDR  MB_GET_CID_ADDR(TX_CID)
 #define MB_RX_CID_ADDR  MB_GET_CID_ADDR(RX_CID)
@@ -6556,7 +6590,7 @@ struct flash_spec {
 };
 
 #define BNX2_MAX_MSIX_HW_VEC    9
-#define BNX2_MAX_MSIX_VEC       2
+#define BNX2_MAX_MSIX_VEC       9
 #define BNX2_BASE_VEC           0
 #define BNX2_TX_VEC             1
 #define BNX2_TX_INT_NUM (BNX2_TX_VEC << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT)
@@ -6568,24 +6602,56 @@ struct bnx2_irq {
         char            name[16];
 };
 
-struct bnx2_napi {
-        struct napi_struct      napi            ____cacheline_aligned;
-        struct bnx2             *bp;
-        struct status_block     *status_blk;
-        struct status_block_msix        *status_blk_msix;
-        u32                     last_status_idx;
-        u32                     int_num;
+struct bnx2_tx_ring_info {
+        u32                     tx_prod_bseq;
+        u16                     tx_prod;
+        u32                     tx_bidx_addr;
+        u32                     tx_bseq_addr;
+
+        struct tx_bd            *tx_desc_ring;
+        struct sw_bd            *tx_buf_ring;
 
         u16                     tx_cons;
         u16                     hw_tx_cons;
 
+        dma_addr_t              tx_desc_mapping;
+};
+
+struct bnx2_rx_ring_info {
         u32                     rx_prod_bseq;
         u16                     rx_prod;
         u16                     rx_cons;
 
+        u32                     rx_bidx_addr;
+        u32                     rx_bseq_addr;
+        u32                     rx_pg_bidx_addr;
+
         u16                     rx_pg_prod;
         u16                     rx_pg_cons;
 
+        struct sw_bd            *rx_buf_ring;
+        struct rx_bd            *rx_desc_ring[MAX_RX_RINGS];
+        struct sw_pg            *rx_pg_ring;
+        struct rx_bd            *rx_pg_desc_ring[MAX_RX_PG_RINGS];
+
+        dma_addr_t              rx_desc_mapping[MAX_RX_RINGS];
+        dma_addr_t              rx_pg_desc_mapping[MAX_RX_PG_RINGS];
+};
+
+struct bnx2_napi {
+        struct napi_struct      napi            ____cacheline_aligned;
+        struct bnx2             *bp;
+        union {
+                struct status_block             *msi;
+                struct status_block_msix        *msix;
+        } status_blk;
+        u16                     *hw_tx_cons_ptr;
+        u16                     *hw_rx_cons_ptr;
+        u32                     last_status_idx;
+        u32                     int_num;
+
+        struct bnx2_rx_ring_info        rx_ring;
+        struct bnx2_tx_ring_info        tx_ring;
 };
 
 struct bnx2 {
@@ -6612,14 +6678,7 @@ struct bnx2 {
 #define BNX2_FLAG_USING_MSI_OR_MSIX     (BNX2_FLAG_USING_MSI | \
                                          BNX2_FLAG_USING_MSIX)
 #define BNX2_FLAG_JUMBO_BROKEN          0x00000800
-
-        /* Put tx producer and consumer fields in separate cache lines. */
-
-        u32             tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
-        u16             tx_prod;
-        u8              tx_vec;
-        u32             tx_bidx_addr;
-        u32             tx_bseq_addr;
+#define BNX2_FLAG_CAN_KEEP_VLAN         0x00001000
 
         struct bnx2_napi        bnx2_napi[BNX2_MAX_MSIX_VEC];
 
@@ -6627,7 +6686,6 @@ struct bnx2 {
         struct                  vlan_group *vlgrp;
 #endif
 
-        u32                     rx_offset;
         u32                     rx_buf_use_size;        /* useable size */
         u32                     rx_buf_size;            /* with alignment */
         u32                     rx_copy_thresh;
@@ -6637,14 +6695,7 @@ struct bnx2 {
 
         u32                     rx_csum;
 
-        struct sw_bd            *rx_buf_ring;
-        struct rx_bd            *rx_desc_ring[MAX_RX_RINGS];
-        struct sw_pg            *rx_pg_ring;
-        struct rx_bd            *rx_pg_desc_ring[MAX_RX_PG_RINGS];
-
         /* TX constants */
-        struct tx_bd    *tx_desc_ring;
-        struct sw_bd    *tx_buf_ring;
         int             tx_ring_size;
         u32             tx_wake_thresh;
 
@@ -6722,16 +6773,11 @@ struct bnx2 {
         u16                     fw_wr_seq;
         u16                     fw_drv_pulse_wr_seq;
 
-        dma_addr_t              tx_desc_mapping;
-
-
         int                     rx_max_ring;
         int                     rx_ring_size;
-        dma_addr_t              rx_desc_mapping[MAX_RX_RINGS];
 
         int                     rx_max_pg_ring;
         int                     rx_pg_ring_size;
-        dma_addr_t              rx_pg_desc_mapping[MAX_RX_PG_RINGS];
 
         u16                     tx_quick_cons_trip;
         u16                     tx_quick_cons_trip_int;
@@ -6750,7 +6796,6 @@ struct bnx2 {
 
         u32                     stats_ticks;
 
-        struct status_block     *status_blk;
         dma_addr_t              status_blk_mapping;
 
         struct statistics_block *stats_blk;
@@ -6812,6 +6857,9 @@ struct bnx2 {
 
         struct bnx2_irq         irq_tbl[BNX2_MAX_MSIX_VEC];
         int                     irq_nvecs;
+
+        u8                      num_tx_rings;
+        u8                      num_rx_rings;
 };
 
 #define REG_RD(bp, offset)                                      \
@@ -6912,6 +6960,7 @@ struct fw_info {
 #define BNX2_DRV_MSG_CODE_DIAG                   0x07000000
 #define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL         0x09000000
 #define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN          0x0b000000
+#define BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE       0x0d000000
 #define BNX2_DRV_MSG_CODE_CMD_SET_LINK           0x10000000
 
 #define BNX2_DRV_MSG_DATA                        0x00ff0000
@@ -7240,6 +7289,10 @@ struct fw_info {
 #define BNX2_FW_CAP_SIGNATURE_MASK               0xffff0000
 #define BNX2_FW_CAP_REMOTE_PHY_CAPABLE           0x00000001
 #define BNX2_FW_CAP_REMOTE_PHY_PRESENT           0x00000002
+#define BNX2_FW_CAP_MFW_CAN_KEEP_VLAN            0x00000008
+#define BNX2_FW_CAP_BC_CAN_KEEP_VLAN             0x00000010
+#define BNX2_FW_CAP_CAN_KEEP_VLAN       (BNX2_FW_CAP_BC_CAN_KEEP_VLAN | \
+                                         BNX2_FW_CAP_MFW_CAN_KEEP_VLAN)
 
 #define BNX2_RPHY_SIGNATURE                     0x36c
 #define BNX2_RPHY_LOAD_SIGNATURE                 0x5a5a5a5a