1 files changed, 2749 insertions, 191 deletions

diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index ca31904893ea..13b6f9b11e01 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -56,6 +56,7 @@ struct rx_bd {
 
 };
 
+#define BNX2_RX_ALIGN                   16
 
 /*
  *  status_block definition
@@ -90,6 +91,7 @@ struct status_block {
                 #define STATUS_ATTN_BITS_DMAE_ABORT             (1L<<25)
                 #define STATUS_ATTN_BITS_FLSH_ABORT             (1L<<26)
                 #define STATUS_ATTN_BITS_GRC_ABORT              (1L<<27)
+                #define STATUS_ATTN_BITS_EPB_ERROR              (1L<<30)
                 #define STATUS_ATTN_BITS_PARITY_ERROR           (1L<<31)
 
         u32 status_attn_bits_ack;
@@ -117,7 +119,8 @@ struct status_block {
         u16 status_completion_producer_index;
         u16 status_cmd_consumer_index;
         u16 status_idx;
-        u16 status_unused;
+        u8 status_unused;
+        u8 status_blk_num;
 #elif defined(__LITTLE_ENDIAN)
         u16 status_tx_quick_consumer_index1;
         u16 status_tx_quick_consumer_index0;
@@ -141,7 +144,8 @@ struct status_block {
         u16 status_rx_quick_consumer_index14;
         u16 status_cmd_consumer_index;
         u16 status_completion_producer_index;
-        u16 status_unused;
+        u8 status_blk_num;
+        u8 status_unused;
         u16 status_idx;
 #endif
 };
@@ -301,6 +305,10 @@ struct l2_fhdr {
 #define BNX2_L2CTX_TXP_BIDX                             0x000000a8
 #define BNX2_L2CTX_TXP_BSEQ                             0x000000ac
 
+#define BNX2_L2CTX_TYPE_XI                              0x00000080
+#define BNX2_L2CTX_CMD_TYPE_XI                          0x00000240
+#define BNX2_L2CTX_TBDR_BHADDR_HI_XI                    0x00000258
+#define BNX2_L2CTX_TBDR_BHADDR_LO_XI                    0x0000025c
 
 /*
  *  l2_bd_chain_context definition
@@ -328,11 +336,15 @@ struct l2_fhdr {
 #define BNX2_PCICFG_MISC_CONFIG                         0x00000068
 #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP         (1L<<2)
 #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP      (1L<<3)
+#define BNX2_PCICFG_MISC_CONFIG_RESERVED1                (1L<<4)
 #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA            (1L<<5)
 #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP     (1L<<6)
 #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA           (1L<<7)
 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ             (1L<<8)
 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY             (1L<<9)
+#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN         (1L<<10)
+#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN         (1L<<11)
+#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN         (1L<<12)
 #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV           (0xffL<<16)
 #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV            (0xfL<<24)
 #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID                  (0xfL<<28)
@@ -347,6 +359,7 @@ struct l2_fhdr {
 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100           (1L<<4)
 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133           (2L<<4)
 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE      (3L<<4)
+#define BNX2_PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE         (1L<<8)
 
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS              0x00000070
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET       (0xfL<<0)
@@ -366,7 +379,7 @@ struct l2_fhdr {
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12   (1L<<8)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6    (2L<<8)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62   (4L<<8)
-#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD     (1L<<11)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER     (1L<<11)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED    (0xfL<<12)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100        (0L<<12)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80         (1L<<12)
@@ -374,18 +387,21 @@ struct l2_fhdr {
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40         (4L<<12)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25         (8L<<12)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP     (1L<<16)
-#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP  (1L<<17)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17   (1L<<17)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18   (1L<<18)
-#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET   (1L<<19)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19   (1L<<19)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED      (0xfffL<<20)
 
 #define BNX2_PCICFG_REG_WINDOW_ADDRESS                  0x00000078
+#define BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL               (0xfffffL<<2)
+
 #define BNX2_PCICFG_REG_WINDOW                          0x00000080
 #define BNX2_PCICFG_INT_ACK_CMD                         0x00000084
 #define BNX2_PCICFG_INT_ACK_CMD_INDEX                    (0xffffL<<0)
 #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID              (1L<<16)
 #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM         (1L<<17)
 #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT                 (1L<<18)
+#define BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM            (0xfL<<24)
 
 #define BNX2_PCICFG_STATUS_BIT_SET_CMD                  0x00000088
 #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD                0x0000008c
@@ -398,9 +414,11 @@ struct l2_fhdr {
  *  offset: 0x400
  */
 #define BNX2_PCI_GRC_WINDOW_ADDR                        0x00000400
-#define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE       (0x3ffffL<<8)
+#define BNX2_PCI_GRC_WINDOW_ADDR_VALUE                   (0x1ffL<<13)
+#define BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN                 (1L<<31)
 
 #define BNX2_PCI_CONFIG_1                               0x00000404
+#define BNX2_PCI_CONFIG_1_RESERVED0                      (0xffL<<0)
 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY                  (0x7L<<8)
 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF              (0L<<8)
 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16               (1L<<8)
@@ -419,6 +437,7 @@ struct l2_fhdr {
 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256             (5L<<11)
 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512             (6L<<11)
 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024            (7L<<11)
+#define BNX2_PCI_CONFIG_1_RESERVED1                      (0x3ffffL<<14)
 
 #define BNX2_PCI_CONFIG_2                               0x00000408
 #define BNX2_PCI_CONFIG_2_BAR1_SIZE                      (0xfL<<0)
@@ -468,9 +487,13 @@ struct l2_fhdr {
 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR              (1L<<23)
 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT               (1L<<24)
 #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT                (1L<<25)
+#define BNX2_PCI_CONFIG_2_RESERVED0                      (0x3fL<<26)
+#define BNX2_PCI_CONFIG_2_BAR_PREFETCH_XI                (1L<<16)
+#define BNX2_PCI_CONFIG_2_RESERVED0_XI                   (0x7fffL<<17)
 
 #define BNX2_PCI_CONFIG_3                               0x0000040c
 #define BNX2_PCI_CONFIG_3_STICKY_BYTE                    (0xffL<<0)
+#define BNX2_PCI_CONFIG_3_REG_STICKY_BYTE                (0xffL<<8)
 #define BNX2_PCI_CONFIG_3_FORCE_PME                      (1L<<24)
 #define BNX2_PCI_CONFIG_3_PME_STATUS                     (1L<<25)
 #define BNX2_PCI_CONFIG_3_PME_ENABLE                     (1L<<26)
@@ -501,8 +524,10 @@ struct l2_fhdr {
 #define BNX2_PCI_VPD_INTF_INTF_REQ                       (1L<<0)
 
 #define BNX2_PCI_VPD_ADDR_FLAG                          0x0000042c
-#define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS                   (0x1fff<<2)
-#define BNX2_PCI_VPD_ADDR_FLAG_WR                        (1<<15)
+#define BNX2_PCI_VPD_ADDR_FLAG_MSK                      0x0000ffff
+#define BNX2_PCI_VPD_ADDR_FLAG_SL                       0L
+#define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS                   (0x1fffL<<2)
+#define BNX2_PCI_VPD_ADDR_FLAG_WR                        (1L<<15)
 
 #define BNX2_PCI_VPD_DATA                               0x00000430
 #define BNX2_PCI_ID_VAL1                                0x00000434
@@ -535,19 +560,26 @@ struct l2_fhdr {
 #define BNX2_PCI_ID_VAL4_CAP_ENA_13                      (13L<<0)
 #define BNX2_PCI_ID_VAL4_CAP_ENA_14                      (14L<<0)
 #define BNX2_PCI_ID_VAL4_CAP_ENA_15                      (15L<<0)
+#define BNX2_PCI_ID_VAL4_RESERVED0                       (0x3L<<4)
 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG                    (0x3L<<6)
 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0                  (0L<<6)
 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1                  (1L<<6)
 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2                  (2L<<6)
 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3                  (3L<<6)
+#define BNX2_PCI_ID_VAL4_MSI_PV_MASK_CAP                 (1L<<8)
 #define BNX2_PCI_ID_VAL4_MSI_LIMIT                       (0x7L<<9)
-#define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE                   (0x7L<<12)
+#define BNX2_PCI_ID_VAL4_MULTI_MSG_CAP                   (0x7L<<12)
 #define BNX2_PCI_ID_VAL4_MSI_ENABLE                      (1L<<15)
 #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE                (1L<<16)
 #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE               (1L<<17)
-#define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE               (0x3L<<21)
-#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE                  (0x7L<<23)
-#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE             (0x7L<<26)
+#define BNX2_PCI_ID_VAL4_RESERVED2                       (0x7L<<18)
+#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21         (0x3L<<21)
+#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B21              (0x3L<<23)
+#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0          (1L<<25)
+#define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10           (0x3L<<26)
+#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B0               (1L<<28)
+#define BNX2_PCI_ID_VAL4_RESERVED3                       (0x7L<<29)
+#define BNX2_PCI_ID_VAL4_RESERVED3_XI                    (0xffffL<<16)
 
 #define BNX2_PCI_ID_VAL5                                0x00000444
 #define BNX2_PCI_ID_VAL5_D1_SUPPORT                      (1L<<0)
@@ -556,6 +588,10 @@ struct l2_fhdr {
 #define BNX2_PCI_ID_VAL5_PME_IN_D1                       (1L<<3)
 #define BNX2_PCI_ID_VAL5_PME_IN_D2                       (1L<<4)
 #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT                   (1L<<5)
+#define BNX2_PCI_ID_VAL5_RESERVED0_TE                    (0x3ffffffL<<6)
+#define BNX2_PCI_ID_VAL5_PM_VERSION_XI                   (0x7L<<6)
+#define BNX2_PCI_ID_VAL5_NO_SOFT_RESET_XI                (1L<<9)
+#define BNX2_PCI_ID_VAL5_RESERVED0_XI                    (0x3fffffL<<10)
 
 #define BNX2_PCI_PCIX_EXTENDED_STATUS                   0x00000448
 #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP           (1L<<8)
@@ -567,12 +603,91 @@ struct l2_fhdr {
 #define BNX2_PCI_ID_VAL6_MAX_LAT                         (0xffL<<0)
 #define BNX2_PCI_ID_VAL6_MIN_GNT                         (0xffL<<8)
 #define BNX2_PCI_ID_VAL6_BIST                            (0xffL<<16)
+#define BNX2_PCI_ID_VAL6_RESERVED0                       (0xffL<<24)
 
 #define BNX2_PCI_MSI_DATA                               0x00000450
-#define BNX2_PCI_MSI_DATA_PCI_MSI_DATA                   (0xffffL<<0)
+#define BNX2_PCI_MSI_DATA_MSI_DATA                       (0xffffL<<0)
 
 #define BNX2_PCI_MSI_ADDR_H                             0x00000454
 #define BNX2_PCI_MSI_ADDR_L                             0x00000458
+#define BNX2_PCI_MSI_ADDR_L_VAL                          (0x3fffffffL<<2)
+
+#define BNX2_PCI_CFG_ACCESS_CMD                         0x0000045c
+#define BNX2_PCI_CFG_ACCESS_CMD_ADR                      (0x3fL<<2)
+#define BNX2_PCI_CFG_ACCESS_CMD_RD_REQ                   (1L<<27)
+#define BNX2_PCI_CFG_ACCESS_CMD_WR_REQ                   (0xfL<<28)
+
+#define BNX2_PCI_CFG_ACCESS_DATA                        0x00000460
+#define BNX2_PCI_MSI_MASK                               0x00000464
+#define BNX2_PCI_MSI_MASK_MSI_MASK                       (0xffffffffL<<0)
+
+#define BNX2_PCI_MSI_PEND                               0x00000468
+#define BNX2_PCI_MSI_PEND_MSI_PEND                       (0xffffffffL<<0)
+
+#define BNX2_PCI_PM_DATA_C                              0x0000046c
+#define BNX2_PCI_PM_DATA_C_PM_DATA_8_PRG                 (0xffL<<0)
+#define BNX2_PCI_PM_DATA_C_RESERVED0                     (0xffffffL<<8)
+
+#define BNX2_PCI_MSIX_CONTROL                           0x000004c0
+#define BNX2_PCI_MSIX_CONTROL_MSIX_TBL_SIZ               (0x7ffL<<0)
+#define BNX2_PCI_MSIX_CONTROL_RESERVED0                  (0x1fffffL<<11)
+
+#define BNX2_PCI_MSIX_TBL_OFF_BIR                       0x000004c4
+#define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR           (0x7L<<0)
+#define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF           (0x1fffffffL<<3)
+
+#define BNX2_PCI_MSIX_PBA_OFF_BIT                       0x000004c8
+#define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR           (0x7L<<0)
+#define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF           (0x1fffffffL<<3)
+
+#define BNX2_PCI_PCIE_CAPABILITY                        0x000004d0
+#define BNX2_PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM       (0x1fL<<0)
+#define BNX2_PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1         (1L<<5)
+
+#define BNX2_PCI_DEVICE_CAPABILITY                      0x000004d4
+#define BNX2_PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED  (0x7L<<0)
+#define BNX2_PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT  (1L<<5)
+#define BNX2_PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY        (0x7L<<6)
+#define BNX2_PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY         (0x7L<<9)
+#define BNX2_PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT    (1L<<15)
+
+#define BNX2_PCI_LINK_CAPABILITY                        0x000004dc
+#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED          (0xfL<<0)
+#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001     (1L<<0)
+#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010     (1L<<0)
+#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_WIDTH          (0x1fL<<4)
+#define BNX2_PCI_LINK_CAPABILITY_CLK_POWER_MGMT          (1L<<9)
+#define BNX2_PCI_LINK_CAPABILITY_ASPM_SUPPORT            (0x3L<<10)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT            (0x7L<<12)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101        (5L<<12)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110        (6L<<12)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT             (0x7L<<15)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_001         (1L<<15)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_010         (2L<<15)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT       (0x7L<<18)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101   (5L<<18)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110   (6L<<18)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT        (0x7L<<21)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001    (1L<<21)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010    (2L<<21)
+#define BNX2_PCI_LINK_CAPABILITY_PORT_NUM                (0xffL<<24)
+
+#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2               0x000004e4
+#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP     (0xfL<<0)
+#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP    (1L<<4)
+#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED       (0x7ffffffL<<5)
+
+#define BNX2_PCI_PCIE_LINK_CAPABILITY_2                 0x000004e8
+#define BNX2_PCI_PCIE_LINK_CAPABILITY_2_RESERVED         (0xffffffffL<<0)
+
+#define BNX2_PCI_GRC_WINDOW1_ADDR                       0x00000610
+#define BNX2_PCI_GRC_WINDOW1_ADDR_VALUE                  (0x1ffL<<13)
+
+#define BNX2_PCI_GRC_WINDOW2_ADDR                       0x00000614
+#define BNX2_PCI_GRC_WINDOW2_ADDR_VALUE                  (0x1ffL<<13)
+
+#define BNX2_PCI_GRC_WINDOW3_ADDR                       0x00000618
+#define BNX2_PCI_GRC_WINDOW3_ADDR_VALUE                  (0x1ffL<<13)
 
 
 /*
@@ -582,13 +697,23 @@ struct l2_fhdr {
 #define BNX2_MISC_COMMAND                               0x00000800
 #define BNX2_MISC_COMMAND_ENABLE_ALL                     (1L<<0)
 #define BNX2_MISC_COMMAND_DISABLE_ALL                    (1L<<1)
-#define BNX2_MISC_COMMAND_CORE_RESET                     (1L<<4)
-#define BNX2_MISC_COMMAND_HARD_RESET                     (1L<<5)
+#define BNX2_MISC_COMMAND_SW_RESET                       (1L<<4)
+#define BNX2_MISC_COMMAND_POR_RESET                      (1L<<5)
+#define BNX2_MISC_COMMAND_HD_RESET                       (1L<<6)
+#define BNX2_MISC_COMMAND_CMN_SW_RESET                   (1L<<7)
 #define BNX2_MISC_COMMAND_PAR_ERROR                      (1L<<8)
+#define BNX2_MISC_COMMAND_CS16_ERR                       (1L<<9)
+#define BNX2_MISC_COMMAND_CS16_ERR_LOC                   (0xfL<<12)
 #define BNX2_MISC_COMMAND_PAR_ERR_RAM                    (0x7fL<<16)
+#define BNX2_MISC_COMMAND_POWERDOWN_EVENT                (1L<<23)
+#define BNX2_MISC_COMMAND_SW_SHUTDOWN                    (1L<<24)
+#define BNX2_MISC_COMMAND_SHUTDOWN_EN                    (1L<<25)
+#define BNX2_MISC_COMMAND_DINTEG_ATTN_EN                 (1L<<26)
+#define BNX2_MISC_COMMAND_PCIE_LINK_IN_L23               (1L<<27)
+#define BNX2_MISC_COMMAND_PCIE_DIS                       (1L<<28)
 
 #define BNX2_MISC_CFG                                   0x00000804
-#define BNX2_MISC_CFG_PCI_GRC_TMOUT                      (1L<<0)
+#define BNX2_MISC_CFG_GRC_TMOUT                          (1L<<0)
 #define BNX2_MISC_CFG_NVM_WR_EN                          (0x3L<<1)
 #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT                  (0L<<1)
 #define BNX2_MISC_CFG_NVM_WR_EN_PCI                      (1L<<1)
@@ -596,16 +721,45 @@ struct l2_fhdr {
 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2                   (3L<<1)
 #define BNX2_MISC_CFG_BIST_EN                            (1L<<3)
 #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC                   (1L<<4)
-#define BNX2_MISC_CFG_BYPASS_BSCAN                       (1L<<5)
-#define BNX2_MISC_CFG_BYPASS_EJTAG                       (1L<<6)
+#define BNX2_MISC_CFG_RESERVED5_TE                       (1L<<5)
+#define BNX2_MISC_CFG_RESERVED6_TE                       (1L<<6)
 #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE                   (1L<<7)
-#define BNX2_MISC_CFG_LEDMODE                            (0x3L<<8)
+#define BNX2_MISC_CFG_LEDMODE                            (0x7L<<8)
 #define BNX2_MISC_CFG_LEDMODE_MAC                        (0L<<8)
-#define BNX2_MISC_CFG_LEDMODE_GPHY1                      (1L<<8)
-#define BNX2_MISC_CFG_LEDMODE_GPHY2                      (2L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY1_TE                    (1L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY2_TE                    (2L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY3_TE                    (3L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY4_TE                    (4L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY5_TE                    (5L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY6_TE                    (6L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY7_TE                    (7L<<8)
+#define BNX2_MISC_CFG_MCP_GRC_TMOUT_TE                   (1L<<11)
+#define BNX2_MISC_CFG_DBU_GRC_TMOUT_TE                   (1L<<12)
+#define BNX2_MISC_CFG_LEDMODE_XI                         (0xfL<<8)
+#define BNX2_MISC_CFG_LEDMODE_MAC_XI                     (0L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY1_XI                    (1L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY2_XI                    (2L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY3_XI                    (3L<<8)
+#define BNX2_MISC_CFG_LEDMODE_MAC2_XI                    (4L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY4_XI                    (5L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY5_XI                    (6L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY6_XI                    (7L<<8)
+#define BNX2_MISC_CFG_LEDMODE_MAC3_XI                    (8L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY7_XI                    (9L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY8_XI                    (10L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY9_XI                    (11L<<8)
+#define BNX2_MISC_CFG_LEDMODE_MAC4_XI                    (12L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY10_XI                   (13L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY11_XI                   (14L<<8)
+#define BNX2_MISC_CFG_LEDMODE_UNUSED_XI                  (15L<<8)
+#define BNX2_MISC_CFG_PORT_SELECT_XI                     (1L<<13)
+#define BNX2_MISC_CFG_PARITY_MODE_XI                     (1L<<14)
 
 #define BNX2_MISC_ID                                    0x00000808
 #define BNX2_MISC_ID_BOND_ID                             (0xfL<<0)
+#define BNX2_MISC_ID_BOND_ID_X                           (0L<<0)
+#define BNX2_MISC_ID_BOND_ID_C                           (3L<<0)
+#define BNX2_MISC_ID_BOND_ID_S                           (12L<<0)
 #define BNX2_MISC_ID_CHIP_METAL                          (0xffL<<4)
 #define BNX2_MISC_ID_CHIP_REV                            (0xfL<<12)
 #define BNX2_MISC_ID_CHIP_NUM                            (0xffffL<<16)
@@ -639,6 +793,8 @@ struct l2_fhdr {
 #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE        (1L<<25)
 #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE   (1L<<26)
 #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE          (1L<<27)
+#define BNX2_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE   (1L<<28)
+#define BNX2_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE  (0x7L<<29)
 
 #define BNX2_MISC_ENABLE_SET_BITS                       0x00000810
 #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
@@ -669,6 +825,8 @@ struct l2_fhdr {
 #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE           (1L<<25)
 #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE      (1L<<26)
 #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE             (1L<<27)
+#define BNX2_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE      (1L<<28)
+#define BNX2_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE     (0x7L<<29)
 
 #define BNX2_MISC_ENABLE_CLR_BITS                       0x00000814
 #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
@@ -699,6 +857,8 @@ struct l2_fhdr {
 #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE           (1L<<25)
 #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE      (1L<<26)
 #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE             (1L<<27)
+#define BNX2_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE      (1L<<28)
+#define BNX2_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE     (0x7L<<29)
 
 #define BNX2_MISC_CLOCK_CONTROL_BITS                    0x00000818
 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET     (0xfL<<0)
@@ -718,30 +878,41 @@ struct l2_fhdr {
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12         (1L<<8)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6  (2L<<8)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62         (4L<<8)
-#define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD           (1L<<11)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI        (0x7L<<8)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_MIN_POWER           (1L<<11)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED  (0xfL<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100      (0L<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80       (1L<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50       (2L<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40       (4L<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25       (8L<<12)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI        (0xfL<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP   (1L<<16)
-#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP        (1L<<17)
-#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18         (1L<<18)
-#define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET         (1L<<19)
-#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED            (0xfffL<<20)
-
-#define BNX2_MISC_GPIO                                  0x0000081c
-#define BNX2_MISC_GPIO_VALUE                             (0xffL<<0)
-#define BNX2_MISC_GPIO_SET                               (0xffL<<8)
-#define BNX2_MISC_GPIO_CLR                               (0xffL<<16)
-#define BNX2_MISC_GPIO_FLOAT                             (0xffL<<24)
-
-#define BNX2_MISC_GPIO_INT                              0x00000820
-#define BNX2_MISC_GPIO_INT_INT_STATE                     (0xfL<<0)
-#define BNX2_MISC_GPIO_INT_OLD_VALUE                     (0xfL<<8)
-#define BNX2_MISC_GPIO_INT_OLD_SET                       (0xfL<<16)
-#define BNX2_MISC_GPIO_INT_OLD_CLR                       (0xfL<<24)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE      (1L<<17)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE      (1L<<18)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE      (1L<<19)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_TE         (0xfffL<<20)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI        (1L<<17)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI        (0x3fL<<18)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI         (0x7L<<24)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI        (1L<<27)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI       (0xfL<<28)
+
+#define BNX2_MISC_SPIO                                  0x0000081c
+#define BNX2_MISC_SPIO_VALUE                             (0xffL<<0)
+#define BNX2_MISC_SPIO_SET                               (0xffL<<8)
+#define BNX2_MISC_SPIO_CLR                               (0xffL<<16)
+#define BNX2_MISC_SPIO_FLOAT                             (0xffL<<24)
+
+#define BNX2_MISC_SPIO_INT                              0x00000820
+#define BNX2_MISC_SPIO_INT_INT_STATE_TE                  (0xfL<<0)
+#define BNX2_MISC_SPIO_INT_OLD_VALUE_TE                  (0xfL<<8)
+#define BNX2_MISC_SPIO_INT_OLD_SET_TE                    (0xfL<<16)
+#define BNX2_MISC_SPIO_INT_OLD_CLR_TE                    (0xfL<<24)
+#define BNX2_MISC_SPIO_INT_INT_STATE_XI                  (0xffL<<0)
+#define BNX2_MISC_SPIO_INT_OLD_VALUE_XI                  (0xffL<<8)
+#define BNX2_MISC_SPIO_INT_OLD_SET_XI                    (0xffL<<16)
+#define BNX2_MISC_SPIO_INT_OLD_CLR_XI                    (0xffL<<24)
 
 #define BNX2_MISC_CONFIG_LFSR                           0x00000824
 #define BNX2_MISC_CONFIG_LFSR_DIV                        (0xffffL<<0)
@@ -775,6 +946,8 @@ struct l2_fhdr {
 #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE            (1L<<25)
 #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE       (1L<<26)
 #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE              (1L<<27)
+#define BNX2_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE       (1L<<28)
+#define BNX2_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE      (0x7L<<29)
 
 #define BNX2_MISC_ARB_REQ0                              0x0000082c
 #define BNX2_MISC_ARB_REQ1                              0x00000830
@@ -831,22 +1004,12 @@ struct l2_fhdr {
 #define BNX2_MISC_ARB_GNT3_30                            (0x7L<<24)
 #define BNX2_MISC_ARB_GNT3_31                            (0x7L<<28)
 
-#define BNX2_MISC_PRBS_CONTROL                          0x00000878
-#define BNX2_MISC_PRBS_CONTROL_EN                        (1L<<0)
-#define BNX2_MISC_PRBS_CONTROL_RSTB                      (1L<<1)
-#define BNX2_MISC_PRBS_CONTROL_INV                       (1L<<2)
-#define BNX2_MISC_PRBS_CONTROL_ERR_CLR                   (1L<<3)
-#define BNX2_MISC_PRBS_CONTROL_ORDER                     (0x3L<<4)
-#define BNX2_MISC_PRBS_CONTROL_ORDER_7TH                 (0L<<4)
-#define BNX2_MISC_PRBS_CONTROL_ORDER_15TH                (1L<<4)
-#define BNX2_MISC_PRBS_CONTROL_ORDER_23RD                (2L<<4)
-#define BNX2_MISC_PRBS_CONTROL_ORDER_31ST                (3L<<4)
-
-#define BNX2_MISC_PRBS_STATUS                           0x0000087c
-#define BNX2_MISC_PRBS_STATUS_LOCK                       (1L<<0)
-#define BNX2_MISC_PRBS_STATUS_STKY                       (1L<<1)
-#define BNX2_MISC_PRBS_STATUS_ERRORS                     (0x3fffL<<2)
-#define BNX2_MISC_PRBS_STATUS_STATE                      (0xfL<<16)
+#define BNX2_MISC_RESERVED1                             0x00000878
+#define BNX2_MISC_RESERVED1_MISC_RESERVED1_VALUE         (0x3fL<<0)
+
+#define BNX2_MISC_RESERVED2                             0x0000087c
+#define BNX2_MISC_RESERVED2_PCIE_DIS                     (1L<<0)
+#define BNX2_MISC_RESERVED2_LINK_IN_L23                  (1L<<1)
 
 #define BNX2_MISC_SM_ASF_CONTROL                        0x00000880
 #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST                 (1L<<0)
@@ -857,13 +1020,15 @@ struct l2_fhdr {
 #define BNX2_MISC_SM_ASF_CONTROL_PL_TO                   (1L<<5)
 #define BNX2_MISC_SM_ASF_CONTROL_RT_TO                   (1L<<6)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT               (1L<<7)
-#define BNX2_MISC_SM_ASF_CONTROL_RES                     (0xfL<<8)
+#define BNX2_MISC_SM_ASF_CONTROL_STRETCH_EN              (1L<<8)
+#define BNX2_MISC_SM_ASF_CONTROL_STRETCH_PULSE           (1L<<9)
+#define BNX2_MISC_SM_ASF_CONTROL_RES                     (0x3L<<10)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN                  (1L<<12)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN               (1L<<13)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT        (1L<<14)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD            (1L<<15)
-#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1           (0x3fL<<16)
-#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2           (0x3fL<<24)
+#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1           (0x7fL<<16)
+#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2           (0x7fL<<23)
 #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0       (1L<<30)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN          (1L<<31)
 
@@ -891,13 +1056,13 @@ struct l2_fhdr {
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS                 (0xfL<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK              (0L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK      (1L<<20)
-#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK        (9L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW           (2L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP            (3L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT         (4L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST      (5L<<20)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK          (6L<<20)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK        (9L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST        (0xdL<<20)
-#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK          (0x6L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE              (1L<<24)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN                 (1L<<25)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN                 (1L<<26)
@@ -955,6 +1120,38 @@ struct l2_fhdr {
 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC                 (1L<<29)
 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM                 (1L<<30)
 #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS            (1L<<31)
+#define BNX2_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI          (1L<<0)
+#define BNX2_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI           (1L<<1)
+#define BNX2_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI     (1L<<2)
+#define BNX2_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI     (1L<<3)
+#define BNX2_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI         (1L<<4)
+#define BNX2_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI         (1L<<5)
+#define BNX2_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI        (1L<<6)
+#define BNX2_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI          (1L<<7)
+#define BNX2_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI         (1L<<8)
+#define BNX2_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI           (1L<<9)
+#define BNX2_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI          (1L<<10)
+#define BNX2_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI         (1L<<11)
+#define BNX2_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI          (1L<<12)
+#define BNX2_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI         (1L<<13)
+#define BNX2_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI        (1L<<14)
+#define BNX2_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI          (1L<<15)
+#define BNX2_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI         (1L<<16)
+#define BNX2_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI           (1L<<17)
+#define BNX2_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI            (1L<<18)
+#define BNX2_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI      (1L<<19)
+#define BNX2_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI      (1L<<20)
+#define BNX2_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI       (1L<<21)
+#define BNX2_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI      (1L<<22)
+#define BNX2_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI       (1L<<23)
+#define BNX2_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI       (1L<<24)
+#define BNX2_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI      (1L<<25)
+#define BNX2_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI      (1L<<26)
+#define BNX2_MISC_PERR_ENA0_TPBUF_PERR_EN_XI             (1L<<27)
+#define BNX2_MISC_PERR_ENA0_THBUF_PERR_EN_XI             (1L<<28)
+#define BNX2_MISC_PERR_ENA0_TDMA_PERR_EN_XI              (1L<<29)
+#define BNX2_MISC_PERR_ENA0_TBDC_PERR_EN_XI              (1L<<30)
+#define BNX2_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI           (1L<<31)
 
 #define BNX2_MISC_PERR_ENA1                             0x000008a8
 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS            (1L<<0)
@@ -989,6 +1186,35 @@ struct l2_fhdr {
 #define BNX2_MISC_PERR_ENA1_RXPQ_MISC                    (1L<<29)
 #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC                   (1L<<30)
 #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC                   (1L<<31)
+#define BNX2_MISC_PERR_ENA1_RBDC_PERR_EN_XI              (1L<<0)
+#define BNX2_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI        (1L<<2)
+#define BNX2_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI          (1L<<3)
+#define BNX2_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI           (1L<<4)
+#define BNX2_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI      (1L<<5)
+#define BNX2_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI      (1L<<6)
+#define BNX2_MISC_PERR_ENA1_TPATQ_PERR_EN_XI             (1L<<7)
+#define BNX2_MISC_PERR_ENA1_MCPQ_PERR_EN_XI              (1L<<8)
+#define BNX2_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI             (1L<<9)
+#define BNX2_MISC_PERR_ENA1_TXPQ_PERR_EN_XI              (1L<<10)
+#define BNX2_MISC_PERR_ENA1_COMTQ_PERR_EN_XI             (1L<<11)
+#define BNX2_MISC_PERR_ENA1_COMQ_PERR_EN_XI              (1L<<12)
+#define BNX2_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI             (1L<<13)
+#define BNX2_MISC_PERR_ENA1_RXPQ_PERR_EN_XI              (1L<<14)
+#define BNX2_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI            (1L<<15)
+#define BNX2_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI             (1L<<16)
+#define BNX2_MISC_PERR_ENA1_TASQ_PERR_EN_XI              (1L<<17)
+#define BNX2_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI             (1L<<18)
+#define BNX2_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI             (1L<<19)
+#define BNX2_MISC_PERR_ENA1_COMXQ_PERR_EN_XI             (1L<<20)
+#define BNX2_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI             (1L<<21)
+#define BNX2_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI            (1L<<22)
+#define BNX2_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI            (1L<<23)
+#define BNX2_MISC_PERR_ENA1_CPQ_PERR_EN_XI               (1L<<24)
+#define BNX2_MISC_PERR_ENA1_CSQ_PERR_EN_XI               (1L<<25)
+#define BNX2_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI          (1L<<26)
+#define BNX2_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI       (1L<<27)
+#define BNX2_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI           (1L<<28)
+#define BNX2_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI            (1L<<29)
 
 #define BNX2_MISC_PERR_ENA2                             0x000008ac
 #define BNX2_MISC_PERR_ENA2_COMQ_MISC                    (1L<<0)
@@ -1000,19 +1226,498 @@ struct l2_fhdr {
 #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC                   (1L<<6)
 #define BNX2_MISC_PERR_ENA2_TPATQ_MISC                   (1L<<7)
 #define BNX2_MISC_PERR_ENA2_TASQ_MISC                    (1L<<8)
+#define BNX2_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI          (1L<<0)
+#define BNX2_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI            (1L<<1)
+#define BNX2_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI            (1L<<2)
+#define BNX2_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI           (1L<<3)
+#define BNX2_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI         (1L<<4)
+#define BNX2_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI            (1L<<5)
+#define BNX2_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI       (1L<<6)
 
 #define BNX2_MISC_DEBUG_VECTOR_SEL                      0x000008b0
 #define BNX2_MISC_DEBUG_VECTOR_SEL_0                     (0xfffL<<0)
 #define BNX2_MISC_DEBUG_VECTOR_SEL_1                     (0xfffL<<12)
+#define BNX2_MISC_DEBUG_VECTOR_SEL_1_XI                  (0xfffL<<15)
 
 #define BNX2_MISC_VREG_CONTROL                          0x000008b4
 #define BNX2_MISC_VREG_CONTROL_1_2                       (0xfL<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_XI               (0xfL<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI        (0L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI        (1L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI        (2L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI         (3L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI         (4L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI         (5L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI         (6L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI           (7L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI        (8L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI        (9L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI        (10L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI        (11L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI       (12L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI       (13L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI       (14L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI       (15L<<0)
 #define BNX2_MISC_VREG_CONTROL_2_5                       (0xfL<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS14                (0L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS12                (1L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS10                (2L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS8                 (3L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS6                 (4L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS4                 (5L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS2                 (6L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_NOM                   (7L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS2                (8L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS4                (9L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS6                (10L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS8                (11L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS10               (12L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS12               (13L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS14               (14L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS16               (15L<<4)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT                  (0xfL<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14           (0L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS12           (1L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS10           (2L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS8            (3L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS6            (4L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS4            (5L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS2            (6L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_NOM              (7L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS2           (8L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS4           (9L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS6           (10L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS8           (11L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS10          (12L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS12          (13L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS14          (14L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS16          (15L<<8)
 
 #define BNX2_MISC_FINAL_CLK_CTL_VAL                     0x000008b8
 #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL       (0x3ffffffL<<6)
 
-#define BNX2_MISC_UNUSED0                               0x000008bc
+#define BNX2_MISC_GP_HW_CTL0                            0x000008bc
+#define BNX2_MISC_GP_HW_CTL0_TX_DRIVE                    (1L<<0)
+#define BNX2_MISC_GP_HW_CTL0_RMII_MODE                   (1L<<1)
+#define BNX2_MISC_GP_HW_CTL0_RMII_CRSDV_SEL              (1L<<2)
+#define BNX2_MISC_GP_HW_CTL0_RVMII_MODE                  (1L<<3)
+#define BNX2_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE  (1L<<4)
+#define BNX2_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE       (1L<<5)
+#define BNX2_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE    (1L<<6)
+#define BNX2_MISC_GP_HW_CTL0_RESERVED1_XI                (0x7L<<4)
+#define BNX2_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY         (1L<<7)
+#define BNX2_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE     (1L<<8)
+#define BNX2_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE         (1L<<9)
+#define BNX2_MISC_GP_HW_CTL0_LED_ACT_SEL_TE              (1L<<10)
+#define BNX2_MISC_GP_HW_CTL0_RESERVED2_XI                (0x7L<<8)
+#define BNX2_MISC_GP_HW_CTL0_UP1_DEF0                    (1L<<11)
+#define BNX2_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF          (1L<<12)
+#define BNX2_MISC_GP_HW_CTL0_FORCE2500_DEF               (1L<<13)
+#define BNX2_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF          (1L<<14)
+#define BNX2_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF         (1L<<15)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI                 (0xfL<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA             (0L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA           (1L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA           (3L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA           (5L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA           (7L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN           (15L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS             (1L<<20)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS             (1L<<21)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT                (0x3L<<22)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P            (0L<<22)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P            (1L<<22)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P            (2L<<22)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P            (3L<<22)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT                (0x3L<<24)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P            (0L<<24)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P            (1L<<24)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P            (2L<<24)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P            (3L<<24)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ            (0x3L<<26)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA      (0L<<26)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA      (1L<<26)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA      (2L<<26)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA      (3L<<26)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ           (0x3L<<28)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA     (0L<<28)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA     (1L<<28)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA     (2L<<28)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA     (3L<<28)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ            (0x3L<<30)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57       (0L<<30)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45       (1L<<30)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62       (2L<<30)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66       (3L<<30)
+
+#define BNX2_MISC_GP_HW_CTL1                            0x000008c0
+#define BNX2_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE         (1L<<0)
+#define BNX2_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE         (1L<<1)
+#define BNX2_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE          (1L<<2)
+#define BNX2_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE          (1L<<3)
+#define BNX2_MISC_GP_HW_CTL1_RESERVED_SOFT_XI            (0xffffL<<0)
+#define BNX2_MISC_GP_HW_CTL1_RESERVED_HARD_XI            (0xffffL<<16)
+
+#define BNX2_MISC_NEW_HW_CTL                            0x000008c4
+#define BNX2_MISC_NEW_HW_CTL_MAIN_POR_BYPASS             (1L<<0)
+#define BNX2_MISC_NEW_HW_CTL_RINGOSC_ENABLE              (1L<<1)
+#define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL0                (1L<<2)
+#define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL1                (1L<<3)
+#define BNX2_MISC_NEW_HW_CTL_RESERVED_SHARED             (0xfffL<<4)
+#define BNX2_MISC_NEW_HW_CTL_RESERVED_SPLIT              (0xffffL<<16)
+
+#define BNX2_MISC_NEW_CORE_CTL                          0x000008c8
+#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS      (1L<<0)
+#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ          (1L<<1)
+#define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN              (0x3fffL<<2)
+#define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC               (0xffffL<<16)
+
+#define BNX2_MISC_ECO_HW_CTL                            0x000008cc
+#define BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN          (1L<<0)
+#define BNX2_MISC_ECO_HW_CTL_RESERVED_SOFT               (0x7fffL<<1)
+#define BNX2_MISC_ECO_HW_CTL_RESERVED_HARD               (0xffffL<<16)
+
+#define BNX2_MISC_ECO_CORE_CTL                          0x000008d0
+#define BNX2_MISC_ECO_CORE_CTL_RESERVED_SOFT             (0xffffL<<0)
+#define BNX2_MISC_ECO_CORE_CTL_RESERVED_HARD             (0xffffL<<16)
+
+#define BNX2_MISC_PPIO                                  0x000008d4
+#define BNX2_MISC_PPIO_VALUE                             (0xfL<<0)
+#define BNX2_MISC_PPIO_SET                               (0xfL<<8)
+#define BNX2_MISC_PPIO_CLR                               (0xfL<<16)
+#define BNX2_MISC_PPIO_FLOAT                             (0xfL<<24)
+
+#define BNX2_MISC_PPIO_INT                              0x000008d8
+#define BNX2_MISC_PPIO_INT_INT_STATE                     (0xfL<<0)
+#define BNX2_MISC_PPIO_INT_OLD_VALUE                     (0xfL<<8)
+#define BNX2_MISC_PPIO_INT_OLD_SET                       (0xfL<<16)
+#define BNX2_MISC_PPIO_INT_OLD_CLR                       (0xfL<<24)
+
+#define BNX2_MISC_RESET_NUMS                            0x000008dc
+#define BNX2_MISC_RESET_NUMS_NUM_HARD_RESETS             (0x7L<<0)
+#define BNX2_MISC_RESET_NUMS_NUM_PCIE_RESETS             (0x7L<<4)
+#define BNX2_MISC_RESET_NUMS_NUM_PERSTB_RESETS           (0x7L<<8)
+#define BNX2_MISC_RESET_NUMS_NUM_CMN_RESETS              (0x7L<<12)
+#define BNX2_MISC_RESET_NUMS_NUM_PORT_RESETS             (0x7L<<16)
+
+#define BNX2_MISC_CS16_ERR                              0x000008e0
+#define BNX2_MISC_CS16_ERR_ENA_PCI                       (1L<<0)
+#define BNX2_MISC_CS16_ERR_ENA_RDMA                      (1L<<1)
+#define BNX2_MISC_CS16_ERR_ENA_TDMA                      (1L<<2)
+#define BNX2_MISC_CS16_ERR_ENA_EMAC                      (1L<<3)
+#define BNX2_MISC_CS16_ERR_ENA_CTX                       (1L<<4)
+#define BNX2_MISC_CS16_ERR_ENA_TBDR                      (1L<<5)
+#define BNX2_MISC_CS16_ERR_ENA_RBDC                      (1L<<6)
+#define BNX2_MISC_CS16_ERR_ENA_COM                       (1L<<7)
+#define BNX2_MISC_CS16_ERR_ENA_CP                        (1L<<8)
+#define BNX2_MISC_CS16_ERR_STA_PCI                       (1L<<16)
+#define BNX2_MISC_CS16_ERR_STA_RDMA                      (1L<<17)
+#define BNX2_MISC_CS16_ERR_STA_TDMA                      (1L<<18)
+#define BNX2_MISC_CS16_ERR_STA_EMAC                      (1L<<19)
+#define BNX2_MISC_CS16_ERR_STA_CTX                       (1L<<20)
+#define BNX2_MISC_CS16_ERR_STA_TBDR                      (1L<<21)
+#define BNX2_MISC_CS16_ERR_STA_RBDC                      (1L<<22)
+#define BNX2_MISC_CS16_ERR_STA_COM                       (1L<<23)
+#define BNX2_MISC_CS16_ERR_STA_CP                        (1L<<24)
+
+#define BNX2_MISC_SPIO_EVENT                            0x000008e4
+#define BNX2_MISC_SPIO_EVENT_ENABLE                      (0xffL<<0)
+
+#define BNX2_MISC_PPIO_EVENT                            0x000008e8
+#define BNX2_MISC_PPIO_EVENT_ENABLE                      (0xfL<<0)
+
+#define BNX2_MISC_DUAL_MEDIA_CTRL                       0x000008ec
+#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID                (0xffL<<0)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X              (0L<<0)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C              (3L<<0)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S              (12L<<0)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP         (0x7L<<8)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN          (1L<<11)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET         (1L<<12)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET         (1L<<13)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET            (1L<<14)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET            (1L<<15)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_LCPLL_RST              (1L<<16)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_RST            (1L<<17)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_RST            (1L<<18)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_RST               (1L<<19)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_RST               (1L<<20)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL               (0x7L<<21)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP              (1L<<24)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE         (1L<<25)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ        (0xfL<<26)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ      (1L<<26)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ      (2L<<26)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ      (4L<<26)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ      (8L<<26)
+
+#define BNX2_MISC_OTP_CMD1                              0x000008f0
+#define BNX2_MISC_OTP_CMD1_FMODE                         (0x7L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_IDLE                    (0L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_WRITE                   (1L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_INIT                    (2L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_SET                     (3L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_RST                     (4L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_VERIFY                  (5L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_RESERVED0               (6L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_RESERVED1               (7L<<0)
+#define BNX2_MISC_OTP_CMD1_USEPINS                       (1L<<8)
+#define BNX2_MISC_OTP_CMD1_PROGSEL                       (1L<<9)
+#define BNX2_MISC_OTP_CMD1_PROGSTART                     (1L<<10)
+#define BNX2_MISC_OTP_CMD1_PCOUNT                        (0x7L<<16)
+#define BNX2_MISC_OTP_CMD1_PBYP                          (1L<<19)
+#define BNX2_MISC_OTP_CMD1_VSEL                          (0xfL<<20)
+#define BNX2_MISC_OTP_CMD1_TM                            (0x7L<<27)
+#define BNX2_MISC_OTP_CMD1_SADBYP                        (1L<<30)
+#define BNX2_MISC_OTP_CMD1_DEBUG                         (1L<<31)
+
+#define BNX2_MISC_OTP_CMD2                              0x000008f4
+#define BNX2_MISC_OTP_CMD2_OTP_ROM_ADDR                  (0x3ffL<<0)
+#define BNX2_MISC_OTP_CMD2_DOSEL                         (0x7fL<<16)
+#define BNX2_MISC_OTP_CMD2_DOSEL_0                       (0L<<16)
+#define BNX2_MISC_OTP_CMD2_DOSEL_1                       (1L<<16)
+#define BNX2_MISC_OTP_CMD2_DOSEL_127                     (127L<<16)
+
+#define BNX2_MISC_OTP_STATUS                            0x000008f8
+#define BNX2_MISC_OTP_STATUS_DATA                        (0xffL<<0)
+#define BNX2_MISC_OTP_STATUS_VALID                       (1L<<8)
+#define BNX2_MISC_OTP_STATUS_BUSY                        (1L<<9)
+#define BNX2_MISC_OTP_STATUS_BUSYSM                      (1L<<10)
+#define BNX2_MISC_OTP_STATUS_DONE                        (1L<<11)
+
+#define BNX2_MISC_OTP_SHIFT1_CMD                        0x000008fc
+#define BNX2_MISC_OTP_SHIFT1_CMD_RESET_MODE_N            (1L<<0)
+#define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_DONE              (1L<<1)
+#define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_START             (1L<<2)
+#define BNX2_MISC_OTP_SHIFT1_CMD_LOAD_DATA               (1L<<3)
+#define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT            (0x1fL<<8)
+
+#define BNX2_MISC_OTP_SHIFT1_DATA                       0x00000900
+#define BNX2_MISC_OTP_SHIFT2_CMD                        0x00000904
+#define BNX2_MISC_OTP_SHIFT2_CMD_RESET_MODE_N            (1L<<0)
+#define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_DONE              (1L<<1)
+#define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_START             (1L<<2)
+#define BNX2_MISC_OTP_SHIFT2_CMD_LOAD_DATA               (1L<<3)
+#define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT            (0x1fL<<8)
+
+#define BNX2_MISC_OTP_SHIFT2_DATA                       0x00000908
+#define BNX2_MISC_BIST_CS0                              0x0000090c
+#define BNX2_MISC_BIST_CS0_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS0_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS0_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS0_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS0_MBIST_GO                      (1L<<9)
+#define BNX2_MISC_BIST_CS0_BIST_OVERRIDE                 (1L<<31)
+
+#define BNX2_MISC_BIST_MEMSTATUS0                       0x00000910
+#define BNX2_MISC_BIST_CS1                              0x00000914
+#define BNX2_MISC_BIST_CS1_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS1_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS1_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS1_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS1_MBIST_GO                      (1L<<9)
+
+#define BNX2_MISC_BIST_MEMSTATUS1                       0x00000918
+#define BNX2_MISC_BIST_CS2                              0x0000091c
+#define BNX2_MISC_BIST_CS2_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS2_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS2_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS2_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS2_MBIST_GO                      (1L<<9)
+
+#define BNX2_MISC_BIST_MEMSTATUS2                       0x00000920
+#define BNX2_MISC_BIST_CS3                              0x00000924
+#define BNX2_MISC_BIST_CS3_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS3_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS3_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS3_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS3_MBIST_GO                      (1L<<9)
+
+#define BNX2_MISC_BIST_MEMSTATUS3                       0x00000928
+#define BNX2_MISC_BIST_CS4                              0x0000092c
+#define BNX2_MISC_BIST_CS4_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS4_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS4_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS4_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS4_MBIST_GO                      (1L<<9)
+
+#define BNX2_MISC_BIST_MEMSTATUS4                       0x00000930
+#define BNX2_MISC_BIST_CS5                              0x00000934
+#define BNX2_MISC_BIST_CS5_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS5_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS5_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS5_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS5_MBIST_GO                      (1L<<9)
+
+#define BNX2_MISC_BIST_MEMSTATUS5                       0x00000938
+#define BNX2_MISC_MEM_TM0                               0x0000093c
+#define BNX2_MISC_MEM_TM0_PCIE_REPLAY_TM                 (0xfL<<0)
+#define BNX2_MISC_MEM_TM0_MCP_SCPAD                      (0xfL<<8)
+#define BNX2_MISC_MEM_TM0_UMP_TM                         (0xffL<<16)
+#define BNX2_MISC_MEM_TM0_HB_MEM_TM                      (0xfL<<24)
+
+#define BNX2_MISC_USPLL_CTRL                            0x00000940
+#define BNX2_MISC_USPLL_CTRL_PH_DET_DIS                  (1L<<0)
+#define BNX2_MISC_USPLL_CTRL_FREQ_DET_DIS                (1L<<1)
+#define BNX2_MISC_USPLL_CTRL_LCPX                        (0x3fL<<2)
+#define BNX2_MISC_USPLL_CTRL_RX                          (0x3L<<8)
+#define BNX2_MISC_USPLL_CTRL_VC_EN                       (1L<<10)
+#define BNX2_MISC_USPLL_CTRL_VCO_MG                      (0x3L<<11)
+#define BNX2_MISC_USPLL_CTRL_KVCO_XF                     (0x7L<<13)
+#define BNX2_MISC_USPLL_CTRL_KVCO_XS                     (0x7L<<16)
+#define BNX2_MISC_USPLL_CTRL_TESTD_EN                    (1L<<19)
+#define BNX2_MISC_USPLL_CTRL_TESTD_SEL                   (0x7L<<20)
+#define BNX2_MISC_USPLL_CTRL_TESTA_EN                    (1L<<23)
+#define BNX2_MISC_USPLL_CTRL_TESTA_SEL                   (0x3L<<24)
+#define BNX2_MISC_USPLL_CTRL_ATTEN_FREF                  (1L<<26)
+#define BNX2_MISC_USPLL_CTRL_DIGITAL_RST                 (1L<<27)
+#define BNX2_MISC_USPLL_CTRL_ANALOG_RST                  (1L<<28)
+#define BNX2_MISC_USPLL_CTRL_LOCK                        (1L<<29)
+
+#define BNX2_MISC_PERR_STATUS0                          0x00000944
+#define BNX2_MISC_PERR_STATUS0_COM_DMAE_PERR             (1L<<0)
+#define BNX2_MISC_PERR_STATUS0_CP_DMAE_PERR              (1L<<1)
+#define BNX2_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR        (1L<<2)
+#define BNX2_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR        (1L<<3)
+#define BNX2_MISC_PERR_STATUS0_CTX_PGTBL_PERR            (1L<<4)
+#define BNX2_MISC_PERR_STATUS0_CTX_CACHE_PERR            (1L<<5)
+#define BNX2_MISC_PERR_STATUS0_CTX_MIRROR_PERR           (1L<<6)
+#define BNX2_MISC_PERR_STATUS0_COM_CTXC_PERR             (1L<<7)
+#define BNX2_MISC_PERR_STATUS0_COM_SCPAD_PERR            (1L<<8)
+#define BNX2_MISC_PERR_STATUS0_CP_CTXC_PERR              (1L<<9)
+#define BNX2_MISC_PERR_STATUS0_CP_SCPAD_PERR             (1L<<10)
+#define BNX2_MISC_PERR_STATUS0_RXP_RBUFC_PERR            (1L<<11)
+#define BNX2_MISC_PERR_STATUS0_RXP_CTXC_PERR             (1L<<12)
+#define BNX2_MISC_PERR_STATUS0_RXP_SCPAD_PERR            (1L<<13)
+#define BNX2_MISC_PERR_STATUS0_TPAT_SCPAD_PERR           (1L<<14)
+#define BNX2_MISC_PERR_STATUS0_TXP_CTXC_PERR             (1L<<15)
+#define BNX2_MISC_PERR_STATUS0_TXP_SCPAD_PERR            (1L<<16)
+#define BNX2_MISC_PERR_STATUS0_CS_TMEM_PERR              (1L<<17)
+#define BNX2_MISC_PERR_STATUS0_MQ_CTX_PERR               (1L<<18)
+#define BNX2_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR         (1L<<19)
+#define BNX2_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR         (1L<<20)
+#define BNX2_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR          (1L<<21)
+#define BNX2_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR         (1L<<22)
+#define BNX2_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR          (1L<<23)
+#define BNX2_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR          (1L<<24)
+#define BNX2_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR         (1L<<25)
+#define BNX2_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR         (1L<<26)
+#define BNX2_MISC_PERR_STATUS0_TPBUF_PERR                (1L<<27)
+#define BNX2_MISC_PERR_STATUS0_THBUF_PERR                (1L<<28)
+#define BNX2_MISC_PERR_STATUS0_TDMA_PERR                 (1L<<29)
+#define BNX2_MISC_PERR_STATUS0_TBDC_PERR                 (1L<<30)
+#define BNX2_MISC_PERR_STATUS0_TSCH_LR_PERR              (1L<<31)
+
+#define BNX2_MISC_PERR_STATUS1                          0x00000948
+#define BNX2_MISC_PERR_STATUS1_RBDC_PERR                 (1L<<0)
+#define BNX2_MISC_PERR_STATUS1_RDMA_DFIFO_PERR           (1L<<2)
+#define BNX2_MISC_PERR_STATUS1_HC_STATS_PERR             (1L<<3)
+#define BNX2_MISC_PERR_STATUS1_HC_MSIX_PERR              (1L<<4)
+#define BNX2_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR         (1L<<5)
+#define BNX2_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR         (1L<<6)
+#define BNX2_MISC_PERR_STATUS1_TPATQ_PERR                (1L<<7)
+#define BNX2_MISC_PERR_STATUS1_MCPQ_PERR                 (1L<<8)
+#define BNX2_MISC_PERR_STATUS1_TDMAQ_PERR                (1L<<9)
+#define BNX2_MISC_PERR_STATUS1_TXPQ_PERR                 (1L<<10)
+#define BNX2_MISC_PERR_STATUS1_COMTQ_PERR                (1L<<11)
+#define BNX2_MISC_PERR_STATUS1_COMQ_PERR                 (1L<<12)
+#define BNX2_MISC_PERR_STATUS1_RLUPQ_PERR                (1L<<13)
+#define BNX2_MISC_PERR_STATUS1_RXPQ_PERR                 (1L<<14)
+#define BNX2_MISC_PERR_STATUS1_RV2PPQ_PERR               (1L<<15)
+#define BNX2_MISC_PERR_STATUS1_RDMAQ_PERR                (1L<<16)
+#define BNX2_MISC_PERR_STATUS1_TASQ_PERR                 (1L<<17)
+#define BNX2_MISC_PERR_STATUS1_TBDRQ_PERR                (1L<<18)
+#define BNX2_MISC_PERR_STATUS1_TSCHQ_PERR                (1L<<19)
+#define BNX2_MISC_PERR_STATUS1_COMXQ_PERR                (1L<<20)
+#define BNX2_MISC_PERR_STATUS1_RXPCQ_PERR                (1L<<21)
+#define BNX2_MISC_PERR_STATUS1_RV2PTQ_PERR               (1L<<22)
+#define BNX2_MISC_PERR_STATUS1_RV2PMQ_PERR               (1L<<23)
+#define BNX2_MISC_PERR_STATUS1_CPQ_PERR                  (1L<<24)
+#define BNX2_MISC_PERR_STATUS1_CSQ_PERR                  (1L<<25)
+#define BNX2_MISC_PERR_STATUS1_RLUP_CID_PERR             (1L<<26)
+#define BNX2_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR          (1L<<27)
+#define BNX2_MISC_PERR_STATUS1_RV2PCSQ_PERR              (1L<<28)
+#define BNX2_MISC_PERR_STATUS1_MQ_IDX_PERR               (1L<<29)
+
+#define BNX2_MISC_PERR_STATUS2                          0x0000094c
+#define BNX2_MISC_PERR_STATUS2_TGT_FIFO_PERR             (1L<<0)
+#define BNX2_MISC_PERR_STATUS2_UMP_TX_PERR               (1L<<1)
+#define BNX2_MISC_PERR_STATUS2_UMP_RX_PERR               (1L<<2)
+#define BNX2_MISC_PERR_STATUS2_MCP_ROM_PERR              (1L<<3)
+#define BNX2_MISC_PERR_STATUS2_MCP_SCPAD_PERR            (1L<<4)
+#define BNX2_MISC_PERR_STATUS2_HB_MEM_PERR               (1L<<5)
+#define BNX2_MISC_PERR_STATUS2_PCIE_REPLAY_PERR          (1L<<6)
+
+#define BNX2_MISC_LCPLL_CTRL0                           0x00000950
+#define BNX2_MISC_LCPLL_CTRL0_OAC                        (0x7L<<0)
+#define BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY              (0L<<0)
+#define BNX2_MISC_LCPLL_CTRL0_OAC_ZERO                   (1L<<0)
+#define BNX2_MISC_LCPLL_CTRL0_OAC_TWENTY                 (3L<<0)
+#define BNX2_MISC_LCPLL_CTRL0_OAC_FORTY                  (7L<<0)
+#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL                   (0x7L<<3)
+#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360               (0L<<3)
+#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_480               (1L<<3)
+#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_600               (3L<<3)
+#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_720               (7L<<3)
+#define BNX2_MISC_LCPLL_CTRL0_BIAS_CTRL                  (0x3L<<6)
+#define BNX2_MISC_LCPLL_CTRL0_PLL_OBSERVE                (0x7L<<8)
+#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL                   (0x3L<<11)
+#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0                 (0L<<11)
+#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_1                 (1L<<11)
+#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_2                 (2L<<11)
+#define BNX2_MISC_LCPLL_CTRL0_PLLSEQSTART                (1L<<13)
+#define BNX2_MISC_LCPLL_CTRL0_RESERVED                   (1L<<14)
+#define BNX2_MISC_LCPLL_CTRL0_CAPRETRY_EN                (1L<<15)
+#define BNX2_MISC_LCPLL_CTRL0_FREQMONITOR_EN             (1L<<16)
+#define BNX2_MISC_LCPLL_CTRL0_FREQDETRESTART_EN          (1L<<17)
+#define BNX2_MISC_LCPLL_CTRL0_FREQDETRETRY_EN            (1L<<18)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN           (1L<<19)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE              (1L<<20)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFPASS              (1L<<21)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN         (1L<<22)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE            (1L<<23)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN         (1L<<24)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS            (1L<<25)
+#define BNX2_MISC_LCPLL_CTRL0_CAPRESTART                 (1L<<26)
+#define BNX2_MISC_LCPLL_CTRL0_CAPSELECTM_EN              (1L<<27)
+
+#define BNX2_MISC_LCPLL_CTRL1                           0x00000954
+#define BNX2_MISC_LCPLL_CTRL1_CAPSELECTM                 (0x1fL<<0)
+#define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN        (1L<<5)
+#define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN           (1L<<6)
+#define BNX2_MISC_LCPLL_CTRL1_SLOWDN_XOR                 (1L<<7)
+
+#define BNX2_MISC_LCPLL_STATUS                          0x00000958
+#define BNX2_MISC_LCPLL_STATUS_FREQDONE_SM               (1L<<0)
+#define BNX2_MISC_LCPLL_STATUS_FREQPASS_SM               (1L<<1)
+#define BNX2_MISC_LCPLL_STATUS_PLLSEQDONE                (1L<<2)
+#define BNX2_MISC_LCPLL_STATUS_PLLSEQPASS                (1L<<3)
+#define BNX2_MISC_LCPLL_STATUS_PLLSTATE                  (0x7L<<4)
+#define BNX2_MISC_LCPLL_STATUS_CAPSTATE                  (0x7L<<7)
+#define BNX2_MISC_LCPLL_STATUS_CAPSELECT                 (0x1fL<<10)
+#define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR          (1L<<15)
+#define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0        (0L<<15)
+#define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1        (1L<<15)
+
+#define BNX2_MISC_OSCFUNDS_CTRL                         0x0000095c
+#define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON                 (1L<<5)
+#define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF             (0L<<5)
+#define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_ON              (1L<<5)
+#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM               (0x3L<<6)
+#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0             (0L<<6)
+#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1             (1L<<6)
+#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2             (2L<<6)
+#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3             (3L<<6)
+#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ                (0x3L<<8)
+#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0              (0L<<8)
+#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1              (1L<<8)
+#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2              (2L<<8)
+#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3              (3L<<8)
+#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ                 (0x3L<<10)
+#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0               (0L<<10)
+#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1               (1L<<10)
+#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2               (2L<<10)
+#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3               (3L<<10)
 
 
 /*
@@ -1031,11 +1736,35 @@ struct l2_fhdr {
 #define BNX2_NVM_COMMAND_WRDI                            (1L<<17)
 #define BNX2_NVM_COMMAND_EWSR                            (1L<<18)
 #define BNX2_NVM_COMMAND_WRSR                            (1L<<19)
+#define BNX2_NVM_COMMAND_RD_ID                           (1L<<20)
+#define BNX2_NVM_COMMAND_RD_STATUS                       (1L<<21)
+#define BNX2_NVM_COMMAND_MODE_256                        (1L<<22)
 
 #define BNX2_NVM_STATUS                                 0x00006404
 #define BNX2_NVM_STATUS_PI_FSM_STATE                     (0xfL<<0)
 #define BNX2_NVM_STATUS_EE_FSM_STATE                     (0xfL<<4)
 #define BNX2_NVM_STATUS_EQ_FSM_STATE                     (0xfL<<8)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_XI                 (0x1fL<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI        (0L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI        (1L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI        (2L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI         (3L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI         (4L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI       (5L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI         (6L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI         (7L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI         (8L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI  (9L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI  (10L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI  (11L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI   (12L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI   (13L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI   (14L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI   (15L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI   (16L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI         (17L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI     (18L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI        (19L<<0)
 
 #define BNX2_NVM_WRITE                                  0x00006408
 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE                   (0xffffffffL<<0)
@@ -1046,6 +1775,10 @@ struct l2_fhdr {
 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B              (8L<<0)
 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO                (16L<<0)
 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI                (32L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI_XI             (1L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO_XI             (2L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI           (4L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI           (8L<<0)
 
 #define BNX2_NVM_ADDR                                   0x0000640c
 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE                     (0xffffffL<<0)
@@ -1056,6 +1789,10 @@ struct l2_fhdr {
 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B                (8L<<0)
 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO                  (16L<<0)
 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI                  (32L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI_XI               (1L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO_XI               (2L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI             (4L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI             (8L<<0)
 
 #define BNX2_NVM_READ                                   0x00006410
 #define BNX2_NVM_READ_NVM_READ_VALUE                     (0xffffffffL<<0)
@@ -1066,6 +1803,10 @@ struct l2_fhdr {
 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B                (8L<<0)
 #define BNX2_NVM_READ_NVM_READ_VALUE_SO                  (16L<<0)
 #define BNX2_NVM_READ_NVM_READ_VALUE_SI                  (32L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_SI_XI               (1L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_SO_XI               (2L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_CS_B_XI             (4L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_SCLK_XI             (8L<<0)
 
 #define BNX2_NVM_CFG1                                   0x00006414
 #define BNX2_NVM_CFG1_FLASH_MODE                         (1L<<0)
@@ -1077,14 +1818,21 @@ struct l2_fhdr {
 #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY              (7L<<4)
 #define BNX2_NVM_CFG1_SPI_CLK_DIV                        (0xfL<<7)
 #define BNX2_NVM_CFG1_SEE_CLK_DIV                        (0x7ffL<<11)
+#define BNX2_NVM_CFG1_STRAP_CONTROL_0                    (1L<<23)
 #define BNX2_NVM_CFG1_PROTECT_MODE                       (1L<<24)
 #define BNX2_NVM_CFG1_FLASH_SIZE                         (1L<<25)
+#define BNX2_NVM_CFG1_FW_USTRAP_1                        (1L<<26)
+#define BNX2_NVM_CFG1_FW_USTRAP_0                        (1L<<27)
+#define BNX2_NVM_CFG1_FW_USTRAP_2                        (1L<<28)
+#define BNX2_NVM_CFG1_FW_USTRAP_3                        (1L<<29)
+#define BNX2_NVM_CFG1_FW_FLASH_TYPE_EN                   (1L<<30)
 #define BNX2_NVM_CFG1_COMPAT_BYPASSS                     (1L<<31)
 
 #define BNX2_NVM_CFG2                                   0x00006418
 #define BNX2_NVM_CFG2_ERASE_CMD                          (0xffL<<0)
 #define BNX2_NVM_CFG2_DUMMY                              (0xffL<<8)
 #define BNX2_NVM_CFG2_STATUS_CMD                         (0xffL<<16)
+#define BNX2_NVM_CFG2_READ_ID                            (0xffL<<24)
 
 #define BNX2_NVM_CFG3                                   0x0000641c
 #define BNX2_NVM_CFG3_BUFFER_RD_CMD                      (0xffL<<0)
@@ -1119,6 +1867,35 @@ struct l2_fhdr {
 #define BNX2_NVM_WRITE1_WRDI_CMD                         (0xffL<<8)
 #define BNX2_NVM_WRITE1_SR_DATA                          (0xffL<<16)
 
+#define BNX2_NVM_CFG4                                   0x0000642c
+#define BNX2_NVM_CFG4_FLASH_SIZE                         (0x7L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_1MBIT                   (0L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_2MBIT                   (1L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_4MBIT                   (2L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_8MBIT                   (3L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_16MBIT                  (4L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_32MBIT                  (5L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_64MBIT                  (6L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_128MBIT                 (7L<<0)
+#define BNX2_NVM_CFG4_FLASH_VENDOR                       (1L<<3)
+#define BNX2_NVM_CFG4_FLASH_VENDOR_ST                    (0L<<3)
+#define BNX2_NVM_CFG4_FLASH_VENDOR_ATMEL                 (1L<<3)
+#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC             (0x3L<<4)
+#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8        (0L<<4)
+#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9        (1L<<4)
+#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10       (2L<<4)
+#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11       (3L<<4)
+#define BNX2_NVM_CFG4_STATUS_BIT_POLARITY                (1L<<6)
+#define BNX2_NVM_CFG4_RESERVED                           (0x1ffffffL<<7)
+
+#define BNX2_NVM_RECONFIG                               0x00006430
+#define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE               (0xfL<<0)
+#define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST            (0L<<0)
+#define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL         (1L<<0)
+#define BNX2_NVM_RECONFIG_RECONFIG_STRAP_VALUE           (0xfL<<4)
+#define BNX2_NVM_RECONFIG_RESERVED                       (0x7fffffL<<8)
+#define BNX2_NVM_RECONFIG_RECONFIG_DONE                  (1L<<31)
+
 
 
 /*
@@ -1140,6 +1917,8 @@ struct l2_fhdr {
 #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT         (1L<<23)
 #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT    (1L<<24)
 #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT  (1L<<25)
+#define BNX2_DMA_STATUS_GLOBAL_ERR_XI                    (1L<<0)
+#define BNX2_DMA_STATUS_BME_XI                           (1L<<4)
 
 #define BNX2_DMA_CONFIG                                 0x00000c08
 #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP                   (1L<<0)
@@ -1161,85 +1940,315 @@ struct l2_fhdr {
 #define BNX2_DMA_CONFIG_BIG_SIZE_128                     (0x2L<<24)
 #define BNX2_DMA_CONFIG_BIG_SIZE_256                     (0x4L<<24)
 #define BNX2_DMA_CONFIG_BIG_SIZE_512                     (0x8L<<24)
+#define BNX2_DMA_CONFIG_DAT_WBSWAP_MODE_XI               (0x3L<<0)
+#define BNX2_DMA_CONFIG_CTL_WBSWAP_MODE_XI               (0x3L<<4)
+#define BNX2_DMA_CONFIG_MAX_PL_XI                        (0x7L<<12)
+#define BNX2_DMA_CONFIG_MAX_PL_128B_XI                   (0L<<12)
+#define BNX2_DMA_CONFIG_MAX_PL_256B_XI                   (1L<<12)
+#define BNX2_DMA_CONFIG_MAX_PL_512B_XI                   (2L<<12)
+#define BNX2_DMA_CONFIG_MAX_PL_EN_XI                     (1L<<15)
+#define BNX2_DMA_CONFIG_MAX_RRS_XI                       (0x7L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_128B_XI                  (0L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_256B_XI                  (1L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_512B_XI                  (2L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_1024B_XI                 (3L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_2048B_XI                 (4L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_4096B_XI                 (5L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_EN_XI                    (1L<<19)
+#define BNX2_DMA_CONFIG_NO_64SWAP_EN_XI                  (1L<<31)
 
 #define BNX2_DMA_BLACKOUT                               0x00000c0c
 #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT              (0xffL<<0)
 #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT          (0xffL<<8)
 #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT              (0xffL<<16)
 
-#define BNX2_DMA_RCHAN_STAT                             0x00000c30
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_0                  (0x7L<<0)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_0                    (1L<<3)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_1                  (0x7L<<4)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_1                    (1L<<7)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_2                  (0x7L<<8)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_2                    (1L<<11)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_3                  (0x7L<<12)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_3                    (1L<<15)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_4                  (0x7L<<16)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_4                    (1L<<19)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_5                  (0x7L<<20)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_5                    (1L<<23)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_6                  (0x7L<<24)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_6                    (1L<<27)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_7                  (0x7L<<28)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_7                    (1L<<31)
-
-#define BNX2_DMA_WCHAN_STAT                             0x00000c34
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_0                  (0x7L<<0)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_0                    (1L<<3)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_1                  (0x7L<<4)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_1                    (1L<<7)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_2                  (0x7L<<8)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_2                    (1L<<11)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_3                  (0x7L<<12)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_3                    (1L<<15)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_4                  (0x7L<<16)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_4                    (1L<<19)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_5                  (0x7L<<20)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_5                    (1L<<23)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_6                  (0x7L<<24)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_6                    (1L<<27)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_7                  (0x7L<<28)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_7                    (1L<<31)
-
-#define BNX2_DMA_RCHAN_ASSIGNMENT                       0x00000c38
-#define BNX2_DMA_RCHAN_ASSIGNMENT_0                      (0xfL<<0)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_1                      (0xfL<<4)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_2                      (0xfL<<8)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_3                      (0xfL<<12)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_4                      (0xfL<<16)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_5                      (0xfL<<20)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_6                      (0xfL<<24)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_7                      (0xfL<<28)
-
-#define BNX2_DMA_WCHAN_ASSIGNMENT                       0x00000c3c
-#define BNX2_DMA_WCHAN_ASSIGNMENT_0                      (0xfL<<0)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_1                      (0xfL<<4)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_2                      (0xfL<<8)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_3                      (0xfL<<12)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_4                      (0xfL<<16)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_5                      (0xfL<<20)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_6                      (0xfL<<24)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_7                      (0xfL<<28)
-
-#define BNX2_DMA_RCHAN_STAT_00                          0x00000c40
-#define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW   (0xffffffffL<<0)
-
-#define BNX2_DMA_RCHAN_STAT_01                          0x00000c44
-#define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH  (0xffffffffL<<0)
-
-#define BNX2_DMA_RCHAN_STAT_02                          0x00000c48
-#define BNX2_DMA_RCHAN_STAT_02_LENGTH                    (0xffffL<<0)
-#define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP                 (1L<<16)
-#define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP                 (1L<<17)
-#define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL              (1L<<18)
-
-#define BNX2_DMA_RCHAN_STAT_10                          0x00000c4c
-#define BNX2_DMA_RCHAN_STAT_11                          0x00000c50
-#define BNX2_DMA_RCHAN_STAT_12                          0x00000c54
-#define BNX2_DMA_RCHAN_STAT_20                          0x00000c58
-#define BNX2_DMA_RCHAN_STAT_21                          0x00000c5c
+#define BNX2_DMA_READ_MASTER_SETTING_0                  0x00000c10
+#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP     (1L<<0)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER  (1L<<1)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY     (1L<<2)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS        (0x7L<<4)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN     (1L<<7)
+#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP     (1L<<8)
+#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER  (1L<<9)
+#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY     (1L<<10)
+#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS        (0x7L<<12)
+#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN     (1L<<15)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP     (1L<<16)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER  (1L<<17)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY     (1L<<18)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS        (0x7L<<20)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN     (1L<<23)
+#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP      (1L<<24)
+#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER   (1L<<25)
+#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PRIORITY      (1L<<26)
+#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS         (0x7L<<28)
+#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN      (1L<<31)
+
+#define BNX2_DMA_READ_MASTER_SETTING_1                  0x00000c14
+#define BNX2_DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP      (1L<<0)
+#define BNX2_DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER   (1L<<1)
+#define BNX2_DMA_READ_MASTER_SETTING_1_COM_PRIORITY      (1L<<2)
+#define BNX2_DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS         (0x7L<<4)
+#define BNX2_DMA_READ_MASTER_SETTING_1_COM_PARAM_EN      (1L<<7)
+#define BNX2_DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP       (1L<<8)
+#define BNX2_DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER    (1L<<9)
+#define BNX2_DMA_READ_MASTER_SETTING_1_CP_PRIORITY       (1L<<10)
+#define BNX2_DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS  (0x7L<<12)
+#define BNX2_DMA_READ_MASTER_SETTING_1_CP_PARAM_EN       (1L<<15)
+
+#define BNX2_DMA_WRITE_MASTER_SETTING_0                 0x00000c18
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP      (1L<<0)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER   (1L<<1)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY      (1L<<2)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD        (1L<<3)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS         (0x7L<<4)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN      (1L<<7)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP    (1L<<8)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER         (1L<<9)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY    (1L<<10)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD      (1L<<11)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS       (0x7L<<12)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN    (1L<<15)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP     (1L<<24)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER  (1L<<25)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY     (1L<<26)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD       (1L<<27)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS        (0x7L<<28)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN     (1L<<31)
+
+#define BNX2_DMA_WRITE_MASTER_SETTING_1                 0x00000c1c
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP     (1L<<0)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER  (1L<<1)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY     (1L<<2)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD       (1L<<3)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS        (0x7L<<4)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN     (1L<<7)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP      (1L<<8)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER   (1L<<9)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY      (1L<<10)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD        (1L<<11)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS         (0x7L<<12)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN      (1L<<15)
+
+#define BNX2_DMA_ARBITER                                0x00000c20
+#define BNX2_DMA_ARBITER_NUM_READS                       (0x7L<<0)
+#define BNX2_DMA_ARBITER_WR_ARB_MODE                     (1L<<4)
+#define BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT              (0L<<4)
+#define BNX2_DMA_ARBITER_WR_ARB_MODE_RND_RBN             (1L<<4)
+#define BNX2_DMA_ARBITER_RD_ARB_MODE                     (0x3L<<5)
+#define BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT              (0L<<5)
+#define BNX2_DMA_ARBITER_RD_ARB_MODE_RND_RBN             (1L<<5)
+#define BNX2_DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN         (2L<<5)
+#define BNX2_DMA_ARBITER_ALT_MODE_EN                     (1L<<8)
+#define BNX2_DMA_ARBITER_RR_MODE                         (1L<<9)
+#define BNX2_DMA_ARBITER_TIMER_MODE                      (1L<<10)
+#define BNX2_DMA_ARBITER_OUSTD_READ_REQ                  (0xfL<<12)
+
+#define BNX2_DMA_ARB_TIMERS                             0x00000c24
+#define BNX2_DMA_ARB_TIMERS_RD_DRR_WAIT_TIME             (0xffL<<0)
+#define BNX2_DMA_ARB_TIMERS_TM_MIN_TIMEOUT               (0xffL<<12)
+#define BNX2_DMA_ARB_TIMERS_TM_MAX_TIMEOUT               (0xfffL<<20)
+
+#define BNX2_DMA_DEBUG_VECT_PEEK                        0x00000c2c
+#define BNX2_DMA_DEBUG_VECT_PEEK_1_VALUE                 (0x7ffL<<0)
+#define BNX2_DMA_DEBUG_VECT_PEEK_1_PEEK_EN               (1L<<11)
+#define BNX2_DMA_DEBUG_VECT_PEEK_1_SEL                   (0xfL<<12)
+#define BNX2_DMA_DEBUG_VECT_PEEK_2_VALUE                 (0x7ffL<<16)
+#define BNX2_DMA_DEBUG_VECT_PEEK_2_PEEK_EN               (1L<<27)
+#define BNX2_DMA_DEBUG_VECT_PEEK_2_SEL                   (0xfL<<28)
+
+#define BNX2_DMA_TAG_RAM_00                             0x00000c30
+#define BNX2_DMA_TAG_RAM_00_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_00_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_00_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_00_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_00_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_00_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_00_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_00_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_01                             0x00000c34
+#define BNX2_DMA_TAG_RAM_01_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_01_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_01_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_01_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_01_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_01_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_01_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_01_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_02                             0x00000c38
+#define BNX2_DMA_TAG_RAM_02_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_02_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_02_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_02_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_02_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_02_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_02_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_02_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_03                             0x00000c3c
+#define BNX2_DMA_TAG_RAM_03_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_03_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_03_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_03_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_03_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_03_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_03_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_03_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_04                             0x00000c40
+#define BNX2_DMA_TAG_RAM_04_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_04_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_04_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_04_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_04_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_04_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_04_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_04_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_05                             0x00000c44
+#define BNX2_DMA_TAG_RAM_05_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_05_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_05_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_05_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_05_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_05_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_05_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_05_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_06                             0x00000c48
+#define BNX2_DMA_TAG_RAM_06_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_06_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_06_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_06_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_06_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_06_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_06_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_06_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_07                             0x00000c4c
+#define BNX2_DMA_TAG_RAM_07_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_07_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_07_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_07_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_07_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_07_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_07_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_07_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_08                             0x00000c50
+#define BNX2_DMA_TAG_RAM_08_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_08_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_08_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_08_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_08_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_08_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_08_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_08_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_09                             0x00000c54
+#define BNX2_DMA_TAG_RAM_09_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_09_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_09_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_09_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_09_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_09_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_09_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_09_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_10                             0x00000c58
+#define BNX2_DMA_TAG_RAM_10_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_10_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_10_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_10_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_10_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_10_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_10_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_10_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_11                             0x00000c5c
+#define BNX2_DMA_TAG_RAM_11_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_11_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_11_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_11_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_11_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_11_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_11_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_11_VALID                        (1L<<10)
+
 #define BNX2_DMA_RCHAN_STAT_22                          0x00000c60
 #define BNX2_DMA_RCHAN_STAT_30                          0x00000c64
 #define BNX2_DMA_RCHAN_STAT_31                          0x00000c68
@@ -1336,6 +2345,25 @@ struct l2_fhdr {
  */
 #define BNX2_CTX_COMMAND                                0x00001000
 #define BNX2_CTX_COMMAND_ENABLED                         (1L<<0)
+#define BNX2_CTX_COMMAND_DISABLE_USAGE_CNT               (1L<<1)
+#define BNX2_CTX_COMMAND_DISABLE_PLRU                    (1L<<2)
+#define BNX2_CTX_COMMAND_DISABLE_COMBINE_READ            (1L<<3)
+#define BNX2_CTX_COMMAND_FLUSH_AHEAD                     (0x1fL<<8)
+#define BNX2_CTX_COMMAND_MEM_INIT                        (1L<<13)
+#define BNX2_CTX_COMMAND_PAGE_SIZE                       (0xfL<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_256                   (0L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_512                   (1L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_1K                    (2L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_2K                    (3L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_4K                    (4L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_8K                    (5L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_16K                   (6L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_32K                   (7L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_64K                   (8L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_128K                  (9L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_256K                  (10L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_512K                  (11L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_1M                    (12L<<16)
 
 #define BNX2_CTX_STATUS                                 0x00001004
 #define BNX2_CTX_STATUS_LOCK_WAIT                        (1L<<0)
@@ -1343,6 +2371,13 @@ struct l2_fhdr {
 #define BNX2_CTX_STATUS_WRITE_STAT                       (1L<<17)
 #define BNX2_CTX_STATUS_ACC_STALL_STAT                   (1L<<18)
 #define BNX2_CTX_STATUS_LOCK_STALL_STAT                  (1L<<19)
+#define BNX2_CTX_STATUS_EXT_READ_STAT                    (1L<<20)
+#define BNX2_CTX_STATUS_EXT_WRITE_STAT                   (1L<<21)
+#define BNX2_CTX_STATUS_MISS_STAT                        (1L<<22)
+#define BNX2_CTX_STATUS_HIT_STAT                         (1L<<23)
+#define BNX2_CTX_STATUS_DEAD_LOCK                        (1L<<24)
+#define BNX2_CTX_STATUS_USAGE_CNT_ERR                    (1L<<25)
+#define BNX2_CTX_STATUS_INVALID_PAGE                     (1L<<26)
 
 #define BNX2_CTX_VIRT_ADDR                              0x00001008
 #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR                     (0x7fffL<<6)
@@ -1357,10 +2392,15 @@ struct l2_fhdr {
 #define BNX2_CTX_LOCK                                   0x00001018
 #define BNX2_CTX_LOCK_TYPE                               (0x7L<<0)
 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID                (0x0L<<0)
-#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE            (0x7L<<0)
 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL            (0x1L<<0)
 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX                  (0x2L<<0)
 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER               (0x4L<<0)
+#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE            (0x7L<<0)
+#define BNX2_CTX_LOCK_TYPE_VOID_XI                       (0L<<0)
+#define BNX2_CTX_LOCK_TYPE_PROTOCOL_XI                   (1L<<0)
+#define BNX2_CTX_LOCK_TYPE_TX_XI                         (2L<<0)
+#define BNX2_CTX_LOCK_TYPE_TIMER_XI                      (4L<<0)
+#define BNX2_CTX_LOCK_TYPE_COMPLETE_XI                   (7L<<0)
 #define BNX2_CTX_LOCK_CID_VALUE                          (0x3fffL<<7)
 #define BNX2_CTX_LOCK_GRANTED                            (1L<<26)
 #define BNX2_CTX_LOCK_MODE                               (0x7L<<27)
@@ -1370,21 +2410,89 @@ struct l2_fhdr {
 #define BNX2_CTX_LOCK_STATUS                             (1L<<30)
 #define BNX2_CTX_LOCK_REQ                                (1L<<31)
 
+#define BNX2_CTX_CTX_CTRL                               0x0000101c
+#define BNX2_CTX_CTX_CTRL_CTX_ADDR                       (0x7ffffL<<2)
+#define BNX2_CTX_CTX_CTRL_MOD_USAGE_CNT                  (0x3L<<21)
+#define BNX2_CTX_CTX_CTRL_NO_RAM_ACC                     (1L<<23)
+#define BNX2_CTX_CTX_CTRL_PREFETCH_SIZE                  (0x3L<<24)
+#define BNX2_CTX_CTX_CTRL_ATTR                           (1L<<26)
+#define BNX2_CTX_CTX_CTRL_WRITE_REQ                      (1L<<30)
+#define BNX2_CTX_CTX_CTRL_READ_REQ                       (1L<<31)
+
+#define BNX2_CTX_CTX_DATA                               0x00001020
 #define BNX2_CTX_ACCESS_STATUS                          0x00001040
 #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED             (0xfL<<0)
 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM            (0x3L<<10)
 #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM           (0x3L<<12)
 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM        (0x3L<<14)
 #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST         (0x7ffL<<17)
+#define BNX2_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI       (0x1fL<<0)
+#define BNX2_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI     (0x1fL<<5)
+#define BNX2_CTX_ACCESS_STATUS_REQUEST_XI                (0x3fffffL<<10)
 
 #define BNX2_CTX_DBG_LOCK_STATUS                        0x00001044
 #define BNX2_CTX_DBG_LOCK_STATUS_SM                      (0x3ffL<<0)
 #define BNX2_CTX_DBG_LOCK_STATUS_MATCH                   (0x3ffL<<22)
 
+#define BNX2_CTX_CACHE_CTRL_STATUS                      0x00001048
+#define BNX2_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW        (1L<<0)
+#define BNX2_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP     (1L<<1)
+#define BNX2_CTX_CACHE_CTRL_STATUS_FLUSH_START           (1L<<6)
+#define BNX2_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT        (0x3fL<<7)
+#define BNX2_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED    (0x3fL<<13)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE       (1L<<19)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE       (1L<<20)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE       (1L<<21)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE       (1L<<22)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE       (1L<<23)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE       (1L<<24)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE       (1L<<25)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE       (1L<<26)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE       (1L<<27)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE       (1L<<28)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE      (1L<<29)
+
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS                   0x0000104c
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_DWC             (0x7L<<0)
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC          (0x7L<<3)
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC           (0x7L<<6)
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC          (0x7L<<9)
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR   (0x7fffL<<16)
+
+#define BNX2_CTX_CACHE_STATUS                           0x00001050
+#define BNX2_CTX_CACHE_STATUS_HELD_ENTRIES               (0x3ffL<<0)
+#define BNX2_CTX_CACHE_STATUS_MAX_HELD_ENTRIES           (0x3ffL<<16)
+
+#define BNX2_CTX_DMA_STATUS                             0x00001054
+#define BNX2_CTX_DMA_STATUS_RD_CHAN0_STATUS              (0x3L<<0)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN1_STATUS              (0x3L<<2)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN2_STATUS              (0x3L<<4)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN3_STATUS              (0x3L<<6)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN4_STATUS              (0x3L<<8)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN5_STATUS              (0x3L<<10)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN6_STATUS              (0x3L<<12)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN7_STATUS              (0x3L<<14)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN8_STATUS              (0x3L<<16)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN9_STATUS              (0x3L<<18)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN10_STATUS             (0x3L<<20)
+
+#define BNX2_CTX_REP_STATUS                             0x00001058
+#define BNX2_CTX_REP_STATUS_ERROR_ENTRY                  (0x3ffL<<0)
+#define BNX2_CTX_REP_STATUS_ERROR_CLIENT_ID              (0x1fL<<10)
+#define BNX2_CTX_REP_STATUS_USAGE_CNT_MAX_ERR            (1L<<16)
+#define BNX2_CTX_REP_STATUS_USAGE_CNT_MIN_ERR            (1L<<17)
+#define BNX2_CTX_REP_STATUS_USAGE_CNT_MISS_ERR           (1L<<18)
+
+#define BNX2_CTX_CKSUM_ERROR_STATUS                     0x0000105c
+#define BNX2_CTX_CKSUM_ERROR_STATUS_CALCULATED           (0xffffL<<0)
+#define BNX2_CTX_CKSUM_ERROR_STATUS_EXPECTED             (0xffffL<<16)
+
 #define BNX2_CTX_CHNL_LOCK_STATUS_0                     0x00001080
 #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID                  (0x3fffL<<0)
 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE                 (0x3L<<14)
 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE                 (1L<<16)
+#define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE_XI              (1L<<14)
+#define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE_XI              (0x7L<<15)
 
 #define BNX2_CTX_CHNL_LOCK_STATUS_1                     0x00001084
 #define BNX2_CTX_CHNL_LOCK_STATUS_2                     0x00001088
@@ -1394,6 +2502,26 @@ struct l2_fhdr {
 #define BNX2_CTX_CHNL_LOCK_STATUS_6                     0x00001098
 #define BNX2_CTX_CHNL_LOCK_STATUS_7                     0x0000109c
 #define BNX2_CTX_CHNL_LOCK_STATUS_8                     0x000010a0
+#define BNX2_CTX_CHNL_LOCK_STATUS_9                     0x000010a4
+
+#define BNX2_CTX_CACHE_DATA                             0x000010c4
+#define BNX2_CTX_HOST_PAGE_TBL_CTRL                     0x000010c8
+#define BNX2_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR        (0x1ffL<<0)
+#define BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ            (1L<<30)
+#define BNX2_CTX_HOST_PAGE_TBL_CTRL_READ_REQ             (1L<<31)
+
+#define BNX2_CTX_HOST_PAGE_TBL_DATA0                    0x000010cc
+#define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID               (1L<<0)
+#define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALUE               (0xffffffL<<8)
+
+#define BNX2_CTX_HOST_PAGE_TBL_DATA1                    0x000010d0
+#define BNX2_CTX_CAM_CTRL                               0x000010d4
+#define BNX2_CTX_CAM_CTRL_CAM_ADDR                       (0x3ffL<<0)
+#define BNX2_CTX_CAM_CTRL_RESET                          (1L<<27)
+#define BNX2_CTX_CAM_CTRL_INVALIDATE                     (1L<<28)
+#define BNX2_CTX_CAM_CTRL_SEARCH                         (1L<<29)
+#define BNX2_CTX_CAM_CTRL_WRITE_REQ                      (1L<<30)
+#define BNX2_CTX_CAM_CTRL_READ_REQ                       (1L<<31)
 
 
 /*
@@ -1407,14 +2535,16 @@ struct l2_fhdr {
 #define BNX2_EMAC_MODE_PORT_NONE                         (0L<<2)
 #define BNX2_EMAC_MODE_PORT_MII                          (1L<<2)
 #define BNX2_EMAC_MODE_PORT_GMII                         (2L<<2)
-#define BNX2_EMAC_MODE_PORT_MII_10                       (3L<<2)
+#define BNX2_EMAC_MODE_PORT_MII_10M                      (3L<<2)
 #define BNX2_EMAC_MODE_MAC_LOOP                          (1L<<4)
-#define BNX2_EMAC_MODE_25G                               (1L<<5)
+#define BNX2_EMAC_MODE_25G_MODE                          (1L<<5)
 #define BNX2_EMAC_MODE_TAGGED_MAC_CTL                    (1L<<7)
 #define BNX2_EMAC_MODE_TX_BURST                          (1L<<8)
 #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA                (1L<<9)
 #define BNX2_EMAC_MODE_EXT_LINK_POL                      (1L<<10)
 #define BNX2_EMAC_MODE_FORCE_LINK                        (1L<<11)
+#define BNX2_EMAC_MODE_SERDES_MODE                       (1L<<12)
+#define BNX2_EMAC_MODE_BOND_OVRD                         (1L<<13)
 #define BNX2_EMAC_MODE_MPKT                              (1L<<18)
 #define BNX2_EMAC_MODE_MPKT_RCVD                         (1L<<19)
 #define BNX2_EMAC_MODE_ACPI_RCVD                         (1L<<20)
@@ -1422,6 +2552,11 @@ struct l2_fhdr {
 #define BNX2_EMAC_STATUS                                0x00001404
 #define BNX2_EMAC_STATUS_LINK                            (1L<<11)
 #define BNX2_EMAC_STATUS_LINK_CHANGE                     (1L<<12)
+#define BNX2_EMAC_STATUS_SERDES_AUTONEG_COMPLETE         (1L<<13)
+#define BNX2_EMAC_STATUS_SERDES_AUTONEG_CHANGE           (1L<<14)
+#define BNX2_EMAC_STATUS_SERDES_NXT_PG_CHANGE            (1L<<16)
+#define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0           (1L<<17)
+#define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE    (1L<<18)
 #define BNX2_EMAC_STATUS_MI_COMPLETE                     (1L<<22)
 #define BNX2_EMAC_STATUS_MI_INT                          (1L<<23)
 #define BNX2_EMAC_STATUS_AP_ERROR                        (1L<<24)
@@ -1429,6 +2564,9 @@ struct l2_fhdr {
 
 #define BNX2_EMAC_ATTENTION_ENA                         0x00001408
 #define BNX2_EMAC_ATTENTION_ENA_LINK                     (1L<<11)
+#define BNX2_EMAC_ATTENTION_ENA_AUTONEG_CHANGE           (1L<<14)
+#define BNX2_EMAC_ATTENTION_ENA_NXT_PG_CHANGE            (1L<<16)
+#define BNX2_EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE     (1L<<18)
 #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE              (1L<<22)
 #define BNX2_EMAC_ATTENTION_ENA_MI_INT                   (1L<<23)
 #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR                 (1L<<24)
@@ -1445,6 +2583,13 @@ struct l2_fhdr {
 #define BNX2_EMAC_LED_100MB                              (1L<<8)
 #define BNX2_EMAC_LED_10MB                               (1L<<9)
 #define BNX2_EMAC_LED_TRAFFIC_STAT                       (1L<<10)
+#define BNX2_EMAC_LED_2500MB                             (1L<<11)
+#define BNX2_EMAC_LED_2500MB_OVERRIDE                    (1L<<12)
+#define BNX2_EMAC_LED_ACTIVITY_SEL                       (0x3L<<17)
+#define BNX2_EMAC_LED_ACTIVITY_SEL_0                     (0L<<17)
+#define BNX2_EMAC_LED_ACTIVITY_SEL_1                     (1L<<17)
+#define BNX2_EMAC_LED_ACTIVITY_SEL_2                     (2L<<17)
+#define BNX2_EMAC_LED_ACTIVITY_SEL_3                     (3L<<17)
 #define BNX2_EMAC_LED_BLNK_RATE                          (0xfffL<<19)
 #define BNX2_EMAC_LED_BLNK_RATE_ENA                      (1L<<31)
 
@@ -1515,9 +2660,15 @@ struct l2_fhdr {
 #define BNX2_EMAC_MDIO_COMM_PHY_ADDR                     (0x1fL<<21)
 #define BNX2_EMAC_MDIO_COMM_COMMAND                      (0x3L<<26)
 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0          (0L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS              (0L<<26)
 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE                (1L<<26)
 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ                 (2L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_22_XI          (1L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_45_XI          (1L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_READ_22_XI           (2L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI       (2L<<26)
 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3          (3L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_READ_45              (3L<<26)
 #define BNX2_EMAC_MDIO_COMM_FAIL                         (1L<<28)
 #define BNX2_EMAC_MDIO_COMM_START_BUSY                   (1L<<29)
 #define BNX2_EMAC_MDIO_COMM_DISEXT                       (1L<<30)
@@ -1534,13 +2685,17 @@ struct l2_fhdr {
 #define BNX2_EMAC_MDIO_MODE_MDIO_OE                      (1L<<10)
 #define BNX2_EMAC_MDIO_MODE_MDC                          (1L<<11)
 #define BNX2_EMAC_MDIO_MODE_MDINT                        (1L<<12)
+#define BNX2_EMAC_MDIO_MODE_EXT_MDINT                    (1L<<13)
 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT                    (0x1fL<<16)
+#define BNX2_EMAC_MDIO_MODE_CLOCK_CNT_XI                 (0x3fL<<16)
+#define BNX2_EMAC_MDIO_MODE_CLAUSE_45_XI                 (1L<<31)
 
 #define BNX2_EMAC_MDIO_AUTO_STATUS                      0x000014b8
 #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR              (1L<<0)
 
 #define BNX2_EMAC_TX_MODE                               0x000014bc
 #define BNX2_EMAC_TX_MODE_RESET                          (1L<<0)
+#define BNX2_EMAC_TX_MODE_CS16_TEST                      (1L<<2)
 #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN                   (1L<<3)
 #define BNX2_EMAC_TX_MODE_FLOW_EN                        (1L<<4)
 #define BNX2_EMAC_TX_MODE_BIG_BACKOFF                    (1L<<5)
@@ -1553,6 +2708,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_TX_STATUS_XON_SENT                     (1L<<2)
 #define BNX2_EMAC_TX_STATUS_LINK_UP                      (1L<<3)
 #define BNX2_EMAC_TX_STATUS_UNDERRUN                     (1L<<4)
+#define BNX2_EMAC_TX_STATUS_CS16_ERROR                   (1L<<5)
 
 #define BNX2_EMAC_TX_LENGTHS                            0x000014c4
 #define BNX2_EMAC_TX_LENGTHS_SLOT                        (0xffL<<0)
@@ -1586,6 +2742,10 @@ struct l2_fhdr {
 #define BNX2_EMAC_MULTICAST_HASH5                       0x000014e4
 #define BNX2_EMAC_MULTICAST_HASH6                       0x000014e8
 #define BNX2_EMAC_MULTICAST_HASH7                       0x000014ec
+#define BNX2_EMAC_CKSUM_ERROR_STATUS                    0x000014f0
+#define BNX2_EMAC_CKSUM_ERROR_STATUS_CALCULATED          (0xffffL<<0)
+#define BNX2_EMAC_CKSUM_ERROR_STATUS_EXPECTED            (0xffffL<<16)
+
 #define BNX2_EMAC_RX_STAT_IFHCINOCTETS                  0x00001500
 #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS               0x00001504
 #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS           0x00001508
@@ -1608,7 +2768,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x0000154c
 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001550
 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x00001554
-#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS  0x00001558
+#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS  0x00001558
 #define BNX2_EMAC_RXMAC_DEBUG0                          0x0000155c
 #define BNX2_EMAC_RXMAC_DEBUG1                          0x00001560
 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT      (1L<<0)
@@ -1661,9 +2821,9 @@ struct l2_fhdr {
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2          (0x1L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3          (0x2L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI            (0x3L<<16)
-#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2          (0x7L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3          (0x5L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1           (0x6L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2          (0x7L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2           (0x7L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3           (0x8L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2            (0x9L<<16)
@@ -1701,7 +2861,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED               (1L<<23)
 #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER             (1L<<24)
 #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA                 (1L<<25)
-#define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND                 (1L<<26)
+#define BNX2_EMAC_RXMAC_DEBUG4_SFD_FOUND                 (1L<<26)
 #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE                   (1L<<27)
 #define BNX2_EMAC_RXMAC_DEBUG4_START                     (1L<<28)
 
@@ -1733,6 +2893,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT            (1L<<19)
 #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN                     (0xfffL<<20)
 
+#define BNX2_EMAC_RX_STAT_FALSECARRIERERRORS            0x00001574
 #define BNX2_EMAC_RX_STAT_AC0                           0x00001580
 #define BNX2_EMAC_RX_STAT_AC1                           0x00001584
 #define BNX2_EMAC_RX_STAT_AC2                           0x00001588
@@ -1757,6 +2918,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_RX_STAT_AC21                          0x000015d4
 #define BNX2_EMAC_RX_STAT_AC22                          0x000015d8
 #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC              0x000015dc
+#define BNX2_EMAC_RX_STAT_AC_28                         0x000015f4
 #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS                 0x00001600
 #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS              0x00001604
 #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS          0x00001608
@@ -1777,7 +2939,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x00001644
 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001648
 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x0000164c
-#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS  0x00001650
+#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS  0x00001650
 #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS    0x00001654
 #define BNX2_EMAC_TXMAC_DEBUG0                          0x00001658
 #define BNX2_EMAC_TXMAC_DEBUG1                          0x0000165c
@@ -1843,16 +3005,16 @@ struct l2_fhdr {
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE          (0x0L<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1          (0x2L<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2          (0x3L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3          (0x4L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2          (0x5L<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3          (0x6L<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1          (0x7L<<16)
-#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2          (0x5L<<16)
-#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3          (0x4L<<16)
-#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE          (0xcL<<16)
-#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD           (0xeL<<16)
-#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME          (0xaL<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1          (0x8L<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2          (0x9L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME          (0xaL<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE          (0xcL<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT          (0xdL<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD           (0xeL<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID              (1L<<20)
 #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC                (1L<<21)
 #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED               (1L<<22)
@@ -1887,8 +3049,11 @@ struct l2_fhdr {
 #define BNX2_EMAC_TX_STAT_AC18                          0x000016c8
 #define BNX2_EMAC_TX_STAT_AC19                          0x000016cc
 #define BNX2_EMAC_TX_STAT_AC20                          0x000016d0
-#define BNX2_EMAC_TX_STAT_AC21                          0x000016d4
 #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC              0x000016d8
+#define BNX2_EMAC_TX_RATE_LIMIT_CTRL                    0x000016fc
+#define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC     (0x7fL<<0)
+#define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM     (0x7fL<<16)
+#define BNX2_EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN     (1L<<31)
 
 
 /*
@@ -1909,8 +3074,15 @@ struct l2_fhdr {
 #define BNX2_RPM_CONFIG_ACPI_KEEP                        (1L<<2)
 #define BNX2_RPM_CONFIG_MP_KEEP                          (1L<<3)
 #define BNX2_RPM_CONFIG_SORT_VECT_VAL                    (0xfL<<4)
+#define BNX2_RPM_CONFIG_DISABLE_WOL_ASSERT               (1L<<30)
 #define BNX2_RPM_CONFIG_IGNORE_VLAN                      (1L<<31)
 
+#define BNX2_RPM_MGMT_PKT_CTRL                          0x0000180c
+#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_SORT                 (0xfL<<0)
+#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_RULE                 (0xfL<<4)
+#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN           (1L<<30)
+#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_EN                   (1L<<31)
+
 #define BNX2_RPM_VLAN_MATCH0                            0x00001810
 #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE        (0xfffL<<0)
 
@@ -1931,6 +3103,7 @@ struct l2_fhdr {
 #define BNX2_RPM_SORT_USER0_PROM_EN                      (1L<<19)
 #define BNX2_RPM_SORT_USER0_VLAN_EN                      (0xfL<<20)
 #define BNX2_RPM_SORT_USER0_PROM_VLAN                    (1L<<24)
+#define BNX2_RPM_SORT_USER0_VLAN_NOTMATCH                (1L<<25)
 #define BNX2_RPM_SORT_USER0_ENA                          (1L<<31)
 
 #define BNX2_RPM_SORT_USER1                             0x00001824
@@ -1968,11 +3141,187 @@ struct l2_fhdr {
 #define BNX2_RPM_STAT_IFINFTQDISCARDS                   0x00001848
 #define BNX2_RPM_STAT_IFINMBUFDISCARD                   0x0000184c
 #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT               0x00001850
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0           0x00001854
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1           0x00001858
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2           0x0000185c
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3           0x00001860
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4           0x00001864
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5           0x00001868
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6           0x0000186c
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7           0x00001870
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN     (1L<<31)
+
 #define BNX2_RPM_STAT_AC0                               0x00001880
 #define BNX2_RPM_STAT_AC1                               0x00001884
 #define BNX2_RPM_STAT_AC2                               0x00001888
 #define BNX2_RPM_STAT_AC3                               0x0000188c
 #define BNX2_RPM_STAT_AC4                               0x00001890
+#define BNX2_RPM_RC_CNTL_16                             0x000018e0
+#define BNX2_RPM_RC_CNTL_16_OFFSET                       (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_16_CLASS                        (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_16_PRIORITY                     (1L<<11)
+#define BNX2_RPM_RC_CNTL_16_P4                           (1L<<12)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE                     (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_START               (0L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_IP                  (1L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP                 (2L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_UDP                 (3L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_DATA                (4L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP_UDP             (5L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_ICMPV6              (6L<<13)
+#define BNX2_RPM_RC_CNTL_16_COMP                         (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_16_COMP_EQUAL                   (0L<<16)
+#define BNX2_RPM_RC_CNTL_16_COMP_NEQUAL                  (1L<<16)
+#define BNX2_RPM_RC_CNTL_16_COMP_GREATER                 (2L<<16)
+#define BNX2_RPM_RC_CNTL_16_COMP_LESS                    (3L<<16)
+#define BNX2_RPM_RC_CNTL_16_MAP                          (1L<<18)
+#define BNX2_RPM_RC_CNTL_16_SBIT                         (1L<<19)
+#define BNX2_RPM_RC_CNTL_16_CMDSEL                       (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_16_DISCARD                      (1L<<25)
+#define BNX2_RPM_RC_CNTL_16_MASK                         (1L<<26)
+#define BNX2_RPM_RC_CNTL_16_P1                           (1L<<27)
+#define BNX2_RPM_RC_CNTL_16_P2                           (1L<<28)
+#define BNX2_RPM_RC_CNTL_16_P3                           (1L<<29)
+#define BNX2_RPM_RC_CNTL_16_NBIT                         (1L<<30)
+
+#define BNX2_RPM_RC_VALUE_MASK_16                       0x000018e4
+#define BNX2_RPM_RC_VALUE_MASK_16_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_16_MASK                   (0xffffL<<16)
+
+#define BNX2_RPM_RC_CNTL_17                             0x000018e8
+#define BNX2_RPM_RC_CNTL_17_OFFSET                       (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_17_CLASS                        (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_17_PRIORITY                     (1L<<11)
+#define BNX2_RPM_RC_CNTL_17_P4                           (1L<<12)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE                     (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_START               (0L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_IP                  (1L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP                 (2L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_UDP                 (3L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_DATA                (4L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP_UDP             (5L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_ICMPV6              (6L<<13)
+#define BNX2_RPM_RC_CNTL_17_COMP                         (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_17_COMP_EQUAL                   (0L<<16)
+#define BNX2_RPM_RC_CNTL_17_COMP_NEQUAL                  (1L<<16)
+#define BNX2_RPM_RC_CNTL_17_COMP_GREATER                 (2L<<16)
+#define BNX2_RPM_RC_CNTL_17_COMP_LESS                    (3L<<16)
+#define BNX2_RPM_RC_CNTL_17_MAP                          (1L<<18)
+#define BNX2_RPM_RC_CNTL_17_SBIT                         (1L<<19)
+#define BNX2_RPM_RC_CNTL_17_CMDSEL                       (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_17_DISCARD                      (1L<<25)
+#define BNX2_RPM_RC_CNTL_17_MASK                         (1L<<26)
+#define BNX2_RPM_RC_CNTL_17_P1                           (1L<<27)
+#define BNX2_RPM_RC_CNTL_17_P2                           (1L<<28)
+#define BNX2_RPM_RC_CNTL_17_P3                           (1L<<29)
+#define BNX2_RPM_RC_CNTL_17_NBIT                         (1L<<30)
+
+#define BNX2_RPM_RC_VALUE_MASK_17                       0x000018ec
+#define BNX2_RPM_RC_VALUE_MASK_17_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_17_MASK                   (0xffffL<<16)
+
+#define BNX2_RPM_RC_CNTL_18                             0x000018f0
+#define BNX2_RPM_RC_CNTL_18_OFFSET                       (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_18_CLASS                        (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_18_PRIORITY                     (1L<<11)
+#define BNX2_RPM_RC_CNTL_18_P4                           (1L<<12)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE                     (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_START               (0L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_IP                  (1L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP                 (2L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_UDP                 (3L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_DATA                (4L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP_UDP             (5L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_ICMPV6              (6L<<13)
+#define BNX2_RPM_RC_CNTL_18_COMP                         (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_18_COMP_EQUAL                   (0L<<16)
+#define BNX2_RPM_RC_CNTL_18_COMP_NEQUAL                  (1L<<16)
+#define BNX2_RPM_RC_CNTL_18_COMP_GREATER                 (2L<<16)
+#define BNX2_RPM_RC_CNTL_18_COMP_LESS                    (3L<<16)
+#define BNX2_RPM_RC_CNTL_18_MAP                          (1L<<18)
+#define BNX2_RPM_RC_CNTL_18_SBIT                         (1L<<19)
+#define BNX2_RPM_RC_CNTL_18_CMDSEL                       (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_18_DISCARD                      (1L<<25)
+#define BNX2_RPM_RC_CNTL_18_MASK                         (1L<<26)
+#define BNX2_RPM_RC_CNTL_18_P1                           (1L<<27)
+#define BNX2_RPM_RC_CNTL_18_P2                           (1L<<28)
+#define BNX2_RPM_RC_CNTL_18_P3                           (1L<<29)
+#define BNX2_RPM_RC_CNTL_18_NBIT                         (1L<<30)
+
+#define BNX2_RPM_RC_VALUE_MASK_18                       0x000018f4
+#define BNX2_RPM_RC_VALUE_MASK_18_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_18_MASK                   (0xffffL<<16)
+
+#define BNX2_RPM_RC_CNTL_19                             0x000018f8
+#define BNX2_RPM_RC_CNTL_19_OFFSET                       (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_19_CLASS                        (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_19_PRIORITY                     (1L<<11)
+#define BNX2_RPM_RC_CNTL_19_P4                           (1L<<12)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE                     (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_START               (0L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_IP                  (1L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP                 (2L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_UDP                 (3L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_DATA                (4L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP_UDP             (5L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_ICMPV6              (6L<<13)
+#define BNX2_RPM_RC_CNTL_19_COMP                         (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_19_COMP_EQUAL                   (0L<<16)
+#define BNX2_RPM_RC_CNTL_19_COMP_NEQUAL                  (1L<<16)
+#define BNX2_RPM_RC_CNTL_19_COMP_GREATER                 (2L<<16)
+#define BNX2_RPM_RC_CNTL_19_COMP_LESS                    (3L<<16)
+#define BNX2_RPM_RC_CNTL_19_MAP                          (1L<<18)
+#define BNX2_RPM_RC_CNTL_19_SBIT                         (1L<<19)
+#define BNX2_RPM_RC_CNTL_19_CMDSEL                       (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_19_DISCARD                      (1L<<25)
+#define BNX2_RPM_RC_CNTL_19_MASK                         (1L<<26)
+#define BNX2_RPM_RC_CNTL_19_P1                           (1L<<27)
+#define BNX2_RPM_RC_CNTL_19_P2                           (1L<<28)
+#define BNX2_RPM_RC_CNTL_19_P3                           (1L<<29)
+#define BNX2_RPM_RC_CNTL_19_NBIT                         (1L<<30)
+
+#define BNX2_RPM_RC_VALUE_MASK_19                       0x000018fc
+#define BNX2_RPM_RC_VALUE_MASK_19_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_19_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_0                              0x00001900
 #define BNX2_RPM_RC_CNTL_0_OFFSET                        (0xffL<<0)
 #define BNX2_RPM_RC_CNTL_0_CLASS                         (0x7L<<8)
@@ -1984,14 +3333,18 @@ struct l2_fhdr {
 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP                  (2L<<13)
 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP                  (3L<<13)
 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA                 (4L<<13)
+#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP_UDP              (5L<<13)
+#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_ICMPV6               (6L<<13)
 #define BNX2_RPM_RC_CNTL_0_COMP                          (0x3L<<16)
 #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL                    (0L<<16)
 #define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL                   (1L<<16)
 #define BNX2_RPM_RC_CNTL_0_COMP_GREATER                  (2L<<16)
 #define BNX2_RPM_RC_CNTL_0_COMP_LESS                     (3L<<16)
+#define BNX2_RPM_RC_CNTL_0_MAP_XI                        (1L<<18)
 #define BNX2_RPM_RC_CNTL_0_SBIT                          (1L<<19)
 #define BNX2_RPM_RC_CNTL_0_CMDSEL                        (0xfL<<20)
 #define BNX2_RPM_RC_CNTL_0_MAP                           (1L<<24)
+#define BNX2_RPM_RC_CNTL_0_CMDSEL_XI                     (0x1fL<<20)
 #define BNX2_RPM_RC_CNTL_0_DISCARD                       (1L<<25)
 #define BNX2_RPM_RC_CNTL_0_MASK                          (1L<<26)
 #define BNX2_RPM_RC_CNTL_0_P1                            (1L<<27)
@@ -2006,81 +3359,518 @@ struct l2_fhdr {
 #define BNX2_RPM_RC_CNTL_1                              0x00001908
 #define BNX2_RPM_RC_CNTL_1_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_1_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_1_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_1_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_1_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_1_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_1_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_1_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_1_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_1_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_1_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_1_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_1_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_1_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_1_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_1_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_1_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_1_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_1_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_1_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_1                        0x0000190c
+#define BNX2_RPM_RC_VALUE_MASK_1_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_1_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_2                              0x00001910
 #define BNX2_RPM_RC_CNTL_2_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_2_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_2_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_2_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_2_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_2_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_2_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_2_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_2_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_2_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_2_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_2_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_2_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_2_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_2_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_2_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_2_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_2_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_2_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_2_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_2                        0x00001914
+#define BNX2_RPM_RC_VALUE_MASK_2_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_2_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_3                              0x00001918
 #define BNX2_RPM_RC_CNTL_3_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_3_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_3_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_3_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_3_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_3_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_3_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_3_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_3_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_3_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_3_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_3_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_3_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_3_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_3_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_3_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_3_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_3_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_3_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_3_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_3                        0x0000191c
+#define BNX2_RPM_RC_VALUE_MASK_3_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_3_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_4                              0x00001920
 #define BNX2_RPM_RC_CNTL_4_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_4_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_4_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_4_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_4_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_4_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_4_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_4_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_4_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_4_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_4_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_4_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_4_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_4_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_4_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_4_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_4_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_4_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_4_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_4_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_4                        0x00001924
+#define BNX2_RPM_RC_VALUE_MASK_4_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_4_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_5                              0x00001928
 #define BNX2_RPM_RC_CNTL_5_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_5_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_5_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_5_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_5_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_5_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_5_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_5_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_5_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_5_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_5_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_5_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_5_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_5_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_5_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_5_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_5_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_5_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_5_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_5_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_5                        0x0000192c
+#define BNX2_RPM_RC_VALUE_MASK_5_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_5_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_6                              0x00001930
 #define BNX2_RPM_RC_CNTL_6_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_6_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_6_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_6_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_6_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_6_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_6_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_6_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_6_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_6_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_6_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_6_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_6_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_6_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_6_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_6_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_6_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_6_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_6_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_6_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_6                        0x00001934
+#define BNX2_RPM_RC_VALUE_MASK_6_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_6_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_7                              0x00001938
 #define BNX2_RPM_RC_CNTL_7_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_7_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_7_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_7_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_7_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_7_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_7_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_7_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_7_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_7_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_7_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_7_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_7_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_7_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_7_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_7_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_7_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_7_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_7_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_7_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_7                        0x0000193c
+#define BNX2_RPM_RC_VALUE_MASK_7_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_7_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_8                              0x00001940
 #define BNX2_RPM_RC_CNTL_8_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_8_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_8_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_8_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_8_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_8_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_8_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_8_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_8_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_8_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_8_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_8_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_8_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_8_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_8_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_8_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_8_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_8_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_8_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_8_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_8                        0x00001944
+#define BNX2_RPM_RC_VALUE_MASK_8_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_8_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_9                              0x00001948
 #define BNX2_RPM_RC_CNTL_9_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_9_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_9_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_9_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_9_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_9_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_9_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_9_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_9_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_9_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_9_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_9_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_9_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_9_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_9_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_9_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_9_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_9_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_9_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_9_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_9                        0x0000194c
+#define BNX2_RPM_RC_VALUE_MASK_9_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_9_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_10                             0x00001950
 #define BNX2_RPM_RC_CNTL_10_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_10_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_10_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_10_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_10_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_10_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_10_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_10_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_10_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_10_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_10_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_10_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_10_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_10_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_10_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_10_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_10_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_10_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_10_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_10_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_10                       0x00001954
+#define BNX2_RPM_RC_VALUE_MASK_10_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_10_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_11                             0x00001958
 #define BNX2_RPM_RC_CNTL_11_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_11_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_11_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_11_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_11_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_11_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_11_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_11_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_11_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_11_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_11_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_11_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_11_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_11_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_11_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_11_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_11_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_11_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_11_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_11_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_11                       0x0000195c
+#define BNX2_RPM_RC_VALUE_MASK_11_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_11_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_12                             0x00001960
 #define BNX2_RPM_RC_CNTL_12_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_12_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_12_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_12_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_12_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_12_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_12_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_12_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_12_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_12_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_12_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_12_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_12_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_12_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_12_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_12_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_12_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_12_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_12_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_12_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_12                       0x00001964
+#define BNX2_RPM_RC_VALUE_MASK_12_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_12_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_13                             0x00001968
 #define BNX2_RPM_RC_CNTL_13_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_13_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_13_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_13_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_13_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_13_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_13_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_13_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_13_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_13_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_13_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_13_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_13_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_13_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_13_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_13_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_13_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_13_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_13_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_13_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_13                       0x0000196c
+#define BNX2_RPM_RC_VALUE_MASK_13_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_13_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_14                             0x00001970
 #define BNX2_RPM_RC_CNTL_14_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_14_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_14_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_14_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_14_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_14_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_14_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_14_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_14_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_14_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_14_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_14_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_14_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_14_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_14_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_14_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_14_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_14_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_14_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_14_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_14                       0x00001974
+#define BNX2_RPM_RC_VALUE_MASK_14_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_14_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_15                             0x00001978
 #define BNX2_RPM_RC_CNTL_15_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_15_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_15_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_15_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_15_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_15_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_15_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_15_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_15_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_15_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_15_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_15_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_15_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_15_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_15_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_15_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_15_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_15_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_15_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_15_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_15                       0x0000197c
+#define BNX2_RPM_RC_VALUE_MASK_15_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_15_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CONFIG                              0x00001980
 #define BNX2_RPM_RC_CONFIG_RULE_ENABLE                   (0xffffL<<0)
+#define BNX2_RPM_RC_CONFIG_RULE_ENABLE_XI                (0xfffffL<<0)
 #define BNX2_RPM_RC_CONFIG_DEF_CLASS                     (0x7L<<24)
+#define BNX2_RPM_RC_CONFIG_KNUM_OVERWRITE                (1L<<31)
 
 #define BNX2_RPM_DEBUG0                                 0x00001984
 #define BNX2_RPM_DEBUG0_FM_BCNT                          (0xffffL<<0)
@@ -2236,6 +4026,16 @@ struct l2_fhdr {
 #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED          (1L<<29)
 #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT                   (1L<<30)
 #define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN                  (1L<<31)
+#define BNX2_RPM_DEBUG9_BEMEM_R_XI                       (0x1fL<<0)
+#define BNX2_RPM_DEBUG9_EO_XI                            (1L<<5)
+#define BNX2_RPM_DEBUG9_AEOF_DE_XI                       (1L<<6)
+#define BNX2_RPM_DEBUG9_SO_XI                            (1L<<7)
+#define BNX2_RPM_DEBUG9_WD64_CT_XI                       (0x1fL<<8)
+#define BNX2_RPM_DEBUG9_EOF_VLDBYTE_XI                   (0x7L<<13)
+#define BNX2_RPM_DEBUG9_ACPI_RDE_PAT_ID_XI               (0xfL<<16)
+#define BNX2_RPM_DEBUG9_CALCRC_RESULT_XI                 (0x3ffL<<20)
+#define BNX2_RPM_DEBUG9_DATA_IN_VL_XI                    (1L<<30)
+#define BNX2_RPM_DEBUG9_CALCRC_BUFFER_VLD_XI             (1L<<31)
 
 #define BNX2_RPM_ACPI_DBG_BUF_W00                       0x000019c0
 #define BNX2_RPM_ACPI_DBG_BUF_W01                       0x000019c4
@@ -2253,6 +4053,56 @@ struct l2_fhdr {
 #define BNX2_RPM_ACPI_DBG_BUF_W31                       0x000019f4
 #define BNX2_RPM_ACPI_DBG_BUF_W32                       0x000019f8
 #define BNX2_RPM_ACPI_DBG_BUF_W33                       0x000019fc
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL                  0x00001a00
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_BYTE_ADDRESS      (0xffffL<<0)
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_DEBUGRD           (1L<<28)
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_MODE              (1L<<29)
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_INIT              (1L<<30)
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_WR                (1L<<31)
+
+#define BNX2_RPM_ACPI_PATTERN_CTRL                      0x00001a04
+#define BNX2_RPM_ACPI_PATTERN_CTRL_PATTERN_ID            (0xfL<<0)
+#define BNX2_RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR            (1L<<30)
+#define BNX2_RPM_ACPI_PATTERN_CTRL_WR                    (1L<<31)
+
+#define BNX2_RPM_ACPI_DATA                              0x00001a08
+#define BNX2_RPM_ACPI_DATA_PATTERN_BE                    (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_LEN0                      0x00001a0c
+#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN3          (0xffL<<0)
+#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN2          (0xffL<<8)
+#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN1          (0xffL<<16)
+#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN0          (0xffL<<24)
+
+#define BNX2_RPM_ACPI_PATTERN_LEN1                      0x00001a10
+#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN7          (0xffL<<0)
+#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN6          (0xffL<<8)
+#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN5          (0xffL<<16)
+#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN4          (0xffL<<24)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC0                      0x00001a18
+#define BNX2_RPM_ACPI_PATTERN_CRC0_PATTERN_CRC0          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC1                      0x00001a1c
+#define BNX2_RPM_ACPI_PATTERN_CRC1_PATTERN_CRC1          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC2                      0x00001a20
+#define BNX2_RPM_ACPI_PATTERN_CRC2_PATTERN_CRC2          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC3                      0x00001a24
+#define BNX2_RPM_ACPI_PATTERN_CRC3_PATTERN_CRC3          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC4                      0x00001a28
+#define BNX2_RPM_ACPI_PATTERN_CRC4_PATTERN_CRC4          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC5                      0x00001a2c
+#define BNX2_RPM_ACPI_PATTERN_CRC5_PATTERN_CRC5          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC6                      0x00001a30
+#define BNX2_RPM_ACPI_PATTERN_CRC6_PATTERN_CRC6          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC7                      0x00001a34
+#define BNX2_RPM_ACPI_PATTERN_CRC7_PATTERN_CRC7          (0xffffffffL<<0)
 
 
 /*
@@ -2263,15 +4113,20 @@ struct l2_fhdr {
 #define BNX2_RBUF_COMMAND_ENABLED                        (1L<<0)
 #define BNX2_RBUF_COMMAND_FREE_INIT                      (1L<<1)
 #define BNX2_RBUF_COMMAND_RAM_INIT                       (1L<<2)
+#define BNX2_RBUF_COMMAND_PKT_OFFSET_OVFL                (1L<<3)
 #define BNX2_RBUF_COMMAND_OVER_FREE                      (1L<<4)
 #define BNX2_RBUF_COMMAND_ALLOC_REQ                      (1L<<5)
+#define BNX2_RBUF_COMMAND_EN_PRI_CHNGE_TE                (1L<<6)
+#define BNX2_RBUF_COMMAND_CU_ISOLATE_XI                  (1L<<5)
+#define BNX2_RBUF_COMMAND_EN_PRI_CHANGE_XI               (1L<<6)
+#define BNX2_RBUF_COMMAND_GRC_ENDIAN_CONV_DIS_XI         (1L<<7)
 
 #define BNX2_RBUF_STATUS1                               0x00200004
 #define BNX2_RBUF_STATUS1_FREE_COUNT                     (0x3ffL<<0)
 
 #define BNX2_RBUF_STATUS2                               0x00200008
-#define BNX2_RBUF_STATUS2_FREE_TAIL                      (0x3ffL<<0)
-#define BNX2_RBUF_STATUS2_FREE_HEAD                      (0x3ffL<<16)
+#define BNX2_RBUF_STATUS2_FREE_TAIL                      (0x1ffL<<0)
+#define BNX2_RBUF_STATUS2_FREE_HEAD                      (0x1ffL<<16)
 
 #define BNX2_RBUF_CONFIG                                0x0020000c
 #define BNX2_RBUF_CONFIG_XOFF_TRIP                       (0x3ffL<<0)
@@ -2279,16 +4134,21 @@ struct l2_fhdr {
 
 #define BNX2_RBUF_FW_BUF_ALLOC                          0x00200010
 #define BNX2_RBUF_FW_BUF_ALLOC_VALUE                     (0x1ffL<<7)
+#define BNX2_RBUF_FW_BUF_ALLOC_TYPE                      (1L<<16)
+#define BNX2_RBUF_FW_BUF_ALLOC_ALLOC_REQ                 (1L<<31)
 
 #define BNX2_RBUF_FW_BUF_FREE                           0x00200014
 #define BNX2_RBUF_FW_BUF_FREE_COUNT                      (0x7fL<<0)
 #define BNX2_RBUF_FW_BUF_FREE_TAIL                       (0x1ffL<<7)
 #define BNX2_RBUF_FW_BUF_FREE_HEAD                       (0x1ffL<<16)
+#define BNX2_RBUF_FW_BUF_FREE_TYPE                       (1L<<25)
+#define BNX2_RBUF_FW_BUF_FREE_FREE_REQ                   (1L<<31)
 
 #define BNX2_RBUF_FW_BUF_SEL                            0x00200018
 #define BNX2_RBUF_FW_BUF_SEL_COUNT                       (0x7fL<<0)
 #define BNX2_RBUF_FW_BUF_SEL_TAIL                        (0x1ffL<<7)
 #define BNX2_RBUF_FW_BUF_SEL_HEAD                        (0x1ffL<<16)
+#define BNX2_RBUF_FW_BUF_SEL_SEL_REQ                     (1L<<31)
 
 #define BNX2_RBUF_CONFIG2                               0x0020001c
 #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP                  (0x3ffL<<0)
@@ -2376,6 +4236,8 @@ struct l2_fhdr {
 #define BNX2_RV2P_INSTR_HIGH_HIGH                        (0x1fL<<0)
 
 #define BNX2_RV2P_INSTR_LOW                             0x00002834
+#define BNX2_RV2P_INSTR_LOW_LOW                          (0xffffffffL<<0)
+
 #define BNX2_RV2P_PROC1_ADDR_CMD                        0x00002838
 #define BNX2_RV2P_PROC1_ADDR_CMD_ADD                     (0x3ffL<<0)
 #define BNX2_RV2P_PROC1_ADDR_CMD_RDWR                    (1L<<31)
@@ -2395,7 +4257,29 @@ struct l2_fhdr {
 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN              (1L<<27)
 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL                  (0xfL<<28)
 
-#define BNX2_RV2P_PFTQ_DATA                             0x00002b40
+#define BNX2_RV2P_MPFE_PFE_CTL                          0x00002afc
+#define BNX2_RV2P_MPFE_PFE_CTL_INC_USAGE_CNT             (1L<<0)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE                  (0xfL<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_0                (0L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_1                (1L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_2                (2L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_3                (3L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_4                (4L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_5                (5L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_6                (6L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_7                (7L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_8                (8L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_9                (9L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_10               (10L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_11               (11L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_12               (12L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_13               (13L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_14               (14L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_15               (15L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_COUNT                 (0xfL<<12)
+#define BNX2_RV2P_MPFE_PFE_CTL_OFFSET                    (0x1ffL<<16)
+
+#define BNX2_RV2P_RV2PPQ                                0x00002b40
 #define BNX2_RV2P_PFTQ_CMD                              0x00002b78
 #define BNX2_RV2P_PFTQ_CMD_OFFSET                        (0x3ffL<<0)
 #define BNX2_RV2P_PFTQ_CMD_WR_TOP                        (1L<<10)
@@ -2416,7 +4300,7 @@ struct l2_fhdr {
 #define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
 #define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
 
-#define BNX2_RV2P_TFTQ_DATA                             0x00002b80
+#define BNX2_RV2P_RV2PTQ                                0x00002b80
 #define BNX2_RV2P_TFTQ_CMD                              0x00002bb8
 #define BNX2_RV2P_TFTQ_CMD_OFFSET                        (0x3ffL<<0)
 #define BNX2_RV2P_TFTQ_CMD_WR_TOP                        (1L<<10)
@@ -2437,7 +4321,7 @@ struct l2_fhdr {
 #define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
 #define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
 
-#define BNX2_RV2P_MFTQ_DATA                             0x00002bc0
+#define BNX2_RV2P_RV2PMQ                                0x00002bc0
 #define BNX2_RV2P_MFTQ_CMD                              0x00002bf8
 #define BNX2_RV2P_MFTQ_CMD_OFFSET                        (0x3ffL<<0)
 #define BNX2_RV2P_MFTQ_CMD_WR_TOP                        (1L<<10)
@@ -2466,18 +4350,26 @@ struct l2_fhdr {
  */
 #define BNX2_MQ_COMMAND                                 0x00003c00
 #define BNX2_MQ_COMMAND_ENABLED                          (1L<<0)
+#define BNX2_MQ_COMMAND_INIT                             (1L<<1)
 #define BNX2_MQ_COMMAND_OVERFLOW                         (1L<<4)
 #define BNX2_MQ_COMMAND_WR_ERROR                         (1L<<5)
 #define BNX2_MQ_COMMAND_RD_ERROR                         (1L<<6)
+#define BNX2_MQ_COMMAND_IDB_CFG_ERROR                    (1L<<7)
+#define BNX2_MQ_COMMAND_IDB_OVERFLOW                     (1L<<10)
+#define BNX2_MQ_COMMAND_NO_BIN_ERROR                     (1L<<11)
+#define BNX2_MQ_COMMAND_NO_MAP_ERROR                     (1L<<12)
 
 #define BNX2_MQ_STATUS                                  0x00003c04
 #define BNX2_MQ_STATUS_CTX_ACCESS_STAT                   (1L<<16)
 #define BNX2_MQ_STATUS_CTX_ACCESS64_STAT                 (1L<<17)
 #define BNX2_MQ_STATUS_PCI_STALL_STAT                    (1L<<18)
+#define BNX2_MQ_STATUS_IDB_OFLOW_STAT                    (1L<<19)
 
 #define BNX2_MQ_CONFIG                                  0x00003c08
 #define BNX2_MQ_CONFIG_TX_HIGH_PRI                       (1L<<0)
 #define BNX2_MQ_CONFIG_HALT_DIS                          (1L<<1)
+#define BNX2_MQ_CONFIG_BIN_MQ_MODE                       (1L<<2)
+#define BNX2_MQ_CONFIG_DIS_IDB_DROP                      (1L<<3)
 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE                  (0x7L<<4)
 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256              (0L<<4)
 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512              (1L<<4)
@@ -2533,6 +4425,7 @@ struct l2_fhdr {
 
 #define BNX2_MQ_MEM_WR_DATA2                            0x00003c80
 #define BNX2_MQ_MEM_WR_DATA2_VALUE                       (0x3fffffffL<<0)
+#define BNX2_MQ_MEM_WR_DATA2_VALUE_XI                    (0x7fffffffL<<0)
 
 #define BNX2_MQ_MEM_RD_ADDR                             0x00003c84
 #define BNX2_MQ_MEM_RD_ADDR_VALUE                        (0x3fL<<0)
@@ -2545,6 +4438,16 @@ struct l2_fhdr {
 
 #define BNX2_MQ_MEM_RD_DATA2                            0x00003c90
 #define BNX2_MQ_MEM_RD_DATA2_VALUE                       (0x3fffffffL<<0)
+#define BNX2_MQ_MEM_RD_DATA2_VALUE_XI                    (0x7fffffffL<<0)
+
+
+/*
+ *  tsch_reg definition
+ *  offset: 0x4c00
+ */
+#define BNX2_TSCH_TSS_CFG                               0x00004c1c
+#define BNX2_TSCH_TSS_CFG_TSS_START_CID                  (0x7ffL<<8)
+#define BNX2_TSCH_TSS_CFG_NUM_OF_TSS_CON                 (0xfL<<24)
 
 
 
@@ -2594,7 +4497,11 @@ struct l2_fhdr {
 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN              (1L<<27)
 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL                  (0xfL<<28)
 
-#define BNX2_TBDR_FTQ_DATA                              0x000053c0
+#define BNX2_TBDR_CKSUM_ERROR_STATUS                    0x00005010
+#define BNX2_TBDR_CKSUM_ERROR_STATUS_CALCULATED          (0xffffL<<0)
+#define BNX2_TBDR_CKSUM_ERROR_STATUS_EXPECTED            (0xffffL<<16)
+
+#define BNX2_TBDR_TBDRQ                                 0x000053c0
 #define BNX2_TBDR_FTQ_CMD                               0x000053f8
 #define BNX2_TBDR_FTQ_CMD_OFFSET                         (0x3ffL<<0)
 #define BNX2_TBDR_FTQ_CMD_WR_TOP                         (1L<<10)
@@ -2624,7 +4531,15 @@ struct l2_fhdr {
 #define BNX2_TDMA_COMMAND                               0x00005c00
 #define BNX2_TDMA_COMMAND_ENABLED                        (1L<<0)
 #define BNX2_TDMA_COMMAND_MASTER_ABORT                   (1L<<4)
+#define BNX2_TDMA_COMMAND_CS16_ERR                       (1L<<5)
 #define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT            (1L<<7)
+#define BNX2_TDMA_COMMAND_MASK_CS1                       (1L<<20)
+#define BNX2_TDMA_COMMAND_MASK_CS2                       (1L<<21)
+#define BNX2_TDMA_COMMAND_MASK_CS3                       (1L<<22)
+#define BNX2_TDMA_COMMAND_MASK_CS4                       (1L<<23)
+#define BNX2_TDMA_COMMAND_FORCE_ILOCK_CKERR              (1L<<24)
+#define BNX2_TDMA_COMMAND_OFIFO_CLR                      (1L<<30)
+#define BNX2_TDMA_COMMAND_IFIFO_CLR                      (1L<<31)
 
 #define BNX2_TDMA_STATUS                                0x00005c04
 #define BNX2_TDMA_STATUS_DMA_WAIT                        (1L<<0)
@@ -2633,10 +4548,18 @@ struct l2_fhdr {
 #define BNX2_TDMA_STATUS_LOCK_WAIT                       (1L<<3)
 #define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT                   (1L<<16)
 #define BNX2_TDMA_STATUS_BURST_CNT                       (1L<<17)
+#define BNX2_TDMA_STATUS_MAX_IFIFO_DEPTH                 (0x3fL<<20)
+#define BNX2_TDMA_STATUS_OFIFO_OVERFLOW                  (1L<<30)
+#define BNX2_TDMA_STATUS_IFIFO_OVERFLOW                  (1L<<31)
 
 #define BNX2_TDMA_CONFIG                                0x00005c08
 #define BNX2_TDMA_CONFIG_ONE_DMA                         (1L<<0)
 #define BNX2_TDMA_CONFIG_ONE_RECORD                      (1L<<1)
+#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN                    (0x3L<<2)
+#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_0                  (0L<<2)
+#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_1                  (1L<<2)
+#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_2                  (2L<<2)
+#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_3                  (3L<<2)
 #define BNX2_TDMA_CONFIG_LIMIT_SZ                        (0xfL<<4)
 #define BNX2_TDMA_CONFIG_LIMIT_SZ_64                     (0L<<4)
 #define BNX2_TDMA_CONFIG_LIMIT_SZ_128                    (0x4L<<4)
@@ -2649,7 +4572,35 @@ struct l2_fhdr {
 #define BNX2_TDMA_CONFIG_LINE_SZ_512                     (8L<<8)
 #define BNX2_TDMA_CONFIG_ALIGN_ENA                       (1L<<15)
 #define BNX2_TDMA_CONFIG_CHK_L2_BD                       (1L<<16)
+#define BNX2_TDMA_CONFIG_CMPL_ENTRY                      (1L<<17)
+#define BNX2_TDMA_CONFIG_OFIFO_CMP                       (1L<<19)
+#define BNX2_TDMA_CONFIG_OFIFO_CMP_3                     (0L<<19)
+#define BNX2_TDMA_CONFIG_OFIFO_CMP_2                     (1L<<19)
 #define BNX2_TDMA_CONFIG_FIFO_CMP                        (0xfL<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_XI                  (0x7L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_0_XI                (0L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_4_XI                (1L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_8_XI                (2L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_16_XI               (3L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_32_XI               (4L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_64_XI               (5L<<20)
+#define BNX2_TDMA_CONFIG_FIFO_CMP_EN_XI                  (1L<<23)
+#define BNX2_TDMA_CONFIG_BYTES_OST_XI                    (0x7L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_512_XI                (0L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_1024_XI               (1L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_2048_XI               (2L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_4096_XI               (3L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_8192_XI               (4L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_16384_XI              (5L<<24)
+#define BNX2_TDMA_CONFIG_HC_BYPASS_XI                    (1L<<27)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_XI                     (0x7L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_128_XI                 (0L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_256_XI                 (1L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_512_XI                 (2L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_1024_XI                (3L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_2048_XI                (4L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_4096_XI                (5L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_EN_XI                  (1L<<31)
 
 #define BNX2_TDMA_PAYLOAD_PROD                          0x00005c0c
 #define BNX2_TDMA_PAYLOAD_PROD_VALUE                     (0x1fffL<<3)
@@ -2685,7 +4636,22 @@ struct l2_fhdr {
 #define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR                (0xfL<<12)
 #define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT              (0x7L<<16)
 
-#define BNX2_TDMA_FTQ_DATA                              0x00005fc0
+#define BNX2_TDMA_PUSH_FSM                              0x00005c90
+#define BNX2_TDMA_BD_IF_DEBUG                           0x00005c94
+#define BNX2_TDMA_DMAD_IF_DEBUG                         0x00005c98
+#define BNX2_TDMA_CTX_IF_DEBUG                          0x00005c9c
+#define BNX2_TDMA_TPBUF_IF_DEBUG                        0x00005ca0
+#define BNX2_TDMA_DR_IF_DEBUG                           0x00005ca4
+#define BNX2_TDMA_TPATQ_IF_DEBUG                        0x00005ca8
+#define BNX2_TDMA_TDMA_ILOCK_CKSUM                      0x00005cac
+#define BNX2_TDMA_TDMA_ILOCK_CKSUM_CALCULATED            (0xffffL<<0)
+#define BNX2_TDMA_TDMA_ILOCK_CKSUM_EXPECTED              (0xffffL<<16)
+
+#define BNX2_TDMA_TDMA_PCIE_CKSUM                       0x00005cb0
+#define BNX2_TDMA_TDMA_PCIE_CKSUM_CALCULATED             (0xffffL<<0)
+#define BNX2_TDMA_TDMA_PCIE_CKSUM_EXPECTED               (0xffffL<<16)
+
+#define BNX2_TDMA_TDMAQ                                 0x00005fc0
 #define BNX2_TDMA_FTQ_CMD                               0x00005ff8
 #define BNX2_TDMA_FTQ_CMD_OFFSET                         (0x3ffL<<0)
 #define BNX2_TDMA_FTQ_CMD_WR_TOP                         (1L<<10)
@@ -2724,6 +4690,8 @@ struct l2_fhdr {
 #define BNX2_HC_COMMAND_FORCE_INT_LOW                    (2L<<19)
 #define BNX2_HC_COMMAND_FORCE_INT_FREE                   (3L<<19)
 #define BNX2_HC_COMMAND_CLR_STAT_NOW                     (1L<<21)
+#define BNX2_HC_COMMAND_MAIN_PWR_INT                     (1L<<22)
+#define BNX2_HC_COMMAND_COAL_ON_NEXT_EVENT               (1L<<27)
 
 #define BNX2_HC_STATUS                                  0x00006804
 #define BNX2_HC_STATUS_MASTER_ABORT                      (1L<<0)
@@ -2746,6 +4714,23 @@ struct l2_fhdr {
 #define BNX2_HC_CONFIG_STATISTIC_PRIORITY                (1L<<5)
 #define BNX2_HC_CONFIG_STATUS_PRIORITY                   (1L<<6)
 #define BNX2_HC_CONFIG_STAT_MEM_ADDR                     (0xffL<<8)
+#define BNX2_HC_CONFIG_PER_MODE                          (1L<<16)
+#define BNX2_HC_CONFIG_ONE_SHOT                          (1L<<17)
+#define BNX2_HC_CONFIG_USE_INT_PARAM                     (1L<<18)
+#define BNX2_HC_CONFIG_SET_MASK_AT_RD                    (1L<<19)
+#define BNX2_HC_CONFIG_PER_COLLECT_LIMIT                 (0xfL<<20)
+#define BNX2_HC_CONFIG_SB_ADDR_INC                       (0x7L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_64B                   (0L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_128B                  (1L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_256B                  (2L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_512B                  (3L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_1024B                 (4L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_2048B                 (5L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_4096B                 (6L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_8192B                 (7L<<24)
+#define BNX2_HC_CONFIG_GEN_STAT_AVG_INTR                 (1L<<29)
+#define BNX2_HC_CONFIG_UNMASK_ALL                        (1L<<30)
+#define BNX2_HC_CONFIG_TX_SEL                            (1L<<31)
 
 #define BNX2_HC_ATTN_BITS_ENABLE                        0x0000680c
 #define BNX2_HC_STATUS_ADDR_L                           0x00006810
@@ -2782,6 +4767,7 @@ struct l2_fhdr {
 
 #define BNX2_HC_PERIODIC_TICKS                          0x0000683c
 #define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS         (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS     (0xffffL<<16)
 
 #define BNX2_HC_STAT_COLLECT_TICKS                      0x00006840
 #define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS    (0xffL<<4)
@@ -2789,6 +4775,10 @@ struct l2_fhdr {
 #define BNX2_HC_STATS_TICKS                             0x00006844
 #define BNX2_HC_STATS_TICKS_HC_STAT_TICKS                (0xffffL<<8)
 
+#define BNX2_HC_STATS_INTERRUPT_STATUS                  0x00006848
+#define BNX2_HC_STATS_INTERRUPT_STATUS_SB_STATUS         (0x1ffL<<0)
+#define BNX2_HC_STATS_INTERRUPT_STATUS_INT_STATUS        (0x1ffL<<16)
+
 #define BNX2_HC_STAT_MEM_DATA                           0x0000684c
 #define BNX2_HC_STAT_GEN_SEL_0                          0x00006850
 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0                 (0x7fL<<0)
@@ -2917,24 +4907,108 @@ struct l2_fhdr {
 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1                 (0x7fL<<8)
 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2                 (0x7fL<<16)
 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3                 (0x7fL<<24)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI              (0xffL<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI    (52L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI    (57L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI    (58L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI    (85L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI    (86L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI    (87L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI    (88L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI    (89L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI    (90L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI    (91L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI    (92L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI   (93L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI         (94L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI       (123L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI       (124L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI     (125L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI   (126L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI    (128L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI  (129L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI      (130L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI       (131L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI       (132L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI   (133L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI    (134L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI  (135L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI      (136L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI       (137L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI       (138L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI   (139L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI    (140L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI  (141L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI      (142L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI       (143L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI       (144L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI   (145L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI    (146L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI  (147L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI      (148L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI       (149L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI       (150L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI   (151L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI    (152L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI  (153L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI      (154L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI       (155L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI       (156L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI   (157L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI    (158L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI  (159L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI      (160L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI       (161L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI       (162L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI   (163L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI    (164L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI  (165L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI      (166L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI       (167L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI       (168L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI   (169L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI    (170L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI  (171L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI      (172L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI       (173L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI       (174L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI   (175L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI       (176L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI      (177L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI    (178L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI              (0xffL<<8)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI              (0xffL<<16)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI              (0xffL<<24)
 
 #define BNX2_HC_STAT_GEN_SEL_1                          0x00006854
 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4                 (0x7fL<<0)
 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5                 (0x7fL<<8)
 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6                 (0x7fL<<16)
 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7                 (0x7fL<<24)
+#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI              (0xffL<<0)
+#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI              (0xffL<<8)
+#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI              (0xffL<<16)
+#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI              (0xffL<<24)
 
 #define BNX2_HC_STAT_GEN_SEL_2                          0x00006858
 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8                 (0x7fL<<0)
 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9                 (0x7fL<<8)
 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10                (0x7fL<<16)
 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11                (0x7fL<<24)
+#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI              (0xffL<<0)
+#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI              (0xffL<<8)
+#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI             (0xffL<<16)
+#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI             (0xffL<<24)
 
 #define BNX2_HC_STAT_GEN_SEL_3                          0x0000685c
 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12                (0x7fL<<0)
 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13                (0x7fL<<8)
 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14                (0x7fL<<16)
 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15                (0x7fL<<24)
+#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI             (0xffL<<0)
+#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI             (0xffL<<8)
+#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI             (0xffL<<16)
+#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI             (0xffL<<24)
 
 #define BNX2_HC_STAT_GEN_STAT0                          0x00006888
 #define BNX2_HC_STAT_GEN_STAT1                          0x0000688c
@@ -2968,6 +5042,7 @@ struct l2_fhdr {
 #define BNX2_HC_STAT_GEN_STAT_AC13                      0x000068fc
 #define BNX2_HC_STAT_GEN_STAT_AC14                      0x00006900
 #define BNX2_HC_STAT_GEN_STAT_AC15                      0x00006904
+#define BNX2_HC_STAT_GEN_STAT_AC                        0x000068c8
 #define BNX2_HC_VIS                                     0x00006908
 #define BNX2_HC_VIS_STAT_BUILD_STATE                     (0xfL<<0)
 #define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE                (0L<<0)
@@ -3038,6 +5113,349 @@ struct l2_fhdr {
 #define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN                (1L<<27)
 #define BNX2_HC_DEBUG_VECT_PEEK_2_SEL                    (0xfL<<28)
 
+#define BNX2_HC_COALESCE_NOW                            0x00006914
+#define BNX2_HC_COALESCE_NOW_COAL_NOW                    (0x1ffL<<1)
+#define BNX2_HC_COALESCE_NOW_COAL_NOW_WO_INT             (0x1ffL<<11)
+#define BNX2_HC_COALESCE_NOW_COAL_ON_NXT_EVENT           (0x1ffL<<21)
+
+#define BNX2_HC_MSIX_BIT_VECTOR                         0x00006918
+#define BNX2_HC_MSIX_BIT_VECTOR_VAL                      (0x1ffL<<0)
+
+#define BNX2_HC_SB_CONFIG_1                             0x00006a00
+#define BNX2_HC_SB_CONFIG_1_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_1_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_1_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_1_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_1_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_1_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_1_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_1_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_1                    0x00006a04
+#define BNX2_HC_TX_QUICK_CONS_TRIP_1_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_1_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_1                        0x00006a08
+#define BNX2_HC_COMP_PROD_TRIP_1_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_1_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_1                    0x00006a0c
+#define BNX2_HC_RX_QUICK_CONS_TRIP_1_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_1_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_1                              0x00006a10
+#define BNX2_HC_RX_TICKS_1_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_1_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_1                              0x00006a14
+#define BNX2_HC_TX_TICKS_1_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_1_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_1                             0x00006a18
+#define BNX2_HC_COM_TICKS_1_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_1_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_1                             0x00006a1c
+#define BNX2_HC_CMD_TICKS_1_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_1_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_1                        0x00006a20
+#define BNX2_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_2                             0x00006a24
+#define BNX2_HC_SB_CONFIG_2_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_2_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_2_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_2_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_2_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_2_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_2_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_2_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_2                    0x00006a28
+#define BNX2_HC_TX_QUICK_CONS_TRIP_2_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_2_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_2                        0x00006a2c
+#define BNX2_HC_COMP_PROD_TRIP_2_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_2_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_2                    0x00006a30
+#define BNX2_HC_RX_QUICK_CONS_TRIP_2_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_2_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_2                              0x00006a34
+#define BNX2_HC_RX_TICKS_2_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_2_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_2                              0x00006a38
+#define BNX2_HC_TX_TICKS_2_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_2_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_2                             0x00006a3c
+#define BNX2_HC_COM_TICKS_2_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_2_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_2                             0x00006a40
+#define BNX2_HC_CMD_TICKS_2_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_2_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_2                        0x00006a44
+#define BNX2_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_3                             0x00006a48
+#define BNX2_HC_SB_CONFIG_3_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_3_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_3_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_3_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_3_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_3_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_3_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_3_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_3                    0x00006a4c
+#define BNX2_HC_TX_QUICK_CONS_TRIP_3_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_3_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_3                        0x00006a50
+#define BNX2_HC_COMP_PROD_TRIP_3_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_3_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_3                    0x00006a54
+#define BNX2_HC_RX_QUICK_CONS_TRIP_3_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_3_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_3                              0x00006a58
+#define BNX2_HC_RX_TICKS_3_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_3_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_3                              0x00006a5c
+#define BNX2_HC_TX_TICKS_3_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_3_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_3                             0x00006a60
+#define BNX2_HC_COM_TICKS_3_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_3_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_3                             0x00006a64
+#define BNX2_HC_CMD_TICKS_3_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_3_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_3                        0x00006a68
+#define BNX2_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_4                             0x00006a6c
+#define BNX2_HC_SB_CONFIG_4_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_4_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_4_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_4_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_4_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_4_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_4_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_4_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_4                    0x00006a70
+#define BNX2_HC_TX_QUICK_CONS_TRIP_4_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_4_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_4                        0x00006a74
+#define BNX2_HC_COMP_PROD_TRIP_4_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_4_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_4                    0x00006a78
+#define BNX2_HC_RX_QUICK_CONS_TRIP_4_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_4_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_4                              0x00006a7c
+#define BNX2_HC_RX_TICKS_4_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_4_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_4                              0x00006a80
+#define BNX2_HC_TX_TICKS_4_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_4_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_4                             0x00006a84
+#define BNX2_HC_COM_TICKS_4_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_4_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_4                             0x00006a88
+#define BNX2_HC_CMD_TICKS_4_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_4_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_4                        0x00006a8c
+#define BNX2_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_5                             0x00006a90
+#define BNX2_HC_SB_CONFIG_5_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_5_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_5_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_5_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_5_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_5_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_5_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_5_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_5                    0x00006a94
+#define BNX2_HC_TX_QUICK_CONS_TRIP_5_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_5_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_5                        0x00006a98
+#define BNX2_HC_COMP_PROD_TRIP_5_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_5_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_5                    0x00006a9c
+#define BNX2_HC_RX_QUICK_CONS_TRIP_5_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_5_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_5                              0x00006aa0
+#define BNX2_HC_RX_TICKS_5_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_5_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_5                              0x00006aa4
+#define BNX2_HC_TX_TICKS_5_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_5_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_5                             0x00006aa8
+#define BNX2_HC_COM_TICKS_5_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_5_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_5                             0x00006aac
+#define BNX2_HC_CMD_TICKS_5_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_5_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_5                        0x00006ab0
+#define BNX2_HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_6                             0x00006ab4
+#define BNX2_HC_SB_CONFIG_6_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_6_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_6_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_6_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_6_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_6_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_6_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_6_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_6                    0x00006ab8
+#define BNX2_HC_TX_QUICK_CONS_TRIP_6_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_6_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_6                        0x00006abc
+#define BNX2_HC_COMP_PROD_TRIP_6_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_6_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_6                    0x00006ac0
+#define BNX2_HC_RX_QUICK_CONS_TRIP_6_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_6_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_6                              0x00006ac4
+#define BNX2_HC_RX_TICKS_6_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_6_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_6                              0x00006ac8
+#define BNX2_HC_TX_TICKS_6_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_6_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_6                             0x00006acc
+#define BNX2_HC_COM_TICKS_6_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_6_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_6                             0x00006ad0
+#define BNX2_HC_CMD_TICKS_6_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_6_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_6                        0x00006ad4
+#define BNX2_HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_7                             0x00006ad8
+#define BNX2_HC_SB_CONFIG_7_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_7_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_7_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_7_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_7_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_7_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_7_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_7_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_7                    0x00006adc
+#define BNX2_HC_TX_QUICK_CONS_TRIP_7_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_7_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_7                        0x00006ae0
+#define BNX2_HC_COMP_PROD_TRIP_7_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_7_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_7                    0x00006ae4
+#define BNX2_HC_RX_QUICK_CONS_TRIP_7_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_7_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_7                              0x00006ae8
+#define BNX2_HC_RX_TICKS_7_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_7_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_7                              0x00006aec
+#define BNX2_HC_TX_TICKS_7_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_7_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_7                             0x00006af0
+#define BNX2_HC_COM_TICKS_7_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_7_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_7                             0x00006af4
+#define BNX2_HC_CMD_TICKS_7_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_7_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_7                        0x00006af8
+#define BNX2_HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_8                             0x00006afc
+#define BNX2_HC_SB_CONFIG_8_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_8_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_8_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_8_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_8_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_8_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_8_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_8_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_8                    0x00006b00
+#define BNX2_HC_TX_QUICK_CONS_TRIP_8_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_8_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_8                        0x00006b04
+#define BNX2_HC_COMP_PROD_TRIP_8_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_8_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_8                    0x00006b08
+#define BNX2_HC_RX_QUICK_CONS_TRIP_8_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_8_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_8                              0x00006b0c
+#define BNX2_HC_RX_TICKS_8_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_8_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_8                              0x00006b10
+#define BNX2_HC_TX_TICKS_8_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_8_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_8                             0x00006b14
+#define BNX2_HC_COM_TICKS_8_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_8_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_8                             0x00006b18
+#define BNX2_HC_CMD_TICKS_8_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_8_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_8                        0x00006b1c
+#define BNX2_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
 
 
 /*
@@ -3063,7 +5481,7 @@ struct l2_fhdr {
 #define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
 #define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
 #define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
-#define BNX2_TXP_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
+#define BNX2_TXP_CPU_STATE_BAD_PC_HALTED                 (1L<<6)
 #define BNX2_TXP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
 #define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
 #define BNX2_TXP_CPU_STATE_SOFT_HALTED                   (1L<<10)
@@ -3111,7 +5529,7 @@ struct l2_fhdr {
 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
 
 #define BNX2_TXP_CPU_REG_FILE                           0x00045200
-#define BNX2_TXP_FTQ_DATA                               0x000453c0
+#define BNX2_TXP_TXPQ                                   0x000453c0
 #define BNX2_TXP_FTQ_CMD                                0x000453f8
 #define BNX2_TXP_FTQ_CMD_OFFSET                          (0x3ffL<<0)
 #define BNX2_TXP_FTQ_CMD_WR_TOP                          (1L<<10)
@@ -3158,7 +5576,7 @@ struct l2_fhdr {
 #define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED           (1L<<3)
 #define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED           (1L<<4)
 #define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED         (1L<<5)
-#define BNX2_TPAT_CPU_STATE_BAD_pc_HALTED                (1L<<6)
+#define BNX2_TPAT_CPU_STATE_BAD_PC_HALTED                (1L<<6)
 #define BNX2_TPAT_CPU_STATE_ALIGN_HALTED                 (1L<<7)
 #define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED             (1L<<8)
 #define BNX2_TPAT_CPU_STATE_SOFT_HALTED                  (1L<<10)
@@ -3206,7 +5624,7 @@ struct l2_fhdr {
 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA               (0x3fffffffL<<2)
 
 #define BNX2_TPAT_CPU_REG_FILE                          0x00085200
-#define BNX2_TPAT_FTQ_DATA                              0x000853c0
+#define BNX2_TPAT_TPATQ                                 0x000853c0
 #define BNX2_TPAT_FTQ_CMD                               0x000853f8
 #define BNX2_TPAT_FTQ_CMD_OFFSET                         (0x3ffL<<0)
 #define BNX2_TPAT_FTQ_CMD_WR_TOP                         (1L<<10)
@@ -3253,7 +5671,7 @@ struct l2_fhdr {
 #define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
 #define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
 #define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
-#define BNX2_RXP_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
+#define BNX2_RXP_CPU_STATE_BAD_PC_HALTED                 (1L<<6)
 #define BNX2_RXP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
 #define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
 #define BNX2_RXP_CPU_STATE_SOFT_HALTED                   (1L<<10)
@@ -3301,7 +5719,29 @@ struct l2_fhdr {
 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
 
 #define BNX2_RXP_CPU_REG_FILE                           0x000c5200
-#define BNX2_RXP_CFTQ_DATA                              0x000c5380
+#define BNX2_RXP_PFE_PFE_CTL                            0x000c537c
+#define BNX2_RXP_PFE_PFE_CTL_INC_USAGE_CNT               (1L<<0)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE                    (0xfL<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_0                  (0L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_1                  (1L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_2                  (2L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_3                  (3L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_4                  (4L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_5                  (5L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_6                  (6L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_7                  (7L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_8                  (8L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_9                  (9L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_10                 (10L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_11                 (11L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_12                 (12L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_13                 (13L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_14                 (14L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_15                 (15L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_COUNT                   (0xfL<<12)
+#define BNX2_RXP_PFE_PFE_CTL_OFFSET                      (0x1ffL<<16)
+
+#define BNX2_RXP_RXPCQ                                  0x000c5380
 #define BNX2_RXP_CFTQ_CMD                               0x000c53b8
 #define BNX2_RXP_CFTQ_CMD_OFFSET                         (0x3ffL<<0)
 #define BNX2_RXP_CFTQ_CMD_WR_TOP                         (1L<<10)
@@ -3322,7 +5762,7 @@ struct l2_fhdr {
 #define BNX2_RXP_CFTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
 #define BNX2_RXP_CFTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
 
-#define BNX2_RXP_FTQ_DATA                               0x000c53c0
+#define BNX2_RXP_RXPQ                                   0x000c53c0
 #define BNX2_RXP_FTQ_CMD                                0x000c53f8
 #define BNX2_RXP_FTQ_CMD_OFFSET                          (0x3ffL<<0)
 #define BNX2_RXP_FTQ_CMD_WR_TOP                          (1L<<10)
@@ -3350,6 +5790,10 @@ struct l2_fhdr {
  *  com_reg definition
  *  offset: 0x100000
  */
+#define BNX2_COM_CKSUM_ERROR_STATUS                     0x00100000
+#define BNX2_COM_CKSUM_ERROR_STATUS_CALCULATED           (0xffffL<<0)
+#define BNX2_COM_CKSUM_ERROR_STATUS_EXPECTED             (0xffffL<<16)
+
 #define BNX2_COM_CPU_MODE                               0x00105000
 #define BNX2_COM_CPU_MODE_LOCAL_RST                      (1L<<0)
 #define BNX2_COM_CPU_MODE_STEP_ENA                       (1L<<1)
@@ -3369,7 +5813,7 @@ struct l2_fhdr {
 #define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
 #define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
 #define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
-#define BNX2_COM_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
+#define BNX2_COM_CPU_STATE_BAD_PC_HALTED                 (1L<<6)
 #define BNX2_COM_CPU_STATE_ALIGN_HALTED                  (1L<<7)
 #define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
 #define BNX2_COM_CPU_STATE_SOFT_HALTED                   (1L<<10)
@@ -3417,7 +5861,29 @@ struct l2_fhdr {
 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
 
 #define BNX2_COM_CPU_REG_FILE                           0x00105200
-#define BNX2_COM_COMXQ_FTQ_DATA                         0x00105340
+#define BNX2_COM_COMTQ_PFE_PFE_CTL                      0x001052bc
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_INC_USAGE_CNT         (1L<<0)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE              (0xfL<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_0            (0L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_1            (1L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_2            (2L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_3            (3L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_4            (4L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_5            (5L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_6            (6L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_7            (7L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_8            (8L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_9            (9L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_10           (10L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_11           (11L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_12           (12L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_13           (13L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_14           (14L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_15           (15L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_COUNT             (0xfL<<12)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_OFFSET                (0x1ffL<<16)
+
+#define BNX2_COM_COMXQ                                  0x00105340
 #define BNX2_COM_COMXQ_FTQ_CMD                          0x00105378
 #define BNX2_COM_COMXQ_FTQ_CMD_OFFSET                    (0x3ffL<<0)
 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP                    (1L<<10)
@@ -3438,7 +5904,7 @@ struct l2_fhdr {
 #define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH                 (0x3ffL<<12)
 #define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH                 (0x3ffL<<22)
 
-#define BNX2_COM_COMTQ_FTQ_DATA                         0x00105380
+#define BNX2_COM_COMTQ                                  0x00105380
 #define BNX2_COM_COMTQ_FTQ_CMD                          0x001053b8
 #define BNX2_COM_COMTQ_FTQ_CMD_OFFSET                    (0x3ffL<<0)
 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP                    (1L<<10)
@@ -3459,7 +5925,7 @@ struct l2_fhdr {
 #define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH                 (0x3ffL<<12)
 #define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH                 (0x3ffL<<22)
 
-#define BNX2_COM_COMQ_FTQ_DATA                          0x001053c0
+#define BNX2_COM_COMQ                                   0x001053c0
 #define BNX2_COM_COMQ_FTQ_CMD                           0x001053f8
 #define BNX2_COM_COMQ_FTQ_CMD_OFFSET                     (0x3ffL<<0)
 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP                     (1L<<10)
@@ -3489,6 +5955,10 @@ struct l2_fhdr {
  *  cp_reg definition
  *  offset: 0x180000
  */
+#define BNX2_CP_CKSUM_ERROR_STATUS                      0x00180000
+#define BNX2_CP_CKSUM_ERROR_STATUS_CALCULATED            (0xffffL<<0)
+#define BNX2_CP_CKSUM_ERROR_STATUS_EXPECTED              (0xffffL<<16)
+
 #define BNX2_CP_CPU_MODE                                0x00185000
 #define BNX2_CP_CPU_MODE_LOCAL_RST                       (1L<<0)
 #define BNX2_CP_CPU_MODE_STEP_ENA                        (1L<<1)
@@ -3508,7 +5978,7 @@ struct l2_fhdr {
 #define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED             (1L<<3)
 #define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED             (1L<<4)
 #define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED           (1L<<5)
-#define BNX2_CP_CPU_STATE_BAD_pc_HALTED                  (1L<<6)
+#define BNX2_CP_CPU_STATE_BAD_PC_HALTED                  (1L<<6)
 #define BNX2_CP_CPU_STATE_ALIGN_HALTED                   (1L<<7)
 #define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED               (1L<<8)
 #define BNX2_CP_CPU_STATE_SOFT_HALTED                    (1L<<10)
@@ -3556,7 +6026,29 @@ struct l2_fhdr {
 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA                 (0x3fffffffL<<2)
 
 #define BNX2_CP_CPU_REG_FILE                            0x00185200
-#define BNX2_CP_CPQ_FTQ_DATA                            0x001853c0
+#define BNX2_CP_CPQ_PFE_PFE_CTL                         0x001853bc
+#define BNX2_CP_CPQ_PFE_PFE_CTL_INC_USAGE_CNT            (1L<<0)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE                 (0xfL<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_0               (0L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_1               (1L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_2               (2L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_3               (3L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_4               (4L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_5               (5L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_6               (6L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_7               (7L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_8               (8L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_9               (9L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_10              (10L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_11              (11L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_12              (12L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_13              (13L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_14              (14L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_15              (15L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_COUNT                (0xfL<<12)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_OFFSET                   (0x1ffL<<16)
+
+#define BNX2_CP_CPQ                                     0x001853c0
 #define BNX2_CP_CPQ_FTQ_CMD                             0x001853f8
 #define BNX2_CP_CPQ_FTQ_CMD_OFFSET                       (0x3ffL<<0)
 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP                       (1L<<10)
@@ -3584,6 +6076,59 @@ struct l2_fhdr {
  *  mcp_reg definition
  *  offset: 0x140000
  */
+#define BNX2_MCP_MCP_CONTROL                            0x00140080
+#define BNX2_MCP_MCP_CONTROL_SMBUS_SEL                   (1L<<30)
+#define BNX2_MCP_MCP_CONTROL_MCP_ISOLATE                 (1L<<31)
+
+#define BNX2_MCP_MCP_ATTENTION_STATUS                   0x00140084
+#define BNX2_MCP_MCP_ATTENTION_STATUS_DRV_DOORBELL       (1L<<29)
+#define BNX2_MCP_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT   (1L<<30)
+#define BNX2_MCP_MCP_ATTENTION_STATUS_CPU_EVENT          (1L<<31)
+
+#define BNX2_MCP_MCP_HEARTBEAT_CONTROL                  0x00140088
+#define BNX2_MCP_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE      (1L<<31)
+
+#define BNX2_MCP_MCP_HEARTBEAT_STATUS                   0x0014008c
+#define BNX2_MCP_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD       (0x7ffL<<0)
+#define BNX2_MCP_MCP_HEARTBEAT_STATUS_VALID              (1L<<31)
+
+#define BNX2_MCP_MCP_HEARTBEAT                          0x00140090
+#define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT       (0x3fffffffL<<0)
+#define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_INC         (1L<<30)
+#define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET       (1L<<31)
+
+#define BNX2_MCP_WATCHDOG_RESET                         0x00140094
+#define BNX2_MCP_WATCHDOG_RESET_WATCHDOG_RESET           (1L<<31)
+
+#define BNX2_MCP_WATCHDOG_CONTROL                       0x00140098
+#define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_TIMEOUT       (0xfffffffL<<0)
+#define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ATTN          (1L<<29)
+#define BNX2_MCP_WATCHDOG_CONTROL_MCP_RST_ENABLE         (1L<<30)
+#define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ENABLE        (1L<<31)
+
+#define BNX2_MCP_ACCESS_LOCK                            0x0014009c
+#define BNX2_MCP_ACCESS_LOCK_LOCK                        (1L<<31)
+
+#define BNX2_MCP_TOE_ID                                 0x001400a0
+#define BNX2_MCP_TOE_ID_FUNCTION_ID                      (1L<<31)
+
+#define BNX2_MCP_MAILBOX_CFG                            0x001400a4
+#define BNX2_MCP_MAILBOX_CFG_MAILBOX_OFFSET              (0x3fffL<<0)
+#define BNX2_MCP_MAILBOX_CFG_MAILBOX_SIZE                (0xfffL<<20)
+
+#define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC                 0x001400a8
+#define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET   (0x3fffL<<0)
+#define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE     (0xfffL<<20)
+
+#define BNX2_MCP_MCP_DOORBELL                           0x001400ac
+#define BNX2_MCP_MCP_DOORBELL_MCP_DOORBELL               (1L<<31)
+
+#define BNX2_MCP_DRIVER_DOORBELL                        0x001400b0
+#define BNX2_MCP_DRIVER_DOORBELL_DRIVER_DOORBELL         (1L<<31)
+
+#define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC             0x001400b4
+#define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC_DRIVER_DOORBELL      (1L<<31)
+
 #define BNX2_MCP_CPU_MODE                               0x00145000
 #define BNX2_MCP_CPU_MODE_LOCAL_RST                      (1L<<0)
 #define BNX2_MCP_CPU_MODE_STEP_ENA                       (1L<<1)
@@ -3603,7 +6148,7 @@ struct l2_fhdr {
 #define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
 #define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
 #define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
-#define BNX2_MCP_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
+#define BNX2_MCP_CPU_STATE_BAD_PC_HALTED                 (1L<<6)
 #define BNX2_MCP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
 #define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
 #define BNX2_MCP_CPU_STATE_SOFT_HALTED                   (1L<<10)
@@ -3651,7 +6196,7 @@ struct l2_fhdr {
 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
 
 #define BNX2_MCP_CPU_REG_FILE                           0x00145200
-#define BNX2_MCP_MCPQ_FTQ_DATA                          0x001453c0
+#define BNX2_MCP_MCPQ                                   0x001453c0
 #define BNX2_MCP_MCPQ_FTQ_CMD                           0x001453f8
 #define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET                     (0x3ffL<<0)
 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP                     (1L<<10)
@@ -3696,6 +6241,8 @@ struct l2_fhdr {
 
 /* 5708 Serdes PHY registers */
 
+#define BCM5708S_BMCR_FORCE_2500                0x20
+
 #define BCM5708S_UP1                            0xb
 
 #define BCM5708S_UP1_2G5                        0x1
@@ -3804,6 +6351,7 @@ struct l2_fhdr {
 #define INVALID_CID_ADDR            0xffffffff
 
 #define TX_CID          16
+#define TX_TSS_CID      32
 #define RX_CID          0
 
 #define MB_TX_CID_ADDR  MB_GET_CID_ADDR(TX_CID)
@@ -3889,6 +6437,8 @@ struct bnx2 {
 
         u32             tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
         u16             tx_prod;
+        u32             tx_bidx_addr;
+        u32             tx_bseq_addr;
 
         u16             tx_cons __attribute__((aligned(L1_CACHE_BYTES)));
         u16             hw_tx_cons;
@@ -3945,6 +6495,7 @@ struct bnx2 {
 #define CHIP_NUM(bp)                    (((bp)->chip_id) & 0xffff0000)
 #define CHIP_NUM_5706                   0x57060000
 #define CHIP_NUM_5708                   0x57080000
+#define CHIP_NUM_5709                   0x57090000
 
 #define CHIP_REV(bp)                    (((bp)->chip_id) & 0x0000f000)
 #define CHIP_REV_Ax                     0x00000000
@@ -4007,6 +6558,10 @@ struct bnx2 {
         struct statistics_block *stats_blk;
         dma_addr_t              stats_blk_mapping;
 
+        int                     ctx_pages;
+        void                    *ctx_blk[4];
+        dma_addr_t              ctx_blk_mapping[4];
+
         u32                     hc_cmd;
         u32                     rx_mode;
 
@@ -4038,6 +6593,7 @@ struct bnx2 {
 
         u8                      serdes_an_pending;
 #define SERDES_AN_TIMEOUT       (HZ / 3)
+#define SERDES_FORCED_TIMEOUT   (HZ / 10)
 
         u8                      mac_addr[8];
 
@@ -4104,41 +6660,43 @@ struct cpu_reg {
 };
 
 struct fw_info {
-        u32 ver_major;
-        u32 ver_minor;
-        u32 ver_fix;
+        const u32 ver_major;
+        const u32 ver_minor;
+        const u32 ver_fix;
 
-        u32 start_addr;
+        const u32 start_addr;
 
         /* Text section. */
-        u32 text_addr;
-        u32 text_len;
-        u32 text_index;
+        const u32 text_addr;
+        const u32 text_len;
+        const u32 text_index;
         u32 *text;
+        u8 *gz_text;
+        const u32 gz_text_len;
 
         /* Data section. */
-        u32 data_addr;
-        u32 data_len;
-        u32 data_index;
-        u32 *data;
+        const u32 data_addr;
+        const u32 data_len;
+        const u32 data_index;
+        const u32 *data;
 
         /* SBSS section. */
-        u32 sbss_addr;
-        u32 sbss_len;
-        u32 sbss_index;
-        u32 *sbss;
+        const u32 sbss_addr;
+        const u32 sbss_len;
+        const u32 sbss_index;
+        const u32 *sbss;
 
         /* BSS section. */
-        u32 bss_addr;
-        u32 bss_len;
-        u32 bss_index;
-        u32 *bss;
+        const u32 bss_addr;
+        const u32 bss_len;
+        const u32 bss_index;
+        const u32 *bss;
 
         /* Read-only section. */
-        u32 rodata_addr;
-        u32 rodata_len;
-        u32 rodata_index;
-        u32 *rodata;
+        const u32 rodata_addr;
+        const u32 rodata_len;
+        const u32 rodata_index;
+        const u32 *rodata;
 };
 
 #define RV2P_PROC1                              0