diff options
Diffstat (limited to 'drivers/net/bnx2.h')
| -rw-r--r-- | drivers/net/bnx2.h | 1457 |
1 files changed, 1311 insertions, 146 deletions
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h index 11e9c55d1dd0..73c785585fc3 100644 --- a/drivers/net/bnx2.h +++ b/drivers/net/bnx2.h | |||
| @@ -56,6 +56,7 @@ struct rx_bd { | |||
| 56 | 56 | ||
| 57 | }; | 57 | }; |
| 58 | 58 | ||
| 59 | #define BNX2_RX_ALIGN 16 | ||
| 59 | 60 | ||
| 60 | /* | 61 | /* |
| 61 | * status_block definition | 62 | * status_block definition |
| @@ -90,6 +91,7 @@ struct status_block { | |||
| 90 | #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) | 91 | #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) |
| 91 | #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) | 92 | #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) |
| 92 | #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) | 93 | #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) |
| 94 | #define STATUS_ATTN_BITS_EPB_ERROR (1L<<30) | ||
| 93 | #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) | 95 | #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) |
| 94 | 96 | ||
| 95 | u32 status_attn_bits_ack; | 97 | u32 status_attn_bits_ack; |
| @@ -117,7 +119,8 @@ struct status_block { | |||
| 117 | u16 status_completion_producer_index; | 119 | u16 status_completion_producer_index; |
| 118 | u16 status_cmd_consumer_index; | 120 | u16 status_cmd_consumer_index; |
| 119 | u16 status_idx; | 121 | u16 status_idx; |
| 120 | u16 status_unused; | 122 | u8 status_unused; |
| 123 | u8 status_blk_num; | ||
| 121 | #elif defined(__LITTLE_ENDIAN) | 124 | #elif defined(__LITTLE_ENDIAN) |
| 122 | u16 status_tx_quick_consumer_index1; | 125 | u16 status_tx_quick_consumer_index1; |
| 123 | u16 status_tx_quick_consumer_index0; | 126 | u16 status_tx_quick_consumer_index0; |
| @@ -141,7 +144,8 @@ struct status_block { | |||
| 141 | u16 status_rx_quick_consumer_index14; | 144 | u16 status_rx_quick_consumer_index14; |
| 142 | u16 status_cmd_consumer_index; | 145 | u16 status_cmd_consumer_index; |
| 143 | u16 status_completion_producer_index; | 146 | u16 status_completion_producer_index; |
| 144 | u16 status_unused; | 147 | u8 status_blk_num; |
| 148 | u8 status_unused; | ||
| 145 | u16 status_idx; | 149 | u16 status_idx; |
| 146 | #endif | 150 | #endif |
| 147 | }; | 151 | }; |
| @@ -301,6 +305,10 @@ struct l2_fhdr { | |||
| 301 | #define BNX2_L2CTX_TXP_BIDX 0x000000a8 | 305 | #define BNX2_L2CTX_TXP_BIDX 0x000000a8 |
| 302 | #define BNX2_L2CTX_TXP_BSEQ 0x000000ac | 306 | #define BNX2_L2CTX_TXP_BSEQ 0x000000ac |
| 303 | 307 | ||
| 308 | #define BNX2_L2CTX_TYPE_XI 0x00000080 | ||
| 309 | #define BNX2_L2CTX_CMD_TYPE_XI 0x00000240 | ||
| 310 | #define BNX2_L2CTX_TBDR_BHADDR_HI_XI 0x00000258 | ||
| 311 | #define BNX2_L2CTX_TBDR_BHADDR_LO_XI 0x0000025c | ||
| 304 | 312 | ||
| 305 | /* | 313 | /* |
| 306 | * l2_bd_chain_context definition | 314 | * l2_bd_chain_context definition |
| @@ -328,11 +336,15 @@ struct l2_fhdr { | |||
| 328 | #define BNX2_PCICFG_MISC_CONFIG 0x00000068 | 336 | #define BNX2_PCICFG_MISC_CONFIG 0x00000068 |
| 329 | #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) | 337 | #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) |
| 330 | #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) | 338 | #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) |
| 339 | #define BNX2_PCICFG_MISC_CONFIG_RESERVED1 (1L<<4) | ||
| 331 | #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) | 340 | #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) |
| 332 | #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) | 341 | #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) |
| 333 | #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) | 342 | #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) |
| 334 | #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) | 343 | #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) |
| 335 | #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) | 344 | #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) |
| 345 | #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN (1L<<10) | ||
| 346 | #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN (1L<<11) | ||
| 347 | #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN (1L<<12) | ||
| 336 | #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) | 348 | #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) |
| 337 | #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) | 349 | #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) |
| 338 | #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) | 350 | #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) |
| @@ -347,6 +359,7 @@ struct l2_fhdr { | |||
| 347 | #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) | 359 | #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) |
| 348 | #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) | 360 | #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) |
| 349 | #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) | 361 | #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) |
| 362 | #define BNX2_PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE (1L<<8) | ||
| 350 | 363 | ||
| 351 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 | 364 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 |
| 352 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) | 365 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) |
| @@ -366,7 +379,7 @@ struct l2_fhdr { | |||
| 366 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) | 379 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) |
| 367 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) | 380 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) |
| 368 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) | 381 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) |
| 369 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) | 382 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER (1L<<11) |
| 370 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) | 383 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) |
| 371 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) | 384 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) |
| 372 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) | 385 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) |
| @@ -374,18 +387,21 @@ struct l2_fhdr { | |||
| 374 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) | 387 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) |
| 375 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) | 388 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) |
| 376 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) | 389 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) |
| 377 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) | 390 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17 (1L<<17) |
| 378 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) | 391 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) |
| 379 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) | 392 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19 (1L<<19) |
| 380 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) | 393 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) |
| 381 | 394 | ||
| 382 | #define BNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078 | 395 | #define BNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078 |
| 396 | #define BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL (0xfffffL<<2) | ||
| 397 | |||
| 383 | #define BNX2_PCICFG_REG_WINDOW 0x00000080 | 398 | #define BNX2_PCICFG_REG_WINDOW 0x00000080 |
| 384 | #define BNX2_PCICFG_INT_ACK_CMD 0x00000084 | 399 | #define BNX2_PCICFG_INT_ACK_CMD 0x00000084 |
| 385 | #define BNX2_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) | 400 | #define BNX2_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) |
| 386 | #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) | 401 | #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) |
| 387 | #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) | 402 | #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) |
| 388 | #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) | 403 | #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) |
| 404 | #define BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM (0xfL<<24) | ||
| 389 | 405 | ||
| 390 | #define BNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088 | 406 | #define BNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088 |
| 391 | #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c | 407 | #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c |
| @@ -398,9 +414,11 @@ struct l2_fhdr { | |||
| 398 | * offset: 0x400 | 414 | * offset: 0x400 |
| 399 | */ | 415 | */ |
| 400 | #define BNX2_PCI_GRC_WINDOW_ADDR 0x00000400 | 416 | #define BNX2_PCI_GRC_WINDOW_ADDR 0x00000400 |
| 401 | #define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8) | 417 | #define BNX2_PCI_GRC_WINDOW_ADDR_VALUE (0x1ffL<<13) |
| 418 | #define BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN (1L<<31) | ||
| 402 | 419 | ||
| 403 | #define BNX2_PCI_CONFIG_1 0x00000404 | 420 | #define BNX2_PCI_CONFIG_1 0x00000404 |
| 421 | #define BNX2_PCI_CONFIG_1_RESERVED0 (0xffL<<0) | ||
| 404 | #define BNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) | 422 | #define BNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) |
| 405 | #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) | 423 | #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) |
| 406 | #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) | 424 | #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) |
| @@ -419,6 +437,7 @@ struct l2_fhdr { | |||
| 419 | #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) | 437 | #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) |
| 420 | #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) | 438 | #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) |
| 421 | #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) | 439 | #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) |
| 440 | #define BNX2_PCI_CONFIG_1_RESERVED1 (0x3ffffL<<14) | ||
| 422 | 441 | ||
| 423 | #define BNX2_PCI_CONFIG_2 0x00000408 | 442 | #define BNX2_PCI_CONFIG_2 0x00000408 |
| 424 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) | 443 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) |
| @@ -468,9 +487,13 @@ struct l2_fhdr { | |||
| 468 | #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) | 487 | #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) |
| 469 | #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) | 488 | #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) |
| 470 | #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) | 489 | #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) |
| 490 | #define BNX2_PCI_CONFIG_2_RESERVED0 (0x3fL<<26) | ||
| 491 | #define BNX2_PCI_CONFIG_2_BAR_PREFETCH_XI (1L<<16) | ||
| 492 | #define BNX2_PCI_CONFIG_2_RESERVED0_XI (0x7fffL<<17) | ||
| 471 | 493 | ||
| 472 | #define BNX2_PCI_CONFIG_3 0x0000040c | 494 | #define BNX2_PCI_CONFIG_3 0x0000040c |
| 473 | #define BNX2_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) | 495 | #define BNX2_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) |
| 496 | #define BNX2_PCI_CONFIG_3_REG_STICKY_BYTE (0xffL<<8) | ||
| 474 | #define BNX2_PCI_CONFIG_3_FORCE_PME (1L<<24) | 497 | #define BNX2_PCI_CONFIG_3_FORCE_PME (1L<<24) |
| 475 | #define BNX2_PCI_CONFIG_3_PME_STATUS (1L<<25) | 498 | #define BNX2_PCI_CONFIG_3_PME_STATUS (1L<<25) |
| 476 | #define BNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26) | 499 | #define BNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26) |
| @@ -501,8 +524,10 @@ struct l2_fhdr { | |||
| 501 | #define BNX2_PCI_VPD_INTF_INTF_REQ (1L<<0) | 524 | #define BNX2_PCI_VPD_INTF_INTF_REQ (1L<<0) |
| 502 | 525 | ||
| 503 | #define BNX2_PCI_VPD_ADDR_FLAG 0x0000042c | 526 | #define BNX2_PCI_VPD_ADDR_FLAG 0x0000042c |
| 504 | #define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) | 527 | #define BNX2_PCI_VPD_ADDR_FLAG_MSK 0x0000ffff |
| 505 | #define BNX2_PCI_VPD_ADDR_FLAG_WR (1<<15) | 528 | #define BNX2_PCI_VPD_ADDR_FLAG_SL 0L |
| 529 | #define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fffL<<2) | ||
| 530 | #define BNX2_PCI_VPD_ADDR_FLAG_WR (1L<<15) | ||
| 506 | 531 | ||
| 507 | #define BNX2_PCI_VPD_DATA 0x00000430 | 532 | #define BNX2_PCI_VPD_DATA 0x00000430 |
| 508 | #define BNX2_PCI_ID_VAL1 0x00000434 | 533 | #define BNX2_PCI_ID_VAL1 0x00000434 |
| @@ -535,19 +560,26 @@ struct l2_fhdr { | |||
| 535 | #define BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) | 560 | #define BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) |
| 536 | #define BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) | 561 | #define BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) |
| 537 | #define BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) | 562 | #define BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) |
| 563 | #define BNX2_PCI_ID_VAL4_RESERVED0 (0x3L<<4) | ||
| 538 | #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) | 564 | #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) |
| 539 | #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) | 565 | #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) |
| 540 | #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) | 566 | #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) |
| 541 | #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) | 567 | #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) |
| 542 | #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) | 568 | #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) |
| 569 | #define BNX2_PCI_ID_VAL4_MSI_PV_MASK_CAP (1L<<8) | ||
| 543 | #define BNX2_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) | 570 | #define BNX2_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) |
| 544 | #define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) | 571 | #define BNX2_PCI_ID_VAL4_MULTI_MSG_CAP (0x7L<<12) |
| 545 | #define BNX2_PCI_ID_VAL4_MSI_ENABLE (1L<<15) | 572 | #define BNX2_PCI_ID_VAL4_MSI_ENABLE (1L<<15) |
| 546 | #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) | 573 | #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) |
| 547 | #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) | 574 | #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) |
| 548 | #define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21) | 575 | #define BNX2_PCI_ID_VAL4_RESERVED2 (0x7L<<18) |
| 549 | #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) | 576 | #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21 (0x3L<<21) |
| 550 | #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26) | 577 | #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B21 (0x3L<<23) |
| 578 | #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0 (1L<<25) | ||
| 579 | #define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10 (0x3L<<26) | ||
| 580 | #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B0 (1L<<28) | ||
| 581 | #define BNX2_PCI_ID_VAL4_RESERVED3 (0x7L<<29) | ||
| 582 | #define BNX2_PCI_ID_VAL4_RESERVED3_XI (0xffffL<<16) | ||
| 551 | 583 | ||
| 552 | #define BNX2_PCI_ID_VAL5 0x00000444 | 584 | #define BNX2_PCI_ID_VAL5 0x00000444 |
| 553 | #define BNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0) | 585 | #define BNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0) |
| @@ -556,6 +588,10 @@ struct l2_fhdr { | |||
| 556 | #define BNX2_PCI_ID_VAL5_PME_IN_D1 (1L<<3) | 588 | #define BNX2_PCI_ID_VAL5_PME_IN_D1 (1L<<3) |
| 557 | #define BNX2_PCI_ID_VAL5_PME_IN_D2 (1L<<4) | 589 | #define BNX2_PCI_ID_VAL5_PME_IN_D2 (1L<<4) |
| 558 | #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) | 590 | #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) |
| 591 | #define BNX2_PCI_ID_VAL5_RESERVED0_TE (0x3ffffffL<<6) | ||
| 592 | #define BNX2_PCI_ID_VAL5_PM_VERSION_XI (0x7L<<6) | ||
| 593 | #define BNX2_PCI_ID_VAL5_NO_SOFT_RESET_XI (1L<<9) | ||
| 594 | #define BNX2_PCI_ID_VAL5_RESERVED0_XI (0x3fffffL<<10) | ||
| 559 | 595 | ||
| 560 | #define BNX2_PCI_PCIX_EXTENDED_STATUS 0x00000448 | 596 | #define BNX2_PCI_PCIX_EXTENDED_STATUS 0x00000448 |
| 561 | #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) | 597 | #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) |
| @@ -567,12 +603,91 @@ struct l2_fhdr { | |||
| 567 | #define BNX2_PCI_ID_VAL6_MAX_LAT (0xffL<<0) | 603 | #define BNX2_PCI_ID_VAL6_MAX_LAT (0xffL<<0) |
| 568 | #define BNX2_PCI_ID_VAL6_MIN_GNT (0xffL<<8) | 604 | #define BNX2_PCI_ID_VAL6_MIN_GNT (0xffL<<8) |
| 569 | #define BNX2_PCI_ID_VAL6_BIST (0xffL<<16) | 605 | #define BNX2_PCI_ID_VAL6_BIST (0xffL<<16) |
| 606 | #define BNX2_PCI_ID_VAL6_RESERVED0 (0xffL<<24) | ||
| 570 | 607 | ||
| 571 | #define BNX2_PCI_MSI_DATA 0x00000450 | 608 | #define BNX2_PCI_MSI_DATA 0x00000450 |
| 572 | #define BNX2_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) | 609 | #define BNX2_PCI_MSI_DATA_MSI_DATA (0xffffL<<0) |
| 573 | 610 | ||
| 574 | #define BNX2_PCI_MSI_ADDR_H 0x00000454 | 611 | #define BNX2_PCI_MSI_ADDR_H 0x00000454 |
| 575 | #define BNX2_PCI_MSI_ADDR_L 0x00000458 | 612 | #define BNX2_PCI_MSI_ADDR_L 0x00000458 |
| 613 | #define BNX2_PCI_MSI_ADDR_L_VAL (0x3fffffffL<<2) | ||
| 614 | |||
| 615 | #define BNX2_PCI_CFG_ACCESS_CMD 0x0000045c | ||
| 616 | #define BNX2_PCI_CFG_ACCESS_CMD_ADR (0x3fL<<2) | ||
| 617 | #define BNX2_PCI_CFG_ACCESS_CMD_RD_REQ (1L<<27) | ||
| 618 | #define BNX2_PCI_CFG_ACCESS_CMD_WR_REQ (0xfL<<28) | ||
| 619 | |||
| 620 | #define BNX2_PCI_CFG_ACCESS_DATA 0x00000460 | ||
| 621 | #define BNX2_PCI_MSI_MASK 0x00000464 | ||
| 622 | #define BNX2_PCI_MSI_MASK_MSI_MASK (0xffffffffL<<0) | ||
| 623 | |||
| 624 | #define BNX2_PCI_MSI_PEND 0x00000468 | ||
| 625 | #define BNX2_PCI_MSI_PEND_MSI_PEND (0xffffffffL<<0) | ||
| 626 | |||
| 627 | #define BNX2_PCI_PM_DATA_C 0x0000046c | ||
| 628 | #define BNX2_PCI_PM_DATA_C_PM_DATA_8_PRG (0xffL<<0) | ||
| 629 | #define BNX2_PCI_PM_DATA_C_RESERVED0 (0xffffffL<<8) | ||
| 630 | |||
| 631 | #define BNX2_PCI_MSIX_CONTROL 0x000004c0 | ||
| 632 | #define BNX2_PCI_MSIX_CONTROL_MSIX_TBL_SIZ (0x7ffL<<0) | ||
| 633 | #define BNX2_PCI_MSIX_CONTROL_RESERVED0 (0x1fffffL<<11) | ||
| 634 | |||
| 635 | #define BNX2_PCI_MSIX_TBL_OFF_BIR 0x000004c4 | ||
| 636 | #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR (0x7L<<0) | ||
| 637 | #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF (0x1fffffffL<<3) | ||
| 638 | |||
| 639 | #define BNX2_PCI_MSIX_PBA_OFF_BIT 0x000004c8 | ||
| 640 | #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR (0x7L<<0) | ||
| 641 | #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF (0x1fffffffL<<3) | ||
| 642 | |||
| 643 | #define BNX2_PCI_PCIE_CAPABILITY 0x000004d0 | ||
| 644 | #define BNX2_PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM (0x1fL<<0) | ||
| 645 | #define BNX2_PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1 (1L<<5) | ||
| 646 | |||
| 647 | #define BNX2_PCI_DEVICE_CAPABILITY 0x000004d4 | ||
| 648 | #define BNX2_PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED (0x7L<<0) | ||
| 649 | #define BNX2_PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT (1L<<5) | ||
| 650 | #define BNX2_PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY (0x7L<<6) | ||
| 651 | #define BNX2_PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY (0x7L<<9) | ||
| 652 | #define BNX2_PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT (1L<<15) | ||
| 653 | |||
| 654 | #define BNX2_PCI_LINK_CAPABILITY 0x000004dc | ||
| 655 | #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED (0xfL<<0) | ||
| 656 | #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001 (1L<<0) | ||
| 657 | #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010 (1L<<0) | ||
| 658 | #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_WIDTH (0x1fL<<4) | ||
| 659 | #define BNX2_PCI_LINK_CAPABILITY_CLK_POWER_MGMT (1L<<9) | ||
| 660 | #define BNX2_PCI_LINK_CAPABILITY_ASPM_SUPPORT (0x3L<<10) | ||
| 661 | #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT (0x7L<<12) | ||
| 662 | #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101 (5L<<12) | ||
| 663 | #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110 (6L<<12) | ||
| 664 | #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT (0x7L<<15) | ||
| 665 | #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_001 (1L<<15) | ||
| 666 | #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_010 (2L<<15) | ||
| 667 | #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT (0x7L<<18) | ||
| 668 | #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101 (5L<<18) | ||
| 669 | #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110 (6L<<18) | ||
| 670 | #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT (0x7L<<21) | ||
| 671 | #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001 (1L<<21) | ||
| 672 | #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010 (2L<<21) | ||
| 673 | #define BNX2_PCI_LINK_CAPABILITY_PORT_NUM (0xffL<<24) | ||
| 674 | |||
| 675 | #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2 0x000004e4 | ||
| 676 | #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP (0xfL<<0) | ||
| 677 | #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP (1L<<4) | ||
| 678 | #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED (0x7ffffffL<<5) | ||
| 679 | |||
| 680 | #define BNX2_PCI_PCIE_LINK_CAPABILITY_2 0x000004e8 | ||
| 681 | #define BNX2_PCI_PCIE_LINK_CAPABILITY_2_RESERVED (0xffffffffL<<0) | ||
| 682 | |||
| 683 | #define BNX2_PCI_GRC_WINDOW1_ADDR 0x00000610 | ||
| 684 | #define BNX2_PCI_GRC_WINDOW1_ADDR_VALUE (0x1ffL<<13) | ||
| 685 | |||
| 686 | #define BNX2_PCI_GRC_WINDOW2_ADDR 0x00000614 | ||
| 687 | #define BNX2_PCI_GRC_WINDOW2_ADDR_VALUE (0x1ffL<<13) | ||
| 688 | |||
| 689 | #define BNX2_PCI_GRC_WINDOW3_ADDR 0x00000618 | ||
| 690 | #define BNX2_PCI_GRC_WINDOW3_ADDR_VALUE (0x1ffL<<13) | ||
| 576 | 691 | ||
| 577 | 692 | ||
| 578 | /* | 693 | /* |
| @@ -582,13 +697,23 @@ struct l2_fhdr { | |||
| 582 | #define BNX2_MISC_COMMAND 0x00000800 | 697 | #define BNX2_MISC_COMMAND 0x00000800 |
| 583 | #define BNX2_MISC_COMMAND_ENABLE_ALL (1L<<0) | 698 | #define BNX2_MISC_COMMAND_ENABLE_ALL (1L<<0) |
| 584 | #define BNX2_MISC_COMMAND_DISABLE_ALL (1L<<1) | 699 | #define BNX2_MISC_COMMAND_DISABLE_ALL (1L<<1) |
| 585 | #define BNX2_MISC_COMMAND_CORE_RESET (1L<<4) | 700 | #define BNX2_MISC_COMMAND_SW_RESET (1L<<4) |
| 586 | #define BNX2_MISC_COMMAND_HARD_RESET (1L<<5) | 701 | #define BNX2_MISC_COMMAND_POR_RESET (1L<<5) |
| 702 | #define BNX2_MISC_COMMAND_HD_RESET (1L<<6) | ||
| 703 | #define BNX2_MISC_COMMAND_CMN_SW_RESET (1L<<7) | ||
| 587 | #define BNX2_MISC_COMMAND_PAR_ERROR (1L<<8) | 704 | #define BNX2_MISC_COMMAND_PAR_ERROR (1L<<8) |
| 705 | #define BNX2_MISC_COMMAND_CS16_ERR (1L<<9) | ||
| 706 | #define BNX2_MISC_COMMAND_CS16_ERR_LOC (0xfL<<12) | ||
| 588 | #define BNX2_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) | 707 | #define BNX2_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) |
| 708 | #define BNX2_MISC_COMMAND_POWERDOWN_EVENT (1L<<23) | ||
| 709 | #define BNX2_MISC_COMMAND_SW_SHUTDOWN (1L<<24) | ||
| 710 | #define BNX2_MISC_COMMAND_SHUTDOWN_EN (1L<<25) | ||
| 711 | #define BNX2_MISC_COMMAND_DINTEG_ATTN_EN (1L<<26) | ||
| 712 | #define BNX2_MISC_COMMAND_PCIE_LINK_IN_L23 (1L<<27) | ||
| 713 | #define BNX2_MISC_COMMAND_PCIE_DIS (1L<<28) | ||
| 589 | 714 | ||
| 590 | #define BNX2_MISC_CFG 0x00000804 | 715 | #define BNX2_MISC_CFG 0x00000804 |
| 591 | #define BNX2_MISC_CFG_PCI_GRC_TMOUT (1L<<0) | 716 | #define BNX2_MISC_CFG_GRC_TMOUT (1L<<0) |
| 592 | #define BNX2_MISC_CFG_NVM_WR_EN (0x3L<<1) | 717 | #define BNX2_MISC_CFG_NVM_WR_EN (0x3L<<1) |
| 593 | #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) | 718 | #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) |
| 594 | #define BNX2_MISC_CFG_NVM_WR_EN_PCI (1L<<1) | 719 | #define BNX2_MISC_CFG_NVM_WR_EN_PCI (1L<<1) |
| @@ -596,16 +721,45 @@ struct l2_fhdr { | |||
| 596 | #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) | 721 | #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) |
| 597 | #define BNX2_MISC_CFG_BIST_EN (1L<<3) | 722 | #define BNX2_MISC_CFG_BIST_EN (1L<<3) |
| 598 | #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) | 723 | #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) |
| 599 | #define BNX2_MISC_CFG_BYPASS_BSCAN (1L<<5) | 724 | #define BNX2_MISC_CFG_RESERVED5_TE (1L<<5) |
| 600 | #define BNX2_MISC_CFG_BYPASS_EJTAG (1L<<6) | 725 | #define BNX2_MISC_CFG_RESERVED6_TE (1L<<6) |
| 601 | #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) | 726 | #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) |
| 602 | #define BNX2_MISC_CFG_LEDMODE (0x3L<<8) | 727 | #define BNX2_MISC_CFG_LEDMODE (0x7L<<8) |
| 603 | #define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8) | 728 | #define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8) |
| 604 | #define BNX2_MISC_CFG_LEDMODE_GPHY1 (1L<<8) | 729 | #define BNX2_MISC_CFG_LEDMODE_PHY1_TE (1L<<8) |
| 605 | #define BNX2_MISC_CFG_LEDMODE_GPHY2 (2L<<8) | 730 | #define BNX2_MISC_CFG_LEDMODE_PHY2_TE (2L<<8) |
| 731 | #define BNX2_MISC_CFG_LEDMODE_PHY3_TE (3L<<8) | ||
| 732 | #define BNX2_MISC_CFG_LEDMODE_PHY4_TE (4L<<8) | ||
| 733 | #define BNX2_MISC_CFG_LEDMODE_PHY5_TE (5L<<8) | ||
| 734 | #define BNX2_MISC_CFG_LEDMODE_PHY6_TE (6L<<8) | ||
| 735 | #define BNX2_MISC_CFG_LEDMODE_PHY7_TE (7L<<8) | ||
| 736 | #define BNX2_MISC_CFG_MCP_GRC_TMOUT_TE (1L<<11) | ||
| 737 | #define BNX2_MISC_CFG_DBU_GRC_TMOUT_TE (1L<<12) | ||
| 738 | #define BNX2_MISC_CFG_LEDMODE_XI (0xfL<<8) | ||
| 739 | #define BNX2_MISC_CFG_LEDMODE_MAC_XI (0L<<8) | ||
| 740 | #define BNX2_MISC_CFG_LEDMODE_PHY1_XI (1L<<8) | ||
| 741 | #define BNX2_MISC_CFG_LEDMODE_PHY2_XI (2L<<8) | ||
| 742 | #define BNX2_MISC_CFG_LEDMODE_PHY3_XI (3L<<8) | ||
| 743 | #define BNX2_MISC_CFG_LEDMODE_MAC2_XI (4L<<8) | ||
| 744 | #define BNX2_MISC_CFG_LEDMODE_PHY4_XI (5L<<8) | ||
| 745 | #define BNX2_MISC_CFG_LEDMODE_PHY5_XI (6L<<8) | ||
| 746 | #define BNX2_MISC_CFG_LEDMODE_PHY6_XI (7L<<8) | ||
| 747 | #define BNX2_MISC_CFG_LEDMODE_MAC3_XI (8L<<8) | ||
| 748 | #define BNX2_MISC_CFG_LEDMODE_PHY7_XI (9L<<8) | ||
| 749 | #define BNX2_MISC_CFG_LEDMODE_PHY8_XI (10L<<8) | ||
| 750 | #define BNX2_MISC_CFG_LEDMODE_PHY9_XI (11L<<8) | ||
| 751 | #define BNX2_MISC_CFG_LEDMODE_MAC4_XI (12L<<8) | ||
| 752 | #define BNX2_MISC_CFG_LEDMODE_PHY10_XI (13L<<8) | ||
| 753 | #define BNX2_MISC_CFG_LEDMODE_PHY11_XI (14L<<8) | ||
| 754 | #define BNX2_MISC_CFG_LEDMODE_UNUSED_XI (15L<<8) | ||
| 755 | #define BNX2_MISC_CFG_PORT_SELECT_XI (1L<<13) | ||
| 756 | #define BNX2_MISC_CFG_PARITY_MODE_XI (1L<<14) | ||
| 606 | 757 | ||
| 607 | #define BNX2_MISC_ID 0x00000808 | 758 | #define BNX2_MISC_ID 0x00000808 |
| 608 | #define BNX2_MISC_ID_BOND_ID (0xfL<<0) | 759 | #define BNX2_MISC_ID_BOND_ID (0xfL<<0) |
| 760 | #define BNX2_MISC_ID_BOND_ID_X (0L<<0) | ||
| 761 | #define BNX2_MISC_ID_BOND_ID_C (3L<<0) | ||
| 762 | #define BNX2_MISC_ID_BOND_ID_S (12L<<0) | ||
| 609 | #define BNX2_MISC_ID_CHIP_METAL (0xffL<<4) | 763 | #define BNX2_MISC_ID_CHIP_METAL (0xffL<<4) |
| 610 | #define BNX2_MISC_ID_CHIP_REV (0xfL<<12) | 764 | #define BNX2_MISC_ID_CHIP_REV (0xfL<<12) |
| 611 | #define BNX2_MISC_ID_CHIP_NUM (0xffffL<<16) | 765 | #define BNX2_MISC_ID_CHIP_NUM (0xffffL<<16) |
| @@ -639,6 +793,8 @@ struct l2_fhdr { | |||
| 639 | #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) | 793 | #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) |
| 640 | #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) | 794 | #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) |
| 641 | #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) | 795 | #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) |
| 796 | #define BNX2_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) | ||
| 797 | #define BNX2_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) | ||
| 642 | 798 | ||
| 643 | #define BNX2_MISC_ENABLE_SET_BITS 0x00000810 | 799 | #define BNX2_MISC_ENABLE_SET_BITS 0x00000810 |
| 644 | #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) | 800 | #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) |
| @@ -669,6 +825,8 @@ struct l2_fhdr { | |||
| 669 | #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) | 825 | #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) |
| 670 | #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) | 826 | #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) |
| 671 | #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) | 827 | #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) |
| 828 | #define BNX2_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) | ||
| 829 | #define BNX2_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) | ||
| 672 | 830 | ||
| 673 | #define BNX2_MISC_ENABLE_CLR_BITS 0x00000814 | 831 | #define BNX2_MISC_ENABLE_CLR_BITS 0x00000814 |
| 674 | #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) | 832 | #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) |
| @@ -699,6 +857,8 @@ struct l2_fhdr { | |||
| 699 | #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) | 857 | #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) |
| 700 | #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) | 858 | #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) |
| 701 | #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) | 859 | #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) |
| 860 | #define BNX2_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) | ||
| 861 | #define BNX2_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) | ||
| 702 | 862 | ||
| 703 | #define BNX2_MISC_CLOCK_CONTROL_BITS 0x00000818 | 863 | #define BNX2_MISC_CLOCK_CONTROL_BITS 0x00000818 |
| 704 | #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) | 864 | #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) |
| @@ -718,30 +878,41 @@ struct l2_fhdr { | |||
| 718 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) | 878 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) |
| 719 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) | 879 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) |
| 720 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) | 880 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) |
| 721 | #define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) | 881 | #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI (0x7L<<8) |
| 882 | #define BNX2_MISC_CLOCK_CONTROL_BITS_MIN_POWER (1L<<11) | ||
| 722 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) | 883 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) |
| 723 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) | 884 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) |
| 724 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) | 885 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) |
| 725 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) | 886 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) |
| 726 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) | 887 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) |
| 727 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) | 888 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) |
| 889 | #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI (0xfL<<12) | ||
| 728 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) | 890 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) |
| 729 | #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) | 891 | #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE (1L<<17) |
| 730 | #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) | 892 | #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE (1L<<18) |
| 731 | #define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) | 893 | #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE (1L<<19) |
| 732 | #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) | 894 | #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_TE (0xfffL<<20) |
| 733 | 895 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI (1L<<17) | |
| 734 | #define BNX2_MISC_GPIO 0x0000081c | 896 | #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI (0x3fL<<18) |
| 735 | #define BNX2_MISC_GPIO_VALUE (0xffL<<0) | 897 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI (0x7L<<24) |
| 736 | #define BNX2_MISC_GPIO_SET (0xffL<<8) | 898 | #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI (1L<<27) |
| 737 | #define BNX2_MISC_GPIO_CLR (0xffL<<16) | 899 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI (0xfL<<28) |
| 738 | #define BNX2_MISC_GPIO_FLOAT (0xffL<<24) | 900 | |
| 739 | 901 | #define BNX2_MISC_SPIO 0x0000081c | |
| 740 | #define BNX2_MISC_GPIO_INT 0x00000820 | 902 | #define BNX2_MISC_SPIO_VALUE (0xffL<<0) |
| 741 | #define BNX2_MISC_GPIO_INT_INT_STATE (0xfL<<0) | 903 | #define BNX2_MISC_SPIO_SET (0xffL<<8) |
| 742 | #define BNX2_MISC_GPIO_INT_OLD_VALUE (0xfL<<8) | 904 | #define BNX2_MISC_SPIO_CLR (0xffL<<16) |
| 743 | #define BNX2_MISC_GPIO_INT_OLD_SET (0xfL<<16) | 905 | #define BNX2_MISC_SPIO_FLOAT (0xffL<<24) |
| 744 | #define BNX2_MISC_GPIO_INT_OLD_CLR (0xfL<<24) | 906 | |
| 907 | #define BNX2_MISC_SPIO_INT 0x00000820 | ||
| 908 | #define BNX2_MISC_SPIO_INT_INT_STATE_TE (0xfL<<0) | ||
| 909 | #define BNX2_MISC_SPIO_INT_OLD_VALUE_TE (0xfL<<8) | ||
| 910 | #define BNX2_MISC_SPIO_INT_OLD_SET_TE (0xfL<<16) | ||
| 911 | #define BNX2_MISC_SPIO_INT_OLD_CLR_TE (0xfL<<24) | ||
| 912 | #define BNX2_MISC_SPIO_INT_INT_STATE_XI (0xffL<<0) | ||
| 913 | #define BNX2_MISC_SPIO_INT_OLD_VALUE_XI (0xffL<<8) | ||
| 914 | #define BNX2_MISC_SPIO_INT_OLD_SET_XI (0xffL<<16) | ||
| 915 | #define BNX2_MISC_SPIO_INT_OLD_CLR_XI (0xffL<<24) | ||
| 745 | 916 | ||
| 746 | #define BNX2_MISC_CONFIG_LFSR 0x00000824 | 917 | #define BNX2_MISC_CONFIG_LFSR 0x00000824 |
| 747 | #define BNX2_MISC_CONFIG_LFSR_DIV (0xffffL<<0) | 918 | #define BNX2_MISC_CONFIG_LFSR_DIV (0xffffL<<0) |
| @@ -775,6 +946,8 @@ struct l2_fhdr { | |||
| 775 | #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) | 946 | #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) |
| 776 | #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) | 947 | #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) |
| 777 | #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) | 948 | #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) |
| 949 | #define BNX2_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) | ||
| 950 | #define BNX2_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) | ||
| 778 | 951 | ||
| 779 | #define BNX2_MISC_ARB_REQ0 0x0000082c | 952 | #define BNX2_MISC_ARB_REQ0 0x0000082c |
| 780 | #define BNX2_MISC_ARB_REQ1 0x00000830 | 953 | #define BNX2_MISC_ARB_REQ1 0x00000830 |
| @@ -831,22 +1004,12 @@ struct l2_fhdr { | |||
| 831 | #define BNX2_MISC_ARB_GNT3_30 (0x7L<<24) | 1004 | #define BNX2_MISC_ARB_GNT3_30 (0x7L<<24) |
| 832 | #define BNX2_MISC_ARB_GNT3_31 (0x7L<<28) | 1005 | #define BNX2_MISC_ARB_GNT3_31 (0x7L<<28) |
| 833 | 1006 | ||
| 834 | #define BNX2_MISC_PRBS_CONTROL 0x00000878 | 1007 | #define BNX2_MISC_RESERVED1 0x00000878 |
| 835 | #define BNX2_MISC_PRBS_CONTROL_EN (1L<<0) | 1008 | #define BNX2_MISC_RESERVED1_MISC_RESERVED1_VALUE (0x3fL<<0) |
| 836 | #define BNX2_MISC_PRBS_CONTROL_RSTB (1L<<1) | 1009 | |
| 837 | #define BNX2_MISC_PRBS_CONTROL_INV (1L<<2) | 1010 | #define BNX2_MISC_RESERVED2 0x0000087c |
| 838 | #define BNX2_MISC_PRBS_CONTROL_ERR_CLR (1L<<3) | 1011 | #define BNX2_MISC_RESERVED2_PCIE_DIS (1L<<0) |
| 839 | #define BNX2_MISC_PRBS_CONTROL_ORDER (0x3L<<4) | 1012 | #define BNX2_MISC_RESERVED2_LINK_IN_L23 (1L<<1) |
| 840 | #define BNX2_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4) | ||
| 841 | #define BNX2_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4) | ||
| 842 | #define BNX2_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4) | ||
| 843 | #define BNX2_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4) | ||
| 844 | |||
| 845 | #define BNX2_MISC_PRBS_STATUS 0x0000087c | ||
| 846 | #define BNX2_MISC_PRBS_STATUS_LOCK (1L<<0) | ||
| 847 | #define BNX2_MISC_PRBS_STATUS_STKY (1L<<1) | ||
| 848 | #define BNX2_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2) | ||
| 849 | #define BNX2_MISC_PRBS_STATUS_STATE (0xfL<<16) | ||
| 850 | 1013 | ||
| 851 | #define BNX2_MISC_SM_ASF_CONTROL 0x00000880 | 1014 | #define BNX2_MISC_SM_ASF_CONTROL 0x00000880 |
| 852 | #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) | 1015 | #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) |
| @@ -857,13 +1020,15 @@ struct l2_fhdr { | |||
| 857 | #define BNX2_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) | 1020 | #define BNX2_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) |
| 858 | #define BNX2_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) | 1021 | #define BNX2_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) |
| 859 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) | 1022 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) |
| 860 | #define BNX2_MISC_SM_ASF_CONTROL_RES (0xfL<<8) | 1023 | #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_EN (1L<<8) |
| 1024 | #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_PULSE (1L<<9) | ||
| 1025 | #define BNX2_MISC_SM_ASF_CONTROL_RES (0x3L<<10) | ||
| 861 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) | 1026 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) |
| 862 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) | 1027 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) |
| 863 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) | 1028 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) |
| 864 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) | 1029 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) |
| 865 | #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16) | 1030 | #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x7fL<<16) |
| 866 | #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24) | 1031 | #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x7fL<<23) |
| 867 | #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) | 1032 | #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) |
| 868 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) | 1033 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) |
| 869 | 1034 | ||
| @@ -891,13 +1056,13 @@ struct l2_fhdr { | |||
| 891 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) | 1056 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) |
| 892 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) | 1057 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) |
| 893 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) | 1058 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) |
| 894 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20) | ||
| 895 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) | 1059 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) |
| 896 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) | 1060 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) |
| 897 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) | 1061 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) |
| 898 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) | 1062 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) |
| 1063 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (6L<<20) | ||
| 1064 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20) | ||
| 899 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) | 1065 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) |
| 900 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20) | ||
| 901 | #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) | 1066 | #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) |
| 902 | #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) | 1067 | #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) |
| 903 | #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) | 1068 | #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) |
| @@ -955,6 +1120,38 @@ struct l2_fhdr { | |||
| 955 | #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) | 1120 | #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) |
| 956 | #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) | 1121 | #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) |
| 957 | #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) | 1122 | #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) |
| 1123 | #define BNX2_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI (1L<<0) | ||
| 1124 | #define BNX2_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI (1L<<1) | ||
| 1125 | #define BNX2_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI (1L<<2) | ||
| 1126 | #define BNX2_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI (1L<<3) | ||
| 1127 | #define BNX2_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI (1L<<4) | ||
| 1128 | #define BNX2_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI (1L<<5) | ||
| 1129 | #define BNX2_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI (1L<<6) | ||
| 1130 | #define BNX2_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI (1L<<7) | ||
| 1131 | #define BNX2_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI (1L<<8) | ||
| 1132 | #define BNX2_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI (1L<<9) | ||
| 1133 | #define BNX2_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI (1L<<10) | ||
| 1134 | #define BNX2_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI (1L<<11) | ||
| 1135 | #define BNX2_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI (1L<<12) | ||
| 1136 | #define BNX2_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI (1L<<13) | ||
| 1137 | #define BNX2_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI (1L<<14) | ||
| 1138 | #define BNX2_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI (1L<<15) | ||
| 1139 | #define BNX2_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI (1L<<16) | ||
| 1140 | #define BNX2_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI (1L<<17) | ||
| 1141 | #define BNX2_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI (1L<<18) | ||
| 1142 | #define BNX2_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI (1L<<19) | ||
| 1143 | #define BNX2_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI (1L<<20) | ||
| 1144 | #define BNX2_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI (1L<<21) | ||
| 1145 | #define BNX2_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI (1L<<22) | ||
| 1146 | #define BNX2_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI (1L<<23) | ||
| 1147 | #define BNX2_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI (1L<<24) | ||
| 1148 | #define BNX2_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI (1L<<25) | ||
| 1149 | #define BNX2_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI (1L<<26) | ||
| 1150 | #define BNX2_MISC_PERR_ENA0_TPBUF_PERR_EN_XI (1L<<27) | ||
| 1151 | #define BNX2_MISC_PERR_ENA0_THBUF_PERR_EN_XI (1L<<28) | ||
| 1152 | #define BNX2_MISC_PERR_ENA0_TDMA_PERR_EN_XI (1L<<29) | ||
| 1153 | #define BNX2_MISC_PERR_ENA0_TBDC_PERR_EN_XI (1L<<30) | ||
| 1154 | #define BNX2_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI (1L<<31) | ||
| 958 | 1155 | ||
| 959 | #define BNX2_MISC_PERR_ENA1 0x000008a8 | 1156 | #define BNX2_MISC_PERR_ENA1 0x000008a8 |
| 960 | #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) | 1157 | #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) |
| @@ -989,6 +1186,35 @@ struct l2_fhdr { | |||
| 989 | #define BNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) | 1186 | #define BNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) |
| 990 | #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) | 1187 | #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) |
| 991 | #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) | 1188 | #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) |
| 1189 | #define BNX2_MISC_PERR_ENA1_RBDC_PERR_EN_XI (1L<<0) | ||
| 1190 | #define BNX2_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI (1L<<2) | ||
| 1191 | #define BNX2_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI (1L<<3) | ||
| 1192 | #define BNX2_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI (1L<<4) | ||
| 1193 | #define BNX2_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI (1L<<5) | ||
| 1194 | #define BNX2_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI (1L<<6) | ||
| 1195 | #define BNX2_MISC_PERR_ENA1_TPATQ_PERR_EN_XI (1L<<7) | ||
| 1196 | #define BNX2_MISC_PERR_ENA1_MCPQ_PERR_EN_XI (1L<<8) | ||
| 1197 | #define BNX2_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI (1L<<9) | ||
| 1198 | #define BNX2_MISC_PERR_ENA1_TXPQ_PERR_EN_XI (1L<<10) | ||
| 1199 | #define BNX2_MISC_PERR_ENA1_COMTQ_PERR_EN_XI (1L<<11) | ||
| 1200 | #define BNX2_MISC_PERR_ENA1_COMQ_PERR_EN_XI (1L<<12) | ||
| 1201 | #define BNX2_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI (1L<<13) | ||
| 1202 | #define BNX2_MISC_PERR_ENA1_RXPQ_PERR_EN_XI (1L<<14) | ||
| 1203 | #define BNX2_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI (1L<<15) | ||
| 1204 | #define BNX2_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI (1L<<16) | ||
| 1205 | #define BNX2_MISC_PERR_ENA1_TASQ_PERR_EN_XI (1L<<17) | ||
| 1206 | #define BNX2_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI (1L<<18) | ||
| 1207 | #define BNX2_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI (1L<<19) | ||
| 1208 | #define BNX2_MISC_PERR_ENA1_COMXQ_PERR_EN_XI (1L<<20) | ||
| 1209 | #define BNX2_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI (1L<<21) | ||
| 1210 | #define BNX2_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI (1L<<22) | ||
| 1211 | #define BNX2_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI (1L<<23) | ||
| 1212 | #define BNX2_MISC_PERR_ENA1_CPQ_PERR_EN_XI (1L<<24) | ||
| 1213 | #define BNX2_MISC_PERR_ENA1_CSQ_PERR_EN_XI (1L<<25) | ||
| 1214 | #define BNX2_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI (1L<<26) | ||
| 1215 | #define BNX2_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI (1L<<27) | ||
| 1216 | #define BNX2_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI (1L<<28) | ||
| 1217 | #define BNX2_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI (1L<<29) | ||
| 992 | 1218 | ||
| 993 | #define BNX2_MISC_PERR_ENA2 0x000008ac | 1219 | #define BNX2_MISC_PERR_ENA2 0x000008ac |
| 994 | #define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0) | 1220 | #define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0) |
| @@ -1000,19 +1226,498 @@ struct l2_fhdr { | |||
| 1000 | #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) | 1226 | #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) |
| 1001 | #define BNX2_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) | 1227 | #define BNX2_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) |
| 1002 | #define BNX2_MISC_PERR_ENA2_TASQ_MISC (1L<<8) | 1228 | #define BNX2_MISC_PERR_ENA2_TASQ_MISC (1L<<8) |
| 1229 | #define BNX2_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI (1L<<0) | ||
| 1230 | #define BNX2_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI (1L<<1) | ||
| 1231 | #define BNX2_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI (1L<<2) | ||
| 1232 | #define BNX2_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI (1L<<3) | ||
| 1233 | #define BNX2_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI (1L<<4) | ||
| 1234 | #define BNX2_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI (1L<<5) | ||
| 1235 | #define BNX2_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI (1L<<6) | ||
| 1003 | 1236 | ||
| 1004 | #define BNX2_MISC_DEBUG_VECTOR_SEL 0x000008b0 | 1237 | #define BNX2_MISC_DEBUG_VECTOR_SEL 0x000008b0 |
| 1005 | #define BNX2_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) | 1238 | #define BNX2_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) |
| 1006 | #define BNX2_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) | 1239 | #define BNX2_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) |
| 1240 | #define BNX2_MISC_DEBUG_VECTOR_SEL_1_XI (0xfffL<<15) | ||
| 1007 | 1241 | ||
| 1008 | #define BNX2_MISC_VREG_CONTROL 0x000008b4 | 1242 | #define BNX2_MISC_VREG_CONTROL 0x000008b4 |
| 1009 | #define BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0) | 1243 | #define BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0) |
| 1244 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_XI (0xfL<<0) | ||
| 1245 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI (0L<<0) | ||
| 1246 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI (1L<<0) | ||
| 1247 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI (2L<<0) | ||
| 1248 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI (3L<<0) | ||
| 1249 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI (4L<<0) | ||
| 1250 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI (5L<<0) | ||
| 1251 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI (6L<<0) | ||
| 1252 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI (7L<<0) | ||
| 1253 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI (8L<<0) | ||
| 1254 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI (9L<<0) | ||
| 1255 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI (10L<<0) | ||
| 1256 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI (11L<<0) | ||
| 1257 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI (12L<<0) | ||
| 1258 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI (13L<<0) | ||
| 1259 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI (14L<<0) | ||
| 1260 | #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI (15L<<0) | ||
| 1010 | #define BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4) | 1261 | #define BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4) |
| 1262 | #define BNX2_MISC_VREG_CONTROL_2_5_PLUS14 (0L<<4) | ||
| 1263 | #define BNX2_MISC_VREG_CONTROL_2_5_PLUS12 (1L<<4) | ||
| 1264 | #define BNX2_MISC_VREG_CONTROL_2_5_PLUS10 (2L<<4) | ||
| 1265 | #define BNX2_MISC_VREG_CONTROL_2_5_PLUS8 (3L<<4) | ||
| 1266 | #define BNX2_MISC_VREG_CONTROL_2_5_PLUS6 (4L<<4) | ||
| 1267 | #define BNX2_MISC_VREG_CONTROL_2_5_PLUS4 (5L<<4) | ||
| 1268 | #define BNX2_MISC_VREG_CONTROL_2_5_PLUS2 (6L<<4) | ||
| 1269 | #define BNX2_MISC_VREG_CONTROL_2_5_NOM (7L<<4) | ||
| 1270 | #define BNX2_MISC_VREG_CONTROL_2_5_MINUS2 (8L<<4) | ||
| 1271 | #define BNX2_MISC_VREG_CONTROL_2_5_MINUS4 (9L<<4) | ||
| 1272 | #define BNX2_MISC_VREG_CONTROL_2_5_MINUS6 (10L<<4) | ||
| 1273 | #define BNX2_MISC_VREG_CONTROL_2_5_MINUS8 (11L<<4) | ||
| 1274 | #define BNX2_MISC_VREG_CONTROL_2_5_MINUS10 (12L<<4) | ||
| 1275 | #define BNX2_MISC_VREG_CONTROL_2_5_MINUS12 (13L<<4) | ||
| 1276 | #define BNX2_MISC_VREG_CONTROL_2_5_MINUS14 (14L<<4) | ||
| 1277 | #define BNX2_MISC_VREG_CONTROL_2_5_MINUS16 (15L<<4) | ||
| 1278 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT (0xfL<<8) | ||
| 1279 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14 (0L<<8) | ||
| 1280 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS12 (1L<<8) | ||
| 1281 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS10 (2L<<8) | ||
| 1282 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS8 (3L<<8) | ||
| 1283 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS6 (4L<<8) | ||
| 1284 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS4 (5L<<8) | ||
| 1285 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS2 (6L<<8) | ||
| 1286 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_NOM (7L<<8) | ||
| 1287 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS2 (8L<<8) | ||
| 1288 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS4 (9L<<8) | ||
| 1289 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS6 (10L<<8) | ||
| 1290 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS8 (11L<<8) | ||
| 1291 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS10 (12L<<8) | ||
| 1292 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS12 (13L<<8) | ||
| 1293 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS14 (14L<<8) | ||
| 1294 | #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS16 (15L<<8) | ||
| 1011 | 1295 | ||
| 1012 | #define BNX2_MISC_FINAL_CLK_CTL_VAL 0x000008b8 | 1296 | #define BNX2_MISC_FINAL_CLK_CTL_VAL 0x000008b8 |
| 1013 | #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) | 1297 | #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) |
| 1014 | 1298 | ||
| 1015 | #define BNX2_MISC_UNUSED0 0x000008bc | 1299 | #define BNX2_MISC_GP_HW_CTL0 0x000008bc |
| 1300 | #define BNX2_MISC_GP_HW_CTL0_TX_DRIVE (1L<<0) | ||
| 1301 | #define BNX2_MISC_GP_HW_CTL0_RMII_MODE (1L<<1) | ||
| 1302 | #define BNX2_MISC_GP_HW_CTL0_RMII_CRSDV_SEL (1L<<2) | ||
| 1303 | #define BNX2_MISC_GP_HW_CTL0_RVMII_MODE (1L<<3) | ||
| 1304 | #define BNX2_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE (1L<<4) | ||
| 1305 | #define BNX2_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE (1L<<5) | ||
| 1306 | #define BNX2_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE (1L<<6) | ||
| 1307 | #define BNX2_MISC_GP_HW_CTL0_RESERVED1_XI (0x7L<<4) | ||
| 1308 | #define BNX2_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY (1L<<7) | ||
| 1309 | #define BNX2_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE (1L<<8) | ||
| 1310 | #define BNX2_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE (1L<<9) | ||
| 1311 | #define BNX2_MISC_GP_HW_CTL0_LED_ACT_SEL_TE (1L<<10) | ||
| 1312 | #define BNX2_MISC_GP_HW_CTL0_RESERVED2_XI (0x7L<<8) | ||
| 1313 | #define BNX2_MISC_GP_HW_CTL0_UP1_DEF0 (1L<<11) | ||
| 1314 | #define BNX2_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF (1L<<12) | ||
| 1315 | #define BNX2_MISC_GP_HW_CTL0_FORCE2500_DEF (1L<<13) | ||
| 1316 | #define BNX2_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF (1L<<14) | ||
| 1317 | #define BNX2_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF (1L<<15) | ||
| 1318 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI (0xfL<<16) | ||
| 1319 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA (0L<<16) | ||
| 1320 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA (1L<<16) | ||
| 1321 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA (3L<<16) | ||
| 1322 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA (5L<<16) | ||
| 1323 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA (7L<<16) | ||
| 1324 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN (15L<<16) | ||
| 1325 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS (1L<<20) | ||
| 1326 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS (1L<<21) | ||
| 1327 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT (0x3L<<22) | ||
| 1328 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P (0L<<22) | ||
| 1329 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P (1L<<22) | ||
| 1330 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P (2L<<22) | ||
| 1331 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P (3L<<22) | ||
| 1332 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT (0x3L<<24) | ||
| 1333 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P (0L<<24) | ||
| 1334 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P (1L<<24) | ||
| 1335 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P (2L<<24) | ||
| 1336 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P (3L<<24) | ||
| 1337 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ (0x3L<<26) | ||
| 1338 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA (0L<<26) | ||
| 1339 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA (1L<<26) | ||
| 1340 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA (2L<<26) | ||
| 1341 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA (3L<<26) | ||
| 1342 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ (0x3L<<28) | ||
| 1343 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA (0L<<28) | ||
| 1344 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA (1L<<28) | ||
| 1345 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA (2L<<28) | ||
| 1346 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA (3L<<28) | ||
| 1347 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ (0x3L<<30) | ||
| 1348 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57 (0L<<30) | ||
| 1349 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45 (1L<<30) | ||
| 1350 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62 (2L<<30) | ||
| 1351 | #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66 (3L<<30) | ||
| 1352 | |||
| 1353 | #define BNX2_MISC_GP_HW_CTL1 0x000008c0 | ||
| 1354 | #define BNX2_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE (1L<<0) | ||
| 1355 | #define BNX2_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE (1L<<1) | ||
| 1356 | #define BNX2_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE (1L<<2) | ||
| 1357 | #define BNX2_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE (1L<<3) | ||
| 1358 | #define BNX2_MISC_GP_HW_CTL1_RESERVED_SOFT_XI (0xffffL<<0) | ||
| 1359 | #define BNX2_MISC_GP_HW_CTL1_RESERVED_HARD_XI (0xffffL<<16) | ||
| 1360 | |||
| 1361 | #define BNX2_MISC_NEW_HW_CTL 0x000008c4 | ||
| 1362 | #define BNX2_MISC_NEW_HW_CTL_MAIN_POR_BYPASS (1L<<0) | ||
| 1363 | #define BNX2_MISC_NEW_HW_CTL_RINGOSC_ENABLE (1L<<1) | ||
| 1364 | #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL0 (1L<<2) | ||
| 1365 | #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL1 (1L<<3) | ||
| 1366 | #define BNX2_MISC_NEW_HW_CTL_RESERVED_SHARED (0xfffL<<4) | ||
| 1367 | #define BNX2_MISC_NEW_HW_CTL_RESERVED_SPLIT (0xffffL<<16) | ||
| 1368 | |||
| 1369 | #define BNX2_MISC_NEW_CORE_CTL 0x000008c8 | ||
| 1370 | #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0) | ||
| 1371 | #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1) | ||
| 1372 | #define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2) | ||
| 1373 | #define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16) | ||
| 1374 | |||
| 1375 | #define BNX2_MISC_ECO_HW_CTL 0x000008cc | ||
| 1376 | #define BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN (1L<<0) | ||
| 1377 | #define BNX2_MISC_ECO_HW_CTL_RESERVED_SOFT (0x7fffL<<1) | ||
| 1378 | #define BNX2_MISC_ECO_HW_CTL_RESERVED_HARD (0xffffL<<16) | ||
| 1379 | |||
| 1380 | #define BNX2_MISC_ECO_CORE_CTL 0x000008d0 | ||
| 1381 | #define BNX2_MISC_ECO_CORE_CTL_RESERVED_SOFT (0xffffL<<0) | ||
| 1382 | #define BNX2_MISC_ECO_CORE_CTL_RESERVED_HARD (0xffffL<<16) | ||
| 1383 | |||
| 1384 | #define BNX2_MISC_PPIO 0x000008d4 | ||
| 1385 | #define BNX2_MISC_PPIO_VALUE (0xfL<<0) | ||
| 1386 | #define BNX2_MISC_PPIO_SET (0xfL<<8) | ||
| 1387 | #define BNX2_MISC_PPIO_CLR (0xfL<<16) | ||
| 1388 | #define BNX2_MISC_PPIO_FLOAT (0xfL<<24) | ||
| 1389 | |||
| 1390 | #define BNX2_MISC_PPIO_INT 0x000008d8 | ||
| 1391 | #define BNX2_MISC_PPIO_INT_INT_STATE (0xfL<<0) | ||
| 1392 | #define BNX2_MISC_PPIO_INT_OLD_VALUE (0xfL<<8) | ||
| 1393 | #define BNX2_MISC_PPIO_INT_OLD_SET (0xfL<<16) | ||
| 1394 | #define BNX2_MISC_PPIO_INT_OLD_CLR (0xfL<<24) | ||
| 1395 | |||
| 1396 | #define BNX2_MISC_RESET_NUMS 0x000008dc | ||
| 1397 | #define BNX2_MISC_RESET_NUMS_NUM_HARD_RESETS (0x7L<<0) | ||
| 1398 | #define BNX2_MISC_RESET_NUMS_NUM_PCIE_RESETS (0x7L<<4) | ||
| 1399 | #define BNX2_MISC_RESET_NUMS_NUM_PERSTB_RESETS (0x7L<<8) | ||
| 1400 | #define BNX2_MISC_RESET_NUMS_NUM_CMN_RESETS (0x7L<<12) | ||
| 1401 | #define BNX2_MISC_RESET_NUMS_NUM_PORT_RESETS (0x7L<<16) | ||
| 1402 | |||
| 1403 | #define BNX2_MISC_CS16_ERR 0x000008e0 | ||
| 1404 | #define BNX2_MISC_CS16_ERR_ENA_PCI (1L<<0) | ||
| 1405 | #define BNX2_MISC_CS16_ERR_ENA_RDMA (1L<<1) | ||
| 1406 | #define BNX2_MISC_CS16_ERR_ENA_TDMA (1L<<2) | ||
| 1407 | #define BNX2_MISC_CS16_ERR_ENA_EMAC (1L<<3) | ||
| 1408 | #define BNX2_MISC_CS16_ERR_ENA_CTX (1L<<4) | ||
| 1409 | #define BNX2_MISC_CS16_ERR_ENA_TBDR (1L<<5) | ||
| 1410 | #define BNX2_MISC_CS16_ERR_ENA_RBDC (1L<<6) | ||
| 1411 | #define BNX2_MISC_CS16_ERR_ENA_COM (1L<<7) | ||
| 1412 | #define BNX2_MISC_CS16_ERR_ENA_CP (1L<<8) | ||
| 1413 | #define BNX2_MISC_CS16_ERR_STA_PCI (1L<<16) | ||
| 1414 | #define BNX2_MISC_CS16_ERR_STA_RDMA (1L<<17) | ||
| 1415 | #define BNX2_MISC_CS16_ERR_STA_TDMA (1L<<18) | ||
| 1416 | #define BNX2_MISC_CS16_ERR_STA_EMAC (1L<<19) | ||
| 1417 | #define BNX2_MISC_CS16_ERR_STA_CTX (1L<<20) | ||
| 1418 | #define BNX2_MISC_CS16_ERR_STA_TBDR (1L<<21) | ||
| 1419 | #define BNX2_MISC_CS16_ERR_STA_RBDC (1L<<22) | ||
| 1420 | #define BNX2_MISC_CS16_ERR_STA_COM (1L<<23) | ||
| 1421 | #define BNX2_MISC_CS16_ERR_STA_CP (1L<<24) | ||
| 1422 | |||
| 1423 | #define BNX2_MISC_SPIO_EVENT 0x000008e4 | ||
| 1424 | #define BNX2_MISC_SPIO_EVENT_ENABLE (0xffL<<0) | ||
| 1425 | |||
| 1426 | #define BNX2_MISC_PPIO_EVENT 0x000008e8 | ||
| 1427 | #define BNX2_MISC_PPIO_EVENT_ENABLE (0xfL<<0) | ||
| 1428 | |||
| 1429 | #define BNX2_MISC_DUAL_MEDIA_CTRL 0x000008ec | ||
| 1430 | #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID (0xffL<<0) | ||
| 1431 | #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0L<<0) | ||
| 1432 | #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C (3L<<0) | ||
| 1433 | #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S (12L<<0) | ||
| 1434 | #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP (0x7L<<8) | ||
| 1435 | #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN (1L<<11) | ||
| 1436 | #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET (1L<<12) | ||
| 1437 | #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET (1L<<13) | ||
| 1438 | #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET (1L<<14) | ||
| 1439 | #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET (1L<<15) | ||
| 1440 | #define BNX2_MISC_DUAL_MEDIA_CTRL_LCPLL_RST (1L<<16) | ||
| 1441 | #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_RST (1L<<17) | ||
| 1442 | #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_RST (1L<<18) | ||
| 1443 | #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_RST (1L<<19) | ||
| 1444 | #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_RST (1L<<20) | ||
| 1445 | #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL (0x7L<<21) | ||
| 1446 | #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP (1L<<24) | ||
| 1447 | #define BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE (1L<<25) | ||
| 1448 | #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ (0xfL<<26) | ||
| 1449 | #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ (1L<<26) | ||
| 1450 | #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ (2L<<26) | ||
| 1451 | #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ (4L<<26) | ||
| 1452 | #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ (8L<<26) | ||
| 1453 | |||
| 1454 | #define BNX2_MISC_OTP_CMD1 0x000008f0 | ||
| 1455 | #define BNX2_MISC_OTP_CMD1_FMODE (0x7L<<0) | ||
| 1456 | #define BNX2_MISC_OTP_CMD1_FMODE_IDLE (0L<<0) | ||
| 1457 | #define BNX2_MISC_OTP_CMD1_FMODE_WRITE (1L<<0) | ||
| 1458 | #define BNX2_MISC_OTP_CMD1_FMODE_INIT (2L<<0) | ||
| 1459 | #define BNX2_MISC_OTP_CMD1_FMODE_SET (3L<<0) | ||
| 1460 | #define BNX2_MISC_OTP_CMD1_FMODE_RST (4L<<0) | ||
| 1461 | #define BNX2_MISC_OTP_CMD1_FMODE_VERIFY (5L<<0) | ||
| 1462 | #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED0 (6L<<0) | ||
| 1463 | #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED1 (7L<<0) | ||
| 1464 | #define BNX2_MISC_OTP_CMD1_USEPINS (1L<<8) | ||
| 1465 | #define BNX2_MISC_OTP_CMD1_PROGSEL (1L<<9) | ||
| 1466 | #define BNX2_MISC_OTP_CMD1_PROGSTART (1L<<10) | ||
| 1467 | #define BNX2_MISC_OTP_CMD1_PCOUNT (0x7L<<16) | ||
| 1468 | #define BNX2_MISC_OTP_CMD1_PBYP (1L<<19) | ||
| 1469 | #define BNX2_MISC_OTP_CMD1_VSEL (0xfL<<20) | ||
| 1470 | #define BNX2_MISC_OTP_CMD1_TM (0x7L<<27) | ||
| 1471 | #define BNX2_MISC_OTP_CMD1_SADBYP (1L<<30) | ||
| 1472 | #define BNX2_MISC_OTP_CMD1_DEBUG (1L<<31) | ||
| 1473 | |||
| 1474 | #define BNX2_MISC_OTP_CMD2 0x000008f4 | ||
| 1475 | #define BNX2_MISC_OTP_CMD2_OTP_ROM_ADDR (0x3ffL<<0) | ||
| 1476 | #define BNX2_MISC_OTP_CMD2_DOSEL (0x7fL<<16) | ||
| 1477 | #define BNX2_MISC_OTP_CMD2_DOSEL_0 (0L<<16) | ||
| 1478 | #define BNX2_MISC_OTP_CMD2_DOSEL_1 (1L<<16) | ||
| 1479 | #define BNX2_MISC_OTP_CMD2_DOSEL_127 (127L<<16) | ||
| 1480 | |||
| 1481 | #define BNX2_MISC_OTP_STATUS 0x000008f8 | ||
| 1482 | #define BNX2_MISC_OTP_STATUS_DATA (0xffL<<0) | ||
| 1483 | #define BNX2_MISC_OTP_STATUS_VALID (1L<<8) | ||
| 1484 | #define BNX2_MISC_OTP_STATUS_BUSY (1L<<9) | ||
| 1485 | #define BNX2_MISC_OTP_STATUS_BUSYSM (1L<<10) | ||
| 1486 | #define BNX2_MISC_OTP_STATUS_DONE (1L<<11) | ||
| 1487 | |||
| 1488 | #define BNX2_MISC_OTP_SHIFT1_CMD 0x000008fc | ||
| 1489 | #define BNX2_MISC_OTP_SHIFT1_CMD_RESET_MODE_N (1L<<0) | ||
| 1490 | #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_DONE (1L<<1) | ||
| 1491 | #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_START (1L<<2) | ||
| 1492 | #define BNX2_MISC_OTP_SHIFT1_CMD_LOAD_DATA (1L<<3) | ||
| 1493 | #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT (0x1fL<<8) | ||
| 1494 | |||
| 1495 | #define BNX2_MISC_OTP_SHIFT1_DATA 0x00000900 | ||
| 1496 | #define BNX2_MISC_OTP_SHIFT2_CMD 0x00000904 | ||
| 1497 | #define BNX2_MISC_OTP_SHIFT2_CMD_RESET_MODE_N (1L<<0) | ||
| 1498 | #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_DONE (1L<<1) | ||
| 1499 | #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_START (1L<<2) | ||
| 1500 | #define BNX2_MISC_OTP_SHIFT2_CMD_LOAD_DATA (1L<<3) | ||
| 1501 | #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT (0x1fL<<8) | ||
| 1502 | |||
| 1503 | #define BNX2_MISC_OTP_SHIFT2_DATA 0x00000908 | ||
| 1504 | #define BNX2_MISC_BIST_CS0 0x0000090c | ||
| 1505 | #define BNX2_MISC_BIST_CS0_MBIST_EN (1L<<0) | ||
| 1506 | #define BNX2_MISC_BIST_CS0_BIST_SETUP (0x3L<<1) | ||
| 1507 | #define BNX2_MISC_BIST_CS0_MBIST_ASYNC_RESET (1L<<3) | ||
| 1508 | #define BNX2_MISC_BIST_CS0_MBIST_DONE (1L<<8) | ||
| 1509 | #define BNX2_MISC_BIST_CS0_MBIST_GO (1L<<9) | ||
| 1510 | #define BNX2_MISC_BIST_CS0_BIST_OVERRIDE (1L<<31) | ||
| 1511 | |||
| 1512 | #define BNX2_MISC_BIST_MEMSTATUS0 0x00000910 | ||
| 1513 | #define BNX2_MISC_BIST_CS1 0x00000914 | ||
| 1514 | #define BNX2_MISC_BIST_CS1_MBIST_EN (1L<<0) | ||
| 1515 | #define BNX2_MISC_BIST_CS1_BIST_SETUP (0x3L<<1) | ||
| 1516 | #define BNX2_MISC_BIST_CS1_MBIST_ASYNC_RESET (1L<<3) | ||
| 1517 | #define BNX2_MISC_BIST_CS1_MBIST_DONE (1L<<8) | ||
| 1518 | #define BNX2_MISC_BIST_CS1_MBIST_GO (1L<<9) | ||
| 1519 | |||
| 1520 | #define BNX2_MISC_BIST_MEMSTATUS1 0x00000918 | ||
| 1521 | #define BNX2_MISC_BIST_CS2 0x0000091c | ||
| 1522 | #define BNX2_MISC_BIST_CS2_MBIST_EN (1L<<0) | ||
| 1523 | #define BNX2_MISC_BIST_CS2_BIST_SETUP (0x3L<<1) | ||
| 1524 | #define BNX2_MISC_BIST_CS2_MBIST_ASYNC_RESET (1L<<3) | ||
| 1525 | #define BNX2_MISC_BIST_CS2_MBIST_DONE (1L<<8) | ||
| 1526 | #define BNX2_MISC_BIST_CS2_MBIST_GO (1L<<9) | ||
| 1527 | |||
| 1528 | #define BNX2_MISC_BIST_MEMSTATUS2 0x00000920 | ||
| 1529 | #define BNX2_MISC_BIST_CS3 0x00000924 | ||
| 1530 | #define BNX2_MISC_BIST_CS3_MBIST_EN (1L<<0) | ||
| 1531 | #define BNX2_MISC_BIST_CS3_BIST_SETUP (0x3L<<1) | ||
| 1532 | #define BNX2_MISC_BIST_CS3_MBIST_ASYNC_RESET (1L<<3) | ||
| 1533 | #define BNX2_MISC_BIST_CS3_MBIST_DONE (1L<<8) | ||
| 1534 | #define BNX2_MISC_BIST_CS3_MBIST_GO (1L<<9) | ||
| 1535 | |||
| 1536 | #define BNX2_MISC_BIST_MEMSTATUS3 0x00000928 | ||
| 1537 | #define BNX2_MISC_BIST_CS4 0x0000092c | ||
| 1538 | #define BNX2_MISC_BIST_CS4_MBIST_EN (1L<<0) | ||
| 1539 | #define BNX2_MISC_BIST_CS4_BIST_SETUP (0x3L<<1) | ||
| 1540 | #define BNX2_MISC_BIST_CS4_MBIST_ASYNC_RESET (1L<<3) | ||
| 1541 | #define BNX2_MISC_BIST_CS4_MBIST_DONE (1L<<8) | ||
| 1542 | #define BNX2_MISC_BIST_CS4_MBIST_GO (1L<<9) | ||
| 1543 | |||
| 1544 | #define BNX2_MISC_BIST_MEMSTATUS4 0x00000930 | ||
| 1545 | #define BNX2_MISC_BIST_CS5 0x00000934 | ||
| 1546 | #define BNX2_MISC_BIST_CS5_MBIST_EN (1L<<0) | ||
| 1547 | #define BNX2_MISC_BIST_CS5_BIST_SETUP (0x3L<<1) | ||
| 1548 | #define BNX2_MISC_BIST_CS5_MBIST_ASYNC_RESET (1L<<3) | ||
| 1549 | #define BNX2_MISC_BIST_CS5_MBIST_DONE (1L<<8) | ||
| 1550 | #define BNX2_MISC_BIST_CS5_MBIST_GO (1L<<9) | ||
| 1551 | |||
| 1552 | #define BNX2_MISC_BIST_MEMSTATUS5 0x00000938 | ||
| 1553 | #define BNX2_MISC_MEM_TM0 0x0000093c | ||
| 1554 | #define BNX2_MISC_MEM_TM0_PCIE_REPLAY_TM (0xfL<<0) | ||
| 1555 | #define BNX2_MISC_MEM_TM0_MCP_SCPAD (0xfL<<8) | ||
| 1556 | #define BNX2_MISC_MEM_TM0_UMP_TM (0xffL<<16) | ||
| 1557 | #define BNX2_MISC_MEM_TM0_HB_MEM_TM (0xfL<<24) | ||
| 1558 | |||
| 1559 | #define BNX2_MISC_USPLL_CTRL 0x00000940 | ||
| 1560 | #define BNX2_MISC_USPLL_CTRL_PH_DET_DIS (1L<<0) | ||
| 1561 | #define BNX2_MISC_USPLL_CTRL_FREQ_DET_DIS (1L<<1) | ||
| 1562 | #define BNX2_MISC_USPLL_CTRL_LCPX (0x3fL<<2) | ||
| 1563 | #define BNX2_MISC_USPLL_CTRL_RX (0x3L<<8) | ||
| 1564 | #define BNX2_MISC_USPLL_CTRL_VC_EN (1L<<10) | ||
| 1565 | #define BNX2_MISC_USPLL_CTRL_VCO_MG (0x3L<<11) | ||
| 1566 | #define BNX2_MISC_USPLL_CTRL_KVCO_XF (0x7L<<13) | ||
| 1567 | #define BNX2_MISC_USPLL_CTRL_KVCO_XS (0x7L<<16) | ||
| 1568 | #define BNX2_MISC_USPLL_CTRL_TESTD_EN (1L<<19) | ||
| 1569 | #define BNX2_MISC_USPLL_CTRL_TESTD_SEL (0x7L<<20) | ||
| 1570 | #define BNX2_MISC_USPLL_CTRL_TESTA_EN (1L<<23) | ||
| 1571 | #define BNX2_MISC_USPLL_CTRL_TESTA_SEL (0x3L<<24) | ||
| 1572 | #define BNX2_MISC_USPLL_CTRL_ATTEN_FREF (1L<<26) | ||
| 1573 | #define BNX2_MISC_USPLL_CTRL_DIGITAL_RST (1L<<27) | ||
| 1574 | #define BNX2_MISC_USPLL_CTRL_ANALOG_RST (1L<<28) | ||
| 1575 | #define BNX2_MISC_USPLL_CTRL_LOCK (1L<<29) | ||
| 1576 | |||
| 1577 | #define BNX2_MISC_PERR_STATUS0 0x00000944 | ||
| 1578 | #define BNX2_MISC_PERR_STATUS0_COM_DMAE_PERR (1L<<0) | ||
| 1579 | #define BNX2_MISC_PERR_STATUS0_CP_DMAE_PERR (1L<<1) | ||
| 1580 | #define BNX2_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR (1L<<2) | ||
| 1581 | #define BNX2_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR (1L<<3) | ||
| 1582 | #define BNX2_MISC_PERR_STATUS0_CTX_PGTBL_PERR (1L<<4) | ||
| 1583 | #define BNX2_MISC_PERR_STATUS0_CTX_CACHE_PERR (1L<<5) | ||
| 1584 | #define BNX2_MISC_PERR_STATUS0_CTX_MIRROR_PERR (1L<<6) | ||
| 1585 | #define BNX2_MISC_PERR_STATUS0_COM_CTXC_PERR (1L<<7) | ||
| 1586 | #define BNX2_MISC_PERR_STATUS0_COM_SCPAD_PERR (1L<<8) | ||
| 1587 | #define BNX2_MISC_PERR_STATUS0_CP_CTXC_PERR (1L<<9) | ||
| 1588 | #define BNX2_MISC_PERR_STATUS0_CP_SCPAD_PERR (1L<<10) | ||
| 1589 | #define BNX2_MISC_PERR_STATUS0_RXP_RBUFC_PERR (1L<<11) | ||
| 1590 | #define BNX2_MISC_PERR_STATUS0_RXP_CTXC_PERR (1L<<12) | ||
| 1591 | #define BNX2_MISC_PERR_STATUS0_RXP_SCPAD_PERR (1L<<13) | ||
| 1592 | #define BNX2_MISC_PERR_STATUS0_TPAT_SCPAD_PERR (1L<<14) | ||
| 1593 | #define BNX2_MISC_PERR_STATUS0_TXP_CTXC_PERR (1L<<15) | ||
| 1594 | #define BNX2_MISC_PERR_STATUS0_TXP_SCPAD_PERR (1L<<16) | ||
| 1595 | #define BNX2_MISC_PERR_STATUS0_CS_TMEM_PERR (1L<<17) | ||
| 1596 | #define BNX2_MISC_PERR_STATUS0_MQ_CTX_PERR (1L<<18) | ||
| 1597 | #define BNX2_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR (1L<<19) | ||
| 1598 | #define BNX2_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR (1L<<20) | ||
| 1599 | #define BNX2_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR (1L<<21) | ||
| 1600 | #define BNX2_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR (1L<<22) | ||
| 1601 | #define BNX2_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR (1L<<23) | ||
| 1602 | #define BNX2_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR (1L<<24) | ||
| 1603 | #define BNX2_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR (1L<<25) | ||
| 1604 | #define BNX2_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR (1L<<26) | ||
| 1605 | #define BNX2_MISC_PERR_STATUS0_TPBUF_PERR (1L<<27) | ||
| 1606 | #define BNX2_MISC_PERR_STATUS0_THBUF_PERR (1L<<28) | ||
| 1607 | #define BNX2_MISC_PERR_STATUS0_TDMA_PERR (1L<<29) | ||
| 1608 | #define BNX2_MISC_PERR_STATUS0_TBDC_PERR (1L<<30) | ||
| 1609 | #define BNX2_MISC_PERR_STATUS0_TSCH_LR_PERR (1L<<31) | ||
| 1610 | |||
| 1611 | #define BNX2_MISC_PERR_STATUS1 0x00000948 | ||
| 1612 | #define BNX2_MISC_PERR_STATUS1_RBDC_PERR (1L<<0) | ||
| 1613 | #define BNX2_MISC_PERR_STATUS1_RDMA_DFIFO_PERR (1L<<2) | ||
| 1614 | #define BNX2_MISC_PERR_STATUS1_HC_STATS_PERR (1L<<3) | ||
| 1615 | #define BNX2_MISC_PERR_STATUS1_HC_MSIX_PERR (1L<<4) | ||
| 1616 | #define BNX2_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR (1L<<5) | ||
| 1617 | #define BNX2_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR (1L<<6) | ||
| 1618 | #define BNX2_MISC_PERR_STATUS1_TPATQ_PERR (1L<<7) | ||
| 1619 | #define BNX2_MISC_PERR_STATUS1_MCPQ_PERR (1L<<8) | ||
| 1620 | #define BNX2_MISC_PERR_STATUS1_TDMAQ_PERR (1L<<9) | ||
| 1621 | #define BNX2_MISC_PERR_STATUS1_TXPQ_PERR (1L<<10) | ||
| 1622 | #define BNX2_MISC_PERR_STATUS1_COMTQ_PERR (1L<<11) | ||
| 1623 | #define BNX2_MISC_PERR_STATUS1_COMQ_PERR (1L<<12) | ||
| 1624 | #define BNX2_MISC_PERR_STATUS1_RLUPQ_PERR (1L<<13) | ||
| 1625 | #define BNX2_MISC_PERR_STATUS1_RXPQ_PERR (1L<<14) | ||
| 1626 | #define BNX2_MISC_PERR_STATUS1_RV2PPQ_PERR (1L<<15) | ||
| 1627 | #define BNX2_MISC_PERR_STATUS1_RDMAQ_PERR (1L<<16) | ||
| 1628 | #define BNX2_MISC_PERR_STATUS1_TASQ_PERR (1L<<17) | ||
| 1629 | #define BNX2_MISC_PERR_STATUS1_TBDRQ_PERR (1L<<18) | ||
| 1630 | #define BNX2_MISC_PERR_STATUS1_TSCHQ_PERR (1L<<19) | ||
| 1631 | #define BNX2_MISC_PERR_STATUS1_COMXQ_PERR (1L<<20) | ||
| 1632 | #define BNX2_MISC_PERR_STATUS1_RXPCQ_PERR (1L<<21) | ||
| 1633 | #define BNX2_MISC_PERR_STATUS1_RV2PTQ_PERR (1L<<22) | ||
| 1634 | #define BNX2_MISC_PERR_STATUS1_RV2PMQ_PERR (1L<<23) | ||
| 1635 | #define BNX2_MISC_PERR_STATUS1_CPQ_PERR (1L<<24) | ||
| 1636 | #define BNX2_MISC_PERR_STATUS1_CSQ_PERR (1L<<25) | ||
| 1637 | #define BNX2_MISC_PERR_STATUS1_RLUP_CID_PERR (1L<<26) | ||
| 1638 | #define BNX2_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR (1L<<27) | ||
| 1639 | #define BNX2_MISC_PERR_STATUS1_RV2PCSQ_PERR (1L<<28) | ||
| 1640 | #define BNX2_MISC_PERR_STATUS1_MQ_IDX_PERR (1L<<29) | ||
| 1641 | |||
| 1642 | #define BNX2_MISC_PERR_STATUS2 0x0000094c | ||
| 1643 | #define BNX2_MISC_PERR_STATUS2_TGT_FIFO_PERR (1L<<0) | ||
| 1644 | #define BNX2_MISC_PERR_STATUS2_UMP_TX_PERR (1L<<1) | ||
| 1645 | #define BNX2_MISC_PERR_STATUS2_UMP_RX_PERR (1L<<2) | ||
| 1646 | #define BNX2_MISC_PERR_STATUS2_MCP_ROM_PERR (1L<<3) | ||
| 1647 | #define BNX2_MISC_PERR_STATUS2_MCP_SCPAD_PERR (1L<<4) | ||
| 1648 | #define BNX2_MISC_PERR_STATUS2_HB_MEM_PERR (1L<<5) | ||
| 1649 | #define BNX2_MISC_PERR_STATUS2_PCIE_REPLAY_PERR (1L<<6) | ||
| 1650 | |||
| 1651 | #define BNX2_MISC_LCPLL_CTRL0 0x00000950 | ||
| 1652 | #define BNX2_MISC_LCPLL_CTRL0_OAC (0x7L<<0) | ||
| 1653 | #define BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY (0L<<0) | ||
| 1654 | #define BNX2_MISC_LCPLL_CTRL0_OAC_ZERO (1L<<0) | ||
| 1655 | #define BNX2_MISC_LCPLL_CTRL0_OAC_TWENTY (3L<<0) | ||
| 1656 | #define BNX2_MISC_LCPLL_CTRL0_OAC_FORTY (7L<<0) | ||
| 1657 | #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL (0x7L<<3) | ||
| 1658 | #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360 (0L<<3) | ||
| 1659 | #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_480 (1L<<3) | ||
| 1660 | #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_600 (3L<<3) | ||
| 1661 | #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_720 (7L<<3) | ||
| 1662 | #define BNX2_MISC_LCPLL_CTRL0_BIAS_CTRL (0x3L<<6) | ||
| 1663 | #define BNX2_MISC_LCPLL_CTRL0_PLL_OBSERVE (0x7L<<8) | ||
| 1664 | #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL (0x3L<<11) | ||
| 1665 | #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0 (0L<<11) | ||
| 1666 | #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_1 (1L<<11) | ||
| 1667 | #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_2 (2L<<11) | ||
| 1668 | #define BNX2_MISC_LCPLL_CTRL0_PLLSEQSTART (1L<<13) | ||
| 1669 | #define BNX2_MISC_LCPLL_CTRL0_RESERVED (1L<<14) | ||
| 1670 | #define BNX2_MISC_LCPLL_CTRL0_CAPRETRY_EN (1L<<15) | ||
| 1671 | #define BNX2_MISC_LCPLL_CTRL0_FREQMONITOR_EN (1L<<16) | ||
| 1672 | #define BNX2_MISC_LCPLL_CTRL0_FREQDETRESTART_EN (1L<<17) | ||
| 1673 | #define BNX2_MISC_LCPLL_CTRL0_FREQDETRETRY_EN (1L<<18) | ||
| 1674 | #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN (1L<<19) | ||
| 1675 | #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE (1L<<20) | ||
| 1676 | #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFPASS (1L<<21) | ||
| 1677 | #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN (1L<<22) | ||
| 1678 | #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE (1L<<23) | ||
| 1679 | #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN (1L<<24) | ||
| 1680 | #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS (1L<<25) | ||
| 1681 | #define BNX2_MISC_LCPLL_CTRL0_CAPRESTART (1L<<26) | ||
| 1682 | #define BNX2_MISC_LCPLL_CTRL0_CAPSELECTM_EN (1L<<27) | ||
| 1683 | |||
| 1684 | #define BNX2_MISC_LCPLL_CTRL1 0x00000954 | ||
| 1685 | #define BNX2_MISC_LCPLL_CTRL1_CAPSELECTM (0x1fL<<0) | ||
| 1686 | #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN (1L<<5) | ||
| 1687 | #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN (1L<<6) | ||
| 1688 | #define BNX2_MISC_LCPLL_CTRL1_SLOWDN_XOR (1L<<7) | ||
| 1689 | |||
| 1690 | #define BNX2_MISC_LCPLL_STATUS 0x00000958 | ||
| 1691 | #define BNX2_MISC_LCPLL_STATUS_FREQDONE_SM (1L<<0) | ||
| 1692 | #define BNX2_MISC_LCPLL_STATUS_FREQPASS_SM (1L<<1) | ||
| 1693 | #define BNX2_MISC_LCPLL_STATUS_PLLSEQDONE (1L<<2) | ||
| 1694 | #define BNX2_MISC_LCPLL_STATUS_PLLSEQPASS (1L<<3) | ||
| 1695 | #define BNX2_MISC_LCPLL_STATUS_PLLSTATE (0x7L<<4) | ||
| 1696 | #define BNX2_MISC_LCPLL_STATUS_CAPSTATE (0x7L<<7) | ||
| 1697 | #define BNX2_MISC_LCPLL_STATUS_CAPSELECT (0x1fL<<10) | ||
| 1698 | #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR (1L<<15) | ||
| 1699 | #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0 (0L<<15) | ||
| 1700 | #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1 (1L<<15) | ||
| 1701 | |||
| 1702 | #define BNX2_MISC_OSCFUNDS_CTRL 0x0000095c | ||
| 1703 | #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON (1L<<5) | ||
| 1704 | #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF (0L<<5) | ||
| 1705 | #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_ON (1L<<5) | ||
| 1706 | #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM (0x3L<<6) | ||
| 1707 | #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0 (0L<<6) | ||
| 1708 | #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1 (1L<<6) | ||
| 1709 | #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2 (2L<<6) | ||
| 1710 | #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3 (3L<<6) | ||
| 1711 | #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ (0x3L<<8) | ||
| 1712 | #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0 (0L<<8) | ||
| 1713 | #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1 (1L<<8) | ||
| 1714 | #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2 (2L<<8) | ||
| 1715 | #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3 (3L<<8) | ||
| 1716 | #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ (0x3L<<10) | ||
| 1717 | #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0 (0L<<10) | ||
| 1718 | #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1 (1L<<10) | ||
| 1719 | #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2 (2L<<10) | ||
| 1720 | #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3 (3L<<10) | ||
| 1016 | 1721 | ||
| 1017 | 1722 | ||
| 1018 | /* | 1723 | /* |
| @@ -1031,11 +1736,35 @@ struct l2_fhdr { | |||
| 1031 | #define BNX2_NVM_COMMAND_WRDI (1L<<17) | 1736 | #define BNX2_NVM_COMMAND_WRDI (1L<<17) |
| 1032 | #define BNX2_NVM_COMMAND_EWSR (1L<<18) | 1737 | #define BNX2_NVM_COMMAND_EWSR (1L<<18) |
| 1033 | #define BNX2_NVM_COMMAND_WRSR (1L<<19) | 1738 | #define BNX2_NVM_COMMAND_WRSR (1L<<19) |
| 1739 | #define BNX2_NVM_COMMAND_RD_ID (1L<<20) | ||
| 1740 | #define BNX2_NVM_COMMAND_RD_STATUS (1L<<21) | ||
| 1741 | #define BNX2_NVM_COMMAND_MODE_256 (1L<<22) | ||
| 1034 | 1742 | ||
| 1035 | #define BNX2_NVM_STATUS 0x00006404 | 1743 | #define BNX2_NVM_STATUS 0x00006404 |
| 1036 | #define BNX2_NVM_STATUS_PI_FSM_STATE (0xfL<<0) | 1744 | #define BNX2_NVM_STATUS_PI_FSM_STATE (0xfL<<0) |
| 1037 | #define BNX2_NVM_STATUS_EE_FSM_STATE (0xfL<<4) | 1745 | #define BNX2_NVM_STATUS_EE_FSM_STATE (0xfL<<4) |
| 1038 | #define BNX2_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) | 1746 | #define BNX2_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) |
| 1747 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_XI (0x1fL<<0) | ||
| 1748 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI (0L<<0) | ||
| 1749 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI (1L<<0) | ||
| 1750 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI (2L<<0) | ||
| 1751 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI (3L<<0) | ||
| 1752 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI (4L<<0) | ||
| 1753 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI (5L<<0) | ||
| 1754 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI (6L<<0) | ||
| 1755 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI (7L<<0) | ||
| 1756 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI (8L<<0) | ||
| 1757 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI (9L<<0) | ||
| 1758 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI (10L<<0) | ||
| 1759 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI (11L<<0) | ||
| 1760 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI (12L<<0) | ||
| 1761 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI (13L<<0) | ||
| 1762 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI (14L<<0) | ||
| 1763 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI (15L<<0) | ||
| 1764 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI (16L<<0) | ||
| 1765 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI (17L<<0) | ||
| 1766 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI (18L<<0) | ||
| 1767 | #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI (19L<<0) | ||
| 1039 | 1768 | ||
| 1040 | #define BNX2_NVM_WRITE 0x00006408 | 1769 | #define BNX2_NVM_WRITE 0x00006408 |
| 1041 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) | 1770 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) |
| @@ -1046,6 +1775,10 @@ struct l2_fhdr { | |||
| 1046 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0) | 1775 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0) |
| 1047 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0) | 1776 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0) |
| 1048 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0) | 1777 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0) |
| 1778 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI_XI (1L<<0) | ||
| 1779 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO_XI (2L<<0) | ||
| 1780 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI (4L<<0) | ||
| 1781 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI (8L<<0) | ||
| 1049 | 1782 | ||
| 1050 | #define BNX2_NVM_ADDR 0x0000640c | 1783 | #define BNX2_NVM_ADDR 0x0000640c |
| 1051 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) | 1784 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) |
| @@ -1056,6 +1789,10 @@ struct l2_fhdr { | |||
| 1056 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0) | 1789 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0) |
| 1057 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) | 1790 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) |
| 1058 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) | 1791 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) |
| 1792 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI_XI (1L<<0) | ||
| 1793 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO_XI (2L<<0) | ||
| 1794 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI (4L<<0) | ||
| 1795 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI (8L<<0) | ||
| 1059 | 1796 | ||
| 1060 | #define BNX2_NVM_READ 0x00006410 | 1797 | #define BNX2_NVM_READ 0x00006410 |
| 1061 | #define BNX2_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) | 1798 | #define BNX2_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) |
| @@ -1066,6 +1803,10 @@ struct l2_fhdr { | |||
| 1066 | #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0) | 1803 | #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0) |
| 1067 | #define BNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0) | 1804 | #define BNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0) |
| 1068 | #define BNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0) | 1805 | #define BNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0) |
| 1806 | #define BNX2_NVM_READ_NVM_READ_VALUE_SI_XI (1L<<0) | ||
| 1807 | #define BNX2_NVM_READ_NVM_READ_VALUE_SO_XI (2L<<0) | ||
| 1808 | #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B_XI (4L<<0) | ||
| 1809 | #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK_XI (8L<<0) | ||
| 1069 | 1810 | ||
| 1070 | #define BNX2_NVM_CFG1 0x00006414 | 1811 | #define BNX2_NVM_CFG1 0x00006414 |
| 1071 | #define BNX2_NVM_CFG1_FLASH_MODE (1L<<0) | 1812 | #define BNX2_NVM_CFG1_FLASH_MODE (1L<<0) |
| @@ -1077,14 +1818,21 @@ struct l2_fhdr { | |||
| 1077 | #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4) | 1818 | #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4) |
| 1078 | #define BNX2_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) | 1819 | #define BNX2_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) |
| 1079 | #define BNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) | 1820 | #define BNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) |
| 1821 | #define BNX2_NVM_CFG1_STRAP_CONTROL_0 (1L<<23) | ||
| 1080 | #define BNX2_NVM_CFG1_PROTECT_MODE (1L<<24) | 1822 | #define BNX2_NVM_CFG1_PROTECT_MODE (1L<<24) |
| 1081 | #define BNX2_NVM_CFG1_FLASH_SIZE (1L<<25) | 1823 | #define BNX2_NVM_CFG1_FLASH_SIZE (1L<<25) |
| 1824 | #define BNX2_NVM_CFG1_FW_USTRAP_1 (1L<<26) | ||
| 1825 | #define BNX2_NVM_CFG1_FW_USTRAP_0 (1L<<27) | ||
| 1826 | #define BNX2_NVM_CFG1_FW_USTRAP_2 (1L<<28) | ||
| 1827 | #define BNX2_NVM_CFG1_FW_USTRAP_3 (1L<<29) | ||
| 1828 | #define BNX2_NVM_CFG1_FW_FLASH_TYPE_EN (1L<<30) | ||
| 1082 | #define BNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31) | 1829 | #define BNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31) |
| 1083 | 1830 | ||
| 1084 | #define BNX2_NVM_CFG2 0x00006418 | 1831 | #define BNX2_NVM_CFG2 0x00006418 |
| 1085 | #define BNX2_NVM_CFG2_ERASE_CMD (0xffL<<0) | 1832 | #define BNX2_NVM_CFG2_ERASE_CMD (0xffL<<0) |
| 1086 | #define BNX2_NVM_CFG2_DUMMY (0xffL<<8) | 1833 | #define BNX2_NVM_CFG2_DUMMY (0xffL<<8) |
| 1087 | #define BNX2_NVM_CFG2_STATUS_CMD (0xffL<<16) | 1834 | #define BNX2_NVM_CFG2_STATUS_CMD (0xffL<<16) |
| 1835 | #define BNX2_NVM_CFG2_READ_ID (0xffL<<24) | ||
| 1088 | 1836 | ||
| 1089 | #define BNX2_NVM_CFG3 0x0000641c | 1837 | #define BNX2_NVM_CFG3 0x0000641c |
| 1090 | #define BNX2_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) | 1838 | #define BNX2_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) |
| @@ -1119,6 +1867,35 @@ struct l2_fhdr { | |||
| 1119 | #define BNX2_NVM_WRITE1_WRDI_CMD (0xffL<<8) | 1867 | #define BNX2_NVM_WRITE1_WRDI_CMD (0xffL<<8) |
| 1120 | #define BNX2_NVM_WRITE1_SR_DATA (0xffL<<16) | 1868 | #define BNX2_NVM_WRITE1_SR_DATA (0xffL<<16) |
| 1121 | 1869 | ||
| 1870 | #define BNX2_NVM_CFG4 0x0000642c | ||
| 1871 | #define BNX2_NVM_CFG4_FLASH_SIZE (0x7L<<0) | ||
| 1872 | #define BNX2_NVM_CFG4_FLASH_SIZE_1MBIT (0L<<0) | ||
| 1873 | #define BNX2_NVM_CFG4_FLASH_SIZE_2MBIT (1L<<0) | ||
| 1874 | #define BNX2_NVM_CFG4_FLASH_SIZE_4MBIT (2L<<0) | ||
| 1875 | #define BNX2_NVM_CFG4_FLASH_SIZE_8MBIT (3L<<0) | ||
| 1876 | #define BNX2_NVM_CFG4_FLASH_SIZE_16MBIT (4L<<0) | ||
| 1877 | #define BNX2_NVM_CFG4_FLASH_SIZE_32MBIT (5L<<0) | ||
| 1878 | #define BNX2_NVM_CFG4_FLASH_SIZE_64MBIT (6L<<0) | ||
| 1879 | #define BNX2_NVM_CFG4_FLASH_SIZE_128MBIT (7L<<0) | ||
| 1880 | #define BNX2_NVM_CFG4_FLASH_VENDOR (1L<<3) | ||
| 1881 | #define BNX2_NVM_CFG4_FLASH_VENDOR_ST (0L<<3) | ||
| 1882 | #define BNX2_NVM_CFG4_FLASH_VENDOR_ATMEL (1L<<3) | ||
| 1883 | #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC (0x3L<<4) | ||
| 1884 | #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8 (0L<<4) | ||
| 1885 | #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9 (1L<<4) | ||
| 1886 | #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10 (2L<<4) | ||
| 1887 | #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11 (3L<<4) | ||
| 1888 | #define BNX2_NVM_CFG4_STATUS_BIT_POLARITY (1L<<6) | ||
| 1889 | #define BNX2_NVM_CFG4_RESERVED (0x1ffffffL<<7) | ||
| 1890 | |||
| 1891 | #define BNX2_NVM_RECONFIG 0x00006430 | ||
| 1892 | #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE (0xfL<<0) | ||
| 1893 | #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST (0L<<0) | ||
| 1894 | #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL (1L<<0) | ||
| 1895 | #define BNX2_NVM_RECONFIG_RECONFIG_STRAP_VALUE (0xfL<<4) | ||
| 1896 | #define BNX2_NVM_RECONFIG_RESERVED (0x7fffffL<<8) | ||
| 1897 | #define BNX2_NVM_RECONFIG_RECONFIG_DONE (1L<<31) | ||
| 1898 | |||
| 1122 | 1899 | ||
| 1123 | 1900 | ||
| 1124 | /* | 1901 | /* |
| @@ -1140,6 +1917,8 @@ struct l2_fhdr { | |||
| 1140 | #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) | 1917 | #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) |
| 1141 | #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) | 1918 | #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) |
| 1142 | #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) | 1919 | #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) |
| 1920 | #define BNX2_DMA_STATUS_GLOBAL_ERR_XI (1L<<0) | ||
| 1921 | #define BNX2_DMA_STATUS_BME_XI (1L<<4) | ||
| 1143 | 1922 | ||
| 1144 | #define BNX2_DMA_CONFIG 0x00000c08 | 1923 | #define BNX2_DMA_CONFIG 0x00000c08 |
| 1145 | #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) | 1924 | #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) |
| @@ -1161,85 +1940,315 @@ struct l2_fhdr { | |||
| 1161 | #define BNX2_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) | 1940 | #define BNX2_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) |
| 1162 | #define BNX2_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) | 1941 | #define BNX2_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) |
| 1163 | #define BNX2_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) | 1942 | #define BNX2_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) |
| 1943 | #define BNX2_DMA_CONFIG_DAT_WBSWAP_MODE_XI (0x3L<<0) | ||
| 1944 | #define BNX2_DMA_CONFIG_CTL_WBSWAP_MODE_XI (0x3L<<4) | ||
| 1945 | #define BNX2_DMA_CONFIG_MAX_PL_XI (0x7L<<12) | ||
| 1946 | #define BNX2_DMA_CONFIG_MAX_PL_128B_XI (0L<<12) | ||
| 1947 | #define BNX2_DMA_CONFIG_MAX_PL_256B_XI (1L<<12) | ||
| 1948 | #define BNX2_DMA_CONFIG_MAX_PL_512B_XI (2L<<12) | ||
| 1949 | #define BNX2_DMA_CONFIG_MAX_PL_EN_XI (1L<<15) | ||
| 1950 | #define BNX2_DMA_CONFIG_MAX_RRS_XI (0x7L<<16) | ||
| 1951 | #define BNX2_DMA_CONFIG_MAX_RRS_128B_XI (0L<<16) | ||
| 1952 | #define BNX2_DMA_CONFIG_MAX_RRS_256B_XI (1L<<16) | ||
| 1953 | #define BNX2_DMA_CONFIG_MAX_RRS_512B_XI (2L<<16) | ||
| 1954 | #define BNX2_DMA_CONFIG_MAX_RRS_1024B_XI (3L<<16) | ||
| 1955 | #define BNX2_DMA_CONFIG_MAX_RRS_2048B_XI (4L<<16) | ||
| 1956 | #define BNX2_DMA_CONFIG_MAX_RRS_4096B_XI (5L<<16) | ||
| 1957 | #define BNX2_DMA_CONFIG_MAX_RRS_EN_XI (1L<<19) | ||
| 1958 | #define BNX2_DMA_CONFIG_NO_64SWAP_EN_XI (1L<<31) | ||
| 1164 | 1959 | ||
| 1165 | #define BNX2_DMA_BLACKOUT 0x00000c0c | 1960 | #define BNX2_DMA_BLACKOUT 0x00000c0c |
| 1166 | #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) | 1961 | #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) |
| 1167 | #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) | 1962 | #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) |
| 1168 | #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) | 1963 | #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) |
| 1169 | 1964 | ||
| 1170 | #define BNX2_DMA_RCHAN_STAT 0x00000c30 | 1965 | #define BNX2_DMA_READ_MASTER_SETTING_0 0x00000c10 |
| 1171 | #define BNX2_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) | 1966 | #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP (1L<<0) |
| 1172 | #define BNX2_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) | 1967 | #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER (1L<<1) |
| 1173 | #define BNX2_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) | 1968 | #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY (1L<<2) |
| 1174 | #define BNX2_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) | 1969 | #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS (0x7L<<4) |
| 1175 | #define BNX2_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) | 1970 | #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN (1L<<7) |
| 1176 | #define BNX2_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) | 1971 | #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP (1L<<8) |
| 1177 | #define BNX2_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) | 1972 | #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER (1L<<9) |
| 1178 | #define BNX2_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) | 1973 | #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY (1L<<10) |
| 1179 | #define BNX2_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) | 1974 | #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS (0x7L<<12) |
| 1180 | #define BNX2_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) | 1975 | #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN (1L<<15) |
| 1181 | #define BNX2_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) | 1976 | #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP (1L<<16) |
| 1182 | #define BNX2_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) | 1977 | #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER (1L<<17) |
| 1183 | #define BNX2_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) | 1978 | #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY (1L<<18) |
| 1184 | #define BNX2_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) | 1979 | #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS (0x7L<<20) |
| 1185 | #define BNX2_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) | 1980 | #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN (1L<<23) |
| 1186 | #define BNX2_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) | 1981 | #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP (1L<<24) |
| 1187 | 1982 | #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER (1L<<25) | |
| 1188 | #define BNX2_DMA_WCHAN_STAT 0x00000c34 | 1983 | #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PRIORITY (1L<<26) |
| 1189 | #define BNX2_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) | 1984 | #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS (0x7L<<28) |
| 1190 | #define BNX2_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) | 1985 | #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN (1L<<31) |
| 1191 | #define BNX2_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) | 1986 | |
| 1192 | #define BNX2_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) | 1987 | #define BNX2_DMA_READ_MASTER_SETTING_1 0x00000c14 |
| 1193 | #define BNX2_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) | 1988 | #define BNX2_DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP (1L<<0) |
| 1194 | #define BNX2_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) | 1989 | #define BNX2_DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER (1L<<1) |
| 1195 | #define BNX2_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) | 1990 | #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PRIORITY (1L<<2) |
| 1196 | #define BNX2_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) | 1991 | #define BNX2_DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS (0x7L<<4) |
| 1197 | #define BNX2_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) | 1992 | #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PARAM_EN (1L<<7) |
| 1198 | #define BNX2_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) | 1993 | #define BNX2_DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP (1L<<8) |
| 1199 | #define BNX2_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) | 1994 | #define BNX2_DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER (1L<<9) |
| 1200 | #define BNX2_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) | 1995 | #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PRIORITY (1L<<10) |
| 1201 | #define BNX2_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) | 1996 | #define BNX2_DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS (0x7L<<12) |
| 1202 | #define BNX2_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) | 1997 | #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PARAM_EN (1L<<15) |
| 1203 | #define BNX2_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) | 1998 | |
| 1204 | #define BNX2_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) | 1999 | #define BNX2_DMA_WRITE_MASTER_SETTING_0 0x00000c18 |
| 1205 | 2000 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP (1L<<0) | |
| 1206 | #define BNX2_DMA_RCHAN_ASSIGNMENT 0x00000c38 | 2001 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER (1L<<1) |
| 1207 | #define BNX2_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) | 2002 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY (1L<<2) |
| 1208 | #define BNX2_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) | 2003 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD (1L<<3) |
| 1209 | #define BNX2_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) | 2004 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS (0x7L<<4) |
| 1210 | #define BNX2_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) | 2005 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN (1L<<7) |
| 1211 | #define BNX2_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) | 2006 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP (1L<<8) |
| 1212 | #define BNX2_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) | 2007 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER (1L<<9) |
| 1213 | #define BNX2_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) | 2008 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY (1L<<10) |
| 1214 | #define BNX2_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) | 2009 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD (1L<<11) |
| 1215 | 2010 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS (0x7L<<12) | |
| 1216 | #define BNX2_DMA_WCHAN_ASSIGNMENT 0x00000c3c | 2011 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN (1L<<15) |
| 1217 | #define BNX2_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) | 2012 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP (1L<<24) |
| 1218 | #define BNX2_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) | 2013 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER (1L<<25) |
| 1219 | #define BNX2_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) | 2014 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY (1L<<26) |
| 1220 | #define BNX2_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) | 2015 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD (1L<<27) |
| 1221 | #define BNX2_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) | 2016 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS (0x7L<<28) |
| 1222 | #define BNX2_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) | 2017 | #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN (1L<<31) |
| 1223 | #define BNX2_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) | 2018 | |
| 1224 | #define BNX2_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) | 2019 | #define BNX2_DMA_WRITE_MASTER_SETTING_1 0x00000c1c |
| 1225 | 2020 | #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP (1L<<0) | |
| 1226 | #define BNX2_DMA_RCHAN_STAT_00 0x00000c40 | 2021 | #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER (1L<<1) |
| 1227 | #define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) | 2022 | #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY (1L<<2) |
| 1228 | 2023 | #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD (1L<<3) | |
| 1229 | #define BNX2_DMA_RCHAN_STAT_01 0x00000c44 | 2024 | #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS (0x7L<<4) |
| 1230 | #define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) | 2025 | #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN (1L<<7) |
| 1231 | 2026 | #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP (1L<<8) | |
| 1232 | #define BNX2_DMA_RCHAN_STAT_02 0x00000c48 | 2027 | #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER (1L<<9) |
| 1233 | #define BNX2_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) | 2028 | #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY (1L<<10) |
| 1234 | #define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16) | 2029 | #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD (1L<<11) |
| 1235 | #define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17) | 2030 | #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS (0x7L<<12) |
| 1236 | #define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18) | 2031 | #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN (1L<<15) |
| 1237 | 2032 | ||
| 1238 | #define BNX2_DMA_RCHAN_STAT_10 0x00000c4c | 2033 | #define BNX2_DMA_ARBITER 0x00000c20 |
| 1239 | #define BNX2_DMA_RCHAN_STAT_11 0x00000c50 | 2034 | #define BNX2_DMA_ARBITER_NUM_READS (0x7L<<0) |
| 1240 | #define BNX2_DMA_RCHAN_STAT_12 0x00000c54 | 2035 | #define BNX2_DMA_ARBITER_WR_ARB_MODE (1L<<4) |
| 1241 | #define BNX2_DMA_RCHAN_STAT_20 0x00000c58 | 2036 | #define BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT (0L<<4) |
| 1242 | #define BNX2_DMA_RCHAN_STAT_21 0x00000c5c | 2037 | #define BNX2_DMA_ARBITER_WR_ARB_MODE_RND_RBN (1L<<4) |
| 2038 | #define BNX2_DMA_ARBITER_RD_ARB_MODE (0x3L<<5) | ||
| 2039 | #define BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT (0L<<5) | ||
| 2040 | #define BNX2_DMA_ARBITER_RD_ARB_MODE_RND_RBN (1L<<5) | ||
| 2041 | #define BNX2_DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN (2L<<5) | ||
| 2042 | #define BNX2_DMA_ARBITER_ALT_MODE_EN (1L<<8) | ||
| 2043 | #define BNX2_DMA_ARBITER_RR_MODE (1L<<9) | ||
| 2044 | #define BNX2_DMA_ARBITER_TIMER_MODE (1L<<10) | ||
| 2045 | #define BNX2_DMA_ARBITER_OUSTD_READ_REQ (0xfL<<12) | ||
| 2046 | |||
| 2047 | #define BNX2_DMA_ARB_TIMERS 0x00000c24 | ||
| 2048 | #define BNX2_DMA_ARB_TIMERS_RD_DRR_WAIT_TIME (0xffL<<0) | ||
| 2049 | #define BNX2_DMA_ARB_TIMERS_TM_MIN_TIMEOUT (0xffL<<12) | ||
| 2050 | #define BNX2_DMA_ARB_TIMERS_TM_MAX_TIMEOUT (0xfffL<<20) | ||
| 2051 | |||
| 2052 | #define BNX2_DMA_DEBUG_VECT_PEEK 0x00000c2c | ||
| 2053 | #define BNX2_DMA_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) | ||
| 2054 | #define BNX2_DMA_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) | ||
| 2055 | #define BNX2_DMA_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) | ||
| 2056 | #define BNX2_DMA_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) | ||
| 2057 | #define BNX2_DMA_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) | ||
| 2058 | #define BNX2_DMA_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) | ||
| 2059 | |||
| 2060 | #define BNX2_DMA_TAG_RAM_00 0x00000c30 | ||
| 2061 | #define BNX2_DMA_TAG_RAM_00_CHANNEL (0xfL<<0) | ||
| 2062 | #define BNX2_DMA_TAG_RAM_00_MASTER (0x7L<<4) | ||
| 2063 | #define BNX2_DMA_TAG_RAM_00_MASTER_CTX (0L<<4) | ||
| 2064 | #define BNX2_DMA_TAG_RAM_00_MASTER_RBDC (1L<<4) | ||
| 2065 | #define BNX2_DMA_TAG_RAM_00_MASTER_TBDC (2L<<4) | ||
| 2066 | #define BNX2_DMA_TAG_RAM_00_MASTER_COM (3L<<4) | ||
| 2067 | #define BNX2_DMA_TAG_RAM_00_MASTER_CP (4L<<4) | ||
| 2068 | #define BNX2_DMA_TAG_RAM_00_MASTER_TDMA (5L<<4) | ||
| 2069 | #define BNX2_DMA_TAG_RAM_00_SWAP (0x3L<<7) | ||
| 2070 | #define BNX2_DMA_TAG_RAM_00_SWAP_CONFIG (0L<<7) | ||
| 2071 | #define BNX2_DMA_TAG_RAM_00_SWAP_DATA (1L<<7) | ||
| 2072 | #define BNX2_DMA_TAG_RAM_00_SWAP_CONTROL (2L<<7) | ||
| 2073 | #define BNX2_DMA_TAG_RAM_00_FUNCTION (1L<<9) | ||
| 2074 | #define BNX2_DMA_TAG_RAM_00_VALID (1L<<10) | ||
| 2075 | |||
| 2076 | #define BNX2_DMA_TAG_RAM_01 0x00000c34 | ||
| 2077 | #define BNX2_DMA_TAG_RAM_01_CHANNEL (0xfL<<0) | ||
| 2078 | #define BNX2_DMA_TAG_RAM_01_MASTER (0x7L<<4) | ||
| 2079 | #define BNX2_DMA_TAG_RAM_01_MASTER_CTX (0L<<4) | ||
| 2080 | #define BNX2_DMA_TAG_RAM_01_MASTER_RBDC (1L<<4) | ||
| 2081 | #define BNX2_DMA_TAG_RAM_01_MASTER_TBDC (2L<<4) | ||
| 2082 | #define BNX2_DMA_TAG_RAM_01_MASTER_COM (3L<<4) | ||
| 2083 | #define BNX2_DMA_TAG_RAM_01_MASTER_CP (4L<<4) | ||
| 2084 | #define BNX2_DMA_TAG_RAM_01_MASTER_TDMA (5L<<4) | ||
| 2085 | #define BNX2_DMA_TAG_RAM_01_SWAP (0x3L<<7) | ||
| 2086 | #define BNX2_DMA_TAG_RAM_01_SWAP_CONFIG (0L<<7) | ||
| 2087 | #define BNX2_DMA_TAG_RAM_01_SWAP_DATA (1L<<7) | ||
| 2088 | #define BNX2_DMA_TAG_RAM_01_SWAP_CONTROL (2L<<7) | ||
| 2089 | #define BNX2_DMA_TAG_RAM_01_FUNCTION (1L<<9) | ||
| 2090 | #define BNX2_DMA_TAG_RAM_01_VALID (1L<<10) | ||
| 2091 | |||
| 2092 | #define BNX2_DMA_TAG_RAM_02 0x00000c38 | ||
| 2093 | #define BNX2_DMA_TAG_RAM_02_CHANNEL (0xfL<<0) | ||
| 2094 | #define BNX2_DMA_TAG_RAM_02_MASTER (0x7L<<4) | ||
| 2095 | #define BNX2_DMA_TAG_RAM_02_MASTER_CTX (0L<<4) | ||
| 2096 | #define BNX2_DMA_TAG_RAM_02_MASTER_RBDC (1L<<4) | ||
| 2097 | #define BNX2_DMA_TAG_RAM_02_MASTER_TBDC (2L<<4) | ||
| 2098 | #define BNX2_DMA_TAG_RAM_02_MASTER_COM (3L<<4) | ||
| 2099 | #define BNX2_DMA_TAG_RAM_02_MASTER_CP (4L<<4) | ||
| 2100 | #define BNX2_DMA_TAG_RAM_02_MASTER_TDMA (5L<<4) | ||
| 2101 | #define BNX2_DMA_TAG_RAM_02_SWAP (0x3L<<7) | ||
| 2102 | #define BNX2_DMA_TAG_RAM_02_SWAP_CONFIG (0L<<7) | ||
| 2103 | #define BNX2_DMA_TAG_RAM_02_SWAP_DATA (1L<<7) | ||
| 2104 | #define BNX2_DMA_TAG_RAM_02_SWAP_CONTROL (2L<<7) | ||
| 2105 | #define BNX2_DMA_TAG_RAM_02_FUNCTION (1L<<9) | ||
| 2106 | #define BNX2_DMA_TAG_RAM_02_VALID (1L<<10) | ||
| 2107 | |||
| 2108 | #define BNX2_DMA_TAG_RAM_03 0x00000c3c | ||
| 2109 | #define BNX2_DMA_TAG_RAM_03_CHANNEL (0xfL<<0) | ||
| 2110 | #define BNX2_DMA_TAG_RAM_03_MASTER (0x7L<<4) | ||
| 2111 | #define BNX2_DMA_TAG_RAM_03_MASTER_CTX (0L<<4) | ||
| 2112 | #define BNX2_DMA_TAG_RAM_03_MASTER_RBDC (1L<<4) | ||
| 2113 | #define BNX2_DMA_TAG_RAM_03_MASTER_TBDC (2L<<4) | ||
| 2114 | #define BNX2_DMA_TAG_RAM_03_MASTER_COM (3L<<4) | ||
| 2115 | #define BNX2_DMA_TAG_RAM_03_MASTER_CP (4L<<4) | ||
| 2116 | #define BNX2_DMA_TAG_RAM_03_MASTER_TDMA (5L<<4) | ||
| 2117 | #define BNX2_DMA_TAG_RAM_03_SWAP (0x3L<<7) | ||
| 2118 | #define BNX2_DMA_TAG_RAM_03_SWAP_CONFIG (0L<<7) | ||
| 2119 | #define BNX2_DMA_TAG_RAM_03_SWAP_DATA (1L<<7) | ||
| 2120 | #define BNX2_DMA_TAG_RAM_03_SWAP_CONTROL (2L<<7) | ||
| 2121 | #define BNX2_DMA_TAG_RAM_03_FUNCTION (1L<<9) | ||
| 2122 | #define BNX2_DMA_TAG_RAM_03_VALID (1L<<10) | ||
| 2123 | |||
| 2124 | #define BNX2_DMA_TAG_RAM_04 0x00000c40 | ||
| 2125 | #define BNX2_DMA_TAG_RAM_04_CHANNEL (0xfL<<0) | ||
| 2126 | #define BNX2_DMA_TAG_RAM_04_MASTER (0x7L<<4) | ||
| 2127 | #define BNX2_DMA_TAG_RAM_04_MASTER_CTX (0L<<4) | ||
| 2128 | #define BNX2_DMA_TAG_RAM_04_MASTER_RBDC (1L<<4) | ||
| 2129 | #define BNX2_DMA_TAG_RAM_04_MASTER_TBDC (2L<<4) | ||
| 2130 | #define BNX2_DMA_TAG_RAM_04_MASTER_COM (3L<<4) | ||
| 2131 | #define BNX2_DMA_TAG_RAM_04_MASTER_CP (4L<<4) | ||
| 2132 | #define BNX2_DMA_TAG_RAM_04_MASTER_TDMA (5L<<4) | ||
| 2133 | #define BNX2_DMA_TAG_RAM_04_SWAP (0x3L<<7) | ||
| 2134 | #define BNX2_DMA_TAG_RAM_04_SWAP_CONFIG (0L<<7) | ||
| 2135 | #define BNX2_DMA_TAG_RAM_04_SWAP_DATA (1L<<7) | ||
| 2136 | #define BNX2_DMA_TAG_RAM_04_SWAP_CONTROL (2L<<7) | ||
| 2137 | #define BNX2_DMA_TAG_RAM_04_FUNCTION (1L<<9) | ||
| 2138 | #define BNX2_DMA_TAG_RAM_04_VALID (1L<<10) | ||
| 2139 | |||
| 2140 | #define BNX2_DMA_TAG_RAM_05 0x00000c44 | ||
| 2141 | #define BNX2_DMA_TAG_RAM_05_CHANNEL (0xfL<<0) | ||
| 2142 | #define BNX2_DMA_TAG_RAM_05_MASTER (0x7L<<4) | ||
| 2143 | #define BNX2_DMA_TAG_RAM_05_MASTER_CTX (0L<<4) | ||
| 2144 | #define BNX2_DMA_TAG_RAM_05_MASTER_RBDC (1L<<4) | ||
| 2145 | #define BNX2_DMA_TAG_RAM_05_MASTER_TBDC (2L<<4) | ||
| 2146 | #define BNX2_DMA_TAG_RAM_05_MASTER_COM (3L<<4) | ||
| 2147 | #define BNX2_DMA_TAG_RAM_05_MASTER_CP (4L<<4) | ||
| 2148 | #define BNX2_DMA_TAG_RAM_05_MASTER_TDMA (5L<<4) | ||
| 2149 | #define BNX2_DMA_TAG_RAM_05_SWAP (0x3L<<7) | ||
| 2150 | #define BNX2_DMA_TAG_RAM_05_SWAP_CONFIG (0L<<7) | ||
| 2151 | #define BNX2_DMA_TAG_RAM_05_SWAP_DATA (1L<<7) | ||
| 2152 | #define BNX2_DMA_TAG_RAM_05_SWAP_CONTROL (2L<<7) | ||
| 2153 | #define BNX2_DMA_TAG_RAM_05_FUNCTION (1L<<9) | ||
| 2154 | #define BNX2_DMA_TAG_RAM_05_VALID (1L<<10) | ||
| 2155 | |||
| 2156 | #define BNX2_DMA_TAG_RAM_06 0x00000c48 | ||
| 2157 | #define BNX2_DMA_TAG_RAM_06_CHANNEL (0xfL<<0) | ||
| 2158 | #define BNX2_DMA_TAG_RAM_06_MASTER (0x7L<<4) | ||
| 2159 | #define BNX2_DMA_TAG_RAM_06_MASTER_CTX (0L<<4) | ||
| 2160 | #define BNX2_DMA_TAG_RAM_06_MASTER_RBDC (1L<<4) | ||
| 2161 | #define BNX2_DMA_TAG_RAM_06_MASTER_TBDC (2L<<4) | ||
| 2162 | #define BNX2_DMA_TAG_RAM_06_MASTER_COM (3L<<4) | ||
| 2163 | #define BNX2_DMA_TAG_RAM_06_MASTER_CP (4L<<4) | ||
| 2164 | #define BNX2_DMA_TAG_RAM_06_MASTER_TDMA (5L<<4) | ||
| 2165 | #define BNX2_DMA_TAG_RAM_06_SWAP (0x3L<<7) | ||
| 2166 | #define BNX2_DMA_TAG_RAM_06_SWAP_CONFIG (0L<<7) | ||
| 2167 | #define BNX2_DMA_TAG_RAM_06_SWAP_DATA (1L<<7) | ||
| 2168 | #define BNX2_DMA_TAG_RAM_06_SWAP_CONTROL (2L<<7) | ||
| 2169 | #define BNX2_DMA_TAG_RAM_06_FUNCTION (1L<<9) | ||
| 2170 | #define BNX2_DMA_TAG_RAM_06_VALID (1L<<10) | ||
| 2171 | |||
| 2172 | #define BNX2_DMA_TAG_RAM_07 0x00000c4c | ||
| 2173 | #define BNX2_DMA_TAG_RAM_07_CHANNEL (0xfL<<0) | ||
| 2174 | #define BNX2_DMA_TAG_RAM_07_MASTER (0x7L<<4) | ||
| 2175 | #define BNX2_DMA_TAG_RAM_07_MASTER_CTX (0L<<4) | ||
| 2176 | #define BNX2_DMA_TAG_RAM_07_MASTER_RBDC (1L<<4) | ||
| 2177 | #define BNX2_DMA_TAG_RAM_07_MASTER_TBDC (2L<<4) | ||
| 2178 | #define BNX2_DMA_TAG_RAM_07_MASTER_COM (3L<<4) | ||
| 2179 | #define BNX2_DMA_TAG_RAM_07_MASTER_CP (4L<<4) | ||
| 2180 | #define BNX2_DMA_TAG_RAM_07_MASTER_TDMA (5L<<4) | ||
| 2181 | #define BNX2_DMA_TAG_RAM_07_SWAP (0x3L<<7) | ||
| 2182 | #define BNX2_DMA_TAG_RAM_07_SWAP_CONFIG (0L<<7) | ||
| 2183 | #define BNX2_DMA_TAG_RAM_07_SWAP_DATA (1L<<7) | ||
| 2184 | #define BNX2_DMA_TAG_RAM_07_SWAP_CONTROL (2L<<7) | ||
| 2185 | #define BNX2_DMA_TAG_RAM_07_FUNCTION (1L<<9) | ||
| 2186 | #define BNX2_DMA_TAG_RAM_07_VALID (1L<<10) | ||
| 2187 | |||
| 2188 | #define BNX2_DMA_TAG_RAM_08 0x00000c50 | ||
| 2189 | #define BNX2_DMA_TAG_RAM_08_CHANNEL (0xfL<<0) | ||
| 2190 | #define BNX2_DMA_TAG_RAM_08_MASTER (0x7L<<4) | ||
| 2191 | #define BNX2_DMA_TAG_RAM_08_MASTER_CTX (0L<<4) | ||
| 2192 | #define BNX2_DMA_TAG_RAM_08_MASTER_RBDC (1L<<4) | ||
| 2193 | #define BNX2_DMA_TAG_RAM_08_MASTER_TBDC (2L<<4) | ||
| 2194 | #define BNX2_DMA_TAG_RAM_08_MASTER_COM (3L<<4) | ||
| 2195 | #define BNX2_DMA_TAG_RAM_08_MASTER_CP (4L<<4) | ||
| 2196 | #define BNX2_DMA_TAG_RAM_08_MASTER_TDMA (5L<<4) | ||
| 2197 | #define BNX2_DMA_TAG_RAM_08_SWAP (0x3L<<7) | ||
| 2198 | #define BNX2_DMA_TAG_RAM_08_SWAP_CONFIG (0L<<7) | ||
| 2199 | #define BNX2_DMA_TAG_RAM_08_SWAP_DATA (1L<<7) | ||
| 2200 | #define BNX2_DMA_TAG_RAM_08_SWAP_CONTROL (2L<<7) | ||
| 2201 | #define BNX2_DMA_TAG_RAM_08_FUNCTION (1L<<9) | ||
| 2202 | #define BNX2_DMA_TAG_RAM_08_VALID (1L<<10) | ||
| 2203 | |||
| 2204 | #define BNX2_DMA_TAG_RAM_09 0x00000c54 | ||
| 2205 | #define BNX2_DMA_TAG_RAM_09_CHANNEL (0xfL<<0) | ||
| 2206 | #define BNX2_DMA_TAG_RAM_09_MASTER (0x7L<<4) | ||
| 2207 | #define BNX2_DMA_TAG_RAM_09_MASTER_CTX (0L<<4) | ||
| 2208 | #define BNX2_DMA_TAG_RAM_09_MASTER_RBDC (1L<<4) | ||
| 2209 | #define BNX2_DMA_TAG_RAM_09_MASTER_TBDC (2L<<4) | ||
| 2210 | #define BNX2_DMA_TAG_RAM_09_MASTER_COM (3L<<4) | ||
| 2211 | #define BNX2_DMA_TAG_RAM_09_MASTER_CP (4L<<4) | ||
| 2212 | #define BNX2_DMA_TAG_RAM_09_MASTER_TDMA (5L<<4) | ||
| 2213 | #define BNX2_DMA_TAG_RAM_09_SWAP (0x3L<<7) | ||
| 2214 | #define BNX2_DMA_TAG_RAM_09_SWAP_CONFIG (0L<<7) | ||
| 2215 | #define BNX2_DMA_TAG_RAM_09_SWAP_DATA (1L<<7) | ||
| 2216 | #define BNX2_DMA_TAG_RAM_09_SWAP_CONTROL (2L<<7) | ||
| 2217 | #define BNX2_DMA_TAG_RAM_09_FUNCTION (1L<<9) | ||
| 2218 | #define BNX2_DMA_TAG_RAM_09_VALID (1L<<10) | ||
| 2219 | |||
| 2220 | #define BNX2_DMA_TAG_RAM_10 0x00000c58 | ||
| 2221 | #define BNX2_DMA_TAG_RAM_10_CHANNEL (0xfL<<0) | ||
| 2222 | #define BNX2_DMA_TAG_RAM_10_MASTER (0x7L<<4) | ||
| 2223 | #define BNX2_DMA_TAG_RAM_10_MASTER_CTX (0L<<4) | ||
| 2224 | #define BNX2_DMA_TAG_RAM_10_MASTER_RBDC (1L<<4) | ||
| 2225 | #define BNX2_DMA_TAG_RAM_10_MASTER_TBDC (2L<<4) | ||
| 2226 | #define BNX2_DMA_TAG_RAM_10_MASTER_COM (3L<<4) | ||
| 2227 | #define BNX2_DMA_TAG_RAM_10_MASTER_CP (4L<<4) | ||
| 2228 | #define BNX2_DMA_TAG_RAM_10_MASTER_TDMA (5L<<4) | ||
| 2229 | #define BNX2_DMA_TAG_RAM_10_SWAP (0x3L<<7) | ||
| 2230 | #define BNX2_DMA_TAG_RAM_10_SWAP_CONFIG (0L<<7) | ||
| 2231 | #define BNX2_DMA_TAG_RAM_10_SWAP_DATA (1L<<7) | ||
| 2232 | #define BNX2_DMA_TAG_RAM_10_SWAP_CONTROL (2L<<7) | ||
| 2233 | #define BNX2_DMA_TAG_RAM_10_FUNCTION (1L<<9) | ||
| 2234 | #define BNX2_DMA_TAG_RAM_10_VALID (1L<<10) | ||
| 2235 | |||
| 2236 | #define BNX2_DMA_TAG_RAM_11 0x00000c5c | ||
| 2237 | #define BNX2_DMA_TAG_RAM_11_CHANNEL (0xfL<<0) | ||
| 2238 | #define BNX2_DMA_TAG_RAM_11_MASTER (0x7L<<4) | ||
| 2239 | #define BNX2_DMA_TAG_RAM_11_MASTER_CTX (0L<<4) | ||
| 2240 | #define BNX2_DMA_TAG_RAM_11_MASTER_RBDC (1L<<4) | ||
| 2241 | #define BNX2_DMA_TAG_RAM_11_MASTER_TBDC (2L<<4) | ||
| 2242 | #define BNX2_DMA_TAG_RAM_11_MASTER_COM (3L<<4) | ||
| 2243 | #define BNX2_DMA_TAG_RAM_11_MASTER_CP (4L<<4) | ||
| 2244 | #define BNX2_DMA_TAG_RAM_11_MASTER_TDMA (5L<<4) | ||
| 2245 | #define BNX2_DMA_TAG_RAM_11_SWAP (0x3L<<7) | ||
| 2246 | #define BNX2_DMA_TAG_RAM_11_SWAP_CONFIG (0L<<7) | ||
| 2247 | #define BNX2_DMA_TAG_RAM_11_SWAP_DATA (1L<<7) | ||
| 2248 | #define BNX2_DMA_TAG_RAM_11_SWAP_CONTROL (2L<<7) | ||
| 2249 | #define BNX2_DMA_TAG_RAM_11_FUNCTION (1L<<9) | ||
| 2250 | #define BNX2_DMA_TAG_RAM_11_VALID (1L<<10) | ||
| 2251 | |||
| 1243 | #define BNX2_DMA_RCHAN_STAT_22 0x00000c60 | 2252 | #define BNX2_DMA_RCHAN_STAT_22 0x00000c60 |
| 1244 | #define BNX2_DMA_RCHAN_STAT_30 0x00000c64 | 2253 | #define BNX2_DMA_RCHAN_STAT_30 0x00000c64 |
| 1245 | #define BNX2_DMA_RCHAN_STAT_31 0x00000c68 | 2254 | #define BNX2_DMA_RCHAN_STAT_31 0x00000c68 |
| @@ -1336,6 +2345,25 @@ struct l2_fhdr { | |||
| 1336 | */ | 2345 | */ |
| 1337 | #define BNX2_CTX_COMMAND 0x00001000 | 2346 | #define BNX2_CTX_COMMAND 0x00001000 |
| 1338 | #define BNX2_CTX_COMMAND_ENABLED (1L<<0) | 2347 | #define BNX2_CTX_COMMAND_ENABLED (1L<<0) |
| 2348 | #define BNX2_CTX_COMMAND_DISABLE_USAGE_CNT (1L<<1) | ||
| 2349 | #define BNX2_CTX_COMMAND_DISABLE_PLRU (1L<<2) | ||
| 2350 | #define BNX2_CTX_COMMAND_DISABLE_COMBINE_READ (1L<<3) | ||
| 2351 | #define BNX2_CTX_COMMAND_FLUSH_AHEAD (0x1fL<<8) | ||
| 2352 | #define BNX2_CTX_COMMAND_MEM_INIT (1L<<13) | ||
| 2353 | #define BNX2_CTX_COMMAND_PAGE_SIZE (0xfL<<16) | ||
| 2354 | #define BNX2_CTX_COMMAND_PAGE_SIZE_256 (0L<<16) | ||
| 2355 | #define BNX2_CTX_COMMAND_PAGE_SIZE_512 (1L<<16) | ||
| 2356 | #define BNX2_CTX_COMMAND_PAGE_SIZE_1K (2L<<16) | ||
| 2357 | #define BNX2_CTX_COMMAND_PAGE_SIZE_2K (3L<<16) | ||
| 2358 | #define BNX2_CTX_COMMAND_PAGE_SIZE_4K (4L<<16) | ||
| 2359 | #define BNX2_CTX_COMMAND_PAGE_SIZE_8K (5L<<16) | ||
| 2360 | #define BNX2_CTX_COMMAND_PAGE_SIZE_16K (6L<<16) | ||
| 2361 | #define BNX2_CTX_COMMAND_PAGE_SIZE_32K (7L<<16) | ||
| 2362 | #define BNX2_CTX_COMMAND_PAGE_SIZE_64K (8L<<16) | ||
| 2363 | #define BNX2_CTX_COMMAND_PAGE_SIZE_128K (9L<<16) | ||
| 2364 | #define BNX2_CTX_COMMAND_PAGE_SIZE_256K (10L<<16) | ||
| 2365 | #define BNX2_CTX_COMMAND_PAGE_SIZE_512K (11L<<16) | ||
| 2366 | #define BNX2_CTX_COMMAND_PAGE_SIZE_1M (12L<<16) | ||
| 1339 | 2367 | ||
| 1340 | #define BNX2_CTX_STATUS 0x00001004 | 2368 | #define BNX2_CTX_STATUS 0x00001004 |
| 1341 | #define BNX2_CTX_STATUS_LOCK_WAIT (1L<<0) | 2369 | #define BNX2_CTX_STATUS_LOCK_WAIT (1L<<0) |
| @@ -1343,6 +2371,13 @@ struct l2_fhdr { | |||
| 1343 | #define BNX2_CTX_STATUS_WRITE_STAT (1L<<17) | 2371 | #define BNX2_CTX_STATUS_WRITE_STAT (1L<<17) |
| 1344 | #define BNX2_CTX_STATUS_ACC_STALL_STAT (1L<<18) | 2372 | #define BNX2_CTX_STATUS_ACC_STALL_STAT (1L<<18) |
| 1345 | #define BNX2_CTX_STATUS_LOCK_STALL_STAT (1L<<19) | 2373 | #define BNX2_CTX_STATUS_LOCK_STALL_STAT (1L<<19) |
| 2374 | #define BNX2_CTX_STATUS_EXT_READ_STAT (1L<<20) | ||
| 2375 | #define BNX2_CTX_STATUS_EXT_WRITE_STAT (1L<<21) | ||
| 2376 | #define BNX2_CTX_STATUS_MISS_STAT (1L<<22) | ||
| 2377 | #define BNX2_CTX_STATUS_HIT_STAT (1L<<23) | ||
| 2378 | #define BNX2_CTX_STATUS_DEAD_LOCK (1L<<24) | ||
| 2379 | #define BNX2_CTX_STATUS_USAGE_CNT_ERR (1L<<25) | ||
| 2380 | #define BNX2_CTX_STATUS_INVALID_PAGE (1L<<26) | ||
| 1346 | 2381 | ||
| 1347 | #define BNX2_CTX_VIRT_ADDR 0x00001008 | 2382 | #define BNX2_CTX_VIRT_ADDR 0x00001008 |
| 1348 | #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) | 2383 | #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) |
| @@ -1357,10 +2392,15 @@ struct l2_fhdr { | |||
| 1357 | #define BNX2_CTX_LOCK 0x00001018 | 2392 | #define BNX2_CTX_LOCK 0x00001018 |
| 1358 | #define BNX2_CTX_LOCK_TYPE (0x7L<<0) | 2393 | #define BNX2_CTX_LOCK_TYPE (0x7L<<0) |
| 1359 | #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) | 2394 | #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) |
| 1360 | #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0) | ||
| 1361 | #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) | 2395 | #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) |
| 1362 | #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) | 2396 | #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) |
| 1363 | #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) | 2397 | #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) |
| 2398 | #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0) | ||
| 2399 | #define BNX2_CTX_LOCK_TYPE_VOID_XI (0L<<0) | ||
| 2400 | #define BNX2_CTX_LOCK_TYPE_PROTOCOL_XI (1L<<0) | ||
| 2401 | #define BNX2_CTX_LOCK_TYPE_TX_XI (2L<<0) | ||
| 2402 | #define BNX2_CTX_LOCK_TYPE_TIMER_XI (4L<<0) | ||
| 2403 | #define BNX2_CTX_LOCK_TYPE_COMPLETE_XI (7L<<0) | ||
| 1364 | #define BNX2_CTX_LOCK_CID_VALUE (0x3fffL<<7) | 2404 | #define BNX2_CTX_LOCK_CID_VALUE (0x3fffL<<7) |
| 1365 | #define BNX2_CTX_LOCK_GRANTED (1L<<26) | 2405 | #define BNX2_CTX_LOCK_GRANTED (1L<<26) |
| 1366 | #define BNX2_CTX_LOCK_MODE (0x7L<<27) | 2406 | #define BNX2_CTX_LOCK_MODE (0x7L<<27) |
| @@ -1370,21 +2410,89 @@ struct l2_fhdr { | |||
| 1370 | #define BNX2_CTX_LOCK_STATUS (1L<<30) | 2410 | #define BNX2_CTX_LOCK_STATUS (1L<<30) |
| 1371 | #define BNX2_CTX_LOCK_REQ (1L<<31) | 2411 | #define BNX2_CTX_LOCK_REQ (1L<<31) |
| 1372 | 2412 | ||
| 2413 | #define BNX2_CTX_CTX_CTRL 0x0000101c | ||
| 2414 | #define BNX2_CTX_CTX_CTRL_CTX_ADDR (0x7ffffL<<2) | ||
| 2415 | #define BNX2_CTX_CTX_CTRL_MOD_USAGE_CNT (0x3L<<21) | ||
| 2416 | #define BNX2_CTX_CTX_CTRL_NO_RAM_ACC (1L<<23) | ||
| 2417 | #define BNX2_CTX_CTX_CTRL_PREFETCH_SIZE (0x3L<<24) | ||
| 2418 | #define BNX2_CTX_CTX_CTRL_ATTR (1L<<26) | ||
| 2419 | #define BNX2_CTX_CTX_CTRL_WRITE_REQ (1L<<30) | ||
| 2420 | #define BNX2_CTX_CTX_CTRL_READ_REQ (1L<<31) | ||
| 2421 | |||
| 2422 | #define BNX2_CTX_CTX_DATA 0x00001020 | ||
| 1373 | #define BNX2_CTX_ACCESS_STATUS 0x00001040 | 2423 | #define BNX2_CTX_ACCESS_STATUS 0x00001040 |
| 1374 | #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) | 2424 | #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) |
| 1375 | #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) | 2425 | #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) |
| 1376 | #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) | 2426 | #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) |
| 1377 | #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) | 2427 | #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) |
| 1378 | #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) | 2428 | #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) |
| 2429 | #define BNX2_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI (0x1fL<<0) | ||
| 2430 | #define BNX2_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI (0x1fL<<5) | ||
| 2431 | #define BNX2_CTX_ACCESS_STATUS_REQUEST_XI (0x3fffffL<<10) | ||
| 1379 | 2432 | ||
| 1380 | #define BNX2_CTX_DBG_LOCK_STATUS 0x00001044 | 2433 | #define BNX2_CTX_DBG_LOCK_STATUS 0x00001044 |
| 1381 | #define BNX2_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) | 2434 | #define BNX2_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) |
| 1382 | #define BNX2_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) | 2435 | #define BNX2_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) |
| 1383 | 2436 | ||
| 2437 | #define BNX2_CTX_CACHE_CTRL_STATUS 0x00001048 | ||
| 2438 | #define BNX2_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW (1L<<0) | ||
| 2439 | #define BNX2_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP (1L<<1) | ||
| 2440 | #define BNX2_CTX_CACHE_CTRL_STATUS_FLUSH_START (1L<<6) | ||
| 2441 | #define BNX2_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT (0x3fL<<7) | ||
| 2442 | #define BNX2_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED (0x3fL<<13) | ||
| 2443 | #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE (1L<<19) | ||
| 2444 | #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE (1L<<20) | ||
| 2445 | #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE (1L<<21) | ||
| 2446 | #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE (1L<<22) | ||
| 2447 | #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE (1L<<23) | ||
| 2448 | #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE (1L<<24) | ||
| 2449 | #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE (1L<<25) | ||
| 2450 | #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE (1L<<26) | ||
| 2451 | #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE (1L<<27) | ||
| 2452 | #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE (1L<<28) | ||
| 2453 | #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE (1L<<29) | ||
| 2454 | |||
| 2455 | #define BNX2_CTX_CACHE_CTRL_SM_STATUS 0x0000104c | ||
| 2456 | #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_DWC (0x7L<<0) | ||
| 2457 | #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC (0x7L<<3) | ||
| 2458 | #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC (0x7L<<6) | ||
| 2459 | #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC (0x7L<<9) | ||
| 2460 | #define BNX2_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR (0x7fffL<<16) | ||
| 2461 | |||
| 2462 | #define BNX2_CTX_CACHE_STATUS 0x00001050 | ||
| 2463 | #define BNX2_CTX_CACHE_STATUS_HELD_ENTRIES (0x3ffL<<0) | ||
| 2464 | #define BNX2_CTX_CACHE_STATUS_MAX_HELD_ENTRIES (0x3ffL<<16) | ||
| 2465 | |||
| 2466 | #define BNX2_CTX_DMA_STATUS 0x00001054 | ||
| 2467 | #define BNX2_CTX_DMA_STATUS_RD_CHAN0_STATUS (0x3L<<0) | ||
| 2468 | #define BNX2_CTX_DMA_STATUS_RD_CHAN1_STATUS (0x3L<<2) | ||
| 2469 | #define BNX2_CTX_DMA_STATUS_RD_CHAN2_STATUS (0x3L<<4) | ||
| 2470 | #define BNX2_CTX_DMA_STATUS_RD_CHAN3_STATUS (0x3L<<6) | ||
| 2471 | #define BNX2_CTX_DMA_STATUS_RD_CHAN4_STATUS (0x3L<<8) | ||
| 2472 | #define BNX2_CTX_DMA_STATUS_RD_CHAN5_STATUS (0x3L<<10) | ||
| 2473 | #define BNX2_CTX_DMA_STATUS_RD_CHAN6_STATUS (0x3L<<12) | ||
| 2474 | #define BNX2_CTX_DMA_STATUS_RD_CHAN7_STATUS (0x3L<<14) | ||
| 2475 | #define BNX2_CTX_DMA_STATUS_RD_CHAN8_STATUS (0x3L<<16) | ||
| 2476 | #define BNX2_CTX_DMA_STATUS_RD_CHAN9_STATUS (0x3L<<18) | ||
| 2477 | #define BNX2_CTX_DMA_STATUS_RD_CHAN10_STATUS (0x3L<<20) | ||
| 2478 | |||
| 2479 | #define BNX2_CTX_REP_STATUS 0x00001058 | ||
| 2480 | #define BNX2_CTX_REP_STATUS_ERROR_ENTRY (0x3ffL<<0) | ||
| 2481 | #define BNX2_CTX_REP_STATUS_ERROR_CLIENT_ID (0x1fL<<10) | ||
| 2482 | #define BNX2_CTX_REP_STATUS_USAGE_CNT_MAX_ERR (1L<<16) | ||
| 2483 | #define BNX2_CTX_REP_STATUS_USAGE_CNT_MIN_ERR (1L<<17) | ||
| 2484 | #define BNX2_CTX_REP_STATUS_USAGE_CNT_MISS_ERR (1L<<18) | ||
| 2485 | |||
| 2486 | #define BNX2_CTX_CKSUM_ERROR_STATUS 0x0000105c | ||
| 2487 | #define BNX2_CTX_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0) | ||
| 2488 | #define BNX2_CTX_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16) | ||
| 2489 | |||
| 1384 | #define BNX2_CTX_CHNL_LOCK_STATUS_0 0x00001080 | 2490 | #define BNX2_CTX_CHNL_LOCK_STATUS_0 0x00001080 |
| 1385 | #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) | 2491 | #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) |
| 1386 | #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) | 2492 | #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) |
| 1387 | #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) | 2493 | #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) |
| 2494 | #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE_XI (1L<<14) | ||
| 2495 | #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE_XI (0x7L<<15) | ||
| 1388 | 2496 | ||
| 1389 | #define BNX2_CTX_CHNL_LOCK_STATUS_1 0x00001084 | 2497 | #define BNX2_CTX_CHNL_LOCK_STATUS_1 0x00001084 |
| 1390 | #define BNX2_CTX_CHNL_LOCK_STATUS_2 0x00001088 | 2498 | #define BNX2_CTX_CHNL_LOCK_STATUS_2 0x00001088 |
| @@ -1394,6 +2502,26 @@ struct l2_fhdr { | |||
| 1394 | #define BNX2_CTX_CHNL_LOCK_STATUS_6 0x00001098 | 2502 | #define BNX2_CTX_CHNL_LOCK_STATUS_6 0x00001098 |
| 1395 | #define BNX2_CTX_CHNL_LOCK_STATUS_7 0x0000109c | 2503 | #define BNX2_CTX_CHNL_LOCK_STATUS_7 0x0000109c |
| 1396 | #define BNX2_CTX_CHNL_LOCK_STATUS_8 0x000010a0 | 2504 | #define BNX2_CTX_CHNL_LOCK_STATUS_8 0x000010a0 |
| 2505 | #define BNX2_CTX_CHNL_LOCK_STATUS_9 0x000010a4 | ||
| 2506 | |||
| 2507 | #define BNX2_CTX_CACHE_DATA 0x000010c4 | ||
| 2508 | #define BNX2_CTX_HOST_PAGE_TBL_CTRL 0x000010c8 | ||
| 2509 | #define BNX2_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR (0x1ffL<<0) | ||
| 2510 | #define BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ (1L<<30) | ||
| 2511 | #define BNX2_CTX_HOST_PAGE_TBL_CTRL_READ_REQ (1L<<31) | ||
| 2512 | |||
| 2513 | #define BNX2_CTX_HOST_PAGE_TBL_DATA0 0x000010cc | ||
| 2514 | #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID (1L<<0) | ||
| 2515 | #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALUE (0xffffffL<<8) | ||
| 2516 | |||
| 2517 | #define BNX2_CTX_HOST_PAGE_TBL_DATA1 0x000010d0 | ||
| 2518 | #define BNX2_CTX_CAM_CTRL 0x000010d4 | ||
| 2519 | #define BNX2_CTX_CAM_CTRL_CAM_ADDR (0x3ffL<<0) | ||
| 2520 | #define BNX2_CTX_CAM_CTRL_RESET (1L<<27) | ||
| 2521 | #define BNX2_CTX_CAM_CTRL_INVALIDATE (1L<<28) | ||
| 2522 | #define BNX2_CTX_CAM_CTRL_SEARCH (1L<<29) | ||
| 2523 | #define BNX2_CTX_CAM_CTRL_WRITE_REQ (1L<<30) | ||
| 2524 | #define BNX2_CTX_CAM_CTRL_READ_REQ (1L<<31) | ||
| 1397 | 2525 | ||
| 1398 | 2526 | ||
| 1399 | /* | 2527 | /* |
| @@ -1407,14 +2535,16 @@ struct l2_fhdr { | |||
| 1407 | #define BNX2_EMAC_MODE_PORT_NONE (0L<<2) | 2535 | #define BNX2_EMAC_MODE_PORT_NONE (0L<<2) |
| 1408 | #define BNX2_EMAC_MODE_PORT_MII (1L<<2) | 2536 | #define BNX2_EMAC_MODE_PORT_MII (1L<<2) |
| 1409 | #define BNX2_EMAC_MODE_PORT_GMII (2L<<2) | 2537 | #define BNX2_EMAC_MODE_PORT_GMII (2L<<2) |
| 1410 | #define BNX2_EMAC_MODE_PORT_MII_10 (3L<<2) | 2538 | #define BNX2_EMAC_MODE_PORT_MII_10M (3L<<2) |
| 1411 | #define BNX2_EMAC_MODE_MAC_LOOP (1L<<4) | 2539 | #define BNX2_EMAC_MODE_MAC_LOOP (1L<<4) |
| 1412 | #define BNX2_EMAC_MODE_25G (1L<<5) | 2540 | #define BNX2_EMAC_MODE_25G_MODE (1L<<5) |
| 1413 | #define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) | 2541 | #define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) |
| 1414 | #define BNX2_EMAC_MODE_TX_BURST (1L<<8) | 2542 | #define BNX2_EMAC_MODE_TX_BURST (1L<<8) |
| 1415 | #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) | 2543 | #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) |
| 1416 | #define BNX2_EMAC_MODE_EXT_LINK_POL (1L<<10) | 2544 | #define BNX2_EMAC_MODE_EXT_LINK_POL (1L<<10) |
| 1417 | #define BNX2_EMAC_MODE_FORCE_LINK (1L<<11) | 2545 | #define BNX2_EMAC_MODE_FORCE_LINK (1L<<11) |
| 2546 | #define BNX2_EMAC_MODE_SERDES_MODE (1L<<12) | ||
| 2547 | #define BNX2_EMAC_MODE_BOND_OVRD (1L<<13) | ||
| 1418 | #define BNX2_EMAC_MODE_MPKT (1L<<18) | 2548 | #define BNX2_EMAC_MODE_MPKT (1L<<18) |
| 1419 | #define BNX2_EMAC_MODE_MPKT_RCVD (1L<<19) | 2549 | #define BNX2_EMAC_MODE_MPKT_RCVD (1L<<19) |
| 1420 | #define BNX2_EMAC_MODE_ACPI_RCVD (1L<<20) | 2550 | #define BNX2_EMAC_MODE_ACPI_RCVD (1L<<20) |
| @@ -1422,6 +2552,11 @@ struct l2_fhdr { | |||
| 1422 | #define BNX2_EMAC_STATUS 0x00001404 | 2552 | #define BNX2_EMAC_STATUS 0x00001404 |
| 1423 | #define BNX2_EMAC_STATUS_LINK (1L<<11) | 2553 | #define BNX2_EMAC_STATUS_LINK (1L<<11) |
| 1424 | #define BNX2_EMAC_STATUS_LINK_CHANGE (1L<<12) | 2554 | #define BNX2_EMAC_STATUS_LINK_CHANGE (1L<<12) |
| 2555 | #define BNX2_EMAC_STATUS_SERDES_AUTONEG_COMPLETE (1L<<13) | ||
| 2556 | #define BNX2_EMAC_STATUS_SERDES_AUTONEG_CHANGE (1L<<14) | ||
| 2557 | #define BNX2_EMAC_STATUS_SERDES_NXT_PG_CHANGE (1L<<16) | ||
| 2558 | #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0 (1L<<17) | ||
| 2559 | #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE (1L<<18) | ||
| 1425 | #define BNX2_EMAC_STATUS_MI_COMPLETE (1L<<22) | 2560 | #define BNX2_EMAC_STATUS_MI_COMPLETE (1L<<22) |
| 1426 | #define BNX2_EMAC_STATUS_MI_INT (1L<<23) | 2561 | #define BNX2_EMAC_STATUS_MI_INT (1L<<23) |
| 1427 | #define BNX2_EMAC_STATUS_AP_ERROR (1L<<24) | 2562 | #define BNX2_EMAC_STATUS_AP_ERROR (1L<<24) |
| @@ -1429,6 +2564,9 @@ struct l2_fhdr { | |||
| 1429 | 2564 | ||
| 1430 | #define BNX2_EMAC_ATTENTION_ENA 0x00001408 | 2565 | #define BNX2_EMAC_ATTENTION_ENA 0x00001408 |
| 1431 | #define BNX2_EMAC_ATTENTION_ENA_LINK (1L<<11) | 2566 | #define BNX2_EMAC_ATTENTION_ENA_LINK (1L<<11) |
| 2567 | #define BNX2_EMAC_ATTENTION_ENA_AUTONEG_CHANGE (1L<<14) | ||
| 2568 | #define BNX2_EMAC_ATTENTION_ENA_NXT_PG_CHANGE (1L<<16) | ||
| 2569 | #define BNX2_EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE (1L<<18) | ||
| 1432 | #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) | 2570 | #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) |
| 1433 | #define BNX2_EMAC_ATTENTION_ENA_MI_INT (1L<<23) | 2571 | #define BNX2_EMAC_ATTENTION_ENA_MI_INT (1L<<23) |
| 1434 | #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) | 2572 | #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) |
| @@ -1445,6 +2583,13 @@ struct l2_fhdr { | |||
| 1445 | #define BNX2_EMAC_LED_100MB (1L<<8) | 2583 | #define BNX2_EMAC_LED_100MB (1L<<8) |
| 1446 | #define BNX2_EMAC_LED_10MB (1L<<9) | 2584 | #define BNX2_EMAC_LED_10MB (1L<<9) |
| 1447 | #define BNX2_EMAC_LED_TRAFFIC_STAT (1L<<10) | 2585 | #define BNX2_EMAC_LED_TRAFFIC_STAT (1L<<10) |
| 2586 | #define BNX2_EMAC_LED_2500MB (1L<<11) | ||
| 2587 | #define BNX2_EMAC_LED_2500MB_OVERRIDE (1L<<12) | ||
| 2588 | #define BNX2_EMAC_LED_ACTIVITY_SEL (0x3L<<17) | ||
| 2589 | #define BNX2_EMAC_LED_ACTIVITY_SEL_0 (0L<<17) | ||
| 2590 | #define BNX2_EMAC_LED_ACTIVITY_SEL_1 (1L<<17) | ||
| 2591 | #define BNX2_EMAC_LED_ACTIVITY_SEL_2 (2L<<17) | ||
| 2592 | #define BNX2_EMAC_LED_ACTIVITY_SEL_3 (3L<<17) | ||
| 1448 | #define BNX2_EMAC_LED_BLNK_RATE (0xfffL<<19) | 2593 | #define BNX2_EMAC_LED_BLNK_RATE (0xfffL<<19) |
| 1449 | #define BNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31) | 2594 | #define BNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31) |
| 1450 | 2595 | ||
| @@ -1515,9 +2660,15 @@ struct l2_fhdr { | |||
| 1515 | #define BNX2_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) | 2660 | #define BNX2_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) |
| 1516 | #define BNX2_EMAC_MDIO_COMM_COMMAND (0x3L<<26) | 2661 | #define BNX2_EMAC_MDIO_COMM_COMMAND (0x3L<<26) |
| 1517 | #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) | 2662 | #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) |
| 2663 | #define BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26) | ||
| 1518 | #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) | 2664 | #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) |
| 1519 | #define BNX2_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) | 2665 | #define BNX2_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) |
| 2666 | #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_22_XI (1L<<26) | ||
| 2667 | #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_45_XI (1L<<26) | ||
| 2668 | #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_22_XI (2L<<26) | ||
| 2669 | #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI (2L<<26) | ||
| 1520 | #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) | 2670 | #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) |
| 2671 | #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26) | ||
| 1521 | #define BNX2_EMAC_MDIO_COMM_FAIL (1L<<28) | 2672 | #define BNX2_EMAC_MDIO_COMM_FAIL (1L<<28) |
| 1522 | #define BNX2_EMAC_MDIO_COMM_START_BUSY (1L<<29) | 2673 | #define BNX2_EMAC_MDIO_COMM_START_BUSY (1L<<29) |
| 1523 | #define BNX2_EMAC_MDIO_COMM_DISEXT (1L<<30) | 2674 | #define BNX2_EMAC_MDIO_COMM_DISEXT (1L<<30) |
| @@ -1534,13 +2685,17 @@ struct l2_fhdr { | |||
| 1534 | #define BNX2_EMAC_MDIO_MODE_MDIO_OE (1L<<10) | 2685 | #define BNX2_EMAC_MDIO_MODE_MDIO_OE (1L<<10) |
| 1535 | #define BNX2_EMAC_MDIO_MODE_MDC (1L<<11) | 2686 | #define BNX2_EMAC_MDIO_MODE_MDC (1L<<11) |
| 1536 | #define BNX2_EMAC_MDIO_MODE_MDINT (1L<<12) | 2687 | #define BNX2_EMAC_MDIO_MODE_MDINT (1L<<12) |
| 2688 | #define BNX2_EMAC_MDIO_MODE_EXT_MDINT (1L<<13) | ||
| 1537 | #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) | 2689 | #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) |
| 2690 | #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT_XI (0x3fL<<16) | ||
| 2691 | #define BNX2_EMAC_MDIO_MODE_CLAUSE_45_XI (1L<<31) | ||
| 1538 | 2692 | ||
| 1539 | #define BNX2_EMAC_MDIO_AUTO_STATUS 0x000014b8 | 2693 | #define BNX2_EMAC_MDIO_AUTO_STATUS 0x000014b8 |
| 1540 | #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) | 2694 | #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) |
| 1541 | 2695 | ||
| 1542 | #define BNX2_EMAC_TX_MODE 0x000014bc | 2696 | #define BNX2_EMAC_TX_MODE 0x000014bc |
| 1543 | #define BNX2_EMAC_TX_MODE_RESET (1L<<0) | 2697 | #define BNX2_EMAC_TX_MODE_RESET (1L<<0) |
| 2698 | #define BNX2_EMAC_TX_MODE_CS16_TEST (1L<<2) | ||
| 1544 | #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) | 2699 | #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) |
| 1545 | #define BNX2_EMAC_TX_MODE_FLOW_EN (1L<<4) | 2700 | #define BNX2_EMAC_TX_MODE_FLOW_EN (1L<<4) |
| 1546 | #define BNX2_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) | 2701 | #define BNX2_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) |
| @@ -1553,6 +2708,7 @@ struct l2_fhdr { | |||
| 1553 | #define BNX2_EMAC_TX_STATUS_XON_SENT (1L<<2) | 2708 | #define BNX2_EMAC_TX_STATUS_XON_SENT (1L<<2) |
| 1554 | #define BNX2_EMAC_TX_STATUS_LINK_UP (1L<<3) | 2709 | #define BNX2_EMAC_TX_STATUS_LINK_UP (1L<<3) |
| 1555 | #define BNX2_EMAC_TX_STATUS_UNDERRUN (1L<<4) | 2710 | #define BNX2_EMAC_TX_STATUS_UNDERRUN (1L<<4) |
| 2711 | #define BNX2_EMAC_TX_STATUS_CS16_ERROR (1L<<5) | ||
| 1556 | 2712 | ||
| 1557 | #define BNX2_EMAC_TX_LENGTHS 0x000014c4 | 2713 | #define BNX2_EMAC_TX_LENGTHS 0x000014c4 |
| 1558 | #define BNX2_EMAC_TX_LENGTHS_SLOT (0xffL<<0) | 2714 | #define BNX2_EMAC_TX_LENGTHS_SLOT (0xffL<<0) |
| @@ -1586,6 +2742,10 @@ struct l2_fhdr { | |||
| 1586 | #define BNX2_EMAC_MULTICAST_HASH5 0x000014e4 | 2742 | #define BNX2_EMAC_MULTICAST_HASH5 0x000014e4 |
| 1587 | #define BNX2_EMAC_MULTICAST_HASH6 0x000014e8 | 2743 | #define BNX2_EMAC_MULTICAST_HASH6 0x000014e8 |
| 1588 | #define BNX2_EMAC_MULTICAST_HASH7 0x000014ec | 2744 | #define BNX2_EMAC_MULTICAST_HASH7 0x000014ec |
| 2745 | #define BNX2_EMAC_CKSUM_ERROR_STATUS 0x000014f0 | ||
| 2746 | #define BNX2_EMAC_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0) | ||
| 2747 | #define BNX2_EMAC_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16) | ||
| 2748 | |||
| 1589 | #define BNX2_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 | 2749 | #define BNX2_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 |
| 1590 | #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 | 2750 | #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 |
| 1591 | #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 | 2751 | #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 |
| @@ -1608,7 +2768,7 @@ struct l2_fhdr { | |||
| 1608 | #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c | 2768 | #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c |
| 1609 | #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 | 2769 | #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 |
| 1610 | #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 | 2770 | #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 |
| 1611 | #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558 | 2771 | #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS 0x00001558 |
| 1612 | #define BNX2_EMAC_RXMAC_DEBUG0 0x0000155c | 2772 | #define BNX2_EMAC_RXMAC_DEBUG0 0x0000155c |
| 1613 | #define BNX2_EMAC_RXMAC_DEBUG1 0x00001560 | 2773 | #define BNX2_EMAC_RXMAC_DEBUG1 0x00001560 |
| 1614 | #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) | 2774 | #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) |
| @@ -1661,9 +2821,9 @@ struct l2_fhdr { | |||
| 1661 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) | 2821 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) |
| 1662 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) | 2822 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) |
| 1663 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) | 2823 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) |
| 1664 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16) | ||
| 1665 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) | 2824 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) |
| 1666 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) | 2825 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) |
| 2826 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16) | ||
| 1667 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) | 2827 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) |
| 1668 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) | 2828 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) |
| 1669 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) | 2829 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) |
| @@ -1701,7 +2861,7 @@ struct l2_fhdr { | |||
| 1701 | #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) | 2861 | #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) |
| 1702 | #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) | 2862 | #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) |
| 1703 | #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) | 2863 | #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) |
| 1704 | #define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26) | 2864 | #define BNX2_EMAC_RXMAC_DEBUG4_SFD_FOUND (1L<<26) |
| 1705 | #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) | 2865 | #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) |
| 1706 | #define BNX2_EMAC_RXMAC_DEBUG4_START (1L<<28) | 2866 | #define BNX2_EMAC_RXMAC_DEBUG4_START (1L<<28) |
| 1707 | 2867 | ||
| @@ -1733,6 +2893,7 @@ struct l2_fhdr { | |||
| 1733 | #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19) | 2893 | #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19) |
| 1734 | #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) | 2894 | #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) |
| 1735 | 2895 | ||
| 2896 | #define BNX2_EMAC_RX_STAT_FALSECARRIERERRORS 0x00001574 | ||
| 1736 | #define BNX2_EMAC_RX_STAT_AC0 0x00001580 | 2897 | #define BNX2_EMAC_RX_STAT_AC0 0x00001580 |
| 1737 | #define BNX2_EMAC_RX_STAT_AC1 0x00001584 | 2898 | #define BNX2_EMAC_RX_STAT_AC1 0x00001584 |
| 1738 | #define BNX2_EMAC_RX_STAT_AC2 0x00001588 | 2899 | #define BNX2_EMAC_RX_STAT_AC2 0x00001588 |
| @@ -1757,6 +2918,7 @@ struct l2_fhdr { | |||
| 1757 | #define BNX2_EMAC_RX_STAT_AC21 0x000015d4 | 2918 | #define BNX2_EMAC_RX_STAT_AC21 0x000015d4 |
| 1758 | #define BNX2_EMAC_RX_STAT_AC22 0x000015d8 | 2919 | #define BNX2_EMAC_RX_STAT_AC22 0x000015d8 |
| 1759 | #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc | 2920 | #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc |
| 2921 | #define BNX2_EMAC_RX_STAT_AC_28 0x000015f4 | ||
| 1760 | #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 | 2922 | #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 |
| 1761 | #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604 | 2923 | #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604 |
| 1762 | #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608 | 2924 | #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608 |
| @@ -1777,7 +2939,7 @@ struct l2_fhdr { | |||
| 1777 | #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644 | 2939 | #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644 |
| 1778 | #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648 | 2940 | #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648 |
| 1779 | #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c | 2941 | #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c |
| 1780 | #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650 | 2942 | #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS 0x00001650 |
| 1781 | #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654 | 2943 | #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654 |
| 1782 | #define BNX2_EMAC_TXMAC_DEBUG0 0x00001658 | 2944 | #define BNX2_EMAC_TXMAC_DEBUG0 0x00001658 |
| 1783 | #define BNX2_EMAC_TXMAC_DEBUG1 0x0000165c | 2945 | #define BNX2_EMAC_TXMAC_DEBUG1 0x0000165c |
| @@ -1843,16 +3005,16 @@ struct l2_fhdr { | |||
| 1843 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16) | 3005 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16) |
| 1844 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16) | 3006 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16) |
| 1845 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16) | 3007 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16) |
| 3008 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16) | ||
| 3009 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16) | ||
| 1846 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16) | 3010 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16) |
| 1847 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16) | 3011 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16) |
| 1848 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16) | ||
| 1849 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16) | ||
| 1850 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16) | ||
| 1851 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16) | ||
| 1852 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16) | ||
| 1853 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16) | 3012 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16) |
| 1854 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16) | 3013 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16) |
| 3014 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16) | ||
| 3015 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16) | ||
| 1855 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16) | 3016 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16) |
| 3017 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16) | ||
| 1856 | #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20) | 3018 | #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20) |
| 1857 | #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21) | 3019 | #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21) |
| 1858 | #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22) | 3020 | #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22) |
| @@ -1887,8 +3049,11 @@ struct l2_fhdr { | |||
| 1887 | #define BNX2_EMAC_TX_STAT_AC18 0x000016c8 | 3049 | #define BNX2_EMAC_TX_STAT_AC18 0x000016c8 |
| 1888 | #define BNX2_EMAC_TX_STAT_AC19 0x000016cc | 3050 | #define BNX2_EMAC_TX_STAT_AC19 0x000016cc |
| 1889 | #define BNX2_EMAC_TX_STAT_AC20 0x000016d0 | 3051 | #define BNX2_EMAC_TX_STAT_AC20 0x000016d0 |
| 1890 | #define BNX2_EMAC_TX_STAT_AC21 0x000016d4 | ||
| 1891 | #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8 | 3052 | #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8 |
| 3053 | #define BNX2_EMAC_TX_RATE_LIMIT_CTRL 0x000016fc | ||
| 3054 | #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC (0x7fL<<0) | ||
| 3055 | #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM (0x7fL<<16) | ||
| 3056 | #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN (1L<<31) | ||
| 1892 | 3057 | ||
| 1893 | 3058 | ||
| 1894 | /* | 3059 | /* |