diff options
Diffstat (limited to 'drivers/net/bnx2.h')
-rw-r--r-- | drivers/net/bnx2.h | 66 |
1 files changed, 64 insertions, 2 deletions
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h index 49a5de253b17..d8cd1afeb23d 100644 --- a/drivers/net/bnx2.h +++ b/drivers/net/bnx2.h | |||
@@ -6338,6 +6338,8 @@ struct l2_fhdr { | |||
6338 | 6338 | ||
6339 | #define RX_COPY_THRESH 92 | 6339 | #define RX_COPY_THRESH 92 |
6340 | 6340 | ||
6341 | #define BNX2_MISC_ENABLE_DEFAULT 0x7ffffff | ||
6342 | |||
6341 | #define DMA_READ_CHANS 5 | 6343 | #define DMA_READ_CHANS 5 |
6342 | #define DMA_WRITE_CHANS 3 | 6344 | #define DMA_WRITE_CHANS 3 |
6343 | 6345 | ||
@@ -6537,6 +6539,7 @@ struct bnx2 { | |||
6537 | #define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 | 6539 | #define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 |
6538 | #define PHY_INT_MODE_LINK_READY_FLAG 0x200 | 6540 | #define PHY_INT_MODE_LINK_READY_FLAG 0x200 |
6539 | #define PHY_DIS_EARLY_DAC_FLAG 0x400 | 6541 | #define PHY_DIS_EARLY_DAC_FLAG 0x400 |
6542 | #define REMOTE_PHY_CAP_FLAG 0x800 | ||
6540 | 6543 | ||
6541 | u32 mii_bmcr; | 6544 | u32 mii_bmcr; |
6542 | u32 mii_bmsr; | 6545 | u32 mii_bmsr; |
@@ -6625,6 +6628,7 @@ struct bnx2 { | |||
6625 | u16 req_line_speed; | 6628 | u16 req_line_speed; |
6626 | u8 req_duplex; | 6629 | u8 req_duplex; |
6627 | 6630 | ||
6631 | u8 phy_port; | ||
6628 | u8 link_up; | 6632 | u8 link_up; |
6629 | 6633 | ||
6630 | u16 line_speed; | 6634 | u16 line_speed; |
@@ -6656,7 +6660,7 @@ struct bnx2 { | |||
6656 | 6660 | ||
6657 | u32 shmem_base; | 6661 | u32 shmem_base; |
6658 | 6662 | ||
6659 | u32 fw_ver; | 6663 | char fw_version[32]; |
6660 | 6664 | ||
6661 | int pm_cap; | 6665 | int pm_cap; |
6662 | int pcix_cap; | 6666 | int pcix_cap; |
@@ -6770,7 +6774,7 @@ struct fw_info { | |||
6770 | * the firmware has timed out, the driver will assume there is no firmware | 6774 | * the firmware has timed out, the driver will assume there is no firmware |
6771 | * running and there won't be any firmware-driver synchronization during a | 6775 | * running and there won't be any firmware-driver synchronization during a |
6772 | * driver reset. */ | 6776 | * driver reset. */ |
6773 | #define FW_ACK_TIME_OUT_MS 100 | 6777 | #define FW_ACK_TIME_OUT_MS 1000 |
6774 | 6778 | ||
6775 | 6779 | ||
6776 | #define BNX2_DRV_RESET_SIGNATURE 0x00000000 | 6780 | #define BNX2_DRV_RESET_SIGNATURE 0x00000000 |
@@ -6788,6 +6792,7 @@ struct fw_info { | |||
6788 | #define BNX2_DRV_MSG_CODE_DIAG 0x07000000 | 6792 | #define BNX2_DRV_MSG_CODE_DIAG 0x07000000 |
6789 | #define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 | 6793 | #define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 |
6790 | #define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000 | 6794 | #define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000 |
6795 | #define BNX2_DRV_MSG_CODE_CMD_SET_LINK 0x10000000 | ||
6791 | 6796 | ||
6792 | #define BNX2_DRV_MSG_DATA 0x00ff0000 | 6797 | #define BNX2_DRV_MSG_DATA 0x00ff0000 |
6793 | #define BNX2_DRV_MSG_DATA_WAIT0 0x00010000 | 6798 | #define BNX2_DRV_MSG_DATA_WAIT0 0x00010000 |
@@ -6836,6 +6841,7 @@ struct fw_info { | |||
6836 | #define BNX2_LINK_STATUS_SERDES_LINK (1<<20) | 6841 | #define BNX2_LINK_STATUS_SERDES_LINK (1<<20) |
6837 | #define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) | 6842 | #define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) |
6838 | #define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) | 6843 | #define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) |
6844 | #define BNX2_LINK_STATUS_HEART_BEAT_EXPIRED (1<<31) | ||
6839 | 6845 | ||
6840 | #define BNX2_DRV_PULSE_MB 0x00000010 | 6846 | #define BNX2_DRV_PULSE_MB 0x00000010 |
6841 | #define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff | 6847 | #define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff |
@@ -6845,6 +6851,30 @@ struct fw_info { | |||
6845 | * This is used for debugging. */ | 6851 | * This is used for debugging. */ |
6846 | #define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 | 6852 | #define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 |
6847 | 6853 | ||
6854 | #define BNX2_DRV_MB_ARG0 0x00000014 | ||
6855 | #define BNX2_NETLINK_SET_LINK_SPEED_10HALF (1<<0) | ||
6856 | #define BNX2_NETLINK_SET_LINK_SPEED_10FULL (1<<1) | ||
6857 | #define BNX2_NETLINK_SET_LINK_SPEED_10 \ | ||
6858 | (BNX2_NETLINK_SET_LINK_SPEED_10HALF | \ | ||
6859 | BNX2_NETLINK_SET_LINK_SPEED_10FULL) | ||
6860 | #define BNX2_NETLINK_SET_LINK_SPEED_100HALF (1<<2) | ||
6861 | #define BNX2_NETLINK_SET_LINK_SPEED_100FULL (1<<3) | ||
6862 | #define BNX2_NETLINK_SET_LINK_SPEED_100 \ | ||
6863 | (BNX2_NETLINK_SET_LINK_SPEED_100HALF | \ | ||
6864 | BNX2_NETLINK_SET_LINK_SPEED_100FULL) | ||
6865 | #define BNX2_NETLINK_SET_LINK_SPEED_1GHALF (1<<4) | ||
6866 | #define BNX2_NETLINK_SET_LINK_SPEED_1GFULL (1<<5) | ||
6867 | #define BNX2_NETLINK_SET_LINK_SPEED_2G5HALF (1<<6) | ||
6868 | #define BNX2_NETLINK_SET_LINK_SPEED_2G5FULL (1<<7) | ||
6869 | #define BNX2_NETLINK_SET_LINK_SPEED_10GHALF (1<<8) | ||
6870 | #define BNX2_NETLINK_SET_LINK_SPEED_10GFULL (1<<9) | ||
6871 | #define BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG (1<<10) | ||
6872 | #define BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE (1<<11) | ||
6873 | #define BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE (1<<12) | ||
6874 | #define BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE (1<<13) | ||
6875 | #define BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED (1<<14) | ||
6876 | #define BNX2_NETLINK_SET_LINK_PHY_RESET (1<<15) | ||
6877 | |||
6848 | #define BNX2_DEV_INFO_SIGNATURE 0x00000020 | 6878 | #define BNX2_DEV_INFO_SIGNATURE 0x00000020 |
6849 | #define BNX2_DEV_INFO_SIGNATURE_MAGIC 0x44564900 | 6879 | #define BNX2_DEV_INFO_SIGNATURE_MAGIC 0x44564900 |
6850 | #define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 | 6880 | #define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 |
@@ -7006,6 +7036,8 @@ struct fw_info { | |||
7006 | #define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff | 7036 | #define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff |
7007 | #define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 | 7037 | #define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 |
7008 | 7038 | ||
7039 | #define BNX2_MFW_VER_PTR 0x00000014c | ||
7040 | |||
7009 | #define BNX2_BC_STATE_RESET_TYPE 0x000001c0 | 7041 | #define BNX2_BC_STATE_RESET_TYPE 0x000001c0 |
7010 | #define BNX2_BC_STATE_RESET_TYPE_SIG 0x00005254 | 7042 | #define BNX2_BC_STATE_RESET_TYPE_SIG 0x00005254 |
7011 | #define BNX2_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff | 7043 | #define BNX2_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff |
@@ -7059,12 +7091,42 @@ struct fw_info { | |||
7059 | #define BNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600) | 7091 | #define BNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600) |
7060 | #define BNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700) | 7092 | #define BNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700) |
7061 | 7093 | ||
7094 | #define BNX2_BC_STATE_CONDITION 0x000001c8 | ||
7095 | #define BNX2_CONDITION_MFW_RUN_UNKNOWN 0x00000000 | ||
7096 | #define BNX2_CONDITION_MFW_RUN_IPMI 0x00002000 | ||
7097 | #define BNX2_CONDITION_MFW_RUN_UMP 0x00004000 | ||
7098 | #define BNX2_CONDITION_MFW_RUN_NCSI 0x00006000 | ||
7099 | #define BNX2_CONDITION_MFW_RUN_NONE 0x0000e000 | ||
7100 | #define BNX2_CONDITION_MFW_RUN_MASK 0x0000e000 | ||
7101 | |||
7062 | #define BNX2_BC_STATE_DEBUG_CMD 0x1dc | 7102 | #define BNX2_BC_STATE_DEBUG_CMD 0x1dc |
7063 | #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 | 7103 | #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 |
7064 | #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 | 7104 | #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 |
7065 | #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff | 7105 | #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff |
7066 | #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff | 7106 | #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff |
7067 | 7107 | ||
7108 | #define BNX2_FW_EVT_CODE_MB 0x354 | ||
7109 | #define BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT 0x00000000 | ||
7110 | #define BNX2_FW_EVT_CODE_LINK_EVENT 0x00000001 | ||
7111 | |||
7112 | #define BNX2_DRV_ACK_CAP_MB 0x364 | ||
7113 | #define BNX2_DRV_ACK_CAP_SIGNATURE 0x35450000 | ||
7114 | #define BNX2_CAPABILITY_SIGNATURE_MASK 0xFFFF0000 | ||
7115 | |||
7116 | #define BNX2_FW_CAP_MB 0x368 | ||
7117 | #define BNX2_FW_CAP_SIGNATURE 0xaa550000 | ||
7118 | #define BNX2_FW_ACK_DRV_SIGNATURE 0x52500000 | ||
7119 | #define BNX2_FW_CAP_SIGNATURE_MASK 0xffff0000 | ||
7120 | #define BNX2_FW_CAP_REMOTE_PHY_CAPABLE 0x00000001 | ||
7121 | #define BNX2_FW_CAP_REMOTE_PHY_PRESENT 0x00000002 | ||
7122 | |||
7123 | #define BNX2_RPHY_SIGNATURE 0x36c | ||
7124 | #define BNX2_RPHY_LOAD_SIGNATURE 0x5a5a5a5a | ||
7125 | |||
7126 | #define BNX2_RPHY_FLAGS 0x370 | ||
7127 | #define BNX2_RPHY_SERDES_LINK 0x374 | ||
7128 | #define BNX2_RPHY_COPPER_LINK 0x378 | ||
7129 | |||
7068 | #define HOST_VIEW_SHMEM_BASE 0x167c00 | 7130 | #define HOST_VIEW_SHMEM_BASE 0x167c00 |
7069 | 7131 | ||
7070 | #endif | 7132 | #endif |