diff options
Diffstat (limited to 'drivers/net/bnx2.c')
-rw-r--r-- | drivers/net/bnx2.c | 120 |
1 files changed, 65 insertions, 55 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 8d0022d0cc45..8e9fe486934e 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c | |||
@@ -266,6 +266,18 @@ bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val) | |||
266 | } | 266 | } |
267 | 267 | ||
268 | static void | 268 | static void |
269 | bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val) | ||
270 | { | ||
271 | bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val); | ||
272 | } | ||
273 | |||
274 | static u32 | ||
275 | bnx2_shmem_rd(struct bnx2 *bp, u32 offset) | ||
276 | { | ||
277 | return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset)); | ||
278 | } | ||
279 | |||
280 | static void | ||
269 | bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) | 281 | bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) |
270 | { | 282 | { |
271 | offset += cid_addr; | 283 | offset += cid_addr; |
@@ -685,7 +697,7 @@ bnx2_report_fw_link(struct bnx2 *bp) | |||
685 | else | 697 | else |
686 | fw_link_status = BNX2_LINK_STATUS_LINK_DOWN; | 698 | fw_link_status = BNX2_LINK_STATUS_LINK_DOWN; |
687 | 699 | ||
688 | REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status); | 700 | bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status); |
689 | } | 701 | } |
690 | 702 | ||
691 | static char * | 703 | static char * |
@@ -1385,7 +1397,7 @@ bnx2_setup_remote_phy(struct bnx2 *bp, u8 port) | |||
1385 | speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE | | 1397 | speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE | |
1386 | BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED; | 1398 | BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED; |
1387 | 1399 | ||
1388 | REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB_ARG0, speed_arg); | 1400 | bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg); |
1389 | 1401 | ||
1390 | spin_unlock_bh(&bp->phy_lock); | 1402 | spin_unlock_bh(&bp->phy_lock); |
1391 | bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0); | 1403 | bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0); |
@@ -1530,9 +1542,9 @@ bnx2_set_default_remote_link(struct bnx2 *bp) | |||
1530 | u32 link; | 1542 | u32 link; |
1531 | 1543 | ||
1532 | if (bp->phy_port == PORT_TP) | 1544 | if (bp->phy_port == PORT_TP) |
1533 | link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_COPPER_LINK); | 1545 | link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK); |
1534 | else | 1546 | else |
1535 | link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_SERDES_LINK); | 1547 | link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK); |
1536 | 1548 | ||
1537 | if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) { | 1549 | if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) { |
1538 | bp->req_line_speed = 0; | 1550 | bp->req_line_speed = 0; |
@@ -1584,7 +1596,7 @@ bnx2_set_default_link(struct bnx2 *bp) | |||
1584 | 1596 | ||
1585 | bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; | 1597 | bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; |
1586 | 1598 | ||
1587 | reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG); | 1599 | reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG); |
1588 | reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK; | 1600 | reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK; |
1589 | if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) { | 1601 | if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) { |
1590 | bp->autoneg = 0; | 1602 | bp->autoneg = 0; |
@@ -1616,7 +1628,7 @@ bnx2_remote_phy_event(struct bnx2 *bp) | |||
1616 | u8 link_up = bp->link_up; | 1628 | u8 link_up = bp->link_up; |
1617 | u8 old_port; | 1629 | u8 old_port; |
1618 | 1630 | ||
1619 | msg = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS); | 1631 | msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); |
1620 | 1632 | ||
1621 | if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED) | 1633 | if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED) |
1622 | bnx2_send_heart_beat(bp); | 1634 | bnx2_send_heart_beat(bp); |
@@ -1693,7 +1705,7 @@ bnx2_set_remote_link(struct bnx2 *bp) | |||
1693 | { | 1705 | { |
1694 | u32 evt_code; | 1706 | u32 evt_code; |
1695 | 1707 | ||
1696 | evt_code = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_EVT_CODE_MB); | 1708 | evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB); |
1697 | switch (evt_code) { | 1709 | switch (evt_code) { |
1698 | case BNX2_FW_EVT_CODE_LINK_EVENT: | 1710 | case BNX2_FW_EVT_CODE_LINK_EVENT: |
1699 | bnx2_remote_phy_event(bp); | 1711 | bnx2_remote_phy_event(bp); |
@@ -1905,14 +1917,13 @@ bnx2_init_5708s_phy(struct bnx2 *bp) | |||
1905 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); | 1917 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); |
1906 | } | 1918 | } |
1907 | 1919 | ||
1908 | val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) & | 1920 | val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) & |
1909 | BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK; | 1921 | BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK; |
1910 | 1922 | ||
1911 | if (val) { | 1923 | if (val) { |
1912 | u32 is_backplane; | 1924 | u32 is_backplane; |
1913 | 1925 | ||
1914 | is_backplane = REG_RD_IND(bp, bp->shmem_base + | 1926 | is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); |
1915 | BNX2_SHARED_HW_CFG_CONFIG); | ||
1916 | if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) { | 1927 | if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) { |
1917 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, | 1928 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, |
1918 | BCM5708S_BLK_ADDR_TX_MISC); | 1929 | BCM5708S_BLK_ADDR_TX_MISC); |
@@ -2111,13 +2122,13 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent) | |||
2111 | bp->fw_wr_seq++; | 2122 | bp->fw_wr_seq++; |
2112 | msg_data |= bp->fw_wr_seq; | 2123 | msg_data |= bp->fw_wr_seq; |
2113 | 2124 | ||
2114 | REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data); | 2125 | bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); |
2115 | 2126 | ||
2116 | /* wait for an acknowledgement. */ | 2127 | /* wait for an acknowledgement. */ |
2117 | for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) { | 2128 | for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) { |
2118 | msleep(10); | 2129 | msleep(10); |
2119 | 2130 | ||
2120 | val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB); | 2131 | val = bnx2_shmem_rd(bp, BNX2_FW_MB); |
2121 | 2132 | ||
2122 | if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ)) | 2133 | if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ)) |
2123 | break; | 2134 | break; |
@@ -2134,7 +2145,7 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent) | |||
2134 | msg_data &= ~BNX2_DRV_MSG_CODE; | 2145 | msg_data &= ~BNX2_DRV_MSG_CODE; |
2135 | msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT; | 2146 | msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT; |
2136 | 2147 | ||
2137 | REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data); | 2148 | bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); |
2138 | 2149 | ||
2139 | return -EBUSY; | 2150 | return -EBUSY; |
2140 | } | 2151 | } |
@@ -2251,11 +2262,12 @@ bnx2_alloc_bad_rbuf(struct bnx2 *bp) | |||
2251 | good_mbuf_cnt = 0; | 2262 | good_mbuf_cnt = 0; |
2252 | 2263 | ||
2253 | /* Allocate a bunch of mbufs and save the good ones in an array. */ | 2264 | /* Allocate a bunch of mbufs and save the good ones in an array. */ |
2254 | val = REG_RD_IND(bp, BNX2_RBUF_STATUS1); | 2265 | val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); |
2255 | while (val & BNX2_RBUF_STATUS1_FREE_COUNT) { | 2266 | while (val & BNX2_RBUF_STATUS1_FREE_COUNT) { |
2256 | REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ); | 2267 | bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND, |
2268 | BNX2_RBUF_COMMAND_ALLOC_REQ); | ||
2257 | 2269 | ||
2258 | val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC); | 2270 | val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC); |
2259 | 2271 | ||
2260 | val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE; | 2272 | val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE; |
2261 | 2273 | ||
@@ -2265,7 +2277,7 @@ bnx2_alloc_bad_rbuf(struct bnx2 *bp) | |||
2265 | good_mbuf_cnt++; | 2277 | good_mbuf_cnt++; |
2266 | } | 2278 | } |
2267 | 2279 | ||
2268 | val = REG_RD_IND(bp, BNX2_RBUF_STATUS1); | 2280 | val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); |
2269 | } | 2281 | } |
2270 | 2282 | ||
2271 | /* Free the good ones back to the mbuf pool thus discarding | 2283 | /* Free the good ones back to the mbuf pool thus discarding |
@@ -2276,7 +2288,7 @@ bnx2_alloc_bad_rbuf(struct bnx2 *bp) | |||
2276 | val = good_mbuf[good_mbuf_cnt]; | 2288 | val = good_mbuf[good_mbuf_cnt]; |
2277 | val = (val << 9) | val | 1; | 2289 | val = (val << 9) | val | 1; |
2278 | 2290 | ||
2279 | REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val); | 2291 | bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val); |
2280 | } | 2292 | } |
2281 | kfree(good_mbuf); | 2293 | kfree(good_mbuf); |
2282 | return 0; | 2294 | return 0; |
@@ -3151,10 +3163,10 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) | |||
3151 | int rc; | 3163 | int rc; |
3152 | 3164 | ||
3153 | /* Halt the CPU. */ | 3165 | /* Halt the CPU. */ |
3154 | val = REG_RD_IND(bp, cpu_reg->mode); | 3166 | val = bnx2_reg_rd_ind(bp, cpu_reg->mode); |
3155 | val |= cpu_reg->mode_value_halt; | 3167 | val |= cpu_reg->mode_value_halt; |
3156 | REG_WR_IND(bp, cpu_reg->mode, val); | 3168 | bnx2_reg_wr_ind(bp, cpu_reg->mode, val); |
3157 | REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); | 3169 | bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); |
3158 | 3170 | ||
3159 | /* Load the Text area. */ | 3171 | /* Load the Text area. */ |
3160 | offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); | 3172 | offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); |
@@ -3167,7 +3179,7 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) | |||
3167 | return rc; | 3179 | return rc; |
3168 | 3180 | ||
3169 | for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { | 3181 | for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { |
3170 | REG_WR_IND(bp, offset, le32_to_cpu(fw->text[j])); | 3182 | bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j])); |
3171 | } | 3183 | } |
3172 | } | 3184 | } |
3173 | 3185 | ||
@@ -3177,7 +3189,7 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) | |||
3177 | int j; | 3189 | int j; |
3178 | 3190 | ||
3179 | for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { | 3191 | for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { |
3180 | REG_WR_IND(bp, offset, fw->data[j]); | 3192 | bnx2_reg_wr_ind(bp, offset, fw->data[j]); |
3181 | } | 3193 | } |
3182 | } | 3194 | } |
3183 | 3195 | ||
@@ -3187,7 +3199,7 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) | |||
3187 | int j; | 3199 | int j; |
3188 | 3200 | ||
3189 | for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { | 3201 | for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { |
3190 | REG_WR_IND(bp, offset, 0); | 3202 | bnx2_reg_wr_ind(bp, offset, 0); |
3191 | } | 3203 | } |
3192 | } | 3204 | } |
3193 | 3205 | ||
@@ -3197,7 +3209,7 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) | |||
3197 | int j; | 3209 | int j; |
3198 | 3210 | ||
3199 | for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { | 3211 | for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { |
3200 | REG_WR_IND(bp, offset, 0); | 3212 | bnx2_reg_wr_ind(bp, offset, 0); |
3201 | } | 3213 | } |
3202 | } | 3214 | } |
3203 | 3215 | ||
@@ -3208,19 +3220,19 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) | |||
3208 | int j; | 3220 | int j; |
3209 | 3221 | ||
3210 | for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { | 3222 | for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { |
3211 | REG_WR_IND(bp, offset, fw->rodata[j]); | 3223 | bnx2_reg_wr_ind(bp, offset, fw->rodata[j]); |
3212 | } | 3224 | } |
3213 | } | 3225 | } |
3214 | 3226 | ||
3215 | /* Clear the pre-fetch instruction. */ | 3227 | /* Clear the pre-fetch instruction. */ |
3216 | REG_WR_IND(bp, cpu_reg->inst, 0); | 3228 | bnx2_reg_wr_ind(bp, cpu_reg->inst, 0); |
3217 | REG_WR_IND(bp, cpu_reg->pc, fw->start_addr); | 3229 | bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr); |
3218 | 3230 | ||
3219 | /* Start the CPU. */ | 3231 | /* Start the CPU. */ |
3220 | val = REG_RD_IND(bp, cpu_reg->mode); | 3232 | val = bnx2_reg_rd_ind(bp, cpu_reg->mode); |
3221 | val &= ~cpu_reg->mode_value_halt; | 3233 | val &= ~cpu_reg->mode_value_halt; |
3222 | REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); | 3234 | bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); |
3223 | REG_WR_IND(bp, cpu_reg->mode, val); | 3235 | bnx2_reg_wr_ind(bp, cpu_reg->mode, val); |
3224 | 3236 | ||
3225 | return 0; | 3237 | return 0; |
3226 | } | 3238 | } |
@@ -3833,7 +3845,7 @@ bnx2_init_nvram(struct bnx2 *bp) | |||
3833 | } | 3845 | } |
3834 | 3846 | ||
3835 | get_flash_size: | 3847 | get_flash_size: |
3836 | val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2); | 3848 | val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2); |
3837 | val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK; | 3849 | val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK; |
3838 | if (val) | 3850 | if (val) |
3839 | bp->flash_size = val; | 3851 | bp->flash_size = val; |
@@ -4142,14 +4154,14 @@ bnx2_init_remote_phy(struct bnx2 *bp) | |||
4142 | if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) | 4154 | if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) |
4143 | return; | 4155 | return; |
4144 | 4156 | ||
4145 | val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_CAP_MB); | 4157 | val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB); |
4146 | if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE) | 4158 | if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE) |
4147 | return; | 4159 | return; |
4148 | 4160 | ||
4149 | if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) { | 4161 | if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) { |
4150 | bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP; | 4162 | bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP; |
4151 | 4163 | ||
4152 | val = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS); | 4164 | val = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); |
4153 | if (val & BNX2_LINK_STATUS_SERDES_LINK) | 4165 | if (val & BNX2_LINK_STATUS_SERDES_LINK) |
4154 | bp->phy_port = PORT_FIBRE; | 4166 | bp->phy_port = PORT_FIBRE; |
4155 | else | 4167 | else |
@@ -4167,8 +4179,7 @@ bnx2_init_remote_phy(struct bnx2 *bp) | |||
4167 | } | 4179 | } |
4168 | sig = BNX2_DRV_ACK_CAP_SIGNATURE | | 4180 | sig = BNX2_DRV_ACK_CAP_SIGNATURE | |
4169 | BNX2_FW_CAP_REMOTE_PHY_CAPABLE; | 4181 | BNX2_FW_CAP_REMOTE_PHY_CAPABLE; |
4170 | REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_ACK_CAP_MB, | 4182 | bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig); |
4171 | sig); | ||
4172 | } | 4183 | } |
4173 | } | 4184 | } |
4174 | } | 4185 | } |
@@ -4204,8 +4215,8 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) | |||
4204 | 4215 | ||
4205 | /* Deposit a driver reset signature so the firmware knows that | 4216 | /* Deposit a driver reset signature so the firmware knows that |
4206 | * this is a soft reset. */ | 4217 | * this is a soft reset. */ |
4207 | REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE, | 4218 | bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE, |
4208 | BNX2_DRV_RESET_SIGNATURE_MAGIC); | 4219 | BNX2_DRV_RESET_SIGNATURE_MAGIC); |
4209 | 4220 | ||
4210 | /* Do a dummy read to force the chip to complete all current transaction | 4221 | /* Do a dummy read to force the chip to complete all current transaction |
4211 | * before we issue a reset. */ | 4222 | * before we issue a reset. */ |
@@ -5006,9 +5017,9 @@ bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size) | |||
5006 | 5017 | ||
5007 | for (offset = 0; offset < size; offset += 4) { | 5018 | for (offset = 0; offset < size; offset += 4) { |
5008 | 5019 | ||
5009 | REG_WR_IND(bp, start + offset, test_pattern[i]); | 5020 | bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]); |
5010 | 5021 | ||
5011 | if (REG_RD_IND(bp, start + offset) != | 5022 | if (bnx2_reg_rd_ind(bp, start + offset) != |
5012 | test_pattern[i]) { | 5023 | test_pattern[i]) { |
5013 | return -ENODEV; | 5024 | return -ENODEV; |
5014 | } | 5025 | } |
@@ -5443,7 +5454,8 @@ bnx2_timer(unsigned long data) | |||
5443 | 5454 | ||
5444 | bnx2_send_heart_beat(bp); | 5455 | bnx2_send_heart_beat(bp); |
5445 | 5456 | ||
5446 | bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT); | 5457 | bp->stats_blk->stat_FwRxDrop = |
5458 | bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT); | ||
5447 | 5459 | ||
5448 | /* workaround occasional corrupted counters */ | 5460 | /* workaround occasional corrupted counters */ |
5449 | if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks) | 5461 | if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks) |
@@ -7158,20 +7170,20 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) | |||
7158 | 7170 | ||
7159 | bnx2_init_nvram(bp); | 7171 | bnx2_init_nvram(bp); |
7160 | 7172 | ||
7161 | reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE); | 7173 | reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE); |
7162 | 7174 | ||
7163 | if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) == | 7175 | if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) == |
7164 | BNX2_SHM_HDR_SIGNATURE_SIG) { | 7176 | BNX2_SHM_HDR_SIGNATURE_SIG) { |
7165 | u32 off = PCI_FUNC(pdev->devfn) << 2; | 7177 | u32 off = PCI_FUNC(pdev->devfn) << 2; |
7166 | 7178 | ||
7167 | bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0 + off); | 7179 | bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off); |
7168 | } else | 7180 | } else |
7169 | bp->shmem_base = HOST_VIEW_SHMEM_BASE; | 7181 | bp->shmem_base = HOST_VIEW_SHMEM_BASE; |
7170 | 7182 | ||
7171 | /* Get the permanent MAC address. First we need to make sure the | 7183 | /* Get the permanent MAC address. First we need to make sure the |
7172 | * firmware is actually running. | 7184 | * firmware is actually running. |
7173 | */ | 7185 | */ |
7174 | reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE); | 7186 | reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE); |
7175 | 7187 | ||
7176 | if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) != | 7188 | if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) != |
7177 | BNX2_DEV_INFO_SIGNATURE_MAGIC) { | 7189 | BNX2_DEV_INFO_SIGNATURE_MAGIC) { |
@@ -7180,7 +7192,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) | |||
7180 | goto err_out_unmap; | 7192 | goto err_out_unmap; |
7181 | } | 7193 | } |
7182 | 7194 | ||
7183 | reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV); | 7195 | reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV); |
7184 | for (i = 0, j = 0; i < 3; i++) { | 7196 | for (i = 0, j = 0; i < 3; i++) { |
7185 | u8 num, k, skip0; | 7197 | u8 num, k, skip0; |
7186 | 7198 | ||
@@ -7194,7 +7206,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) | |||
7194 | if (i != 2) | 7206 | if (i != 2) |
7195 | bp->fw_version[j++] = '.'; | 7207 | bp->fw_version[j++] = '.'; |
7196 | } | 7208 | } |
7197 | reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE); | 7209 | reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE); |
7198 | if (reg & BNX2_PORT_FEATURE_WOL_ENABLED) | 7210 | if (reg & BNX2_PORT_FEATURE_WOL_ENABLED) |
7199 | bp->wol = 1; | 7211 | bp->wol = 1; |
7200 | 7212 | ||
@@ -7202,34 +7214,33 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) | |||
7202 | bp->flags |= BNX2_FLAG_ASF_ENABLE; | 7214 | bp->flags |= BNX2_FLAG_ASF_ENABLE; |
7203 | 7215 | ||
7204 | for (i = 0; i < 30; i++) { | 7216 | for (i = 0; i < 30; i++) { |
7205 | reg = REG_RD_IND(bp, bp->shmem_base + | 7217 | reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); |
7206 | BNX2_BC_STATE_CONDITION); | ||
7207 | if (reg & BNX2_CONDITION_MFW_RUN_MASK) | 7218 | if (reg & BNX2_CONDITION_MFW_RUN_MASK) |
7208 | break; | 7219 | break; |
7209 | msleep(10); | 7220 | msleep(10); |
7210 | } | 7221 | } |
7211 | } | 7222 | } |
7212 | reg = REG_RD_IND(bp, bp->shmem_base + BNX2_BC_STATE_CONDITION); | 7223 | reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); |
7213 | reg &= BNX2_CONDITION_MFW_RUN_MASK; | 7224 | reg &= BNX2_CONDITION_MFW_RUN_MASK; |
7214 | if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN && | 7225 | if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN && |
7215 | reg != BNX2_CONDITION_MFW_RUN_NONE) { | 7226 | reg != BNX2_CONDITION_MFW_RUN_NONE) { |
7216 | int i; | 7227 | int i; |
7217 | u32 addr = REG_RD_IND(bp, bp->shmem_base + BNX2_MFW_VER_PTR); | 7228 | u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR); |
7218 | 7229 | ||
7219 | bp->fw_version[j++] = ' '; | 7230 | bp->fw_version[j++] = ' '; |
7220 | for (i = 0; i < 3; i++) { | 7231 | for (i = 0; i < 3; i++) { |
7221 | reg = REG_RD_IND(bp, addr + i * 4); | 7232 | reg = bnx2_reg_rd_ind(bp, addr + i * 4); |
7222 | reg = swab32(reg); | 7233 | reg = swab32(reg); |
7223 | memcpy(&bp->fw_version[j], ®, 4); | 7234 | memcpy(&bp->fw_version[j], ®, 4); |
7224 | j += 4; | 7235 | j += 4; |
7225 | } | 7236 | } |
7226 | } | 7237 | } |
7227 | 7238 | ||
7228 | reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER); | 7239 | reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER); |
7229 | bp->mac_addr[0] = (u8) (reg >> 8); | 7240 | bp->mac_addr[0] = (u8) (reg >> 8); |
7230 | bp->mac_addr[1] = (u8) reg; | 7241 | bp->mac_addr[1] = (u8) reg; |
7231 | 7242 | ||
7232 | reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER); | 7243 | reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER); |
7233 | bp->mac_addr[2] = (u8) (reg >> 24); | 7244 | bp->mac_addr[2] = (u8) (reg >> 24); |
7234 | bp->mac_addr[3] = (u8) (reg >> 16); | 7245 | bp->mac_addr[3] = (u8) (reg >> 16); |
7235 | bp->mac_addr[4] = (u8) (reg >> 8); | 7246 | bp->mac_addr[4] = (u8) (reg >> 8); |
@@ -7268,8 +7279,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) | |||
7268 | bp->phy_port = PORT_TP; | 7279 | bp->phy_port = PORT_TP; |
7269 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { | 7280 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
7270 | bp->phy_port = PORT_FIBRE; | 7281 | bp->phy_port = PORT_FIBRE; |
7271 | reg = REG_RD_IND(bp, bp->shmem_base + | 7282 | reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); |
7272 | BNX2_SHARED_HW_CFG_CONFIG); | ||
7273 | if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) { | 7283 | if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) { |
7274 | bp->flags |= BNX2_FLAG_NO_WOL; | 7284 | bp->flags |= BNX2_FLAG_NO_WOL; |
7275 | bp->wol = 0; | 7285 | bp->wol = 0; |