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Diffstat (limited to 'drivers/net/bnx2.c')
-rw-r--r--drivers/net/bnx2.c75
1 files changed, 45 insertions, 30 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index a1a3d0e5d2b4..0e2218dadb3d 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -57,8 +57,8 @@
57 57
58#define DRV_MODULE_NAME "bnx2" 58#define DRV_MODULE_NAME "bnx2"
59#define PFX DRV_MODULE_NAME ": " 59#define PFX DRV_MODULE_NAME ": "
60#define DRV_MODULE_VERSION "1.8.1" 60#define DRV_MODULE_VERSION "1.8.2"
61#define DRV_MODULE_RELDATE "Oct 7, 2008" 61#define DRV_MODULE_RELDATE "Nov 10, 2008"
62 62
63#define RUN_AT(x) (jiffies + (x)) 63#define RUN_AT(x) (jiffies + (x))
64 64
@@ -89,6 +89,7 @@ typedef enum {
89 BCM5709, 89 BCM5709,
90 BCM5709S, 90 BCM5709S,
91 BCM5716, 91 BCM5716,
92 BCM5716S,
92} board_t; 93} board_t;
93 94
94/* indexed by board_t, above */ 95/* indexed by board_t, above */
@@ -105,6 +106,7 @@ static struct {
105 { "Broadcom NetXtreme II BCM5709 1000Base-T" }, 106 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
106 { "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 107 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
107 { "Broadcom NetXtreme II BCM5716 1000Base-T" }, 108 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
109 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
108 }; 110 };
109 111
110static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = { 112static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
@@ -128,6 +130,8 @@ static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S }, 130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
129 { PCI_VENDOR_ID_BROADCOM, 0x163b, 131 { PCI_VENDOR_ID_BROADCOM, 0x163b,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 }, 132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
133 { PCI_VENDOR_ID_BROADCOM, 0x163c,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
131 { 0, } 135 { 0, }
132}; 136};
133 137
@@ -1652,7 +1656,7 @@ bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1652 * exchanging base pages plus 3 next pages and 1656 * exchanging base pages plus 3 next pages and
1653 * normally completes in about 120 msec. 1657 * normally completes in about 120 msec.
1654 */ 1658 */
1655 bp->current_interval = SERDES_AN_TIMEOUT; 1659 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1656 bp->serdes_an_pending = 1; 1660 bp->serdes_an_pending = 1;
1657 mod_timer(&bp->timer, jiffies + bp->current_interval); 1661 mod_timer(&bp->timer, jiffies + bp->current_interval);
1658 } else { 1662 } else {
@@ -2274,7 +2278,7 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2274 return 0; 2278 return 0;
2275 2279
2276 /* wait for an acknowledgement. */ 2280 /* wait for an acknowledgement. */
2277 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) { 2281 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2278 msleep(10); 2282 msleep(10);
2279 2283
2280 val = bnx2_shmem_rd(bp, BNX2_FW_MB); 2284 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
@@ -3000,7 +3004,6 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3000#endif 3004#endif
3001 netif_receive_skb(skb); 3005 netif_receive_skb(skb);
3002 3006
3003 bp->dev->last_rx = jiffies;
3004 rx_pkt++; 3007 rx_pkt++;
3005 3008
3006next_rx: 3009next_rx:
@@ -4493,7 +4496,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4493static int 4496static int
4494bnx2_init_chip(struct bnx2 *bp) 4497bnx2_init_chip(struct bnx2 *bp)
4495{ 4498{
4496 u32 val; 4499 u32 val, mtu;
4497 int rc, i; 4500 int rc, i;
4498 4501
4499 /* Make sure the interrupt is not active. */ 4502 /* Make sure the interrupt is not active. */
@@ -4585,11 +4588,19 @@ bnx2_init_chip(struct bnx2 *bp)
4585 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); 4588 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4586 4589
4587 /* Program the MTU. Also include 4 bytes for CRC32. */ 4590 /* Program the MTU. Also include 4 bytes for CRC32. */
4588 val = bp->dev->mtu + ETH_HLEN + 4; 4591 mtu = bp->dev->mtu;
4592 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4589 if (val > (MAX_ETHERNET_PACKET_SIZE + 4)) 4593 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4590 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; 4594 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4591 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); 4595 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4592 4596
4597 if (mtu < 1500)
4598 mtu = 1500;
4599
4600 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4601 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4602 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4603
4593 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) 4604 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4594 bp->bnx2_napi[i].last_status_idx = 0; 4605 bp->bnx2_napi[i].last_status_idx = 0;
4595 4606
@@ -5719,7 +5730,7 @@ bnx2_5708_serdes_timer(struct bnx2 *bp)
5719 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 5730 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5720 if (bmcr & BMCR_ANENABLE) { 5731 if (bmcr & BMCR_ANENABLE) {
5721 bnx2_enable_forced_2g5(bp); 5732 bnx2_enable_forced_2g5(bp);
5722 bp->current_interval = SERDES_FORCED_TIMEOUT; 5733 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
5723 } else { 5734 } else {
5724 bnx2_disable_forced_2g5(bp); 5735 bnx2_disable_forced_2g5(bp);
5725 bp->serdes_an_pending = 2; 5736 bp->serdes_an_pending = 2;
@@ -6173,7 +6184,7 @@ bnx2_get_stats(struct net_device *dev)
6173{ 6184{
6174 struct bnx2 *bp = netdev_priv(dev); 6185 struct bnx2 *bp = netdev_priv(dev);
6175 struct statistics_block *stats_blk = bp->stats_blk; 6186 struct statistics_block *stats_blk = bp->stats_blk;
6176 struct net_device_stats *net_stats = &bp->net_stats; 6187 struct net_device_stats *net_stats = &dev->stats;
6177 6188
6178 if (bp->stats_blk == NULL) { 6189 if (bp->stats_blk == NULL) {
6179 return net_stats; 6190 return net_stats;
@@ -6540,7 +6551,7 @@ bnx2_nway_reset(struct net_device *dev)
6540 6551
6541 spin_lock_bh(&bp->phy_lock); 6552 spin_lock_bh(&bp->phy_lock);
6542 6553
6543 bp->current_interval = SERDES_AN_TIMEOUT; 6554 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6544 bp->serdes_an_pending = 1; 6555 bp->serdes_an_pending = 1;
6545 mod_timer(&bp->timer, jiffies + bp->current_interval); 6556 mod_timer(&bp->timer, jiffies + bp->current_interval);
6546 } 6557 }
@@ -7615,7 +7626,8 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7615 7626
7616 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || 7627 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7617 (CHIP_ID(bp) == CHIP_ID_5708_B0) || 7628 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7618 (CHIP_ID(bp) == CHIP_ID_5708_B1)) { 7629 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
7630 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
7619 bp->flags |= BNX2_FLAG_NO_WOL; 7631 bp->flags |= BNX2_FLAG_NO_WOL;
7620 bp->wol = 0; 7632 bp->wol = 0;
7621 } 7633 }
@@ -7724,6 +7736,25 @@ bnx2_init_napi(struct bnx2 *bp)
7724 } 7736 }
7725} 7737}
7726 7738
7739static const struct net_device_ops bnx2_netdev_ops = {
7740 .ndo_open = bnx2_open,
7741 .ndo_start_xmit = bnx2_start_xmit,
7742 .ndo_stop = bnx2_close,
7743 .ndo_get_stats = bnx2_get_stats,
7744 .ndo_set_rx_mode = bnx2_set_rx_mode,
7745 .ndo_do_ioctl = bnx2_ioctl,
7746 .ndo_validate_addr = eth_validate_addr,
7747 .ndo_set_mac_address = bnx2_change_mac_addr,
7748 .ndo_change_mtu = bnx2_change_mtu,
7749 .ndo_tx_timeout = bnx2_tx_timeout,
7750#ifdef BCM_VLAN
7751 .ndo_vlan_rx_register = bnx2_vlan_rx_register,
7752#endif
7753#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7754 .ndo_poll_controller = poll_bnx2,
7755#endif
7756};
7757
7727static int __devinit 7758static int __devinit
7728bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 7759bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7729{ 7760{
@@ -7732,7 +7763,6 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7732 struct bnx2 *bp; 7763 struct bnx2 *bp;
7733 int rc; 7764 int rc;
7734 char str[40]; 7765 char str[40];
7735 DECLARE_MAC_BUF(mac);
7736 7766
7737 if (version_printed++ == 0) 7767 if (version_printed++ == 0)
7738 printk(KERN_INFO "%s", version); 7768 printk(KERN_INFO "%s", version);
@@ -7749,28 +7779,13 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7749 return rc; 7779 return rc;
7750 } 7780 }
7751 7781
7752 dev->open = bnx2_open; 7782 dev->netdev_ops = &bnx2_netdev_ops;
7753 dev->hard_start_xmit = bnx2_start_xmit;
7754 dev->stop = bnx2_close;
7755 dev->get_stats = bnx2_get_stats;
7756 dev->set_rx_mode = bnx2_set_rx_mode;
7757 dev->do_ioctl = bnx2_ioctl;
7758 dev->set_mac_address = bnx2_change_mac_addr;
7759 dev->change_mtu = bnx2_change_mtu;
7760 dev->tx_timeout = bnx2_tx_timeout;
7761 dev->watchdog_timeo = TX_TIMEOUT; 7783 dev->watchdog_timeo = TX_TIMEOUT;
7762#ifdef BCM_VLAN
7763 dev->vlan_rx_register = bnx2_vlan_rx_register;
7764#endif
7765 dev->ethtool_ops = &bnx2_ethtool_ops; 7784 dev->ethtool_ops = &bnx2_ethtool_ops;
7766 7785
7767 bp = netdev_priv(dev); 7786 bp = netdev_priv(dev);
7768 bnx2_init_napi(bp); 7787 bnx2_init_napi(bp);
7769 7788
7770#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7771 dev->poll_controller = poll_bnx2;
7772#endif
7773
7774 pci_set_drvdata(pdev, dev); 7789 pci_set_drvdata(pdev, dev);
7775 7790
7776 memcpy(dev->dev_addr, bp->mac_addr, 6); 7791 memcpy(dev->dev_addr, bp->mac_addr, 6);
@@ -7799,14 +7814,14 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7799 } 7814 }
7800 7815
7801 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, " 7816 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
7802 "IRQ %d, node addr %s\n", 7817 "IRQ %d, node addr %pM\n",
7803 dev->name, 7818 dev->name,
7804 board_info[ent->driver_data].name, 7819 board_info[ent->driver_data].name,
7805 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A', 7820 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7806 ((CHIP_ID(bp) & 0x0ff0) >> 4), 7821 ((CHIP_ID(bp) & 0x0ff0) >> 4),
7807 bnx2_bus_string(bp, str), 7822 bnx2_bus_string(bp, str),
7808 dev->base_addr, 7823 dev->base_addr,
7809 bp->pdev->irq, print_mac(mac, dev->dev_addr)); 7824 bp->pdev->irq, dev->dev_addr);
7810 7825
7811 return 0; 7826 return 0;
7812} 7827}