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Diffstat (limited to 'drivers/net/bnx2.c')
-rw-r--r--drivers/net/bnx2.c308
1 files changed, 199 insertions, 109 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 49fa1e4413fa..a24200d0a616 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -1,6 +1,6 @@
1/* bnx2.c: Broadcom NX2 network driver. 1/* bnx2.c: Broadcom NX2 network driver.
2 * 2 *
3 * Copyright (c) 2004, 2005 Broadcom Corporation 3 * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by 6 * it under the terms of the GNU General Public License as published by
@@ -14,8 +14,8 @@
14 14
15#define DRV_MODULE_NAME "bnx2" 15#define DRV_MODULE_NAME "bnx2"
16#define PFX DRV_MODULE_NAME ": " 16#define PFX DRV_MODULE_NAME ": "
17#define DRV_MODULE_VERSION "1.4.30" 17#define DRV_MODULE_VERSION "1.4.31"
18#define DRV_MODULE_RELDATE "October 11, 2005" 18#define DRV_MODULE_RELDATE "January 19, 2006"
19 19
20#define RUN_AT(x) (jiffies + (x)) 20#define RUN_AT(x) (jiffies + (x))
21 21
@@ -316,6 +316,10 @@ bnx2_enable_int(struct bnx2 *bp)
316 u32 val; 316 u32 val;
317 317
318 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 318 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
319 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
320 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
321
322 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
319 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx); 323 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
320 324
321 val = REG_RD(bp, BNX2_HC_COMMAND); 325 val = REG_RD(bp, BNX2_HC_COMMAND);
@@ -1171,7 +1175,8 @@ bnx2_init_5708s_phy(struct bnx2 *bp)
1171 } 1175 }
1172 1176
1173 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || 1177 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1174 (CHIP_ID(bp) == CHIP_ID_5708_B0)) { 1178 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1179 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1175 /* increase tx signal amplitude */ 1180 /* increase tx signal amplitude */
1176 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, 1181 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1177 BCM5708S_BLK_ADDR_TX_MISC); 1182 BCM5708S_BLK_ADDR_TX_MISC);
@@ -1326,44 +1331,78 @@ bnx2_set_mac_loopback(struct bnx2 *bp)
1326 return 0; 1331 return 0;
1327} 1332}
1328 1333
1334static int bnx2_test_link(struct bnx2 *);
1335
1336static int
1337bnx2_set_phy_loopback(struct bnx2 *bp)
1338{
1339 u32 mac_mode;
1340 int rc, i;
1341
1342 spin_lock_bh(&bp->phy_lock);
1343 rc = bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
1344 BMCR_SPEED1000);
1345 spin_unlock_bh(&bp->phy_lock);
1346 if (rc)
1347 return rc;
1348
1349 for (i = 0; i < 10; i++) {
1350 if (bnx2_test_link(bp) == 0)
1351 break;
1352 udelay(10);
1353 }
1354
1355 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1356 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1357 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1358 BNX2_EMAC_MODE_25G);
1359
1360 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
1361 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1362 bp->link_up = 1;
1363 return 0;
1364}
1365
1329static int 1366static int
1330bnx2_fw_sync(struct bnx2 *bp, u32 msg_data) 1367bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1331{ 1368{
1332 int i; 1369 int i;
1333 u32 val; 1370 u32 val;
1334 1371
1335 if (bp->fw_timed_out)
1336 return -EBUSY;
1337
1338 bp->fw_wr_seq++; 1372 bp->fw_wr_seq++;
1339 msg_data |= bp->fw_wr_seq; 1373 msg_data |= bp->fw_wr_seq;
1340 1374
1341 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data); 1375 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1342 1376
1343 /* wait for an acknowledgement. */ 1377 /* wait for an acknowledgement. */
1344 for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) { 1378 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
1345 udelay(5); 1379 msleep(10);
1346 1380
1347 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB); 1381 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1348 1382
1349 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ)) 1383 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1350 break; 1384 break;
1351 } 1385 }
1386 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1387 return 0;
1352 1388
1353 /* If we timed out, inform the firmware that this is the case. */ 1389 /* If we timed out, inform the firmware that this is the case. */
1354 if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) && 1390 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1355 ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) { 1391 if (!silent)
1392 printk(KERN_ERR PFX "fw sync timeout, reset code = "
1393 "%x\n", msg_data);
1356 1394
1357 msg_data &= ~BNX2_DRV_MSG_CODE; 1395 msg_data &= ~BNX2_DRV_MSG_CODE;
1358 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT; 1396 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1359 1397
1360 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data); 1398 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1361 1399
1362 bp->fw_timed_out = 1;
1363
1364 return -EBUSY; 1400 return -EBUSY;
1365 } 1401 }
1366 1402
1403 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1404 return -EIO;
1405
1367 return 0; 1406 return 0;
1368} 1407}
1369 1408
@@ -1657,7 +1696,7 @@ bnx2_rx_int(struct bnx2 *bp, int budget)
1657 rmb(); 1696 rmb();
1658 while (sw_cons != hw_cons) { 1697 while (sw_cons != hw_cons) {
1659 unsigned int len; 1698 unsigned int len;
1660 u16 status; 1699 u32 status;
1661 struct sw_bd *rx_buf; 1700 struct sw_bd *rx_buf;
1662 struct sk_buff *skb; 1701 struct sk_buff *skb;
1663 1702
@@ -1673,7 +1712,7 @@ bnx2_rx_int(struct bnx2 *bp, int budget)
1673 rx_hdr = (struct l2_fhdr *) skb->data; 1712 rx_hdr = (struct l2_fhdr *) skb->data;
1674 len = rx_hdr->l2_fhdr_pkt_len - 4; 1713 len = rx_hdr->l2_fhdr_pkt_len - 4;
1675 1714
1676 if (rx_hdr->l2_fhdr_errors & 1715 if ((status = rx_hdr->l2_fhdr_status) &
1677 (L2_FHDR_ERRORS_BAD_CRC | 1716 (L2_FHDR_ERRORS_BAD_CRC |
1678 L2_FHDR_ERRORS_PHY_DECODE | 1717 L2_FHDR_ERRORS_PHY_DECODE |
1679 L2_FHDR_ERRORS_ALIGNMENT | 1718 L2_FHDR_ERRORS_ALIGNMENT |
@@ -1732,15 +1771,13 @@ reuse_rx:
1732 1771
1733 } 1772 }
1734 1773
1735 status = rx_hdr->l2_fhdr_status;
1736 skb->ip_summed = CHECKSUM_NONE; 1774 skb->ip_summed = CHECKSUM_NONE;
1737 if (bp->rx_csum && 1775 if (bp->rx_csum &&
1738 (status & (L2_FHDR_STATUS_TCP_SEGMENT | 1776 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1739 L2_FHDR_STATUS_UDP_DATAGRAM))) { 1777 L2_FHDR_STATUS_UDP_DATAGRAM))) {
1740 1778
1741 u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum; 1779 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
1742 1780 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
1743 if (cksum == 0xffff)
1744 skb->ip_summed = CHECKSUM_UNNECESSARY; 1781 skb->ip_summed = CHECKSUM_UNNECESSARY;
1745 } 1782 }
1746 1783
@@ -1794,7 +1831,7 @@ static irqreturn_t
1794bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs) 1831bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1795{ 1832{
1796 struct net_device *dev = dev_instance; 1833 struct net_device *dev = dev_instance;
1797 struct bnx2 *bp = dev->priv; 1834 struct bnx2 *bp = netdev_priv(dev);
1798 1835
1799 prefetch(bp->status_blk); 1836 prefetch(bp->status_blk);
1800 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 1837 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
@@ -1814,7 +1851,7 @@ static irqreturn_t
1814bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs) 1851bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1815{ 1852{
1816 struct net_device *dev = dev_instance; 1853 struct net_device *dev = dev_instance;
1817 struct bnx2 *bp = dev->priv; 1854 struct bnx2 *bp = netdev_priv(dev);
1818 1855
1819 /* When using INTx, it is possible for the interrupt to arrive 1856 /* When using INTx, it is possible for the interrupt to arrive
1820 * at the CPU before the status block posted prior to the 1857 * at the CPU before the status block posted prior to the
@@ -1859,7 +1896,7 @@ bnx2_has_work(struct bnx2 *bp)
1859static int 1896static int
1860bnx2_poll(struct net_device *dev, int *budget) 1897bnx2_poll(struct net_device *dev, int *budget)
1861{ 1898{
1862 struct bnx2 *bp = dev->priv; 1899 struct bnx2 *bp = netdev_priv(dev);
1863 1900
1864 if ((bp->status_blk->status_attn_bits & 1901 if ((bp->status_blk->status_attn_bits &
1865 STATUS_ATTN_BITS_LINK_STATE) != 1902 STATUS_ATTN_BITS_LINK_STATE) !=
@@ -1891,9 +1928,20 @@ bnx2_poll(struct net_device *dev, int *budget)
1891 1928
1892 if (!bnx2_has_work(bp)) { 1929 if (!bnx2_has_work(bp)) {
1893 netif_rx_complete(dev); 1930 netif_rx_complete(dev);
1931 if (likely(bp->flags & USING_MSI_FLAG)) {
1932 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1933 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1934 bp->last_status_idx);
1935 return 0;
1936 }
1937 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1938 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1939 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
1940 bp->last_status_idx);
1941
1894 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 1942 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1895 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 1943 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1896 bp->last_status_idx); 1944 bp->last_status_idx);
1897 return 0; 1945 return 0;
1898 } 1946 }
1899 1947
@@ -1906,7 +1954,7 @@ bnx2_poll(struct net_device *dev, int *budget)
1906static void 1954static void
1907bnx2_set_rx_mode(struct net_device *dev) 1955bnx2_set_rx_mode(struct net_device *dev)
1908{ 1956{
1909 struct bnx2 *bp = dev->priv; 1957 struct bnx2 *bp = netdev_priv(dev);
1910 u32 rx_mode, sort_mode; 1958 u32 rx_mode, sort_mode;
1911 int i; 1959 int i;
1912 1960
@@ -1916,11 +1964,11 @@ bnx2_set_rx_mode(struct net_device *dev)
1916 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG); 1964 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1917 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN; 1965 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1918#ifdef BCM_VLAN 1966#ifdef BCM_VLAN
1919 if (!bp->vlgrp) { 1967 if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
1920 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; 1968 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1921 }
1922#else 1969#else
1923 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; 1970 if (!(bp->flags & ASF_ENABLE_FLAG))
1971 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1924#endif 1972#endif
1925 if (dev->flags & IFF_PROMISC) { 1973 if (dev->flags & IFF_PROMISC) {
1926 /* Promiscuous mode. */ 1974 /* Promiscuous mode. */
@@ -2338,7 +2386,6 @@ bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
2338 val |= BNX2_EMAC_MODE_PORT_MII | 2386 val |= BNX2_EMAC_MODE_PORT_MII |
2339 BNX2_EMAC_MODE_MPKT_RCVD | 2387 BNX2_EMAC_MODE_MPKT_RCVD |
2340 BNX2_EMAC_MODE_ACPI_RCVD | 2388 BNX2_EMAC_MODE_ACPI_RCVD |
2341 BNX2_EMAC_MODE_FORCE_LINK |
2342 BNX2_EMAC_MODE_MPKT; 2389 BNX2_EMAC_MODE_MPKT;
2343 2390
2344 REG_WR(bp, BNX2_EMAC_MODE, val); 2391 REG_WR(bp, BNX2_EMAC_MODE, val);
@@ -2374,7 +2421,8 @@ bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
2374 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; 2421 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2375 } 2422 }
2376 2423
2377 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg); 2424 if (!(bp->flags & NO_WOL_FLAG))
2425 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
2378 2426
2379 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 2427 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2380 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || 2428 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
@@ -2708,9 +2756,16 @@ bnx2_init_nvram(struct bnx2 *bp)
2708 if (j == entry_count) { 2756 if (j == entry_count) {
2709 bp->flash_info = NULL; 2757 bp->flash_info = NULL;
2710 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n"); 2758 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
2711 rc = -ENODEV; 2759 return -ENODEV;
2712 } 2760 }
2713 2761
2762 val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
2763 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
2764 if (val)
2765 bp->flash_size = val;
2766 else
2767 bp->flash_size = bp->flash_info->total_size;
2768
2714 return rc; 2769 return rc;
2715} 2770}
2716 2771
@@ -3014,16 +3069,14 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3014 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS); 3069 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3015 udelay(5); 3070 udelay(5);
3016 3071
3072 /* Wait for the firmware to tell us it is ok to issue a reset. */
3073 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3074
3017 /* Deposit a driver reset signature so the firmware knows that 3075 /* Deposit a driver reset signature so the firmware knows that
3018 * this is a soft reset. */ 3076 * this is a soft reset. */
3019 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE, 3077 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3020 BNX2_DRV_RESET_SIGNATURE_MAGIC); 3078 BNX2_DRV_RESET_SIGNATURE_MAGIC);
3021 3079
3022 bp->fw_timed_out = 0;
3023
3024 /* Wait for the firmware to tell us it is ok to issue a reset. */
3025 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code);
3026
3027 /* Do a dummy read to force the chip to complete all current transaction 3080 /* Do a dummy read to force the chip to complete all current transaction
3028 * before we issue a reset. */ 3081 * before we issue a reset. */
3029 val = REG_RD(bp, BNX2_MISC_ID); 3082 val = REG_RD(bp, BNX2_MISC_ID);
@@ -3062,10 +3115,10 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3062 return -ENODEV; 3115 return -ENODEV;
3063 } 3116 }
3064 3117
3065 bp->fw_timed_out = 0;
3066
3067 /* Wait for the firmware to finish its initialization. */ 3118 /* Wait for the firmware to finish its initialization. */
3068 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code); 3119 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3120 if (rc)
3121 return rc;
3069 3122
3070 if (CHIP_ID(bp) == CHIP_ID_5706_A0) { 3123 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3071 /* Adjust the voltage regular to two steps lower. The default 3124 /* Adjust the voltage regular to two steps lower. The default
@@ -3083,6 +3136,7 @@ static int
3083bnx2_init_chip(struct bnx2 *bp) 3136bnx2_init_chip(struct bnx2 *bp)
3084{ 3137{
3085 u32 val; 3138 u32 val;
3139 int rc;
3086 3140
3087 /* Make sure the interrupt is not active. */ 3141 /* Make sure the interrupt is not active. */
3088 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT); 3142 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
@@ -3098,7 +3152,7 @@ bnx2_init_chip(struct bnx2 *bp)
3098 3152
3099 val |= (0x2 << 20) | (1 << 11); 3153 val |= (0x2 << 20) | (1 << 11);
3100 3154
3101 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133)) 3155 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
3102 val |= (1 << 23); 3156 val |= (1 << 23);
3103 3157
3104 if ((CHIP_NUM(bp) == CHIP_NUM_5706) && 3158 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
@@ -3218,17 +3272,22 @@ bnx2_init_chip(struct bnx2 *bp)
3218 3272
3219 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3273 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3220 3274
3275 if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
3276 BNX2_PORT_FEATURE_ASF_ENABLED)
3277 bp->flags |= ASF_ENABLE_FLAG;
3278
3221 /* Initialize the receive filter. */ 3279 /* Initialize the receive filter. */
3222 bnx2_set_rx_mode(bp->dev); 3280 bnx2_set_rx_mode(bp->dev);
3223 3281
3224 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET); 3282 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
3283 0);
3225 3284
3226 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff); 3285 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
3227 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS); 3286 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
3228 3287
3229 udelay(20); 3288 udelay(20);
3230 3289
3231 return 0; 3290 return rc;
3232} 3291}
3233 3292
3234 3293
@@ -3880,26 +3939,33 @@ bnx2_test_memory(struct bnx2 *bp)
3880 return ret; 3939 return ret;
3881} 3940}
3882 3941
3942#define BNX2_MAC_LOOPBACK 0
3943#define BNX2_PHY_LOOPBACK 1
3944
3883static int 3945static int
3884bnx2_test_loopback(struct bnx2 *bp) 3946bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
3885{ 3947{
3886 unsigned int pkt_size, num_pkts, i; 3948 unsigned int pkt_size, num_pkts, i;
3887 struct sk_buff *skb, *rx_skb; 3949 struct sk_buff *skb, *rx_skb;
3888 unsigned char *packet; 3950 unsigned char *packet;
3889 u16 rx_start_idx, rx_idx, send_idx; 3951 u16 rx_start_idx, rx_idx;
3890 u32 send_bseq, val; 3952 u32 val;
3891 dma_addr_t map; 3953 dma_addr_t map;
3892 struct tx_bd *txbd; 3954 struct tx_bd *txbd;
3893 struct sw_bd *rx_buf; 3955 struct sw_bd *rx_buf;
3894 struct l2_fhdr *rx_hdr; 3956 struct l2_fhdr *rx_hdr;
3895 int ret = -ENODEV; 3957 int ret = -ENODEV;
3896 3958
3897 if (!netif_running(bp->dev)) 3959 if (loopback_mode == BNX2_MAC_LOOPBACK) {
3898 return -ENODEV; 3960 bp->loopback = MAC_LOOPBACK;
3899 3961 bnx2_set_mac_loopback(bp);
3900 bp->loopback = MAC_LOOPBACK; 3962 }
3901 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG); 3963 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
3902 bnx2_set_mac_loopback(bp); 3964 bp->loopback = 0;
3965 bnx2_set_phy_loopback(bp);
3966 }
3967 else
3968 return -EINVAL;
3903 3969
3904 pkt_size = 1514; 3970 pkt_size = 1514;
3905 skb = dev_alloc_skb(pkt_size); 3971 skb = dev_alloc_skb(pkt_size);
@@ -3921,11 +3987,9 @@ bnx2_test_loopback(struct bnx2 *bp)
3921 udelay(5); 3987 udelay(5);
3922 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0; 3988 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3923 3989
3924 send_idx = 0;
3925 send_bseq = 0;
3926 num_pkts = 0; 3990 num_pkts = 0;
3927 3991
3928 txbd = &bp->tx_desc_ring[send_idx]; 3992 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
3929 3993
3930 txbd->tx_bd_haddr_hi = (u64) map >> 32; 3994 txbd->tx_bd_haddr_hi = (u64) map >> 32;
3931 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; 3995 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
@@ -3933,13 +3997,11 @@ bnx2_test_loopback(struct bnx2 *bp)
3933 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END; 3997 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3934 3998
3935 num_pkts++; 3999 num_pkts++;
3936 send_idx = NEXT_TX_BD(send_idx); 4000 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
3937 4001 bp->tx_prod_bseq += pkt_size;
3938 send_bseq += pkt_size;
3939
3940 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3941 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3942 4002
4003 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, bp->tx_prod);
4004 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
3943 4005
3944 udelay(100); 4006 udelay(100);
3945 4007
@@ -3952,7 +4014,7 @@ bnx2_test_loopback(struct bnx2 *bp)
3952 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE); 4014 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3953 dev_kfree_skb_irq(skb); 4015 dev_kfree_skb_irq(skb);
3954 4016
3955 if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) { 4017 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_prod) {
3956 goto loopback_test_done; 4018 goto loopback_test_done;
3957 } 4019 }
3958 4020
@@ -3971,7 +4033,7 @@ bnx2_test_loopback(struct bnx2 *bp)
3971 pci_unmap_addr(rx_buf, mapping), 4033 pci_unmap_addr(rx_buf, mapping),
3972 bp->rx_buf_size, PCI_DMA_FROMDEVICE); 4034 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3973 4035
3974 if (rx_hdr->l2_fhdr_errors & 4036 if (rx_hdr->l2_fhdr_status &
3975 (L2_FHDR_ERRORS_BAD_CRC | 4037 (L2_FHDR_ERRORS_BAD_CRC |
3976 L2_FHDR_ERRORS_PHY_DECODE | 4038 L2_FHDR_ERRORS_PHY_DECODE |
3977 L2_FHDR_ERRORS_ALIGNMENT | 4039 L2_FHDR_ERRORS_ALIGNMENT |
@@ -3998,6 +4060,30 @@ loopback_test_done:
3998 return ret; 4060 return ret;
3999} 4061}
4000 4062
4063#define BNX2_MAC_LOOPBACK_FAILED 1
4064#define BNX2_PHY_LOOPBACK_FAILED 2
4065#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
4066 BNX2_PHY_LOOPBACK_FAILED)
4067
4068static int
4069bnx2_test_loopback(struct bnx2 *bp)
4070{
4071 int rc = 0;
4072
4073 if (!netif_running(bp->dev))
4074 return BNX2_LOOPBACK_FAILED;
4075
4076 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
4077 spin_lock_bh(&bp->phy_lock);
4078 bnx2_init_phy(bp);
4079 spin_unlock_bh(&bp->phy_lock);
4080 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
4081 rc |= BNX2_MAC_LOOPBACK_FAILED;
4082 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
4083 rc |= BNX2_PHY_LOOPBACK_FAILED;
4084 return rc;
4085}
4086
4001#define NVRAM_SIZE 0x200 4087#define NVRAM_SIZE 0x200
4002#define CRC32_RESIDUAL 0xdebb20e3 4088#define CRC32_RESIDUAL 0xdebb20e3
4003 4089
@@ -4167,7 +4253,7 @@ bnx2_restart_timer:
4167static int 4253static int
4168bnx2_open(struct net_device *dev) 4254bnx2_open(struct net_device *dev)
4169{ 4255{
4170 struct bnx2 *bp = dev->priv; 4256 struct bnx2 *bp = netdev_priv(dev);
4171 int rc; 4257 int rc;
4172 4258
4173 bnx2_set_power_state(bp, PCI_D0); 4259 bnx2_set_power_state(bp, PCI_D0);
@@ -4280,7 +4366,7 @@ bnx2_reset_task(void *data)
4280static void 4366static void
4281bnx2_tx_timeout(struct net_device *dev) 4367bnx2_tx_timeout(struct net_device *dev)
4282{ 4368{
4283 struct bnx2 *bp = dev->priv; 4369 struct bnx2 *bp = netdev_priv(dev);
4284 4370
4285 /* This allows the netif to be shutdown gracefully before resetting */ 4371 /* This allows the netif to be shutdown gracefully before resetting */
4286 schedule_work(&bp->reset_task); 4372 schedule_work(&bp->reset_task);
@@ -4291,7 +4377,7 @@ bnx2_tx_timeout(struct net_device *dev)
4291static void 4377static void
4292bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp) 4378bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4293{ 4379{
4294 struct bnx2 *bp = dev->priv; 4380 struct bnx2 *bp = netdev_priv(dev);
4295 4381
4296 bnx2_netif_stop(bp); 4382 bnx2_netif_stop(bp);
4297 4383
@@ -4305,7 +4391,7 @@ bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4305static void 4391static void
4306bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid) 4392bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4307{ 4393{
4308 struct bnx2 *bp = dev->priv; 4394 struct bnx2 *bp = netdev_priv(dev);
4309 4395
4310 bnx2_netif_stop(bp); 4396 bnx2_netif_stop(bp);
4311 4397
@@ -4326,7 +4412,7 @@ bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4326static int 4412static int
4327bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) 4413bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4328{ 4414{
4329 struct bnx2 *bp = dev->priv; 4415 struct bnx2 *bp = netdev_priv(dev);
4330 dma_addr_t mapping; 4416 dma_addr_t mapping;
4331 struct tx_bd *txbd; 4417 struct tx_bd *txbd;
4332 struct sw_bd *tx_buf; 4418 struct sw_bd *tx_buf;
@@ -4455,7 +4541,7 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4455static int 4541static int
4456bnx2_close(struct net_device *dev) 4542bnx2_close(struct net_device *dev)
4457{ 4543{
4458 struct bnx2 *bp = dev->priv; 4544 struct bnx2 *bp = netdev_priv(dev);
4459 u32 reset_code; 4545 u32 reset_code;
4460 4546
4461 /* Calling flush_scheduled_work() may deadlock because 4547 /* Calling flush_scheduled_work() may deadlock because
@@ -4467,7 +4553,9 @@ bnx2_close(struct net_device *dev)
4467 4553
4468 bnx2_netif_stop(bp); 4554 bnx2_netif_stop(bp);
4469 del_timer_sync(&bp->timer); 4555 del_timer_sync(&bp->timer);
4470 if (bp->wol) 4556 if (bp->flags & NO_WOL_FLAG)
4557 reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
4558 else if (bp->wol)
4471 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; 4559 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4472 else 4560 else
4473 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; 4561 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
@@ -4501,7 +4589,7 @@ bnx2_close(struct net_device *dev)
4501static struct net_device_stats * 4589static struct net_device_stats *
4502bnx2_get_stats(struct net_device *dev) 4590bnx2_get_stats(struct net_device *dev)
4503{ 4591{
4504 struct bnx2 *bp = dev->priv; 4592 struct bnx2 *bp = netdev_priv(dev);
4505 struct statistics_block *stats_blk = bp->stats_blk; 4593 struct statistics_block *stats_blk = bp->stats_blk;
4506 struct net_device_stats *net_stats = &bp->net_stats; 4594 struct net_device_stats *net_stats = &bp->net_stats;
4507 4595
@@ -4575,7 +4663,7 @@ bnx2_get_stats(struct net_device *dev)
4575static int 4663static int
4576bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 4664bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4577{ 4665{
4578 struct bnx2 *bp = dev->priv; 4666 struct bnx2 *bp = netdev_priv(dev);
4579 4667
4580 cmd->supported = SUPPORTED_Autoneg; 4668 cmd->supported = SUPPORTED_Autoneg;
4581 if (bp->phy_flags & PHY_SERDES_FLAG) { 4669 if (bp->phy_flags & PHY_SERDES_FLAG) {
@@ -4622,7 +4710,7 @@ bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4622static int 4710static int
4623bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 4711bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4624{ 4712{
4625 struct bnx2 *bp = dev->priv; 4713 struct bnx2 *bp = netdev_priv(dev);
4626 u8 autoneg = bp->autoneg; 4714 u8 autoneg = bp->autoneg;
4627 u8 req_duplex = bp->req_duplex; 4715 u8 req_duplex = bp->req_duplex;
4628 u16 req_line_speed = bp->req_line_speed; 4716 u16 req_line_speed = bp->req_line_speed;
@@ -4694,7 +4782,7 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4694static void 4782static void
4695bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 4783bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4696{ 4784{
4697 struct bnx2 *bp = dev->priv; 4785 struct bnx2 *bp = netdev_priv(dev);
4698 4786
4699 strcpy(info->driver, DRV_MODULE_NAME); 4787 strcpy(info->driver, DRV_MODULE_NAME);
4700 strcpy(info->version, DRV_MODULE_VERSION); 4788 strcpy(info->version, DRV_MODULE_VERSION);
@@ -4702,15 +4790,14 @@ bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4702 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0'; 4790 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4703 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0'; 4791 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4704 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0'; 4792 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4705 info->fw_version[6] = (bp->fw_ver & 0xff) + '0'; 4793 info->fw_version[1] = info->fw_version[3] = '.';
4706 info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.'; 4794 info->fw_version[5] = 0;
4707 info->fw_version[7] = 0;
4708} 4795}
4709 4796
4710static void 4797static void
4711bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4798bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4712{ 4799{
4713 struct bnx2 *bp = dev->priv; 4800 struct bnx2 *bp = netdev_priv(dev);
4714 4801
4715 if (bp->flags & NO_WOL_FLAG) { 4802 if (bp->flags & NO_WOL_FLAG) {
4716 wol->supported = 0; 4803 wol->supported = 0;
@@ -4729,7 +4816,7 @@ bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4729static int 4816static int
4730bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4817bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4731{ 4818{
4732 struct bnx2 *bp = dev->priv; 4819 struct bnx2 *bp = netdev_priv(dev);
4733 4820
4734 if (wol->wolopts & ~WAKE_MAGIC) 4821 if (wol->wolopts & ~WAKE_MAGIC)
4735 return -EINVAL; 4822 return -EINVAL;
@@ -4749,7 +4836,7 @@ bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4749static int 4836static int
4750bnx2_nway_reset(struct net_device *dev) 4837bnx2_nway_reset(struct net_device *dev)
4751{ 4838{
4752 struct bnx2 *bp = dev->priv; 4839 struct bnx2 *bp = netdev_priv(dev);
4753 u32 bmcr; 4840 u32 bmcr;
4754 4841
4755 if (!(bp->autoneg & AUTONEG_SPEED)) { 4842 if (!(bp->autoneg & AUTONEG_SPEED)) {
@@ -4785,19 +4872,19 @@ bnx2_nway_reset(struct net_device *dev)
4785static int 4872static int
4786bnx2_get_eeprom_len(struct net_device *dev) 4873bnx2_get_eeprom_len(struct net_device *dev)
4787{ 4874{
4788 struct bnx2 *bp = dev->priv; 4875 struct bnx2 *bp = netdev_priv(dev);
4789 4876
4790 if (bp->flash_info == 0) 4877 if (bp->flash_info == NULL)
4791 return 0; 4878 return 0;
4792 4879
4793 return (int) bp->flash_info->total_size; 4880 return (int) bp->flash_size;
4794} 4881}
4795 4882
4796static int 4883static int
4797bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4884bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4798 u8 *eebuf) 4885 u8 *eebuf)
4799{ 4886{
4800 struct bnx2 *bp = dev->priv; 4887 struct bnx2 *bp = netdev_priv(dev);
4801 int rc; 4888 int rc;
4802 4889
4803 /* parameters already validated in ethtool_get_eeprom */ 4890 /* parameters already validated in ethtool_get_eeprom */
@@ -4811,7 +4898,7 @@ static int
4811bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4898bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4812 u8 *eebuf) 4899 u8 *eebuf)
4813{ 4900{
4814 struct bnx2 *bp = dev->priv; 4901 struct bnx2 *bp = netdev_priv(dev);
4815 int rc; 4902 int rc;
4816 4903
4817 /* parameters already validated in ethtool_set_eeprom */ 4904 /* parameters already validated in ethtool_set_eeprom */
@@ -4824,7 +4911,7 @@ bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4824static int 4911static int
4825bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) 4912bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4826{ 4913{
4827 struct bnx2 *bp = dev->priv; 4914 struct bnx2 *bp = netdev_priv(dev);
4828 4915
4829 memset(coal, 0, sizeof(struct ethtool_coalesce)); 4916 memset(coal, 0, sizeof(struct ethtool_coalesce));
4830 4917
@@ -4846,7 +4933,7 @@ bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4846static int 4933static int
4847bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) 4934bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4848{ 4935{
4849 struct bnx2 *bp = dev->priv; 4936 struct bnx2 *bp = netdev_priv(dev);
4850 4937
4851 bp->rx_ticks = (u16) coal->rx_coalesce_usecs; 4938 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4852 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff; 4939 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
@@ -4890,7 +4977,7 @@ bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4890static void 4977static void
4891bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) 4978bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4892{ 4979{
4893 struct bnx2 *bp = dev->priv; 4980 struct bnx2 *bp = netdev_priv(dev);
4894 4981
4895 ering->rx_max_pending = MAX_RX_DESC_CNT; 4982 ering->rx_max_pending = MAX_RX_DESC_CNT;
4896 ering->rx_mini_max_pending = 0; 4983 ering->rx_mini_max_pending = 0;
@@ -4907,7 +4994,7 @@ bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4907static int 4994static int
4908bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) 4995bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4909{ 4996{
4910 struct bnx2 *bp = dev->priv; 4997 struct bnx2 *bp = netdev_priv(dev);
4911 4998
4912 if ((ering->rx_pending > MAX_RX_DESC_CNT) || 4999 if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4913 (ering->tx_pending > MAX_TX_DESC_CNT) || 5000 (ering->tx_pending > MAX_TX_DESC_CNT) ||
@@ -4930,7 +5017,7 @@ bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4930static void 5017static void
4931bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) 5018bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4932{ 5019{
4933 struct bnx2 *bp = dev->priv; 5020 struct bnx2 *bp = netdev_priv(dev);
4934 5021
4935 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0); 5022 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4936 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0); 5023 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
@@ -4940,7 +5027,7 @@ bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4940static int 5027static int
4941bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) 5028bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4942{ 5029{
4943 struct bnx2 *bp = dev->priv; 5030 struct bnx2 *bp = netdev_priv(dev);
4944 5031
4945 bp->req_flow_ctrl = 0; 5032 bp->req_flow_ctrl = 0;
4946 if (epause->rx_pause) 5033 if (epause->rx_pause)
@@ -4967,7 +5054,7 @@ bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4967static u32 5054static u32
4968bnx2_get_rx_csum(struct net_device *dev) 5055bnx2_get_rx_csum(struct net_device *dev)
4969{ 5056{
4970 struct bnx2 *bp = dev->priv; 5057 struct bnx2 *bp = netdev_priv(dev);
4971 5058
4972 return bp->rx_csum; 5059 return bp->rx_csum;
4973} 5060}
@@ -4975,7 +5062,7 @@ bnx2_get_rx_csum(struct net_device *dev)
4975static int 5062static int
4976bnx2_set_rx_csum(struct net_device *dev, u32 data) 5063bnx2_set_rx_csum(struct net_device *dev, u32 data)
4977{ 5064{
4978 struct bnx2 *bp = dev->priv; 5065 struct bnx2 *bp = netdev_priv(dev);
4979 5066
4980 bp->rx_csum = data; 5067 bp->rx_csum = data;
4981 return 0; 5068 return 0;
@@ -5124,7 +5211,7 @@ bnx2_self_test_count(struct net_device *dev)
5124static void 5211static void
5125bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf) 5212bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5126{ 5213{
5127 struct bnx2 *bp = dev->priv; 5214 struct bnx2 *bp = netdev_priv(dev);
5128 5215
5129 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS); 5216 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
5130 if (etest->flags & ETH_TEST_FL_OFFLINE) { 5217 if (etest->flags & ETH_TEST_FL_OFFLINE) {
@@ -5140,10 +5227,8 @@ bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5140 buf[1] = 1; 5227 buf[1] = 1;
5141 etest->flags |= ETH_TEST_FL_FAILED; 5228 etest->flags |= ETH_TEST_FL_FAILED;
5142 } 5229 }
5143 if (bnx2_test_loopback(bp) != 0) { 5230 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
5144 buf[2] = 1;
5145 etest->flags |= ETH_TEST_FL_FAILED; 5231 etest->flags |= ETH_TEST_FL_FAILED;
5146 }
5147 5232
5148 if (!netif_running(bp->dev)) { 5233 if (!netif_running(bp->dev)) {
5149 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); 5234 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
@@ -5200,7 +5285,7 @@ static void
5200bnx2_get_ethtool_stats(struct net_device *dev, 5285bnx2_get_ethtool_stats(struct net_device *dev,
5201 struct ethtool_stats *stats, u64 *buf) 5286 struct ethtool_stats *stats, u64 *buf)
5202{ 5287{
5203 struct bnx2 *bp = dev->priv; 5288 struct bnx2 *bp = netdev_priv(dev);
5204 int i; 5289 int i;
5205 u32 *hw_stats = (u32 *) bp->stats_blk; 5290 u32 *hw_stats = (u32 *) bp->stats_blk;
5206 u8 *stats_len_arr = NULL; 5291 u8 *stats_len_arr = NULL;
@@ -5240,7 +5325,7 @@ bnx2_get_ethtool_stats(struct net_device *dev,
5240static int 5325static int
5241bnx2_phys_id(struct net_device *dev, u32 data) 5326bnx2_phys_id(struct net_device *dev, u32 data)
5242{ 5327{
5243 struct bnx2 *bp = dev->priv; 5328 struct bnx2 *bp = netdev_priv(dev);
5244 int i; 5329 int i;
5245 u32 save; 5330 u32 save;
5246 5331
@@ -5312,7 +5397,7 @@ static int
5312bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 5397bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5313{ 5398{
5314 struct mii_ioctl_data *data = if_mii(ifr); 5399 struct mii_ioctl_data *data = if_mii(ifr);
5315 struct bnx2 *bp = dev->priv; 5400 struct bnx2 *bp = netdev_priv(dev);
5316 int err; 5401 int err;
5317 5402
5318 switch(cmd) { 5403 switch(cmd) {
@@ -5354,7 +5439,7 @@ static int
5354bnx2_change_mac_addr(struct net_device *dev, void *p) 5439bnx2_change_mac_addr(struct net_device *dev, void *p)
5355{ 5440{
5356 struct sockaddr *addr = p; 5441 struct sockaddr *addr = p;
5357 struct bnx2 *bp = dev->priv; 5442 struct bnx2 *bp = netdev_priv(dev);
5358 5443
5359 if (!is_valid_ether_addr(addr->sa_data)) 5444 if (!is_valid_ether_addr(addr->sa_data))
5360 return -EINVAL; 5445 return -EINVAL;
@@ -5370,7 +5455,7 @@ bnx2_change_mac_addr(struct net_device *dev, void *p)
5370static int 5455static int
5371bnx2_change_mtu(struct net_device *dev, int new_mtu) 5456bnx2_change_mtu(struct net_device *dev, int new_mtu)
5372{ 5457{
5373 struct bnx2 *bp = dev->priv; 5458 struct bnx2 *bp = netdev_priv(dev);
5374 5459
5375 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) || 5460 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5376 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE)) 5461 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
@@ -5391,7 +5476,7 @@ bnx2_change_mtu(struct net_device *dev, int new_mtu)
5391static void 5476static void
5392poll_bnx2(struct net_device *dev) 5477poll_bnx2(struct net_device *dev)
5393{ 5478{
5394 struct bnx2 *bp = dev->priv; 5479 struct bnx2 *bp = netdev_priv(dev);
5395 5480
5396 disable_irq(bp->pdev->irq); 5481 disable_irq(bp->pdev->irq);
5397 bnx2_interrupt(bp->pdev->irq, dev, NULL); 5482 bnx2_interrupt(bp->pdev->irq, dev, NULL);
@@ -5409,7 +5494,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5409 5494
5410 SET_MODULE_OWNER(dev); 5495 SET_MODULE_OWNER(dev);
5411 SET_NETDEV_DEV(dev, &pdev->dev); 5496 SET_NETDEV_DEV(dev, &pdev->dev);
5412 bp = dev->priv; 5497 bp = netdev_priv(dev);
5413 5498
5414 bp->flags = 0; 5499 bp->flags = 0;
5415 bp->phy_flags = 0; 5500 bp->phy_flags = 0;
@@ -5629,6 +5714,9 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5629 } 5714 }
5630 } 5715 }
5631 5716
5717 if (CHIP_NUM(bp) == CHIP_NUM_5708)
5718 bp->flags |= NO_WOL_FLAG;
5719
5632 if (CHIP_ID(bp) == CHIP_ID_5706_A0) { 5720 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5633 bp->tx_quick_cons_trip_int = 5721 bp->tx_quick_cons_trip_int =
5634 bp->tx_quick_cons_trip; 5722 bp->tx_quick_cons_trip;
@@ -5725,7 +5813,7 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5725 dev->ethtool_ops = &bnx2_ethtool_ops; 5813 dev->ethtool_ops = &bnx2_ethtool_ops;
5726 dev->weight = 64; 5814 dev->weight = 64;
5727 5815
5728 bp = dev->priv; 5816 bp = netdev_priv(dev);
5729 5817
5730#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER) 5818#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5731 dev->poll_controller = poll_bnx2; 5819 dev->poll_controller = poll_bnx2;
@@ -5784,7 +5872,7 @@ static void __devexit
5784bnx2_remove_one(struct pci_dev *pdev) 5872bnx2_remove_one(struct pci_dev *pdev)
5785{ 5873{
5786 struct net_device *dev = pci_get_drvdata(pdev); 5874 struct net_device *dev = pci_get_drvdata(pdev);
5787 struct bnx2 *bp = dev->priv; 5875 struct bnx2 *bp = netdev_priv(dev);
5788 5876
5789 flush_scheduled_work(); 5877 flush_scheduled_work();
5790 5878
@@ -5803,7 +5891,7 @@ static int
5803bnx2_suspend(struct pci_dev *pdev, pm_message_t state) 5891bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
5804{ 5892{
5805 struct net_device *dev = pci_get_drvdata(pdev); 5893 struct net_device *dev = pci_get_drvdata(pdev);
5806 struct bnx2 *bp = dev->priv; 5894 struct bnx2 *bp = netdev_priv(dev);
5807 u32 reset_code; 5895 u32 reset_code;
5808 5896
5809 if (!netif_running(dev)) 5897 if (!netif_running(dev))
@@ -5812,7 +5900,9 @@ bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
5812 bnx2_netif_stop(bp); 5900 bnx2_netif_stop(bp);
5813 netif_device_detach(dev); 5901 netif_device_detach(dev);
5814 del_timer_sync(&bp->timer); 5902 del_timer_sync(&bp->timer);
5815 if (bp->wol) 5903 if (bp->flags & NO_WOL_FLAG)
5904 reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
5905 else if (bp->wol)
5816 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; 5906 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5817 else 5907 else
5818 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; 5908 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
@@ -5826,7 +5916,7 @@ static int
5826bnx2_resume(struct pci_dev *pdev) 5916bnx2_resume(struct pci_dev *pdev)
5827{ 5917{
5828 struct net_device *dev = pci_get_drvdata(pdev); 5918 struct net_device *dev = pci_get_drvdata(pdev);
5829 struct bnx2 *bp = dev->priv; 5919 struct bnx2 *bp = netdev_priv(dev);
5830 5920
5831 if (!netif_running(dev)) 5921 if (!netif_running(dev))
5832 return 0; 5922 return 0;