diff options
Diffstat (limited to 'drivers/net/bnx2.c')
-rw-r--r-- | drivers/net/bnx2.c | 50 |
1 files changed, 32 insertions, 18 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 471c7f3e8a4a..15853be4680a 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c | |||
@@ -56,8 +56,8 @@ | |||
56 | 56 | ||
57 | #define DRV_MODULE_NAME "bnx2" | 57 | #define DRV_MODULE_NAME "bnx2" |
58 | #define PFX DRV_MODULE_NAME ": " | 58 | #define PFX DRV_MODULE_NAME ": " |
59 | #define DRV_MODULE_VERSION "1.7.3" | 59 | #define DRV_MODULE_VERSION "1.7.4" |
60 | #define DRV_MODULE_RELDATE "January 29, 2008" | 60 | #define DRV_MODULE_RELDATE "February 18, 2008" |
61 | 61 | ||
62 | #define RUN_AT(x) (jiffies + (x)) | 62 | #define RUN_AT(x) (jiffies + (x)) |
63 | 63 | ||
@@ -1273,14 +1273,20 @@ bnx2_set_link(struct bnx2 *bp) | |||
1273 | 1273 | ||
1274 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && | 1274 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
1275 | (CHIP_NUM(bp) == CHIP_NUM_5706)) { | 1275 | (CHIP_NUM(bp) == CHIP_NUM_5706)) { |
1276 | u32 val; | 1276 | u32 val, an_dbg; |
1277 | 1277 | ||
1278 | if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) { | 1278 | if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) { |
1279 | bnx2_5706s_force_link_dn(bp, 0); | 1279 | bnx2_5706s_force_link_dn(bp, 0); |
1280 | bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN; | 1280 | bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN; |
1281 | } | 1281 | } |
1282 | val = REG_RD(bp, BNX2_EMAC_STATUS); | 1282 | val = REG_RD(bp, BNX2_EMAC_STATUS); |
1283 | if (val & BNX2_EMAC_STATUS_LINK) | 1283 | |
1284 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); | ||
1285 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); | ||
1286 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); | ||
1287 | |||
1288 | if ((val & BNX2_EMAC_STATUS_LINK) && | ||
1289 | !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC)) | ||
1284 | bmsr |= BMSR_LSTATUS; | 1290 | bmsr |= BMSR_LSTATUS; |
1285 | else | 1291 | else |
1286 | bmsr &= ~BMSR_LSTATUS; | 1292 | bmsr &= ~BMSR_LSTATUS; |
@@ -5356,11 +5362,15 @@ bnx2_test_intr(struct bnx2 *bp) | |||
5356 | return -ENODEV; | 5362 | return -ENODEV; |
5357 | } | 5363 | } |
5358 | 5364 | ||
5365 | /* Determining link for parallel detection. */ | ||
5359 | static int | 5366 | static int |
5360 | bnx2_5706_serdes_has_link(struct bnx2 *bp) | 5367 | bnx2_5706_serdes_has_link(struct bnx2 *bp) |
5361 | { | 5368 | { |
5362 | u32 mode_ctl, an_dbg, exp; | 5369 | u32 mode_ctl, an_dbg, exp; |
5363 | 5370 | ||
5371 | if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL) | ||
5372 | return 0; | ||
5373 | |||
5364 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL); | 5374 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL); |
5365 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl); | 5375 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl); |
5366 | 5376 | ||
@@ -5390,13 +5400,6 @@ bnx2_5706_serdes_timer(struct bnx2 *bp) | |||
5390 | int check_link = 1; | 5400 | int check_link = 1; |
5391 | 5401 | ||
5392 | spin_lock(&bp->phy_lock); | 5402 | spin_lock(&bp->phy_lock); |
5393 | if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) { | ||
5394 | bnx2_5706s_force_link_dn(bp, 0); | ||
5395 | bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN; | ||
5396 | spin_unlock(&bp->phy_lock); | ||
5397 | return; | ||
5398 | } | ||
5399 | |||
5400 | if (bp->serdes_an_pending) { | 5403 | if (bp->serdes_an_pending) { |
5401 | bp->serdes_an_pending--; | 5404 | bp->serdes_an_pending--; |
5402 | check_link = 0; | 5405 | check_link = 0; |
@@ -5420,7 +5423,6 @@ bnx2_5706_serdes_timer(struct bnx2 *bp) | |||
5420 | (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) { | 5423 | (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) { |
5421 | u32 phy2; | 5424 | u32 phy2; |
5422 | 5425 | ||
5423 | check_link = 0; | ||
5424 | bnx2_write_phy(bp, 0x17, 0x0f01); | 5426 | bnx2_write_phy(bp, 0x17, 0x0f01); |
5425 | bnx2_read_phy(bp, 0x15, &phy2); | 5427 | bnx2_read_phy(bp, 0x15, &phy2); |
5426 | if (phy2 & 0x20) { | 5428 | if (phy2 & 0x20) { |
@@ -5435,17 +5437,21 @@ bnx2_5706_serdes_timer(struct bnx2 *bp) | |||
5435 | } else | 5437 | } else |
5436 | bp->current_interval = bp->timer_interval; | 5438 | bp->current_interval = bp->timer_interval; |
5437 | 5439 | ||
5438 | if (bp->link_up && (bp->autoneg & AUTONEG_SPEED) && check_link) { | 5440 | if (check_link) { |
5439 | u32 val; | 5441 | u32 val; |
5440 | 5442 | ||
5441 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); | 5443 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); |
5442 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); | 5444 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); |
5443 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); | 5445 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); |
5444 | 5446 | ||
5445 | if (val & MISC_SHDW_AN_DBG_NOSYNC) { | 5447 | if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) { |
5446 | bnx2_5706s_force_link_dn(bp, 1); | 5448 | if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) { |
5447 | bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN; | 5449 | bnx2_5706s_force_link_dn(bp, 1); |
5448 | } | 5450 | bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN; |
5451 | } else | ||
5452 | bnx2_set_link(bp); | ||
5453 | } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC)) | ||
5454 | bnx2_set_link(bp); | ||
5449 | } | 5455 | } |
5450 | spin_unlock(&bp->phy_lock); | 5456 | spin_unlock(&bp->phy_lock); |
5451 | } | 5457 | } |
@@ -7326,7 +7332,15 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) | |||
7326 | bp->flags |= BNX2_FLAG_NO_WOL; | 7332 | bp->flags |= BNX2_FLAG_NO_WOL; |
7327 | bp->wol = 0; | 7333 | bp->wol = 0; |
7328 | } | 7334 | } |
7329 | if (CHIP_NUM(bp) != CHIP_NUM_5706) { | 7335 | if (CHIP_NUM(bp) == CHIP_NUM_5706) { |
7336 | /* Don't do parallel detect on this board because of | ||
7337 | * some board problems. The link will not go down | ||
7338 | * if we do parallel detect. | ||
7339 | */ | ||
7340 | if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP && | ||
7341 | pdev->subsystem_device == 0x310c) | ||
7342 | bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL; | ||
7343 | } else { | ||
7330 | bp->phy_addr = 2; | 7344 | bp->phy_addr = 2; |
7331 | if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) | 7345 | if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) |
7332 | bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE; | 7346 | bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE; |