diff options
Diffstat (limited to 'drivers/net/bnx2.c')
-rw-r--r-- | drivers/net/bnx2.c | 94 |
1 files changed, 54 insertions, 40 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 9e8222f9e90e..d4a3dac21dcf 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c | |||
@@ -57,8 +57,8 @@ | |||
57 | 57 | ||
58 | #define DRV_MODULE_NAME "bnx2" | 58 | #define DRV_MODULE_NAME "bnx2" |
59 | #define PFX DRV_MODULE_NAME ": " | 59 | #define PFX DRV_MODULE_NAME ": " |
60 | #define DRV_MODULE_VERSION "1.8.1" | 60 | #define DRV_MODULE_VERSION "1.9.0" |
61 | #define DRV_MODULE_RELDATE "Oct 7, 2008" | 61 | #define DRV_MODULE_RELDATE "Dec 16, 2008" |
62 | 62 | ||
63 | #define RUN_AT(x) (jiffies + (x)) | 63 | #define RUN_AT(x) (jiffies + (x)) |
64 | 64 | ||
@@ -89,6 +89,7 @@ typedef enum { | |||
89 | BCM5709, | 89 | BCM5709, |
90 | BCM5709S, | 90 | BCM5709S, |
91 | BCM5716, | 91 | BCM5716, |
92 | BCM5716S, | ||
92 | } board_t; | 93 | } board_t; |
93 | 94 | ||
94 | /* indexed by board_t, above */ | 95 | /* indexed by board_t, above */ |
@@ -105,6 +106,7 @@ static struct { | |||
105 | { "Broadcom NetXtreme II BCM5709 1000Base-T" }, | 106 | { "Broadcom NetXtreme II BCM5709 1000Base-T" }, |
106 | { "Broadcom NetXtreme II BCM5709 1000Base-SX" }, | 107 | { "Broadcom NetXtreme II BCM5709 1000Base-SX" }, |
107 | { "Broadcom NetXtreme II BCM5716 1000Base-T" }, | 108 | { "Broadcom NetXtreme II BCM5716 1000Base-T" }, |
109 | { "Broadcom NetXtreme II BCM5716 1000Base-SX" }, | ||
108 | }; | 110 | }; |
109 | 111 | ||
110 | static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = { | 112 | static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = { |
@@ -128,6 +130,8 @@ static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = { | |||
128 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S }, | 130 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S }, |
129 | { PCI_VENDOR_ID_BROADCOM, 0x163b, | 131 | { PCI_VENDOR_ID_BROADCOM, 0x163b, |
130 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 }, | 132 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 }, |
133 | { PCI_VENDOR_ID_BROADCOM, 0x163c, | ||
134 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S }, | ||
131 | { 0, } | 135 | { 0, } |
132 | }; | 136 | }; |
133 | 137 | ||
@@ -1652,7 +1656,7 @@ bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port) | |||
1652 | * exchanging base pages plus 3 next pages and | 1656 | * exchanging base pages plus 3 next pages and |
1653 | * normally completes in about 120 msec. | 1657 | * normally completes in about 120 msec. |
1654 | */ | 1658 | */ |
1655 | bp->current_interval = SERDES_AN_TIMEOUT; | 1659 | bp->current_interval = BNX2_SERDES_AN_TIMEOUT; |
1656 | bp->serdes_an_pending = 1; | 1660 | bp->serdes_an_pending = 1; |
1657 | mod_timer(&bp->timer, jiffies + bp->current_interval); | 1661 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
1658 | } else { | 1662 | } else { |
@@ -2274,7 +2278,7 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent) | |||
2274 | return 0; | 2278 | return 0; |
2275 | 2279 | ||
2276 | /* wait for an acknowledgement. */ | 2280 | /* wait for an acknowledgement. */ |
2277 | for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) { | 2281 | for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) { |
2278 | msleep(10); | 2282 | msleep(10); |
2279 | 2283 | ||
2280 | val = bnx2_shmem_rd(bp, BNX2_FW_MB); | 2284 | val = bnx2_shmem_rd(bp, BNX2_FW_MB); |
@@ -3000,7 +3004,6 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) | |||
3000 | #endif | 3004 | #endif |
3001 | netif_receive_skb(skb); | 3005 | netif_receive_skb(skb); |
3002 | 3006 | ||
3003 | bp->dev->last_rx = jiffies; | ||
3004 | rx_pkt++; | 3007 | rx_pkt++; |
3005 | 3008 | ||
3006 | next_rx: | 3009 | next_rx: |
@@ -3040,7 +3043,6 @@ bnx2_msi(int irq, void *dev_instance) | |||
3040 | { | 3043 | { |
3041 | struct bnx2_napi *bnapi = dev_instance; | 3044 | struct bnx2_napi *bnapi = dev_instance; |
3042 | struct bnx2 *bp = bnapi->bp; | 3045 | struct bnx2 *bp = bnapi->bp; |
3043 | struct net_device *dev = bp->dev; | ||
3044 | 3046 | ||
3045 | prefetch(bnapi->status_blk.msi); | 3047 | prefetch(bnapi->status_blk.msi); |
3046 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, | 3048 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
@@ -3051,7 +3053,7 @@ bnx2_msi(int irq, void *dev_instance) | |||
3051 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) | 3053 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) |
3052 | return IRQ_HANDLED; | 3054 | return IRQ_HANDLED; |
3053 | 3055 | ||
3054 | netif_rx_schedule(dev, &bnapi->napi); | 3056 | netif_rx_schedule(&bnapi->napi); |
3055 | 3057 | ||
3056 | return IRQ_HANDLED; | 3058 | return IRQ_HANDLED; |
3057 | } | 3059 | } |
@@ -3061,7 +3063,6 @@ bnx2_msi_1shot(int irq, void *dev_instance) | |||
3061 | { | 3063 | { |
3062 | struct bnx2_napi *bnapi = dev_instance; | 3064 | struct bnx2_napi *bnapi = dev_instance; |
3063 | struct bnx2 *bp = bnapi->bp; | 3065 | struct bnx2 *bp = bnapi->bp; |
3064 | struct net_device *dev = bp->dev; | ||
3065 | 3066 | ||
3066 | prefetch(bnapi->status_blk.msi); | 3067 | prefetch(bnapi->status_blk.msi); |
3067 | 3068 | ||
@@ -3069,7 +3070,7 @@ bnx2_msi_1shot(int irq, void *dev_instance) | |||
3069 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) | 3070 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) |
3070 | return IRQ_HANDLED; | 3071 | return IRQ_HANDLED; |
3071 | 3072 | ||
3072 | netif_rx_schedule(dev, &bnapi->napi); | 3073 | netif_rx_schedule(&bnapi->napi); |
3073 | 3074 | ||
3074 | return IRQ_HANDLED; | 3075 | return IRQ_HANDLED; |
3075 | } | 3076 | } |
@@ -3079,7 +3080,6 @@ bnx2_interrupt(int irq, void *dev_instance) | |||
3079 | { | 3080 | { |
3080 | struct bnx2_napi *bnapi = dev_instance; | 3081 | struct bnx2_napi *bnapi = dev_instance; |
3081 | struct bnx2 *bp = bnapi->bp; | 3082 | struct bnx2 *bp = bnapi->bp; |
3082 | struct net_device *dev = bp->dev; | ||
3083 | struct status_block *sblk = bnapi->status_blk.msi; | 3083 | struct status_block *sblk = bnapi->status_blk.msi; |
3084 | 3084 | ||
3085 | /* When using INTx, it is possible for the interrupt to arrive | 3085 | /* When using INTx, it is possible for the interrupt to arrive |
@@ -3106,9 +3106,9 @@ bnx2_interrupt(int irq, void *dev_instance) | |||
3106 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) | 3106 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) |
3107 | return IRQ_HANDLED; | 3107 | return IRQ_HANDLED; |
3108 | 3108 | ||
3109 | if (netif_rx_schedule_prep(dev, &bnapi->napi)) { | 3109 | if (netif_rx_schedule_prep(&bnapi->napi)) { |
3110 | bnapi->last_status_idx = sblk->status_idx; | 3110 | bnapi->last_status_idx = sblk->status_idx; |
3111 | __netif_rx_schedule(dev, &bnapi->napi); | 3111 | __netif_rx_schedule(&bnapi->napi); |
3112 | } | 3112 | } |
3113 | 3113 | ||
3114 | return IRQ_HANDLED; | 3114 | return IRQ_HANDLED; |
@@ -3218,7 +3218,7 @@ static int bnx2_poll_msix(struct napi_struct *napi, int budget) | |||
3218 | rmb(); | 3218 | rmb(); |
3219 | if (likely(!bnx2_has_fast_work(bnapi))) { | 3219 | if (likely(!bnx2_has_fast_work(bnapi))) { |
3220 | 3220 | ||
3221 | netif_rx_complete(bp->dev, napi); | 3221 | netif_rx_complete(napi); |
3222 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | | 3222 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | |
3223 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | 3223 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | |
3224 | bnapi->last_status_idx); | 3224 | bnapi->last_status_idx); |
@@ -3251,7 +3251,7 @@ static int bnx2_poll(struct napi_struct *napi, int budget) | |||
3251 | 3251 | ||
3252 | rmb(); | 3252 | rmb(); |
3253 | if (likely(!bnx2_has_work(bnapi))) { | 3253 | if (likely(!bnx2_has_work(bnapi))) { |
3254 | netif_rx_complete(bp->dev, napi); | 3254 | netif_rx_complete(napi); |
3255 | if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) { | 3255 | if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) { |
3256 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, | 3256 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
3257 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | 3257 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | |
@@ -4493,7 +4493,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) | |||
4493 | static int | 4493 | static int |
4494 | bnx2_init_chip(struct bnx2 *bp) | 4494 | bnx2_init_chip(struct bnx2 *bp) |
4495 | { | 4495 | { |
4496 | u32 val; | 4496 | u32 val, mtu; |
4497 | int rc, i; | 4497 | int rc, i; |
4498 | 4498 | ||
4499 | /* Make sure the interrupt is not active. */ | 4499 | /* Make sure the interrupt is not active. */ |
@@ -4585,11 +4585,19 @@ bnx2_init_chip(struct bnx2 *bp) | |||
4585 | REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); | 4585 | REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); |
4586 | 4586 | ||
4587 | /* Program the MTU. Also include 4 bytes for CRC32. */ | 4587 | /* Program the MTU. Also include 4 bytes for CRC32. */ |
4588 | val = bp->dev->mtu + ETH_HLEN + 4; | 4588 | mtu = bp->dev->mtu; |
4589 | val = mtu + ETH_HLEN + ETH_FCS_LEN; | ||
4589 | if (val > (MAX_ETHERNET_PACKET_SIZE + 4)) | 4590 | if (val > (MAX_ETHERNET_PACKET_SIZE + 4)) |
4590 | val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; | 4591 | val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; |
4591 | REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); | 4592 | REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); |
4592 | 4593 | ||
4594 | if (mtu < 1500) | ||
4595 | mtu = 1500; | ||
4596 | |||
4597 | bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu)); | ||
4598 | bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu)); | ||
4599 | bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu)); | ||
4600 | |||
4593 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) | 4601 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) |
4594 | bp->bnx2_napi[i].last_status_idx = 0; | 4602 | bp->bnx2_napi[i].last_status_idx = 0; |
4595 | 4603 | ||
@@ -5719,7 +5727,7 @@ bnx2_5708_serdes_timer(struct bnx2 *bp) | |||
5719 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | 5727 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
5720 | if (bmcr & BMCR_ANENABLE) { | 5728 | if (bmcr & BMCR_ANENABLE) { |
5721 | bnx2_enable_forced_2g5(bp); | 5729 | bnx2_enable_forced_2g5(bp); |
5722 | bp->current_interval = SERDES_FORCED_TIMEOUT; | 5730 | bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT; |
5723 | } else { | 5731 | } else { |
5724 | bnx2_disable_forced_2g5(bp); | 5732 | bnx2_disable_forced_2g5(bp); |
5725 | bp->serdes_an_pending = 2; | 5733 | bp->serdes_an_pending = 2; |
@@ -5816,6 +5824,8 @@ bnx2_enable_msix(struct bnx2 *bp, int msix_vecs) | |||
5816 | { | 5824 | { |
5817 | int i, rc; | 5825 | int i, rc; |
5818 | struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC]; | 5826 | struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC]; |
5827 | struct net_device *dev = bp->dev; | ||
5828 | const int len = sizeof(bp->irq_tbl[0].name); | ||
5819 | 5829 | ||
5820 | bnx2_setup_msix_tbl(bp); | 5830 | bnx2_setup_msix_tbl(bp); |
5821 | REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1); | 5831 | REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1); |
@@ -5826,7 +5836,7 @@ bnx2_enable_msix(struct bnx2 *bp, int msix_vecs) | |||
5826 | msix_ent[i].entry = i; | 5836 | msix_ent[i].entry = i; |
5827 | msix_ent[i].vector = 0; | 5837 | msix_ent[i].vector = 0; |
5828 | 5838 | ||
5829 | strcpy(bp->irq_tbl[i].name, bp->dev->name); | 5839 | snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i); |
5830 | bp->irq_tbl[i].handler = bnx2_msi_1shot; | 5840 | bp->irq_tbl[i].handler = bnx2_msi_1shot; |
5831 | } | 5841 | } |
5832 | 5842 | ||
@@ -6173,7 +6183,7 @@ bnx2_get_stats(struct net_device *dev) | |||
6173 | { | 6183 | { |
6174 | struct bnx2 *bp = netdev_priv(dev); | 6184 | struct bnx2 *bp = netdev_priv(dev); |
6175 | struct statistics_block *stats_blk = bp->stats_blk; | 6185 | struct statistics_block *stats_blk = bp->stats_blk; |
6176 | struct net_device_stats *net_stats = &bp->net_stats; | 6186 | struct net_device_stats *net_stats = &dev->stats; |
6177 | 6187 | ||
6178 | if (bp->stats_blk == NULL) { | 6188 | if (bp->stats_blk == NULL) { |
6179 | return net_stats; | 6189 | return net_stats; |
@@ -6540,7 +6550,7 @@ bnx2_nway_reset(struct net_device *dev) | |||
6540 | 6550 | ||
6541 | spin_lock_bh(&bp->phy_lock); | 6551 | spin_lock_bh(&bp->phy_lock); |
6542 | 6552 | ||
6543 | bp->current_interval = SERDES_AN_TIMEOUT; | 6553 | bp->current_interval = BNX2_SERDES_AN_TIMEOUT; |
6544 | bp->serdes_an_pending = 1; | 6554 | bp->serdes_an_pending = 1; |
6545 | mod_timer(&bp->timer, jiffies + bp->current_interval); | 6555 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
6546 | } | 6556 | } |
@@ -7615,7 +7625,8 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) | |||
7615 | 7625 | ||
7616 | if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || | 7626 | if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || |
7617 | (CHIP_ID(bp) == CHIP_ID_5708_B0) || | 7627 | (CHIP_ID(bp) == CHIP_ID_5708_B0) || |
7618 | (CHIP_ID(bp) == CHIP_ID_5708_B1)) { | 7628 | (CHIP_ID(bp) == CHIP_ID_5708_B1) || |
7629 | !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) { | ||
7619 | bp->flags |= BNX2_FLAG_NO_WOL; | 7630 | bp->flags |= BNX2_FLAG_NO_WOL; |
7620 | bp->wol = 0; | 7631 | bp->wol = 0; |
7621 | } | 7632 | } |
@@ -7724,6 +7735,25 @@ bnx2_init_napi(struct bnx2 *bp) | |||
7724 | } | 7735 | } |
7725 | } | 7736 | } |
7726 | 7737 | ||
7738 | static const struct net_device_ops bnx2_netdev_ops = { | ||
7739 | .ndo_open = bnx2_open, | ||
7740 | .ndo_start_xmit = bnx2_start_xmit, | ||
7741 | .ndo_stop = bnx2_close, | ||
7742 | .ndo_get_stats = bnx2_get_stats, | ||
7743 | .ndo_set_rx_mode = bnx2_set_rx_mode, | ||
7744 | .ndo_do_ioctl = bnx2_ioctl, | ||
7745 | .ndo_validate_addr = eth_validate_addr, | ||
7746 | .ndo_set_mac_address = bnx2_change_mac_addr, | ||
7747 | .ndo_change_mtu = bnx2_change_mtu, | ||
7748 | .ndo_tx_timeout = bnx2_tx_timeout, | ||
7749 | #ifdef BCM_VLAN | ||
7750 | .ndo_vlan_rx_register = bnx2_vlan_rx_register, | ||
7751 | #endif | ||
7752 | #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER) | ||
7753 | .ndo_poll_controller = poll_bnx2, | ||
7754 | #endif | ||
7755 | }; | ||
7756 | |||
7727 | static int __devinit | 7757 | static int __devinit |
7728 | bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | 7758 | bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
7729 | { | 7759 | { |
@@ -7732,7 +7762,6 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
7732 | struct bnx2 *bp; | 7762 | struct bnx2 *bp; |
7733 | int rc; | 7763 | int rc; |
7734 | char str[40]; | 7764 | char str[40]; |
7735 | DECLARE_MAC_BUF(mac); | ||
7736 | 7765 | ||
7737 | if (version_printed++ == 0) | 7766 | if (version_printed++ == 0) |
7738 | printk(KERN_INFO "%s", version); | 7767 | printk(KERN_INFO "%s", version); |
@@ -7749,28 +7778,13 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
7749 | return rc; | 7778 | return rc; |
7750 | } | 7779 | } |
7751 | 7780 | ||
7752 | dev->open = bnx2_open; | 7781 | dev->netdev_ops = &bnx2_netdev_ops; |
7753 | dev->hard_start_xmit = bnx2_start_xmit; | ||
7754 | dev->stop = bnx2_close; | ||
7755 | dev->get_stats = bnx2_get_stats; | ||
7756 | dev->set_rx_mode = bnx2_set_rx_mode; | ||
7757 | dev->do_ioctl = bnx2_ioctl; | ||
7758 | dev->set_mac_address = bnx2_change_mac_addr; | ||
7759 | dev->change_mtu = bnx2_change_mtu; | ||
7760 | dev->tx_timeout = bnx2_tx_timeout; | ||
7761 | dev->watchdog_timeo = TX_TIMEOUT; | 7782 | dev->watchdog_timeo = TX_TIMEOUT; |
7762 | #ifdef BCM_VLAN | ||
7763 | dev->vlan_rx_register = bnx2_vlan_rx_register; | ||
7764 | #endif | ||
7765 | dev->ethtool_ops = &bnx2_ethtool_ops; | 7783 | dev->ethtool_ops = &bnx2_ethtool_ops; |
7766 | 7784 | ||
7767 | bp = netdev_priv(dev); | 7785 | bp = netdev_priv(dev); |
7768 | bnx2_init_napi(bp); | 7786 | bnx2_init_napi(bp); |
7769 | 7787 | ||
7770 | #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER) | ||
7771 | dev->poll_controller = poll_bnx2; | ||
7772 | #endif | ||
7773 | |||
7774 | pci_set_drvdata(pdev, dev); | 7788 | pci_set_drvdata(pdev, dev); |
7775 | 7789 | ||
7776 | memcpy(dev->dev_addr, bp->mac_addr, 6); | 7790 | memcpy(dev->dev_addr, bp->mac_addr, 6); |
@@ -7799,14 +7813,14 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
7799 | } | 7813 | } |
7800 | 7814 | ||
7801 | printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, " | 7815 | printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, " |
7802 | "IRQ %d, node addr %s\n", | 7816 | "IRQ %d, node addr %pM\n", |
7803 | dev->name, | 7817 | dev->name, |
7804 | board_info[ent->driver_data].name, | 7818 | board_info[ent->driver_data].name, |
7805 | ((CHIP_ID(bp) & 0xf000) >> 12) + 'A', | 7819 | ((CHIP_ID(bp) & 0xf000) >> 12) + 'A', |
7806 | ((CHIP_ID(bp) & 0x0ff0) >> 4), | 7820 | ((CHIP_ID(bp) & 0x0ff0) >> 4), |
7807 | bnx2_bus_string(bp, str), | 7821 | bnx2_bus_string(bp, str), |
7808 | dev->base_addr, | 7822 | dev->base_addr, |
7809 | bp->pdev->irq, print_mac(mac, dev->dev_addr)); | 7823 | bp->pdev->irq, dev->dev_addr); |
7810 | 7824 | ||
7811 | return 0; | 7825 | return 0; |
7812 | } | 7826 | } |