diff options
Diffstat (limited to 'drivers/net/bnx2.c')
-rw-r--r-- | drivers/net/bnx2.c | 41 |
1 files changed, 21 insertions, 20 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index c12e5ea61819..e85f5ec48f96 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c | |||
@@ -54,8 +54,8 @@ | |||
54 | 54 | ||
55 | #define DRV_MODULE_NAME "bnx2" | 55 | #define DRV_MODULE_NAME "bnx2" |
56 | #define PFX DRV_MODULE_NAME ": " | 56 | #define PFX DRV_MODULE_NAME ": " |
57 | #define DRV_MODULE_VERSION "1.5.5" | 57 | #define DRV_MODULE_VERSION "1.5.8" |
58 | #define DRV_MODULE_RELDATE "February 1, 2007" | 58 | #define DRV_MODULE_RELDATE "April 24, 2007" |
59 | 59 | ||
60 | #define RUN_AT(x) (jiffies + (x)) | 60 | #define RUN_AT(x) (jiffies + (x)) |
61 | 61 | ||
@@ -2033,8 +2033,8 @@ bnx2_has_work(struct bnx2 *bp) | |||
2033 | (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)) | 2033 | (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)) |
2034 | return 1; | 2034 | return 1; |
2035 | 2035 | ||
2036 | if (((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) != | 2036 | if ((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != |
2037 | bp->link_up) | 2037 | (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) |
2038 | return 1; | 2038 | return 1; |
2039 | 2039 | ||
2040 | return 0; | 2040 | return 0; |
@@ -3099,20 +3099,18 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, | |||
3099 | 3099 | ||
3100 | if ((align_start = (offset32 & 3))) { | 3100 | if ((align_start = (offset32 & 3))) { |
3101 | offset32 &= ~3; | 3101 | offset32 &= ~3; |
3102 | len32 += (4 - align_start); | 3102 | len32 += align_start; |
3103 | if (len32 < 4) | ||
3104 | len32 = 4; | ||
3103 | if ((rc = bnx2_nvram_read(bp, offset32, start, 4))) | 3105 | if ((rc = bnx2_nvram_read(bp, offset32, start, 4))) |
3104 | return rc; | 3106 | return rc; |
3105 | } | 3107 | } |
3106 | 3108 | ||
3107 | if (len32 & 3) { | 3109 | if (len32 & 3) { |
3108 | if ((len32 > 4) || !align_start) { | 3110 | align_end = 4 - (len32 & 3); |
3109 | align_end = 4 - (len32 & 3); | 3111 | len32 += align_end; |
3110 | len32 += align_end; | 3112 | if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4))) |
3111 | if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, | 3113 | return rc; |
3112 | end, 4))) { | ||
3113 | return rc; | ||
3114 | } | ||
3115 | } | ||
3116 | } | 3114 | } |
3117 | 3115 | ||
3118 | if (align_start || align_end) { | 3116 | if (align_start || align_end) { |
@@ -3187,17 +3185,17 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, | |||
3187 | if ((rc = bnx2_enable_nvram_write(bp)) != 0) | 3185 | if ((rc = bnx2_enable_nvram_write(bp)) != 0) |
3188 | goto nvram_write_end; | 3186 | goto nvram_write_end; |
3189 | 3187 | ||
3190 | /* Erase the page */ | ||
3191 | if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0) | ||
3192 | goto nvram_write_end; | ||
3193 | |||
3194 | /* Re-enable the write again for the actual write */ | ||
3195 | bnx2_enable_nvram_write(bp); | ||
3196 | |||
3197 | /* Loop to write back the buffer data from page_start to | 3188 | /* Loop to write back the buffer data from page_start to |
3198 | * data_start */ | 3189 | * data_start */ |
3199 | i = 0; | 3190 | i = 0; |
3200 | if (bp->flash_info->buffered == 0) { | 3191 | if (bp->flash_info->buffered == 0) { |
3192 | /* Erase the page */ | ||
3193 | if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0) | ||
3194 | goto nvram_write_end; | ||
3195 | |||
3196 | /* Re-enable the write again for the actual write */ | ||
3197 | bnx2_enable_nvram_write(bp); | ||
3198 | |||
3201 | for (addr = page_start; addr < data_start; | 3199 | for (addr = page_start; addr < data_start; |
3202 | addr += 4, i += 4) { | 3200 | addr += 4, i += 4) { |
3203 | 3201 | ||
@@ -3423,6 +3421,9 @@ bnx2_init_chip(struct bnx2 *bp) | |||
3423 | val = REG_RD(bp, BNX2_MQ_CONFIG); | 3421 | val = REG_RD(bp, BNX2_MQ_CONFIG); |
3424 | val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; | 3422 | val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; |
3425 | val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; | 3423 | val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; |
3424 | if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1) | ||
3425 | val |= BNX2_MQ_CONFIG_HALT_DIS; | ||
3426 | |||
3426 | REG_WR(bp, BNX2_MQ_CONFIG, val); | 3427 | REG_WR(bp, BNX2_MQ_CONFIG, val); |
3427 | 3428 | ||
3428 | val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); | 3429 | val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); |