diff options
Diffstat (limited to 'drivers/net/benet/be_cmds.c')
-rw-r--r-- | drivers/net/benet/be_cmds.c | 293 |
1 files changed, 147 insertions, 146 deletions
diff --git a/drivers/net/benet/be_cmds.c b/drivers/net/benet/be_cmds.c index 583517ed56f0..20278b9d5edb 100644 --- a/drivers/net/benet/be_cmds.c +++ b/drivers/net/benet/be_cmds.c | |||
@@ -16,15 +16,16 @@ | |||
16 | */ | 16 | */ |
17 | 17 | ||
18 | #include "be.h" | 18 | #include "be.h" |
19 | #include "be_cmds.h" | ||
19 | 20 | ||
20 | static void be_mcc_notify(struct be_ctrl_info *ctrl) | 21 | static void be_mcc_notify(struct be_adapter *adapter) |
21 | { | 22 | { |
22 | struct be_queue_info *mccq = &ctrl->mcc_obj.q; | 23 | struct be_queue_info *mccq = &adapter->mcc_obj.q; |
23 | u32 val = 0; | 24 | u32 val = 0; |
24 | 25 | ||
25 | val |= mccq->id & DB_MCCQ_RING_ID_MASK; | 26 | val |= mccq->id & DB_MCCQ_RING_ID_MASK; |
26 | val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; | 27 | val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; |
27 | iowrite32(val, ctrl->db + DB_MCCQ_OFFSET); | 28 | iowrite32(val, adapter->db + DB_MCCQ_OFFSET); |
28 | } | 29 | } |
29 | 30 | ||
30 | /* To check if valid bit is set, check the entire word as we don't know | 31 | /* To check if valid bit is set, check the entire word as we don't know |
@@ -47,7 +48,7 @@ static inline void be_mcc_compl_use(struct be_mcc_cq_entry *compl) | |||
47 | compl->flags = 0; | 48 | compl->flags = 0; |
48 | } | 49 | } |
49 | 50 | ||
50 | static int be_mcc_compl_process(struct be_ctrl_info *ctrl, | 51 | static int be_mcc_compl_process(struct be_adapter *adapter, |
51 | struct be_mcc_cq_entry *compl) | 52 | struct be_mcc_cq_entry *compl) |
52 | { | 53 | { |
53 | u16 compl_status, extd_status; | 54 | u16 compl_status, extd_status; |
@@ -70,11 +71,11 @@ static int be_mcc_compl_process(struct be_ctrl_info *ctrl, | |||
70 | } | 71 | } |
71 | 72 | ||
72 | /* Link state evt is a string of bytes; no need for endian swapping */ | 73 | /* Link state evt is a string of bytes; no need for endian swapping */ |
73 | static void be_async_link_state_process(struct be_ctrl_info *ctrl, | 74 | static void be_async_link_state_process(struct be_adapter *adapter, |
74 | struct be_async_event_link_state *evt) | 75 | struct be_async_event_link_state *evt) |
75 | { | 76 | { |
76 | ctrl->async_cb(ctrl->adapter_ctxt, | 77 | be_link_status_update(adapter, |
77 | evt->port_link_status == ASYNC_EVENT_LINK_UP ? true : false); | 78 | evt->port_link_status == ASYNC_EVENT_LINK_UP); |
78 | } | 79 | } |
79 | 80 | ||
80 | static inline bool is_link_state_evt(u32 trailer) | 81 | static inline bool is_link_state_evt(u32 trailer) |
@@ -84,9 +85,9 @@ static inline bool is_link_state_evt(u32 trailer) | |||
84 | ASYNC_EVENT_CODE_LINK_STATE); | 85 | ASYNC_EVENT_CODE_LINK_STATE); |
85 | } | 86 | } |
86 | 87 | ||
87 | static struct be_mcc_cq_entry *be_mcc_compl_get(struct be_ctrl_info *ctrl) | 88 | static struct be_mcc_cq_entry *be_mcc_compl_get(struct be_adapter *adapter) |
88 | { | 89 | { |
89 | struct be_queue_info *mcc_cq = &ctrl->mcc_obj.cq; | 90 | struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq; |
90 | struct be_mcc_cq_entry *compl = queue_tail_node(mcc_cq); | 91 | struct be_mcc_cq_entry *compl = queue_tail_node(mcc_cq); |
91 | 92 | ||
92 | if (be_mcc_compl_is_new(compl)) { | 93 | if (be_mcc_compl_is_new(compl)) { |
@@ -96,40 +97,40 @@ static struct be_mcc_cq_entry *be_mcc_compl_get(struct be_ctrl_info *ctrl) | |||
96 | return NULL; | 97 | return NULL; |
97 | } | 98 | } |
98 | 99 | ||
99 | void be_process_mcc(struct be_ctrl_info *ctrl) | 100 | void be_process_mcc(struct be_adapter *adapter) |
100 | { | 101 | { |
101 | struct be_mcc_cq_entry *compl; | 102 | struct be_mcc_cq_entry *compl; |
102 | int num = 0; | 103 | int num = 0; |
103 | 104 | ||
104 | spin_lock_bh(&ctrl->mcc_cq_lock); | 105 | spin_lock_bh(&adapter->mcc_cq_lock); |
105 | while ((compl = be_mcc_compl_get(ctrl))) { | 106 | while ((compl = be_mcc_compl_get(adapter))) { |
106 | if (compl->flags & CQE_FLAGS_ASYNC_MASK) { | 107 | if (compl->flags & CQE_FLAGS_ASYNC_MASK) { |
107 | /* Interpret flags as an async trailer */ | 108 | /* Interpret flags as an async trailer */ |
108 | BUG_ON(!is_link_state_evt(compl->flags)); | 109 | BUG_ON(!is_link_state_evt(compl->flags)); |
109 | 110 | ||
110 | /* Interpret compl as a async link evt */ | 111 | /* Interpret compl as a async link evt */ |
111 | be_async_link_state_process(ctrl, | 112 | be_async_link_state_process(adapter, |
112 | (struct be_async_event_link_state *) compl); | 113 | (struct be_async_event_link_state *) compl); |
113 | } else { | 114 | } else { |
114 | be_mcc_compl_process(ctrl, compl); | 115 | be_mcc_compl_process(adapter, compl); |
115 | atomic_dec(&ctrl->mcc_obj.q.used); | 116 | atomic_dec(&adapter->mcc_obj.q.used); |
116 | } | 117 | } |
117 | be_mcc_compl_use(compl); | 118 | be_mcc_compl_use(compl); |
118 | num++; | 119 | num++; |
119 | } | 120 | } |
120 | if (num) | 121 | if (num) |
121 | be_cq_notify(ctrl, ctrl->mcc_obj.cq.id, true, num); | 122 | be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, num); |
122 | spin_unlock_bh(&ctrl->mcc_cq_lock); | 123 | spin_unlock_bh(&adapter->mcc_cq_lock); |
123 | } | 124 | } |
124 | 125 | ||
125 | /* Wait till no more pending mcc requests are present */ | 126 | /* Wait till no more pending mcc requests are present */ |
126 | static void be_mcc_wait_compl(struct be_ctrl_info *ctrl) | 127 | static void be_mcc_wait_compl(struct be_adapter *adapter) |
127 | { | 128 | { |
128 | #define mcc_timeout 50000 /* 5s timeout */ | 129 | #define mcc_timeout 50000 /* 5s timeout */ |
129 | int i; | 130 | int i; |
130 | for (i = 0; i < mcc_timeout; i++) { | 131 | for (i = 0; i < mcc_timeout; i++) { |
131 | be_process_mcc(ctrl); | 132 | be_process_mcc(adapter); |
132 | if (atomic_read(&ctrl->mcc_obj.q.used) == 0) | 133 | if (atomic_read(&adapter->mcc_obj.q.used) == 0) |
133 | break; | 134 | break; |
134 | udelay(100); | 135 | udelay(100); |
135 | } | 136 | } |
@@ -138,10 +139,10 @@ static void be_mcc_wait_compl(struct be_ctrl_info *ctrl) | |||
138 | } | 139 | } |
139 | 140 | ||
140 | /* Notify MCC requests and wait for completion */ | 141 | /* Notify MCC requests and wait for completion */ |
141 | static void be_mcc_notify_wait(struct be_ctrl_info *ctrl) | 142 | static void be_mcc_notify_wait(struct be_adapter *adapter) |
142 | { | 143 | { |
143 | be_mcc_notify(ctrl); | 144 | be_mcc_notify(adapter); |
144 | be_mcc_wait_compl(ctrl); | 145 | be_mcc_wait_compl(adapter); |
145 | } | 146 | } |
146 | 147 | ||
147 | static int be_mbox_db_ready_wait(void __iomem *db) | 148 | static int be_mbox_db_ready_wait(void __iomem *db) |
@@ -173,12 +174,12 @@ static int be_mbox_db_ready_wait(void __iomem *db) | |||
173 | * Insert the mailbox address into the doorbell in two steps | 174 | * Insert the mailbox address into the doorbell in two steps |
174 | * Polls on the mbox doorbell till a command completion (or a timeout) occurs | 175 | * Polls on the mbox doorbell till a command completion (or a timeout) occurs |
175 | */ | 176 | */ |
176 | static int be_mbox_db_ring(struct be_ctrl_info *ctrl) | 177 | static int be_mbox_db_ring(struct be_adapter *adapter) |
177 | { | 178 | { |
178 | int status; | 179 | int status; |
179 | u32 val = 0; | 180 | u32 val = 0; |
180 | void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET; | 181 | void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET; |
181 | struct be_dma_mem *mbox_mem = &ctrl->mbox_mem; | 182 | struct be_dma_mem *mbox_mem = &adapter->mbox_mem; |
182 | struct be_mcc_mailbox *mbox = mbox_mem->va; | 183 | struct be_mcc_mailbox *mbox = mbox_mem->va; |
183 | struct be_mcc_cq_entry *cqe = &mbox->cqe; | 184 | struct be_mcc_cq_entry *cqe = &mbox->cqe; |
184 | 185 | ||
@@ -208,7 +209,7 @@ static int be_mbox_db_ring(struct be_ctrl_info *ctrl) | |||
208 | 209 | ||
209 | /* A cq entry has been made now */ | 210 | /* A cq entry has been made now */ |
210 | if (be_mcc_compl_is_new(cqe)) { | 211 | if (be_mcc_compl_is_new(cqe)) { |
211 | status = be_mcc_compl_process(ctrl, &mbox->cqe); | 212 | status = be_mcc_compl_process(adapter, &mbox->cqe); |
212 | be_mcc_compl_use(cqe); | 213 | be_mcc_compl_use(cqe); |
213 | if (status) | 214 | if (status) |
214 | return status; | 215 | return status; |
@@ -219,9 +220,9 @@ static int be_mbox_db_ring(struct be_ctrl_info *ctrl) | |||
219 | return 0; | 220 | return 0; |
220 | } | 221 | } |
221 | 222 | ||
222 | static int be_POST_stage_get(struct be_ctrl_info *ctrl, u16 *stage) | 223 | static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage) |
223 | { | 224 | { |
224 | u32 sem = ioread32(ctrl->csr + MPU_EP_SEMAPHORE_OFFSET); | 225 | u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET); |
225 | 226 | ||
226 | *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK; | 227 | *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK; |
227 | if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK) | 228 | if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK) |
@@ -230,11 +231,11 @@ static int be_POST_stage_get(struct be_ctrl_info *ctrl, u16 *stage) | |||
230 | return 0; | 231 | return 0; |
231 | } | 232 | } |
232 | 233 | ||
233 | static int be_POST_stage_poll(struct be_ctrl_info *ctrl, u16 poll_stage) | 234 | static int be_POST_stage_poll(struct be_adapter *adapter, u16 poll_stage) |
234 | { | 235 | { |
235 | u16 stage, cnt, error; | 236 | u16 stage, cnt, error; |
236 | for (cnt = 0; cnt < 5000; cnt++) { | 237 | for (cnt = 0; cnt < 5000; cnt++) { |
237 | error = be_POST_stage_get(ctrl, &stage); | 238 | error = be_POST_stage_get(adapter, &stage); |
238 | if (error) | 239 | if (error) |
239 | return -1; | 240 | return -1; |
240 | 241 | ||
@@ -248,11 +249,11 @@ static int be_POST_stage_poll(struct be_ctrl_info *ctrl, u16 poll_stage) | |||
248 | } | 249 | } |
249 | 250 | ||
250 | 251 | ||
251 | int be_cmd_POST(struct be_ctrl_info *ctrl) | 252 | int be_cmd_POST(struct be_adapter *adapter) |
252 | { | 253 | { |
253 | u16 stage, error; | 254 | u16 stage, error; |
254 | 255 | ||
255 | error = be_POST_stage_get(ctrl, &stage); | 256 | error = be_POST_stage_get(adapter, &stage); |
256 | if (error) | 257 | if (error) |
257 | goto err; | 258 | goto err; |
258 | 259 | ||
@@ -263,14 +264,14 @@ int be_cmd_POST(struct be_ctrl_info *ctrl) | |||
263 | goto err; | 264 | goto err; |
264 | 265 | ||
265 | /* On awaiting host rdy, reset and again poll on awaiting host rdy */ | 266 | /* On awaiting host rdy, reset and again poll on awaiting host rdy */ |
266 | iowrite32(POST_STAGE_BE_RESET, ctrl->csr + MPU_EP_SEMAPHORE_OFFSET); | 267 | iowrite32(POST_STAGE_BE_RESET, adapter->csr + MPU_EP_SEMAPHORE_OFFSET); |
267 | error = be_POST_stage_poll(ctrl, POST_STAGE_AWAITING_HOST_RDY); | 268 | error = be_POST_stage_poll(adapter, POST_STAGE_AWAITING_HOST_RDY); |
268 | if (error) | 269 | if (error) |
269 | goto err; | 270 | goto err; |
270 | 271 | ||
271 | /* Now kickoff POST and poll on armfw ready */ | 272 | /* Now kickoff POST and poll on armfw ready */ |
272 | iowrite32(POST_STAGE_HOST_RDY, ctrl->csr + MPU_EP_SEMAPHORE_OFFSET); | 273 | iowrite32(POST_STAGE_HOST_RDY, adapter->csr + MPU_EP_SEMAPHORE_OFFSET); |
273 | error = be_POST_stage_poll(ctrl, POST_STAGE_ARMFW_RDY); | 274 | error = be_POST_stage_poll(adapter, POST_STAGE_ARMFW_RDY); |
274 | if (error) | 275 | if (error) |
275 | goto err; | 276 | goto err; |
276 | 277 | ||
@@ -367,16 +368,16 @@ static inline struct be_mcc_wrb *wrb_from_mcc(struct be_queue_info *mccq) | |||
367 | return wrb; | 368 | return wrb; |
368 | } | 369 | } |
369 | 370 | ||
370 | int be_cmd_eq_create(struct be_ctrl_info *ctrl, | 371 | int be_cmd_eq_create(struct be_adapter *adapter, |
371 | struct be_queue_info *eq, int eq_delay) | 372 | struct be_queue_info *eq, int eq_delay) |
372 | { | 373 | { |
373 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 374 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
374 | struct be_cmd_req_eq_create *req = embedded_payload(wrb); | 375 | struct be_cmd_req_eq_create *req = embedded_payload(wrb); |
375 | struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); | 376 | struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); |
376 | struct be_dma_mem *q_mem = &eq->dma_mem; | 377 | struct be_dma_mem *q_mem = &eq->dma_mem; |
377 | int status; | 378 | int status; |
378 | 379 | ||
379 | spin_lock(&ctrl->mbox_lock); | 380 | spin_lock(&adapter->mbox_lock); |
380 | memset(wrb, 0, sizeof(*wrb)); | 381 | memset(wrb, 0, sizeof(*wrb)); |
381 | 382 | ||
382 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | 383 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); |
@@ -387,7 +388,7 @@ int be_cmd_eq_create(struct be_ctrl_info *ctrl, | |||
387 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | 388 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); |
388 | 389 | ||
389 | AMAP_SET_BITS(struct amap_eq_context, func, req->context, | 390 | AMAP_SET_BITS(struct amap_eq_context, func, req->context, |
390 | ctrl->pci_func); | 391 | adapter->pci_func); |
391 | AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); | 392 | AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); |
392 | /* 4byte eqe*/ | 393 | /* 4byte eqe*/ |
393 | AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); | 394 | AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); |
@@ -399,24 +400,24 @@ int be_cmd_eq_create(struct be_ctrl_info *ctrl, | |||
399 | 400 | ||
400 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | 401 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); |
401 | 402 | ||
402 | status = be_mbox_db_ring(ctrl); | 403 | status = be_mbox_db_ring(adapter); |
403 | if (!status) { | 404 | if (!status) { |
404 | eq->id = le16_to_cpu(resp->eq_id); | 405 | eq->id = le16_to_cpu(resp->eq_id); |
405 | eq->created = true; | 406 | eq->created = true; |
406 | } | 407 | } |
407 | spin_unlock(&ctrl->mbox_lock); | 408 | spin_unlock(&adapter->mbox_lock); |
408 | return status; | 409 | return status; |
409 | } | 410 | } |
410 | 411 | ||
411 | int be_cmd_mac_addr_query(struct be_ctrl_info *ctrl, u8 *mac_addr, | 412 | int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, |
412 | u8 type, bool permanent, u32 if_handle) | 413 | u8 type, bool permanent, u32 if_handle) |
413 | { | 414 | { |
414 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 415 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
415 | struct be_cmd_req_mac_query *req = embedded_payload(wrb); | 416 | struct be_cmd_req_mac_query *req = embedded_payload(wrb); |
416 | struct be_cmd_resp_mac_query *resp = embedded_payload(wrb); | 417 | struct be_cmd_resp_mac_query *resp = embedded_payload(wrb); |
417 | int status; | 418 | int status; |
418 | 419 | ||
419 | spin_lock(&ctrl->mbox_lock); | 420 | spin_lock(&adapter->mbox_lock); |
420 | memset(wrb, 0, sizeof(*wrb)); | 421 | memset(wrb, 0, sizeof(*wrb)); |
421 | 422 | ||
422 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | 423 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); |
@@ -432,22 +433,22 @@ int be_cmd_mac_addr_query(struct be_ctrl_info *ctrl, u8 *mac_addr, | |||
432 | req->permanent = 0; | 433 | req->permanent = 0; |
433 | } | 434 | } |
434 | 435 | ||
435 | status = be_mbox_db_ring(ctrl); | 436 | status = be_mbox_db_ring(adapter); |
436 | if (!status) | 437 | if (!status) |
437 | memcpy(mac_addr, resp->mac.addr, ETH_ALEN); | 438 | memcpy(mac_addr, resp->mac.addr, ETH_ALEN); |
438 | 439 | ||
439 | spin_unlock(&ctrl->mbox_lock); | 440 | spin_unlock(&adapter->mbox_lock); |
440 | return status; | 441 | return status; |
441 | } | 442 | } |
442 | 443 | ||
443 | int be_cmd_pmac_add(struct be_ctrl_info *ctrl, u8 *mac_addr, | 444 | int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, |
444 | u32 if_id, u32 *pmac_id) | 445 | u32 if_id, u32 *pmac_id) |
445 | { | 446 | { |
446 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 447 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
447 | struct be_cmd_req_pmac_add *req = embedded_payload(wrb); | 448 | struct be_cmd_req_pmac_add *req = embedded_payload(wrb); |
448 | int status; | 449 | int status; |
449 | 450 | ||
450 | spin_lock(&ctrl->mbox_lock); | 451 | spin_lock(&adapter->mbox_lock); |
451 | memset(wrb, 0, sizeof(*wrb)); | 452 | memset(wrb, 0, sizeof(*wrb)); |
452 | 453 | ||
453 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | 454 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); |
@@ -458,23 +459,23 @@ int be_cmd_pmac_add(struct be_ctrl_info *ctrl, u8 *mac_addr, | |||
458 | req->if_id = cpu_to_le32(if_id); | 459 | req->if_id = cpu_to_le32(if_id); |
459 | memcpy(req->mac_address, mac_addr, ETH_ALEN); | 460 | memcpy(req->mac_address, mac_addr, ETH_ALEN); |
460 | 461 | ||
461 | status = be_mbox_db_ring(ctrl); | 462 | status = be_mbox_db_ring(adapter); |
462 | if (!status) { | 463 | if (!status) { |
463 | struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb); | 464 | struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb); |
464 | *pmac_id = le32_to_cpu(resp->pmac_id); | 465 | *pmac_id = le32_to_cpu(resp->pmac_id); |
465 | } | 466 | } |
466 | 467 | ||
467 | spin_unlock(&ctrl->mbox_lock); | 468 | spin_unlock(&adapter->mbox_lock); |
468 | return status; | 469 | return status; |
469 | } | 470 | } |
470 | 471 | ||
471 | int be_cmd_pmac_del(struct be_ctrl_info *ctrl, u32 if_id, u32 pmac_id) | 472 | int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id) |
472 | { | 473 | { |
473 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 474 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
474 | struct be_cmd_req_pmac_del *req = embedded_payload(wrb); | 475 | struct be_cmd_req_pmac_del *req = embedded_payload(wrb); |
475 | int status; | 476 | int status; |
476 | 477 | ||
477 | spin_lock(&ctrl->mbox_lock); | 478 | spin_lock(&adapter->mbox_lock); |
478 | memset(wrb, 0, sizeof(*wrb)); | 479 | memset(wrb, 0, sizeof(*wrb)); |
479 | 480 | ||
480 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | 481 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); |
@@ -485,24 +486,24 @@ int be_cmd_pmac_del(struct be_ctrl_info *ctrl, u32 if_id, u32 pmac_id) | |||
485 | req->if_id = cpu_to_le32(if_id); | 486 | req->if_id = cpu_to_le32(if_id); |
486 | req->pmac_id = cpu_to_le32(pmac_id); | 487 | req->pmac_id = cpu_to_le32(pmac_id); |
487 | 488 | ||
488 | status = be_mbox_db_ring(ctrl); | 489 | status = be_mbox_db_ring(adapter); |
489 | spin_unlock(&ctrl->mbox_lock); | 490 | spin_unlock(&adapter->mbox_lock); |
490 | 491 | ||
491 | return status; | 492 | return status; |
492 | } | 493 | } |
493 | 494 | ||
494 | int be_cmd_cq_create(struct be_ctrl_info *ctrl, | 495 | int be_cmd_cq_create(struct be_adapter *adapter, |
495 | struct be_queue_info *cq, struct be_queue_info *eq, | 496 | struct be_queue_info *cq, struct be_queue_info *eq, |
496 | bool sol_evts, bool no_delay, int coalesce_wm) | 497 | bool sol_evts, bool no_delay, int coalesce_wm) |
497 | { | 498 | { |
498 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 499 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
499 | struct be_cmd_req_cq_create *req = embedded_payload(wrb); | 500 | struct be_cmd_req_cq_create *req = embedded_payload(wrb); |
500 | struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); | 501 | struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); |
501 | struct be_dma_mem *q_mem = &cq->dma_mem; | 502 | struct be_dma_mem *q_mem = &cq->dma_mem; |
502 | void *ctxt = &req->context; | 503 | void *ctxt = &req->context; |
503 | int status; | 504 | int status; |
504 | 505 | ||
505 | spin_lock(&ctrl->mbox_lock); | 506 | spin_lock(&adapter->mbox_lock); |
506 | memset(wrb, 0, sizeof(*wrb)); | 507 | memset(wrb, 0, sizeof(*wrb)); |
507 | 508 | ||
508 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | 509 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); |
@@ -521,17 +522,17 @@ int be_cmd_cq_create(struct be_ctrl_info *ctrl, | |||
521 | AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1); | 522 | AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1); |
522 | AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id); | 523 | AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id); |
523 | AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1); | 524 | AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1); |
524 | AMAP_SET_BITS(struct amap_cq_context, func, ctxt, ctrl->pci_func); | 525 | AMAP_SET_BITS(struct amap_cq_context, func, ctxt, adapter->pci_func); |
525 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | 526 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); |
526 | 527 | ||
527 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | 528 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); |
528 | 529 | ||
529 | status = be_mbox_db_ring(ctrl); | 530 | status = be_mbox_db_ring(adapter); |
530 | if (!status) { | 531 | if (!status) { |
531 | cq->id = le16_to_cpu(resp->cq_id); | 532 | cq->id = le16_to_cpu(resp->cq_id); |
532 | cq->created = true; | 533 | cq->created = true; |
533 | } | 534 | } |
534 | spin_unlock(&ctrl->mbox_lock); | 535 | spin_unlock(&adapter->mbox_lock); |
535 | 536 | ||
536 | return status; | 537 | return status; |
537 | } | 538 | } |
@@ -544,17 +545,17 @@ static u32 be_encoded_q_len(int q_len) | |||
544 | return len_encoded; | 545 | return len_encoded; |
545 | } | 546 | } |
546 | 547 | ||
547 | int be_cmd_mccq_create(struct be_ctrl_info *ctrl, | 548 | int be_cmd_mccq_create(struct be_adapter *adapter, |
548 | struct be_queue_info *mccq, | 549 | struct be_queue_info *mccq, |
549 | struct be_queue_info *cq) | 550 | struct be_queue_info *cq) |
550 | { | 551 | { |
551 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 552 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
552 | struct be_cmd_req_mcc_create *req = embedded_payload(wrb); | 553 | struct be_cmd_req_mcc_create *req = embedded_payload(wrb); |
553 | struct be_dma_mem *q_mem = &mccq->dma_mem; | 554 | struct be_dma_mem *q_mem = &mccq->dma_mem; |
554 | void *ctxt = &req->context; | 555 | void *ctxt = &req->context; |
555 | int status; | 556 | int status; |
556 | 557 | ||
557 | spin_lock(&ctrl->mbox_lock); | 558 | spin_lock(&adapter->mbox_lock); |
558 | memset(wrb, 0, sizeof(*wrb)); | 559 | memset(wrb, 0, sizeof(*wrb)); |
559 | 560 | ||
560 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | 561 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); |
@@ -564,7 +565,7 @@ int be_cmd_mccq_create(struct be_ctrl_info *ctrl, | |||
564 | 565 | ||
565 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | 566 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); |
566 | 567 | ||
567 | AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, ctrl->pci_func); | 568 | AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, adapter->pci_func); |
568 | AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1); | 569 | AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1); |
569 | AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt, | 570 | AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt, |
570 | be_encoded_q_len(mccq->len)); | 571 | be_encoded_q_len(mccq->len)); |
@@ -574,29 +575,29 @@ int be_cmd_mccq_create(struct be_ctrl_info *ctrl, | |||
574 | 575 | ||
575 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | 576 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); |
576 | 577 | ||
577 | status = be_mbox_db_ring(ctrl); | 578 | status = be_mbox_db_ring(adapter); |
578 | if (!status) { | 579 | if (!status) { |
579 | struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); | 580 | struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); |
580 | mccq->id = le16_to_cpu(resp->id); | 581 | mccq->id = le16_to_cpu(resp->id); |
581 | mccq->created = true; | 582 | mccq->created = true; |
582 | } | 583 | } |
583 | spin_unlock(&ctrl->mbox_lock); | 584 | spin_unlock(&adapter->mbox_lock); |
584 | 585 | ||
585 | return status; | 586 | return status; |
586 | } | 587 | } |
587 | 588 | ||
588 | int be_cmd_txq_create(struct be_ctrl_info *ctrl, | 589 | int be_cmd_txq_create(struct be_adapter *adapter, |
589 | struct be_queue_info *txq, | 590 | struct be_queue_info *txq, |
590 | struct be_queue_info *cq) | 591 | struct be_queue_info *cq) |
591 | { | 592 | { |
592 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 593 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
593 | struct be_cmd_req_eth_tx_create *req = embedded_payload(wrb); | 594 | struct be_cmd_req_eth_tx_create *req = embedded_payload(wrb); |
594 | struct be_dma_mem *q_mem = &txq->dma_mem; | 595 | struct be_dma_mem *q_mem = &txq->dma_mem; |
595 | void *ctxt = &req->context; | 596 | void *ctxt = &req->context; |
596 | int status; | 597 | int status; |
597 | u32 len_encoded; | 598 | u32 len_encoded; |
598 | 599 | ||
599 | spin_lock(&ctrl->mbox_lock); | 600 | spin_lock(&adapter->mbox_lock); |
600 | memset(wrb, 0, sizeof(*wrb)); | 601 | memset(wrb, 0, sizeof(*wrb)); |
601 | 602 | ||
602 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | 603 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); |
@@ -613,7 +614,7 @@ int be_cmd_txq_create(struct be_ctrl_info *ctrl, | |||
613 | len_encoded = 0; | 614 | len_encoded = 0; |
614 | AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, len_encoded); | 615 | AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, len_encoded); |
615 | AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt, | 616 | AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt, |
616 | ctrl->pci_func); | 617 | adapter->pci_func); |
617 | AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1); | 618 | AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1); |
618 | AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id); | 619 | AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id); |
619 | 620 | ||
@@ -621,27 +622,27 @@ int be_cmd_txq_create(struct be_ctrl_info *ctrl, | |||
621 | 622 | ||
622 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | 623 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); |
623 | 624 | ||
624 | status = be_mbox_db_ring(ctrl); | 625 | status = be_mbox_db_ring(adapter); |
625 | if (!status) { | 626 | if (!status) { |
626 | struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb); | 627 | struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb); |
627 | txq->id = le16_to_cpu(resp->cid); | 628 | txq->id = le16_to_cpu(resp->cid); |
628 | txq->created = true; | 629 | txq->created = true; |
629 | } | 630 | } |
630 | spin_unlock(&ctrl->mbox_lock); | 631 | spin_unlock(&adapter->mbox_lock); |
631 | 632 | ||
632 | return status; | 633 | return status; |
633 | } | 634 | } |
634 | 635 | ||
635 | int be_cmd_rxq_create(struct be_ctrl_info *ctrl, | 636 | int be_cmd_rxq_create(struct be_adapter *adapter, |
636 | struct be_queue_info *rxq, u16 cq_id, u16 frag_size, | 637 | struct be_queue_info *rxq, u16 cq_id, u16 frag_size, |
637 | u16 max_frame_size, u32 if_id, u32 rss) | 638 | u16 max_frame_size, u32 if_id, u32 rss) |
638 | { | 639 | { |
639 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 640 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
640 | struct be_cmd_req_eth_rx_create *req = embedded_payload(wrb); | 641 | struct be_cmd_req_eth_rx_create *req = embedded_payload(wrb); |
641 | struct be_dma_mem *q_mem = &rxq->dma_mem; | 642 | struct be_dma_mem *q_mem = &rxq->dma_mem; |
642 | int status; | 643 | int status; |
643 | 644 | ||
644 | spin_lock(&ctrl->mbox_lock); | 645 | spin_lock(&adapter->mbox_lock); |
645 | memset(wrb, 0, sizeof(*wrb)); | 646 | memset(wrb, 0, sizeof(*wrb)); |
646 | 647 | ||
647 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | 648 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); |
@@ -657,27 +658,27 @@ int be_cmd_rxq_create(struct be_ctrl_info *ctrl, | |||
657 | req->max_frame_size = cpu_to_le16(max_frame_size); | 658 | req->max_frame_size = cpu_to_le16(max_frame_size); |
658 | req->rss_queue = cpu_to_le32(rss); | 659 | req->rss_queue = cpu_to_le32(rss); |
659 | 660 | ||
660 | status = be_mbox_db_ring(ctrl); | 661 | status = be_mbox_db_ring(adapter); |
661 | if (!status) { | 662 | if (!status) { |
662 | struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb); | 663 | struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb); |
663 | rxq->id = le16_to_cpu(resp->id); | 664 | rxq->id = le16_to_cpu(resp->id); |
664 | rxq->created = true; | 665 | rxq->created = true; |
665 | } | 666 | } |
666 | spin_unlock(&ctrl->mbox_lock); | 667 | spin_unlock(&adapter->mbox_lock); |
667 | 668 | ||
668 | return status; | 669 | return status; |
669 | } | 670 | } |
670 | 671 | ||
671 | /* Generic destroyer function for all types of queues */ | 672 | /* Generic destroyer function for all types of queues */ |
672 | int be_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, | 673 | int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, |
673 | int queue_type) | 674 | int queue_type) |
674 | { | 675 | { |
675 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 676 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
676 | struct be_cmd_req_q_destroy *req = embedded_payload(wrb); | 677 | struct be_cmd_req_q_destroy *req = embedded_payload(wrb); |
677 | u8 subsys = 0, opcode = 0; | 678 | u8 subsys = 0, opcode = 0; |
678 | int status; | 679 | int status; |
679 | 680 | ||
680 | spin_lock(&ctrl->mbox_lock); | 681 | spin_lock(&adapter->mbox_lock); |
681 | 682 | ||
682 | memset(wrb, 0, sizeof(*wrb)); | 683 | memset(wrb, 0, sizeof(*wrb)); |
683 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | 684 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); |
@@ -711,22 +712,22 @@ int be_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, | |||
711 | be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req)); | 712 | be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req)); |
712 | req->id = cpu_to_le16(q->id); | 713 | req->id = cpu_to_le16(q->id); |
713 | 714 | ||
714 | status = be_mbox_db_ring(ctrl); | 715 | status = be_mbox_db_ring(adapter); |
715 | err: | 716 | err: |
716 | spin_unlock(&ctrl->mbox_lock); | 717 | spin_unlock(&adapter->mbox_lock); |
717 | 718 | ||
718 | return status; | 719 | return status; |
719 | } | 720 | } |
720 | 721 | ||
721 | /* Create an rx filtering policy configuration on an i/f */ | 722 | /* Create an rx filtering policy configuration on an i/f */ |
722 | int be_cmd_if_create(struct be_ctrl_info *ctrl, u32 flags, u8 *mac, | 723 | int be_cmd_if_create(struct be_adapter *adapter, u32 flags, u8 *mac, |
723 | bool pmac_invalid, u32 *if_handle, u32 *pmac_id) | 724 | bool pmac_invalid, u32 *if_handle, u32 *pmac_id) |
724 | { | 725 | { |
725 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 726 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
726 | struct be_cmd_req_if_create *req = embedded_payload(wrb); | 727 | struct be_cmd_req_if_create *req = embedded_payload(wrb); |
727 | int status; | 728 | int status; |
728 | 729 | ||
729 | spin_lock(&ctrl->mbox_lock); | 730 | spin_lock(&adapter->mbox_lock); |
730 | memset(wrb, 0, sizeof(*wrb)); | 731 | memset(wrb, 0, sizeof(*wrb)); |
731 | 732 | ||
732 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | 733 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); |
@@ -739,7 +740,7 @@ int be_cmd_if_create(struct be_ctrl_info *ctrl, u32 flags, u8 *mac, | |||
739 | if (!pmac_invalid) | 740 | if (!pmac_invalid) |
740 | memcpy(req->mac_addr, mac, ETH_ALEN); | 741 | memcpy(req->mac_addr, mac, ETH_ALEN); |
741 | 742 | ||
742 | status = be_mbox_db_ring(ctrl); | 743 | status = be_mbox_db_ring(adapter); |
743 | if (!status) { | 744 | if (!status) { |
744 | struct be_cmd_resp_if_create *resp = embedded_payload(wrb); | 745 | struct be_cmd_resp_if_create *resp = embedded_payload(wrb); |
745 | *if_handle = le32_to_cpu(resp->interface_id); | 746 | *if_handle = le32_to_cpu(resp->interface_id); |
@@ -747,17 +748,17 @@ int be_cmd_if_create(struct be_ctrl_info *ctrl, u32 flags, u8 *mac, | |||
747 | *pmac_id = le32_to_cpu(resp->pmac_id); | 748 | *pmac_id = le32_to_cpu(resp->pmac_id); |
748 | } | 749 | } |
749 | 750 | ||
750 | spin_unlock(&ctrl->mbox_lock); | 751 | spin_unlock(&adapter->mbox_lock); |
751 | return status; | 752 | return status; |
752 | } | 753 | } |
753 | 754 | ||
754 | int be_cmd_if_destroy(struct be_ctrl_info *ctrl, u32 interface_id) | 755 | int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id) |
755 | { | 756 | { |
756 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 757 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
757 | struct be_cmd_req_if_destroy *req = embedded_payload(wrb); | 758 | struct be_cmd_req_if_destroy *req = embedded_payload(wrb); |
758 | int status; | 759 | int status; |
759 | 760 | ||
760 | spin_lock(&ctrl->mbox_lock); | 761 | spin_lock(&adapter->mbox_lock); |
761 | memset(wrb, 0, sizeof(*wrb)); | 762 | memset(wrb, 0, sizeof(*wrb)); |
762 | 763 | ||
763 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | 764 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); |
@@ -766,9 +767,9 @@ int be_cmd_if_destroy(struct be_ctrl_info *ctrl, u32 interface_id) | |||
766 | OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req)); | 767 | OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req)); |
767 | 768 | ||
768 | req->interface_id = cpu_to_le32(interface_id); | 769 | req->interface_id = cpu_to_le32(interface_id); |
769 | status = be_mbox_db_ring(ctrl); | 770 | status = be_mbox_db_ring(adapter); |
770 | 771 | ||
771 | spin_unlock(&ctrl->mbox_lock); | 772 | spin_unlock(&adapter->mbox_lock); |
772 | 773 | ||
773 | return status; | 774 | return status; |
774 | } | 775 | } |
@@ -776,14 +777,14 @@ int be_cmd_if_destroy(struct be_ctrl_info *ctrl, u32 interface_id) | |||
776 | /* Get stats is a non embedded command: the request is not embedded inside | 777 | /* Get stats is a non embedded command: the request is not embedded inside |
777 | * WRB but is a separate dma memory block | 778 | * WRB but is a separate dma memory block |
778 | */ | 779 | */ |
779 | int be_cmd_get_stats(struct be_ctrl_info *ctrl, struct be_dma_mem *nonemb_cmd) | 780 | int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd) |
780 | { | 781 | { |
781 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 782 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
782 | struct be_cmd_req_get_stats *req = nonemb_cmd->va; | 783 | struct be_cmd_req_get_stats *req = nonemb_cmd->va; |
783 | struct be_sge *sge = nonembedded_sgl(wrb); | 784 | struct be_sge *sge = nonembedded_sgl(wrb); |
784 | int status; | 785 | int status; |
785 | 786 | ||
786 | spin_lock(&ctrl->mbox_lock); | 787 | spin_lock(&adapter->mbox_lock); |
787 | memset(wrb, 0, sizeof(*wrb)); | 788 | memset(wrb, 0, sizeof(*wrb)); |
788 | 789 | ||
789 | memset(req, 0, sizeof(*req)); | 790 | memset(req, 0, sizeof(*req)); |
@@ -796,24 +797,24 @@ int be_cmd_get_stats(struct be_ctrl_info *ctrl, struct be_dma_mem *nonemb_cmd) | |||
796 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | 797 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); |
797 | sge->len = cpu_to_le32(nonemb_cmd->size); | 798 | sge->len = cpu_to_le32(nonemb_cmd->size); |
798 | 799 | ||
799 | status = be_mbox_db_ring(ctrl); | 800 | status = be_mbox_db_ring(adapter); |
800 | if (!status) { | 801 | if (!status) { |
801 | struct be_cmd_resp_get_stats *resp = nonemb_cmd->va; | 802 | struct be_cmd_resp_get_stats *resp = nonemb_cmd->va; |
802 | be_dws_le_to_cpu(&resp->hw_stats, sizeof(resp->hw_stats)); | 803 | be_dws_le_to_cpu(&resp->hw_stats, sizeof(resp->hw_stats)); |
803 | } | 804 | } |
804 | 805 | ||
805 | spin_unlock(&ctrl->mbox_lock); | 806 | spin_unlock(&adapter->mbox_lock); |
806 | return status; | 807 | return status; |
807 | } | 808 | } |
808 | 809 | ||
809 | int be_cmd_link_status_query(struct be_ctrl_info *ctrl, | 810 | int be_cmd_link_status_query(struct be_adapter *adapter, |
810 | bool *link_up) | 811 | bool *link_up) |
811 | { | 812 | { |
812 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 813 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
813 | struct be_cmd_req_link_status *req = embedded_payload(wrb); | 814 | struct be_cmd_req_link_status *req = embedded_payload(wrb); |
814 | int status; | 815 | int status; |
815 | 816 | ||
816 | spin_lock(&ctrl->mbox_lock); | 817 | spin_lock(&adapter->mbox_lock); |
817 | 818 | ||
818 | *link_up = false; | 819 | *link_up = false; |
819 | memset(wrb, 0, sizeof(*wrb)); | 820 | memset(wrb, 0, sizeof(*wrb)); |
@@ -823,24 +824,24 @@ int be_cmd_link_status_query(struct be_ctrl_info *ctrl, | |||
823 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | 824 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
824 | OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req)); | 825 | OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req)); |
825 | 826 | ||
826 | status = be_mbox_db_ring(ctrl); | 827 | status = be_mbox_db_ring(adapter); |
827 | if (!status) { | 828 | if (!status) { |
828 | struct be_cmd_resp_link_status *resp = embedded_payload(wrb); | 829 | struct be_cmd_resp_link_status *resp = embedded_payload(wrb); |
829 | if (resp->mac_speed != PHY_LINK_SPEED_ZERO) | 830 | if (resp->mac_speed != PHY_LINK_SPEED_ZERO) |
830 | *link_up = true; | 831 | *link_up = true; |
831 | } | 832 | } |
832 | 833 | ||
833 | spin_unlock(&ctrl->mbox_lock); | 834 | spin_unlock(&adapter->mbox_lock); |
834 | return status; | 835 | return status; |
835 | } | 836 | } |
836 | 837 | ||
837 | int be_cmd_get_fw_ver(struct be_ctrl_info *ctrl, char *fw_ver) | 838 | int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver) |
838 | { | 839 | { |
839 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 840 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
840 | struct be_cmd_req_get_fw_version *req = embedded_payload(wrb); | 841 | struct be_cmd_req_get_fw_version *req = embedded_payload(wrb); |
841 | int status; | 842 | int status; |
842 | 843 | ||
843 | spin_lock(&ctrl->mbox_lock); | 844 | spin_lock(&adapter->mbox_lock); |
844 | memset(wrb, 0, sizeof(*wrb)); | 845 | memset(wrb, 0, sizeof(*wrb)); |
845 | 846 | ||
846 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | 847 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); |
@@ -848,24 +849,24 @@ int be_cmd_get_fw_ver(struct be_ctrl_info *ctrl, char *fw_ver) | |||
848 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | 849 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
849 | OPCODE_COMMON_GET_FW_VERSION, sizeof(*req)); | 850 | OPCODE_COMMON_GET_FW_VERSION, sizeof(*req)); |
850 | 851 | ||
851 | status = be_mbox_db_ring(ctrl); | 852 | status = be_mbox_db_ring(adapter); |
852 | if (!status) { | 853 | if (!status) { |
853 | struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); | 854 | struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); |
854 | strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN); | 855 | strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN); |
855 | } | 856 | } |
856 | 857 | ||
857 | spin_unlock(&ctrl->mbox_lock); | 858 | spin_unlock(&adapter->mbox_lock); |
858 | return status; | 859 | return status; |
859 | } | 860 | } |
860 | 861 | ||
861 | /* set the EQ delay interval of an EQ to specified value */ | 862 | /* set the EQ delay interval of an EQ to specified value */ |
862 | int be_cmd_modify_eqd(struct be_ctrl_info *ctrl, u32 eq_id, u32 eqd) | 863 | int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd) |
863 | { | 864 | { |
864 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 865 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
865 | struct be_cmd_req_modify_eq_delay *req = embedded_payload(wrb); | 866 | struct be_cmd_req_modify_eq_delay *req = embedded_payload(wrb); |
866 | int status; | 867 | int status; |
867 | 868 | ||
868 | spin_lock(&ctrl->mbox_lock); | 869 | spin_lock(&adapter->mbox_lock); |
869 | memset(wrb, 0, sizeof(*wrb)); | 870 | memset(wrb, 0, sizeof(*wrb)); |
870 | 871 | ||
871 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | 872 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); |
@@ -878,20 +879,20 @@ int be_cmd_modify_eqd(struct be_ctrl_info *ctrl, u32 eq_id, u32 eqd) | |||
878 | req->delay[0].phase = 0; | 879 | req->delay[0].phase = 0; |
879 | req->delay[0].delay_multiplier = cpu_to_le32(eqd); | 880 | req->delay[0].delay_multiplier = cpu_to_le32(eqd); |
880 | 881 | ||
881 | status = be_mbox_db_ring(ctrl); | 882 | status = be_mbox_db_ring(adapter); |
882 | 883 | ||
883 | spin_unlock(&ctrl->mbox_lock); | 884 | spin_unlock(&adapter->mbox_lock); |
884 | return status; | 885 | return status; |
885 | } | 886 | } |
886 | 887 | ||
887 | int be_cmd_vlan_config(struct be_ctrl_info *ctrl, u32 if_id, u16 *vtag_array, | 888 | int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, |
888 | u32 num, bool untagged, bool promiscuous) | 889 | u32 num, bool untagged, bool promiscuous) |
889 | { | 890 | { |
890 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 891 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
891 | struct be_cmd_req_vlan_config *req = embedded_payload(wrb); | 892 | struct be_cmd_req_vlan_config *req = embedded_payload(wrb); |
892 | int status; | 893 | int status; |
893 | 894 | ||
894 | spin_lock(&ctrl->mbox_lock); | 895 | spin_lock(&adapter->mbox_lock); |
895 | memset(wrb, 0, sizeof(*wrb)); | 896 | memset(wrb, 0, sizeof(*wrb)); |
896 | 897 | ||
897 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | 898 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); |
@@ -908,21 +909,21 @@ int be_cmd_vlan_config(struct be_ctrl_info *ctrl, u32 if_id, u16 *vtag_array, | |||
908 | req->num_vlan * sizeof(vtag_array[0])); | 909 | req->num_vlan * sizeof(vtag_array[0])); |
909 | } | 910 | } |
910 | 911 | ||
911 | status = be_mbox_db_ring(ctrl); | 912 | status = be_mbox_db_ring(adapter); |
912 | 913 | ||
913 | spin_unlock(&ctrl->mbox_lock); | 914 | spin_unlock(&adapter->mbox_lock); |
914 | return status; | 915 | return status; |
915 | } | 916 | } |
916 | 917 | ||
917 | /* Use MCC for this command as it may be called in BH context */ | 918 | /* Use MCC for this command as it may be called in BH context */ |
918 | int be_cmd_promiscuous_config(struct be_ctrl_info *ctrl, u8 port_num, bool en) | 919 | int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en) |
919 | { | 920 | { |
920 | struct be_mcc_wrb *wrb; | 921 | struct be_mcc_wrb *wrb; |
921 | struct be_cmd_req_promiscuous_config *req; | 922 | struct be_cmd_req_promiscuous_config *req; |
922 | 923 | ||
923 | spin_lock_bh(&ctrl->mcc_lock); | 924 | spin_lock_bh(&adapter->mcc_lock); |
924 | 925 | ||
925 | wrb = wrb_from_mcc(&ctrl->mcc_obj.q); | 926 | wrb = wrb_from_mcc(&adapter->mcc_obj.q); |
926 | BUG_ON(!wrb); | 927 | BUG_ON(!wrb); |
927 | 928 | ||
928 | req = embedded_payload(wrb); | 929 | req = embedded_payload(wrb); |
@@ -937,9 +938,9 @@ int be_cmd_promiscuous_config(struct be_ctrl_info *ctrl, u8 port_num, bool en) | |||
937 | else | 938 | else |
938 | req->port0_promiscuous = en; | 939 | req->port0_promiscuous = en; |
939 | 940 | ||
940 | be_mcc_notify_wait(ctrl); | 941 | be_mcc_notify_wait(adapter); |
941 | 942 | ||
942 | spin_unlock_bh(&ctrl->mcc_lock); | 943 | spin_unlock_bh(&adapter->mcc_lock); |
943 | return 0; | 944 | return 0; |
944 | } | 945 | } |
945 | 946 | ||
@@ -947,16 +948,16 @@ int be_cmd_promiscuous_config(struct be_ctrl_info *ctrl, u8 port_num, bool en) | |||
947 | * Use MCC for this command as it may be called in BH context | 948 | * Use MCC for this command as it may be called in BH context |
948 | * (mc == NULL) => multicast promiscous | 949 | * (mc == NULL) => multicast promiscous |
949 | */ | 950 | */ |
950 | int be_cmd_multicast_set(struct be_ctrl_info *ctrl, u32 if_id, | 951 | int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id, |
951 | struct dev_mc_list *mc_list, u32 mc_count) | 952 | struct dev_mc_list *mc_list, u32 mc_count) |
952 | { | 953 | { |
953 | #define BE_MAX_MC 32 /* set mcast promisc if > 32 */ | 954 | #define BE_MAX_MC 32 /* set mcast promisc if > 32 */ |
954 | struct be_mcc_wrb *wrb; | 955 | struct be_mcc_wrb *wrb; |
955 | struct be_cmd_req_mcast_mac_config *req; | 956 | struct be_cmd_req_mcast_mac_config *req; |
956 | 957 | ||
957 | spin_lock_bh(&ctrl->mcc_lock); | 958 | spin_lock_bh(&adapter->mcc_lock); |
958 | 959 | ||
959 | wrb = wrb_from_mcc(&ctrl->mcc_obj.q); | 960 | wrb = wrb_from_mcc(&adapter->mcc_obj.q); |
960 | BUG_ON(!wrb); | 961 | BUG_ON(!wrb); |
961 | 962 | ||
962 | req = embedded_payload(wrb); | 963 | req = embedded_payload(wrb); |
@@ -979,20 +980,20 @@ int be_cmd_multicast_set(struct be_ctrl_info *ctrl, u32 if_id, | |||
979 | req->promiscuous = 1; | 980 | req->promiscuous = 1; |
980 | } | 981 | } |
981 | 982 | ||
982 | be_mcc_notify_wait(ctrl); | 983 | be_mcc_notify_wait(adapter); |
983 | 984 | ||
984 | spin_unlock_bh(&ctrl->mcc_lock); | 985 | spin_unlock_bh(&adapter->mcc_lock); |
985 | 986 | ||
986 | return 0; | 987 | return 0; |
987 | } | 988 | } |
988 | 989 | ||
989 | int be_cmd_set_flow_control(struct be_ctrl_info *ctrl, u32 tx_fc, u32 rx_fc) | 990 | int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc) |
990 | { | 991 | { |
991 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 992 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
992 | struct be_cmd_req_set_flow_control *req = embedded_payload(wrb); | 993 | struct be_cmd_req_set_flow_control *req = embedded_payload(wrb); |
993 | int status; | 994 | int status; |
994 | 995 | ||
995 | spin_lock(&ctrl->mbox_lock); | 996 | spin_lock(&adapter->mbox_lock); |
996 | 997 | ||
997 | memset(wrb, 0, sizeof(*wrb)); | 998 | memset(wrb, 0, sizeof(*wrb)); |
998 | 999 | ||
@@ -1004,19 +1005,19 @@ int be_cmd_set_flow_control(struct be_ctrl_info *ctrl, u32 tx_fc, u32 rx_fc) | |||
1004 | req->tx_flow_control = cpu_to_le16((u16)tx_fc); | 1005 | req->tx_flow_control = cpu_to_le16((u16)tx_fc); |
1005 | req->rx_flow_control = cpu_to_le16((u16)rx_fc); | 1006 | req->rx_flow_control = cpu_to_le16((u16)rx_fc); |
1006 | 1007 | ||
1007 | status = be_mbox_db_ring(ctrl); | 1008 | status = be_mbox_db_ring(adapter); |
1008 | 1009 | ||
1009 | spin_unlock(&ctrl->mbox_lock); | 1010 | spin_unlock(&adapter->mbox_lock); |
1010 | return status; | 1011 | return status; |
1011 | } | 1012 | } |
1012 | 1013 | ||
1013 | int be_cmd_get_flow_control(struct be_ctrl_info *ctrl, u32 *tx_fc, u32 *rx_fc) | 1014 | int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc) |
1014 | { | 1015 | { |
1015 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 1016 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
1016 | struct be_cmd_req_get_flow_control *req = embedded_payload(wrb); | 1017 | struct be_cmd_req_get_flow_control *req = embedded_payload(wrb); |
1017 | int status; | 1018 | int status; |
1018 | 1019 | ||
1019 | spin_lock(&ctrl->mbox_lock); | 1020 | spin_lock(&adapter->mbox_lock); |
1020 | 1021 | ||
1021 | memset(wrb, 0, sizeof(*wrb)); | 1022 | memset(wrb, 0, sizeof(*wrb)); |
1022 | 1023 | ||
@@ -1025,7 +1026,7 @@ int be_cmd_get_flow_control(struct be_ctrl_info *ctrl, u32 *tx_fc, u32 *rx_fc) | |||
1025 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | 1026 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1026 | OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req)); | 1027 | OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req)); |
1027 | 1028 | ||
1028 | status = be_mbox_db_ring(ctrl); | 1029 | status = be_mbox_db_ring(adapter); |
1029 | if (!status) { | 1030 | if (!status) { |
1030 | struct be_cmd_resp_get_flow_control *resp = | 1031 | struct be_cmd_resp_get_flow_control *resp = |
1031 | embedded_payload(wrb); | 1032 | embedded_payload(wrb); |
@@ -1033,17 +1034,17 @@ int be_cmd_get_flow_control(struct be_ctrl_info *ctrl, u32 *tx_fc, u32 *rx_fc) | |||
1033 | *rx_fc = le16_to_cpu(resp->rx_flow_control); | 1034 | *rx_fc = le16_to_cpu(resp->rx_flow_control); |
1034 | } | 1035 | } |
1035 | 1036 | ||
1036 | spin_unlock(&ctrl->mbox_lock); | 1037 | spin_unlock(&adapter->mbox_lock); |
1037 | return status; | 1038 | return status; |
1038 | } | 1039 | } |
1039 | 1040 | ||
1040 | int be_cmd_query_fw_cfg(struct be_ctrl_info *ctrl, u32 *port_num) | 1041 | int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num) |
1041 | { | 1042 | { |
1042 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | 1043 | struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem); |
1043 | struct be_cmd_req_query_fw_cfg *req = embedded_payload(wrb); | 1044 | struct be_cmd_req_query_fw_cfg *req = embedded_payload(wrb); |
1044 | int status; | 1045 | int status; |
1045 | 1046 | ||
1046 | spin_lock(&ctrl->mbox_lock); | 1047 | spin_lock(&adapter->mbox_lock); |
1047 | 1048 | ||
1048 | memset(wrb, 0, sizeof(*wrb)); | 1049 | memset(wrb, 0, sizeof(*wrb)); |
1049 | 1050 | ||
@@ -1052,12 +1053,12 @@ int be_cmd_query_fw_cfg(struct be_ctrl_info *ctrl, u32 *port_num) | |||
1052 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | 1053 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1053 | OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req)); | 1054 | OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req)); |
1054 | 1055 | ||
1055 | status = be_mbox_db_ring(ctrl); | 1056 | status = be_mbox_db_ring(adapter); |
1056 | if (!status) { | 1057 | if (!status) { |
1057 | struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); | 1058 | struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); |
1058 | *port_num = le32_to_cpu(resp->phys_port); | 1059 | *port_num = le32_to_cpu(resp->phys_port); |
1059 | } | 1060 | } |
1060 | 1061 | ||
1061 | spin_unlock(&ctrl->mbox_lock); | 1062 | spin_unlock(&adapter->mbox_lock); |
1062 | return status; | 1063 | return status; |
1063 | } | 1064 | } |