diff options
Diffstat (limited to 'drivers/net/atl1e/atl1e_hw.h')
| -rw-r--r-- | drivers/net/atl1e/atl1e_hw.h | 111 |
1 files changed, 4 insertions, 107 deletions
diff --git a/drivers/net/atl1e/atl1e_hw.h b/drivers/net/atl1e/atl1e_hw.h index 5ea2f4d86cfa..74df16aef793 100644 --- a/drivers/net/atl1e/atl1e_hw.h +++ b/drivers/net/atl1e/atl1e_hw.h | |||
| @@ -629,127 +629,24 @@ s32 atl1e_restart_autoneg(struct atl1e_hw *hw); | |||
| 629 | 629 | ||
| 630 | /***************************** MII definition ***************************************/ | 630 | /***************************** MII definition ***************************************/ |
| 631 | /* PHY Common Register */ | 631 | /* PHY Common Register */ |
| 632 | #define MII_BMCR 0x00 | ||
| 633 | #define MII_BMSR 0x01 | ||
| 634 | #define MII_PHYSID1 0x02 | ||
| 635 | #define MII_PHYSID2 0x03 | ||
| 636 | #define MII_ADVERTISE 0x04 | ||
| 637 | #define MII_LPA 0x05 | ||
| 638 | #define MII_EXPANSION 0x06 | ||
| 639 | #define MII_AT001_CR 0x09 | ||
| 640 | #define MII_AT001_SR 0x0A | ||
| 641 | #define MII_AT001_ESR 0x0F | ||
| 642 | #define MII_AT001_PSCR 0x10 | 632 | #define MII_AT001_PSCR 0x10 |
| 643 | #define MII_AT001_PSSR 0x11 | 633 | #define MII_AT001_PSSR 0x11 |
| 644 | #define MII_INT_CTRL 0x12 | 634 | #define MII_INT_CTRL 0x12 |
| 645 | #define MII_INT_STATUS 0x13 | 635 | #define MII_INT_STATUS 0x13 |
| 646 | #define MII_SMARTSPEED 0x14 | 636 | #define MII_SMARTSPEED 0x14 |
| 647 | #define MII_RERRCOUNTER 0x15 | ||
| 648 | #define MII_SREVISION 0x16 | ||
| 649 | #define MII_RESV1 0x17 | ||
| 650 | #define MII_LBRERROR 0x18 | 637 | #define MII_LBRERROR 0x18 |
| 651 | #define MII_PHYADDR 0x19 | ||
| 652 | #define MII_RESV2 0x1a | 638 | #define MII_RESV2 0x1a |
| 653 | #define MII_TPISTATUS 0x1b | ||
| 654 | #define MII_NCONFIG 0x1c | ||
| 655 | 639 | ||
| 656 | #define MII_DBG_ADDR 0x1D | 640 | #define MII_DBG_ADDR 0x1D |
| 657 | #define MII_DBG_DATA 0x1E | 641 | #define MII_DBG_DATA 0x1E |
| 658 | 642 | ||
| 659 | |||
| 660 | /* PHY Control Register */ | ||
| 661 | #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ | ||
| 662 | #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ | ||
| 663 | #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ | ||
| 664 | #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ | ||
| 665 | #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ | ||
| 666 | #define MII_CR_POWER_DOWN 0x0800 /* Power down */ | ||
| 667 | #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ | ||
| 668 | #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ | ||
| 669 | #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ | ||
| 670 | #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ | ||
| 671 | #define MII_CR_SPEED_MASK 0x2040 | ||
| 672 | #define MII_CR_SPEED_1000 0x0040 | ||
| 673 | #define MII_CR_SPEED_100 0x2000 | ||
| 674 | #define MII_CR_SPEED_10 0x0000 | ||
| 675 | |||
| 676 | |||
| 677 | /* PHY Status Register */ | ||
| 678 | #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ | ||
| 679 | #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ | ||
| 680 | #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ | ||
| 681 | #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ | ||
| 682 | #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ | ||
| 683 | #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ | ||
| 684 | #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ | ||
| 685 | #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ | ||
| 686 | #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ | ||
| 687 | #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ | ||
| 688 | #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ | ||
| 689 | #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ | ||
| 690 | #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ | ||
| 691 | #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ | ||
| 692 | #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ | ||
| 693 | |||
| 694 | /* Link partner ability register. */ | ||
| 695 | #define MII_LPA_SLCT 0x001f /* Same as advertise selector */ | ||
| 696 | #define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ | ||
| 697 | #define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ | ||
| 698 | #define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ | ||
| 699 | #define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ | ||
| 700 | #define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */ | ||
| 701 | #define MII_LPA_PAUSE 0x0400 /* PAUSE */ | ||
| 702 | #define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */ | ||
| 703 | #define MII_LPA_RFAULT 0x2000 /* Link partner faulted */ | ||
| 704 | #define MII_LPA_LPACK 0x4000 /* Link partner acked us */ | ||
| 705 | #define MII_LPA_NPAGE 0x8000 /* Next page bit */ | ||
| 706 | |||
| 707 | /* Autoneg Advertisement Register */ | 643 | /* Autoneg Advertisement Register */ |
| 708 | #define MII_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ | 644 | #define MII_AR_DEFAULT_CAP_MASK 0 |
| 709 | #define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ | ||
| 710 | #define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ | ||
| 711 | #define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ | ||
| 712 | #define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ | ||
| 713 | #define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ | ||
| 714 | #define MII_AR_PAUSE 0x0400 /* Pause operation desired */ | ||
| 715 | #define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ | ||
| 716 | #define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ | ||
| 717 | #define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ | ||
| 718 | #define MII_AR_SPEED_MASK 0x01E0 | ||
| 719 | #define MII_AR_DEFAULT_CAP_MASK 0x0DE0 | ||
| 720 | 645 | ||
| 721 | /* 1000BASE-T Control Register */ | 646 | /* 1000BASE-T Control Register */ |
| 722 | #define MII_AT001_CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ | 647 | #define MII_AT001_CR_1000T_SPEED_MASK \ |
| 723 | #define MII_AT001_CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ | 648 | (ADVERTISE_1000FULL | ADVERTISE_1000HALF) |
| 724 | #define MII_AT001_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ | 649 | #define MII_AT001_CR_1000T_DEFAULT_CAP_MASK MII_AT001_CR_1000T_SPEED_MASK |
| 725 | /* 0=DTE device */ | ||
| 726 | #define MII_AT001_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ | ||
| 727 | /* 0=Configure PHY as Slave */ | ||
| 728 | #define MII_AT001_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ | ||
| 729 | /* 0=Automatic Master/Slave config */ | ||
| 730 | #define MII_AT001_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ | ||
| 731 | #define MII_AT001_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ | ||
| 732 | #define MII_AT001_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ | ||
| 733 | #define MII_AT001_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ | ||
| 734 | #define MII_AT001_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ | ||
| 735 | #define MII_AT001_CR_1000T_SPEED_MASK 0x0300 | ||
| 736 | #define MII_AT001_CR_1000T_DEFAULT_CAP_MASK 0x0300 | ||
| 737 | |||
| 738 | /* 1000BASE-T Status Register */ | ||
| 739 | #define MII_AT001_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ | ||
| 740 | #define MII_AT001_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ | ||
| 741 | #define MII_AT001_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ | ||
| 742 | #define MII_AT001_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ | ||
| 743 | #define MII_AT001_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ | ||
| 744 | #define MII_AT001_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ | ||
| 745 | #define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT 12 | ||
| 746 | #define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT 13 | ||
| 747 | |||
| 748 | /* Extended Status Register */ | ||
| 749 | #define MII_AT001_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ | ||
| 750 | #define MII_AT001_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ | ||
| 751 | #define MII_AT001_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ | ||
| 752 | #define MII_AT001_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ | ||
| 753 | 650 | ||
| 754 | /* AT001 PHY Specific Control Register */ | 651 | /* AT001 PHY Specific Control Register */ |
| 755 | #define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ | 652 | #define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ |